2 * Copyright (c) 2013-2016 Qlogic Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
30 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
31 * Content: Contains Hardware dependant functions
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
40 #include "ql_inline.h"
44 #include "ql_minidump.h"
50 static void qla_del_rcv_cntxt(qla_host_t *ha);
51 static int qla_init_rcv_cntxt(qla_host_t *ha);
52 static void qla_del_xmt_cntxt(qla_host_t *ha);
53 static int qla_init_xmt_cntxt(qla_host_t *ha);
54 static int qla_mbx_cmd(qla_host_t *ha, uint32_t *h_mbox, uint32_t n_hmbox,
55 uint32_t *fw_mbox, uint32_t n_fwmbox, uint32_t no_pause);
56 static int qla_config_intr_cntxt(qla_host_t *ha, uint32_t start_idx,
57 uint32_t num_intrs, uint32_t create);
58 static int qla_config_rss(qla_host_t *ha, uint16_t cntxt_id);
59 static int qla_config_intr_coalesce(qla_host_t *ha, uint16_t cntxt_id,
60 int tenable, int rcv);
61 static int qla_set_mac_rcv_mode(qla_host_t *ha, uint32_t mode);
62 static int qla_link_event_req(qla_host_t *ha, uint16_t cntxt_id);
64 static int qla_tx_tso(qla_host_t *ha, struct mbuf *mp, q80_tx_cmd_t *tx_cmd,
66 static int qla_hw_add_all_mcast(qla_host_t *ha);
67 static int qla_hw_del_all_mcast(qla_host_t *ha);
68 static int qla_add_rcv_rings(qla_host_t *ha, uint32_t sds_idx, uint32_t nsds);
70 static int qla_init_nic_func(qla_host_t *ha);
71 static int qla_stop_nic_func(qla_host_t *ha);
72 static int qla_query_fw_dcbx_caps(qla_host_t *ha);
73 static int qla_set_port_config(qla_host_t *ha, uint32_t cfg_bits);
74 static int qla_get_port_config(qla_host_t *ha, uint32_t *cfg_bits);
75 static void qla_get_quick_stats(qla_host_t *ha);
76 static int qla_set_cam_search_mode(qla_host_t *ha, uint32_t search_mode);
77 static int qla_get_cam_search_mode(qla_host_t *ha);
79 static void ql_minidump_free(qla_host_t *ha);
83 qla_sysctl_get_drvr_stats(SYSCTL_HANDLER_ARGS)
89 err = sysctl_handle_int(oidp, &ret, 0, req);
91 if (err || !req->newptr)
96 ha = (qla_host_t *)arg1;
98 for (i = 0; i < ha->hw.num_sds_rings; i++) {
100 device_printf(ha->pci_dev,
101 "%s: sds_ring[%d] = %p\n", __func__,i,
102 (void *)ha->hw.sds[i].intr_count);
104 device_printf(ha->pci_dev,
105 "%s: sds_ring[%d].spurious_intr_count = %p\n",
107 i, (void *)ha->hw.sds[i].spurious_intr_count);
109 device_printf(ha->pci_dev,
110 "%s: sds_ring[%d].rx_free = %d\n", __func__,i,
111 ha->hw.sds[i].rx_free);
114 for (i = 0; i < ha->hw.num_tx_rings; i++)
115 device_printf(ha->pci_dev,
116 "%s: tx[%d] = %p\n", __func__,i,
117 (void *)ha->tx_ring[i].count);
119 for (i = 0; i < ha->hw.num_rds_rings; i++)
120 device_printf(ha->pci_dev,
121 "%s: rds_ring[%d] = %p\n", __func__,i,
122 (void *)ha->hw.rds[i].count);
124 device_printf(ha->pci_dev, "%s: lro_pkt_count = %p\n", __func__,
125 (void *)ha->lro_pkt_count);
127 device_printf(ha->pci_dev, "%s: lro_bytes = %p\n", __func__,
128 (void *)ha->lro_bytes);
130 #ifdef QL_ENABLE_ISCSI_TLV
131 device_printf(ha->pci_dev, "%s: iscsi_pkts = %p\n", __func__,
132 (void *)ha->hw.iscsi_pkt_count);
133 #endif /* #ifdef QL_ENABLE_ISCSI_TLV */
140 qla_sysctl_get_quick_stats(SYSCTL_HANDLER_ARGS)
145 err = sysctl_handle_int(oidp, &ret, 0, req);
147 if (err || !req->newptr)
151 ha = (qla_host_t *)arg1;
152 qla_get_quick_stats(ha);
160 qla_stop_pegs(qla_host_t *ha)
164 ql_rdwr_indreg32(ha, Q8_CRB_PEG_0, &val, 0);
165 ql_rdwr_indreg32(ha, Q8_CRB_PEG_1, &val, 0);
166 ql_rdwr_indreg32(ha, Q8_CRB_PEG_2, &val, 0);
167 ql_rdwr_indreg32(ha, Q8_CRB_PEG_3, &val, 0);
168 ql_rdwr_indreg32(ha, Q8_CRB_PEG_4, &val, 0);
169 device_printf(ha->pci_dev, "%s PEGS HALTED!!!!!\n", __func__);
173 qla_sysctl_stop_pegs(SYSCTL_HANDLER_ARGS)
178 err = sysctl_handle_int(oidp, &ret, 0, req);
181 if (err || !req->newptr)
185 ha = (qla_host_t *)arg1;
186 (void)QLA_LOCK(ha, __func__, 0);
188 QLA_UNLOCK(ha, __func__);
193 #endif /* #ifdef QL_DBG */
196 qla_validate_set_port_cfg_bit(uint32_t bits)
198 if ((bits & 0xF) > 1)
201 if (((bits >> 4) & 0xF) > 2)
204 if (((bits >> 8) & 0xF) > 2)
211 qla_sysctl_port_cfg(SYSCTL_HANDLER_ARGS)
217 err = sysctl_handle_int(oidp, &ret, 0, req);
219 if (err || !req->newptr)
222 if ((qla_validate_set_port_cfg_bit((uint32_t)ret) == 0)) {
224 ha = (qla_host_t *)arg1;
226 err = qla_get_port_config(ha, &cfg_bits);
229 goto qla_sysctl_set_port_cfg_exit;
232 cfg_bits |= Q8_PORT_CFG_BITS_DCBX_ENABLE;
234 cfg_bits &= ~Q8_PORT_CFG_BITS_DCBX_ENABLE;
238 cfg_bits &= ~Q8_PORT_CFG_BITS_PAUSE_CFG_MASK;
240 if ((ret & 0xF) == 0) {
241 cfg_bits |= Q8_PORT_CFG_BITS_PAUSE_DISABLED;
242 } else if ((ret & 0xF) == 1){
243 cfg_bits |= Q8_PORT_CFG_BITS_PAUSE_STD;
245 cfg_bits |= Q8_PORT_CFG_BITS_PAUSE_PPM;
249 cfg_bits &= ~Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK;
252 cfg_bits |= Q8_PORT_CFG_BITS_STDPAUSE_XMT_RCV;
253 } else if (ret == 1){
254 cfg_bits |= Q8_PORT_CFG_BITS_STDPAUSE_XMT;
256 cfg_bits |= Q8_PORT_CFG_BITS_STDPAUSE_RCV;
259 err = qla_set_port_config(ha, cfg_bits);
261 ha = (qla_host_t *)arg1;
263 err = qla_get_port_config(ha, &cfg_bits);
266 qla_sysctl_set_port_cfg_exit:
271 qla_sysctl_set_cam_search_mode(SYSCTL_HANDLER_ARGS)
276 err = sysctl_handle_int(oidp, &ret, 0, req);
278 if (err || !req->newptr)
281 ha = (qla_host_t *)arg1;
283 if ((ret == Q8_HW_CONFIG_CAM_SEARCH_MODE_INTERNAL) ||
284 (ret == Q8_HW_CONFIG_CAM_SEARCH_MODE_AUTO)) {
285 err = qla_set_cam_search_mode(ha, (uint32_t)ret);
287 device_printf(ha->pci_dev, "%s: ret = %d\n", __func__, ret);
294 qla_sysctl_get_cam_search_mode(SYSCTL_HANDLER_ARGS)
299 err = sysctl_handle_int(oidp, &ret, 0, req);
301 if (err || !req->newptr)
304 ha = (qla_host_t *)arg1;
305 err = qla_get_cam_search_mode(ha);
312 * Name: ql_hw_add_sysctls
313 * Function: Add P3Plus specific sysctls
316 ql_hw_add_sysctls(qla_host_t *ha)
322 ha->hw.num_sds_rings = MAX_SDS_RINGS;
323 ha->hw.num_rds_rings = MAX_RDS_RINGS;
324 ha->hw.num_tx_rings = NUM_TX_RINGS;
326 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
327 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
328 OID_AUTO, "num_rds_rings", CTLFLAG_RD, &ha->hw.num_rds_rings,
329 ha->hw.num_rds_rings, "Number of Rcv Descriptor Rings");
331 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
332 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
333 OID_AUTO, "num_sds_rings", CTLFLAG_RD, &ha->hw.num_sds_rings,
334 ha->hw.num_sds_rings, "Number of Status Descriptor Rings");
336 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
337 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
338 OID_AUTO, "num_tx_rings", CTLFLAG_RD, &ha->hw.num_tx_rings,
339 ha->hw.num_tx_rings, "Number of Transmit Rings");
341 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
342 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
343 OID_AUTO, "tx_ring_index", CTLFLAG_RW, &ha->txr_idx,
344 ha->txr_idx, "Tx Ring Used");
346 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
347 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
348 OID_AUTO, "drvr_stats", CTLTYPE_INT | CTLFLAG_RW,
350 qla_sysctl_get_drvr_stats, "I", "Driver Maintained Statistics");
352 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
353 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
354 OID_AUTO, "quick_stats", CTLTYPE_INT | CTLFLAG_RW,
356 qla_sysctl_get_quick_stats, "I", "Quick Statistics");
358 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
359 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
360 OID_AUTO, "max_tx_segs", CTLFLAG_RD, &ha->hw.max_tx_segs,
361 ha->hw.max_tx_segs, "Max # of Segments in a non-TSO pkt");
363 ha->hw.sds_cidx_thres = 32;
364 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
365 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
366 OID_AUTO, "sds_cidx_thres", CTLFLAG_RW, &ha->hw.sds_cidx_thres,
367 ha->hw.sds_cidx_thres,
368 "Number of SDS entries to process before updating"
369 " SDS Ring Consumer Index");
371 ha->hw.rds_pidx_thres = 32;
372 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
373 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
374 OID_AUTO, "rds_pidx_thres", CTLFLAG_RW, &ha->hw.rds_pidx_thres,
375 ha->hw.rds_pidx_thres,
376 "Number of Rcv Rings Entries to post before updating"
377 " RDS Ring Producer Index");
379 ha->hw.rcv_intr_coalesce = (3 << 16) | 256;
380 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
381 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
382 OID_AUTO, "rcv_intr_coalesce", CTLFLAG_RW,
383 &ha->hw.rcv_intr_coalesce,
384 ha->hw.rcv_intr_coalesce,
385 "Rcv Intr Coalescing Parameters\n"
386 "\tbits 15:0 max packets\n"
387 "\tbits 31:16 max micro-seconds to wait\n"
389 "\tifconfig <if> down && ifconfig <if> up\n"
390 "\tto take effect \n");
392 ha->hw.xmt_intr_coalesce = (64 << 16) | 64;
393 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
394 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
395 OID_AUTO, "xmt_intr_coalesce", CTLFLAG_RW,
396 &ha->hw.xmt_intr_coalesce,
397 ha->hw.xmt_intr_coalesce,
398 "Xmt Intr Coalescing Parameters\n"
399 "\tbits 15:0 max packets\n"
400 "\tbits 31:16 max micro-seconds to wait\n"
402 "\tifconfig <if> down && ifconfig <if> up\n"
403 "\tto take effect \n");
405 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
406 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
407 OID_AUTO, "port_cfg", CTLTYPE_INT | CTLFLAG_RW,
409 qla_sysctl_port_cfg, "I",
410 "Set Port Configuration if values below "
411 "otherwise Get Port Configuration\n"
412 "\tBits 0-3 ; 1 = DCBX Enable; 0 = DCBX Disable\n"
413 "\tBits 4-7 : 0 = no pause; 1 = std ; 2 = ppm \n"
414 "\tBits 8-11: std pause cfg; 0 = xmt and rcv;"
415 " 1 = xmt only; 2 = rcv only;\n"
418 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
419 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
420 OID_AUTO, "set_cam_search_mode", CTLTYPE_INT | CTLFLAG_RW,
422 qla_sysctl_set_cam_search_mode, "I",
423 "Set CAM Search Mode"
424 "\t 1 = search mode internal\n"
425 "\t 2 = search mode auto\n");
427 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
428 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
429 OID_AUTO, "get_cam_search_mode", CTLTYPE_INT | CTLFLAG_RW,
431 qla_sysctl_get_cam_search_mode, "I",
432 "Get CAM Search Mode"
433 "\t 1 = search mode internal\n"
434 "\t 2 = search mode auto\n");
436 ha->hw.enable_9kb = 1;
438 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
439 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
440 OID_AUTO, "enable_9kb", CTLFLAG_RW, &ha->hw.enable_9kb,
441 ha->hw.enable_9kb, "Enable 9Kbyte Buffers when MTU = 9000");
443 ha->hw.enable_hw_lro = 1;
445 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
446 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
447 OID_AUTO, "enable_hw_lro", CTLFLAG_RW, &ha->hw.enable_hw_lro,
448 ha->hw.enable_hw_lro, "Enable Hardware LRO; Default is true \n"
449 "\t 1 : Hardware LRO if LRO is enabled\n"
450 "\t 0 : Software LRO if LRO is enabled\n"
451 "\t Any change requires ifconfig down/up to take effect\n"
452 "\t Note that LRO may be turned off/on via ifconfig\n");
454 ha->hw.mdump_active = 0;
455 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
456 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
457 OID_AUTO, "minidump_active", CTLFLAG_RW, &ha->hw.mdump_active,
459 "Minidump retrieval is Active");
461 ha->hw.mdump_done = 0;
462 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
463 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
464 OID_AUTO, "mdump_done", CTLFLAG_RW,
465 &ha->hw.mdump_done, ha->hw.mdump_done,
466 "Minidump has been done and available for retrieval");
468 ha->hw.mdump_capture_mask = 0xF;
469 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
470 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
471 OID_AUTO, "minidump_capture_mask", CTLFLAG_RW,
472 &ha->hw.mdump_capture_mask, ha->hw.mdump_capture_mask,
473 "Minidump capture mask");
477 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
478 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
479 OID_AUTO, "err_inject",
480 CTLFLAG_RW, &ha->err_inject, ha->err_inject,
481 "Error to be injected\n"
482 "\t\t\t 0: No Errors\n"
483 "\t\t\t 1: rcv: rxb struct invalid\n"
484 "\t\t\t 2: rcv: mp == NULL\n"
485 "\t\t\t 3: lro: rxb struct invalid\n"
486 "\t\t\t 4: lro: mp == NULL\n"
487 "\t\t\t 5: rcv: num handles invalid\n"
488 "\t\t\t 6: reg: indirect reg rd_wr failure\n"
489 "\t\t\t 7: ocm: offchip memory rd_wr failure\n"
490 "\t\t\t 8: mbx: mailbox command failure\n"
491 "\t\t\t 9: heartbeat failure\n"
492 "\t\t\t A: temperature failure\n"
493 "\t\t\t 11: m_getcl or m_getjcl failure\n" );
495 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
496 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
497 OID_AUTO, "peg_stop", CTLTYPE_INT | CTLFLAG_RW,
499 qla_sysctl_stop_pegs, "I", "Peg Stop");
501 #endif /* #ifdef QL_DBG */
503 ha->hw.user_pri_nic = 0;
504 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
505 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
506 OID_AUTO, "user_pri_nic", CTLFLAG_RW, &ha->hw.user_pri_nic,
508 "VLAN Tag User Priority for Normal Ethernet Packets");
510 ha->hw.user_pri_iscsi = 4;
511 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
512 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
513 OID_AUTO, "user_pri_iscsi", CTLFLAG_RW, &ha->hw.user_pri_iscsi,
514 ha->hw.user_pri_iscsi,
515 "VLAN Tag User Priority for iSCSI Packets");
520 ql_hw_link_status(qla_host_t *ha)
522 device_printf(ha->pci_dev, "cable_oui\t\t 0x%08x\n", ha->hw.cable_oui);
524 if (ha->hw.link_up) {
525 device_printf(ha->pci_dev, "link Up\n");
527 device_printf(ha->pci_dev, "link Down\n");
530 if (ha->hw.flags.fduplex) {
531 device_printf(ha->pci_dev, "Full Duplex\n");
533 device_printf(ha->pci_dev, "Half Duplex\n");
536 if (ha->hw.flags.autoneg) {
537 device_printf(ha->pci_dev, "Auto Negotiation Enabled\n");
539 device_printf(ha->pci_dev, "Auto Negotiation Disabled\n");
542 switch (ha->hw.link_speed) {
544 device_printf(ha->pci_dev, "link speed\t\t 10Gps\n");
548 device_printf(ha->pci_dev, "link speed\t\t 1Gps\n");
552 device_printf(ha->pci_dev, "link speed\t\t 100Mbps\n");
556 device_printf(ha->pci_dev, "link speed\t\t Unknown\n");
560 switch (ha->hw.module_type) {
563 device_printf(ha->pci_dev, "Module Type 10GBase-LRM\n");
567 device_printf(ha->pci_dev, "Module Type 10GBase-LR\n");
571 device_printf(ha->pci_dev, "Module Type 10GBase-SR\n");
575 device_printf(ha->pci_dev,
576 "Module Type 10GE Passive Copper(Compliant)[%d m]\n",
577 ha->hw.cable_length);
581 device_printf(ha->pci_dev, "Module Type 10GE Active"
582 " Limiting Copper(Compliant)[%d m]\n",
583 ha->hw.cable_length);
587 device_printf(ha->pci_dev,
588 "Module Type 10GE Passive Copper"
589 " (Legacy, Best Effort)[%d m]\n",
590 ha->hw.cable_length);
594 device_printf(ha->pci_dev, "Module Type 1000Base-SX\n");
598 device_printf(ha->pci_dev, "Module Type 1000Base-LX\n");
602 device_printf(ha->pci_dev, "Module Type 1000Base-CX\n");
606 device_printf(ha->pci_dev, "Module Type 1000Base-T\n");
610 device_printf(ha->pci_dev, "Module Type 1GE Passive Copper"
611 "(Legacy, Best Effort)\n");
615 device_printf(ha->pci_dev, "Unknown Module Type 0x%x\n",
620 if (ha->hw.link_faults == 1)
621 device_printf(ha->pci_dev, "SFP Power Fault\n");
626 * Function: Frees the DMA'able memory allocated in ql_alloc_dma()
629 ql_free_dma(qla_host_t *ha)
633 if (ha->hw.dma_buf.flags.sds_ring) {
634 for (i = 0; i < ha->hw.num_sds_rings; i++) {
635 ql_free_dmabuf(ha, &ha->hw.dma_buf.sds_ring[i]);
637 ha->hw.dma_buf.flags.sds_ring = 0;
640 if (ha->hw.dma_buf.flags.rds_ring) {
641 for (i = 0; i < ha->hw.num_rds_rings; i++) {
642 ql_free_dmabuf(ha, &ha->hw.dma_buf.rds_ring[i]);
644 ha->hw.dma_buf.flags.rds_ring = 0;
647 if (ha->hw.dma_buf.flags.tx_ring) {
648 ql_free_dmabuf(ha, &ha->hw.dma_buf.tx_ring);
649 ha->hw.dma_buf.flags.tx_ring = 0;
651 ql_minidump_free(ha);
656 * Function: Allocates DMA'able memory for Tx/Rx Rings, Tx/Rx Contexts.
659 ql_alloc_dma(qla_host_t *ha)
662 uint32_t i, j, size, tx_ring_size;
664 qla_hw_tx_cntxt_t *tx_cntxt;
670 QL_DPRINT2(ha, (dev, "%s: enter\n", __func__));
674 * Allocate Transmit Ring
676 tx_ring_size = (sizeof(q80_tx_cmd_t) * NUM_TX_DESCRIPTORS);
677 size = (tx_ring_size * ha->hw.num_tx_rings);
679 hw->dma_buf.tx_ring.alignment = 8;
680 hw->dma_buf.tx_ring.size = size + PAGE_SIZE;
682 if (ql_alloc_dmabuf(ha, &hw->dma_buf.tx_ring)) {
683 device_printf(dev, "%s: tx ring alloc failed\n", __func__);
684 goto ql_alloc_dma_exit;
687 vaddr = (uint8_t *)hw->dma_buf.tx_ring.dma_b;
688 paddr = hw->dma_buf.tx_ring.dma_addr;
690 for (i = 0; i < ha->hw.num_tx_rings; i++) {
691 tx_cntxt = (qla_hw_tx_cntxt_t *)&hw->tx_cntxt[i];
693 tx_cntxt->tx_ring_base = (q80_tx_cmd_t *)vaddr;
694 tx_cntxt->tx_ring_paddr = paddr;
696 vaddr += tx_ring_size;
697 paddr += tx_ring_size;
700 for (i = 0; i < ha->hw.num_tx_rings; i++) {
701 tx_cntxt = (qla_hw_tx_cntxt_t *)&hw->tx_cntxt[i];
703 tx_cntxt->tx_cons = (uint32_t *)vaddr;
704 tx_cntxt->tx_cons_paddr = paddr;
706 vaddr += sizeof (uint32_t);
707 paddr += sizeof (uint32_t);
710 ha->hw.dma_buf.flags.tx_ring = 1;
712 QL_DPRINT2(ha, (dev, "%s: tx_ring phys %p virt %p\n",
713 __func__, (void *)(hw->dma_buf.tx_ring.dma_addr),
714 hw->dma_buf.tx_ring.dma_b));
716 * Allocate Receive Descriptor Rings
719 for (i = 0; i < hw->num_rds_rings; i++) {
721 hw->dma_buf.rds_ring[i].alignment = 8;
722 hw->dma_buf.rds_ring[i].size =
723 (sizeof(q80_recv_desc_t)) * NUM_RX_DESCRIPTORS;
725 if (ql_alloc_dmabuf(ha, &hw->dma_buf.rds_ring[i])) {
726 device_printf(dev, "%s: rds ring[%d] alloc failed\n",
729 for (j = 0; j < i; j++)
730 ql_free_dmabuf(ha, &hw->dma_buf.rds_ring[j]);
732 goto ql_alloc_dma_exit;
734 QL_DPRINT4(ha, (dev, "%s: rx_ring[%d] phys %p virt %p\n",
735 __func__, i, (void *)(hw->dma_buf.rds_ring[i].dma_addr),
736 hw->dma_buf.rds_ring[i].dma_b));
739 hw->dma_buf.flags.rds_ring = 1;
742 * Allocate Status Descriptor Rings
745 for (i = 0; i < hw->num_sds_rings; i++) {
746 hw->dma_buf.sds_ring[i].alignment = 8;
747 hw->dma_buf.sds_ring[i].size =
748 (sizeof(q80_stat_desc_t)) * NUM_STATUS_DESCRIPTORS;
750 if (ql_alloc_dmabuf(ha, &hw->dma_buf.sds_ring[i])) {
751 device_printf(dev, "%s: sds ring alloc failed\n",
754 for (j = 0; j < i; j++)
755 ql_free_dmabuf(ha, &hw->dma_buf.sds_ring[j]);
757 goto ql_alloc_dma_exit;
759 QL_DPRINT4(ha, (dev, "%s: sds_ring[%d] phys %p virt %p\n",
761 (void *)(hw->dma_buf.sds_ring[i].dma_addr),
762 hw->dma_buf.sds_ring[i].dma_b));
764 for (i = 0; i < hw->num_sds_rings; i++) {
765 hw->sds[i].sds_ring_base =
766 (q80_stat_desc_t *)hw->dma_buf.sds_ring[i].dma_b;
769 hw->dma_buf.flags.sds_ring = 1;
778 #define Q8_MBX_MSEC_DELAY 5000
781 qla_mbx_cmd(qla_host_t *ha, uint32_t *h_mbox, uint32_t n_hmbox,
782 uint32_t *fw_mbox, uint32_t n_fwmbox, uint32_t no_pause)
788 if (QL_ERR_INJECT(ha, INJCT_MBX_CMD_FAILURE)) {
790 ha->qla_initiate_recovery = 1;
791 goto exit_qla_mbx_cmd;
797 i = Q8_MBX_MSEC_DELAY;
800 data = READ_REG32(ha, Q8_HOST_MBOX_CNTRL);
806 qla_mdelay(__func__, 1);
812 device_printf(ha->pci_dev, "%s: host_mbx_cntrl 0x%08x\n",
815 ha->qla_initiate_recovery = 1;
816 goto exit_qla_mbx_cmd;
819 for (i = 0; i < n_hmbox; i++) {
820 WRITE_REG32(ha, (Q8_HOST_MBOX0 + (i << 2)), *h_mbox);
824 WRITE_REG32(ha, Q8_HOST_MBOX_CNTRL, 0x1);
827 i = Q8_MBX_MSEC_DELAY;
829 data = READ_REG32(ha, Q8_FW_MBOX_CNTRL);
831 if ((data & 0x3) == 1) {
832 data = READ_REG32(ha, Q8_FW_MBOX0);
833 if ((data & 0xF000) != 0x8000)
839 qla_mdelay(__func__, 1);
844 device_printf(ha->pci_dev, "%s: fw_mbx_cntrl 0x%08x\n",
847 ha->qla_initiate_recovery = 1;
848 goto exit_qla_mbx_cmd;
851 for (i = 0; i < n_fwmbox; i++) {
852 *fw_mbox++ = READ_REG32(ha, (Q8_FW_MBOX0 + (i << 2)));
855 WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0);
856 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
863 qla_get_nic_partition(qla_host_t *ha, uint32_t *supports_9kb,
867 device_t dev = ha->pci_dev;
869 bzero(ha->hw.mbox, (sizeof (uint32_t) * Q8_NUM_MBOX));
873 mbox[0] = Q8_MBX_GET_NIC_PARTITION | (0x2 << 16) | (0x2 << 29);
875 if (qla_mbx_cmd(ha, mbox, 2, mbox, 19, 0)) {
876 device_printf(dev, "%s: failed0\n", __func__);
881 if (supports_9kb != NULL) {
882 if (mbox[16] & 0x80) /* bit 7 of mbox 16 */
888 if (num_rcvq != NULL)
889 *num_rcvq = ((mbox[6] >> 16) & 0xFFFF);
891 if ((err != 1) && (err != 0)) {
892 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
899 qla_config_intr_cntxt(qla_host_t *ha, uint32_t start_idx, uint32_t num_intrs,
903 device_t dev = ha->pci_dev;
904 q80_config_intr_t *c_intr;
905 q80_config_intr_rsp_t *c_intr_rsp;
907 c_intr = (q80_config_intr_t *)ha->hw.mbox;
908 bzero(c_intr, (sizeof (q80_config_intr_t)));
910 c_intr->opcode = Q8_MBX_CONFIG_INTR;
912 c_intr->count_version = (sizeof (q80_config_intr_t) >> 2);
913 c_intr->count_version |= Q8_MBX_CMD_VERSION;
915 c_intr->nentries = num_intrs;
917 for (i = 0; i < num_intrs; i++) {
919 c_intr->intr[i].cmd_type = Q8_MBX_CONFIG_INTR_CREATE;
920 c_intr->intr[i].msix_index = start_idx + 1 + i;
922 c_intr->intr[i].cmd_type = Q8_MBX_CONFIG_INTR_DELETE;
923 c_intr->intr[i].msix_index =
924 ha->hw.intr_id[(start_idx + i)];
927 c_intr->intr[i].cmd_type |= Q8_MBX_CONFIG_INTR_TYPE_MSI_X;
930 if (qla_mbx_cmd(ha, (uint32_t *)c_intr,
931 (sizeof (q80_config_intr_t) >> 2),
932 ha->hw.mbox, (sizeof (q80_config_intr_rsp_t) >> 2), 0)) {
933 device_printf(dev, "%s: failed0\n", __func__);
937 c_intr_rsp = (q80_config_intr_rsp_t *)ha->hw.mbox;
939 err = Q8_MBX_RSP_STATUS(c_intr_rsp->regcnt_status);
942 device_printf(dev, "%s: failed1 [0x%08x, %d]\n", __func__, err,
943 c_intr_rsp->nentries);
945 for (i = 0; i < c_intr_rsp->nentries; i++) {
946 device_printf(dev, "%s: [%d]:[0x%x 0x%x 0x%x]\n",
948 c_intr_rsp->intr[i].status,
949 c_intr_rsp->intr[i].intr_id,
950 c_intr_rsp->intr[i].intr_src);
956 for (i = 0; ((i < num_intrs) && create); i++) {
957 if (!c_intr_rsp->intr[i].status) {
958 ha->hw.intr_id[(start_idx + i)] =
959 c_intr_rsp->intr[i].intr_id;
960 ha->hw.intr_src[(start_idx + i)] =
961 c_intr_rsp->intr[i].intr_src;
969 * Name: qla_config_rss
970 * Function: Configure RSS for the context/interface.
972 static const uint64_t rss_key[] = { 0xbeac01fa6a42b73bULL,
973 0x8030f20c77cb2da3ULL,
974 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
975 0x255b0ec26d5a56daULL };
978 qla_config_rss(qla_host_t *ha, uint16_t cntxt_id)
980 q80_config_rss_t *c_rss;
981 q80_config_rss_rsp_t *c_rss_rsp;
983 device_t dev = ha->pci_dev;
985 c_rss = (q80_config_rss_t *)ha->hw.mbox;
986 bzero(c_rss, (sizeof (q80_config_rss_t)));
988 c_rss->opcode = Q8_MBX_CONFIG_RSS;
990 c_rss->count_version = (sizeof (q80_config_rss_t) >> 2);
991 c_rss->count_version |= Q8_MBX_CMD_VERSION;
993 c_rss->hash_type = (Q8_MBX_RSS_HASH_TYPE_IPV4_TCP_IP |
994 Q8_MBX_RSS_HASH_TYPE_IPV6_TCP_IP);
995 //c_rss->hash_type = (Q8_MBX_RSS_HASH_TYPE_IPV4_TCP |
996 // Q8_MBX_RSS_HASH_TYPE_IPV6_TCP);
998 c_rss->flags = Q8_MBX_RSS_FLAGS_ENABLE_RSS;
999 c_rss->flags |= Q8_MBX_RSS_FLAGS_USE_IND_TABLE;
1001 c_rss->indtbl_mask = Q8_MBX_RSS_INDTBL_MASK;
1003 c_rss->indtbl_mask |= Q8_MBX_RSS_FLAGS_MULTI_RSS_VALID;
1004 c_rss->flags |= Q8_MBX_RSS_FLAGS_TYPE_CRSS;
1006 c_rss->cntxt_id = cntxt_id;
1008 for (i = 0; i < 5; i++) {
1009 c_rss->rss_key[i] = rss_key[i];
1012 if (qla_mbx_cmd(ha, (uint32_t *)c_rss,
1013 (sizeof (q80_config_rss_t) >> 2),
1014 ha->hw.mbox, (sizeof(q80_config_rss_rsp_t) >> 2), 0)) {
1015 device_printf(dev, "%s: failed0\n", __func__);
1018 c_rss_rsp = (q80_config_rss_rsp_t *)ha->hw.mbox;
1020 err = Q8_MBX_RSP_STATUS(c_rss_rsp->regcnt_status);
1023 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
1030 qla_set_rss_ind_table(qla_host_t *ha, uint32_t start_idx, uint32_t count,
1031 uint16_t cntxt_id, uint8_t *ind_table)
1033 q80_config_rss_ind_table_t *c_rss_ind;
1034 q80_config_rss_ind_table_rsp_t *c_rss_ind_rsp;
1036 device_t dev = ha->pci_dev;
1038 if ((count > Q8_RSS_IND_TBL_SIZE) ||
1039 ((start_idx + count - 1) > Q8_RSS_IND_TBL_MAX_IDX)) {
1040 device_printf(dev, "%s: illegal count [%d, %d]\n", __func__,
1045 c_rss_ind = (q80_config_rss_ind_table_t *)ha->hw.mbox;
1046 bzero(c_rss_ind, sizeof (q80_config_rss_ind_table_t));
1048 c_rss_ind->opcode = Q8_MBX_CONFIG_RSS_TABLE;
1049 c_rss_ind->count_version = (sizeof (q80_config_rss_ind_table_t) >> 2);
1050 c_rss_ind->count_version |= Q8_MBX_CMD_VERSION;
1052 c_rss_ind->start_idx = start_idx;
1053 c_rss_ind->end_idx = start_idx + count - 1;
1054 c_rss_ind->cntxt_id = cntxt_id;
1055 bcopy(ind_table, c_rss_ind->ind_table, count);
1057 if (qla_mbx_cmd(ha, (uint32_t *)c_rss_ind,
1058 (sizeof (q80_config_rss_ind_table_t) >> 2), ha->hw.mbox,
1059 (sizeof(q80_config_rss_ind_table_rsp_t) >> 2), 0)) {
1060 device_printf(dev, "%s: failed0\n", __func__);
1064 c_rss_ind_rsp = (q80_config_rss_ind_table_rsp_t *)ha->hw.mbox;
1065 err = Q8_MBX_RSP_STATUS(c_rss_ind_rsp->regcnt_status);
1068 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
1075 * Name: qla_config_intr_coalesce
1076 * Function: Configure Interrupt Coalescing.
1079 qla_config_intr_coalesce(qla_host_t *ha, uint16_t cntxt_id, int tenable,
1082 q80_config_intr_coalesc_t *intrc;
1083 q80_config_intr_coalesc_rsp_t *intrc_rsp;
1085 device_t dev = ha->pci_dev;
1087 intrc = (q80_config_intr_coalesc_t *)ha->hw.mbox;
1088 bzero(intrc, (sizeof (q80_config_intr_coalesc_t)));
1090 intrc->opcode = Q8_MBX_CONFIG_INTR_COALESCE;
1091 intrc->count_version = (sizeof (q80_config_intr_coalesc_t) >> 2);
1092 intrc->count_version |= Q8_MBX_CMD_VERSION;
1095 intrc->flags = Q8_MBX_INTRC_FLAGS_RCV;
1096 intrc->max_pkts = ha->hw.rcv_intr_coalesce & 0xFFFF;
1097 intrc->max_mswait = (ha->hw.rcv_intr_coalesce >> 16) & 0xFFFF;
1099 intrc->flags = Q8_MBX_INTRC_FLAGS_XMT;
1100 intrc->max_pkts = ha->hw.xmt_intr_coalesce & 0xFFFF;
1101 intrc->max_mswait = (ha->hw.xmt_intr_coalesce >> 16) & 0xFFFF;
1104 intrc->cntxt_id = cntxt_id;
1107 intrc->flags |= Q8_MBX_INTRC_FLAGS_PERIODIC;
1108 intrc->timer_type = Q8_MBX_INTRC_TIMER_PERIODIC;
1110 for (i = 0; i < ha->hw.num_sds_rings; i++) {
1111 intrc->sds_ring_mask |= (1 << i);
1113 intrc->ms_timeout = 1000;
1116 if (qla_mbx_cmd(ha, (uint32_t *)intrc,
1117 (sizeof (q80_config_intr_coalesc_t) >> 2),
1118 ha->hw.mbox, (sizeof(q80_config_intr_coalesc_rsp_t) >> 2), 0)) {
1119 device_printf(dev, "%s: failed0\n", __func__);
1122 intrc_rsp = (q80_config_intr_coalesc_rsp_t *)ha->hw.mbox;
1124 err = Q8_MBX_RSP_STATUS(intrc_rsp->regcnt_status);
1127 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
1136 * Name: qla_config_mac_addr
1137 * Function: binds a MAC address to the context/interface.
1138 * Can be unicast, multicast or broadcast.
1141 qla_config_mac_addr(qla_host_t *ha, uint8_t *mac_addr, uint32_t add_mac,
1144 q80_config_mac_addr_t *cmac;
1145 q80_config_mac_addr_rsp_t *cmac_rsp;
1147 device_t dev = ha->pci_dev;
1149 uint8_t *mac_cpy = mac_addr;
1151 if (num_mac > Q8_MAX_MAC_ADDRS) {
1152 device_printf(dev, "%s: %s num_mac [0x%x] > Q8_MAX_MAC_ADDRS\n",
1153 __func__, (add_mac ? "Add" : "Del"), num_mac);
1157 cmac = (q80_config_mac_addr_t *)ha->hw.mbox;
1158 bzero(cmac, (sizeof (q80_config_mac_addr_t)));
1160 cmac->opcode = Q8_MBX_CONFIG_MAC_ADDR;
1161 cmac->count_version = sizeof (q80_config_mac_addr_t) >> 2;
1162 cmac->count_version |= Q8_MBX_CMD_VERSION;
1165 cmac->cmd = Q8_MBX_CMAC_CMD_ADD_MAC_ADDR;
1167 cmac->cmd = Q8_MBX_CMAC_CMD_DEL_MAC_ADDR;
1169 cmac->cmd |= Q8_MBX_CMAC_CMD_CAM_INGRESS;
1171 cmac->nmac_entries = num_mac;
1172 cmac->cntxt_id = ha->hw.rcv_cntxt_id;
1174 for (i = 0; i < num_mac; i++) {
1175 bcopy(mac_addr, cmac->mac_addr[i].addr, Q8_ETHER_ADDR_LEN);
1176 mac_addr = mac_addr + ETHER_ADDR_LEN;
1179 if (qla_mbx_cmd(ha, (uint32_t *)cmac,
1180 (sizeof (q80_config_mac_addr_t) >> 2),
1181 ha->hw.mbox, (sizeof(q80_config_mac_addr_rsp_t) >> 2), 1)) {
1182 device_printf(dev, "%s: %s failed0\n", __func__,
1183 (add_mac ? "Add" : "Del"));
1186 cmac_rsp = (q80_config_mac_addr_rsp_t *)ha->hw.mbox;
1188 err = Q8_MBX_RSP_STATUS(cmac_rsp->regcnt_status);
1191 device_printf(dev, "%s: %s failed1 [0x%08x]\n", __func__,
1192 (add_mac ? "Add" : "Del"), err);
1193 for (i = 0; i < num_mac; i++) {
1194 device_printf(dev, "%s: %02x:%02x:%02x:%02x:%02x:%02x\n",
1195 __func__, mac_cpy[0], mac_cpy[1], mac_cpy[2],
1196 mac_cpy[3], mac_cpy[4], mac_cpy[5]);
1197 mac_cpy += ETHER_ADDR_LEN;
1207 * Name: qla_set_mac_rcv_mode
1208 * Function: Enable/Disable AllMulticast and Promiscous Modes.
1211 qla_set_mac_rcv_mode(qla_host_t *ha, uint32_t mode)
1213 q80_config_mac_rcv_mode_t *rcv_mode;
1215 q80_config_mac_rcv_mode_rsp_t *rcv_mode_rsp;
1216 device_t dev = ha->pci_dev;
1218 rcv_mode = (q80_config_mac_rcv_mode_t *)ha->hw.mbox;
1219 bzero(rcv_mode, (sizeof (q80_config_mac_rcv_mode_t)));
1221 rcv_mode->opcode = Q8_MBX_CONFIG_MAC_RX_MODE;
1222 rcv_mode->count_version = sizeof (q80_config_mac_rcv_mode_t) >> 2;
1223 rcv_mode->count_version |= Q8_MBX_CMD_VERSION;
1225 rcv_mode->mode = mode;
1227 rcv_mode->cntxt_id = ha->hw.rcv_cntxt_id;
1229 if (qla_mbx_cmd(ha, (uint32_t *)rcv_mode,
1230 (sizeof (q80_config_mac_rcv_mode_t) >> 2),
1231 ha->hw.mbox, (sizeof(q80_config_mac_rcv_mode_rsp_t) >> 2), 1)) {
1232 device_printf(dev, "%s: failed0\n", __func__);
1235 rcv_mode_rsp = (q80_config_mac_rcv_mode_rsp_t *)ha->hw.mbox;
1237 err = Q8_MBX_RSP_STATUS(rcv_mode_rsp->regcnt_status);
1240 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
1248 ql_set_promisc(qla_host_t *ha)
1252 ha->hw.mac_rcv_mode |= Q8_MBX_MAC_RCV_PROMISC_ENABLE;
1253 ret = qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode);
1258 qla_reset_promisc(qla_host_t *ha)
1260 ha->hw.mac_rcv_mode &= ~Q8_MBX_MAC_RCV_PROMISC_ENABLE;
1261 (void)qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode);
1265 ql_set_allmulti(qla_host_t *ha)
1269 ha->hw.mac_rcv_mode |= Q8_MBX_MAC_ALL_MULTI_ENABLE;
1270 ret = qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode);
1275 qla_reset_allmulti(qla_host_t *ha)
1277 ha->hw.mac_rcv_mode &= ~Q8_MBX_MAC_ALL_MULTI_ENABLE;
1278 (void)qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode);
1282 * Name: ql_set_max_mtu
1284 * Sets the maximum transfer unit size for the specified rcv context.
1287 ql_set_max_mtu(qla_host_t *ha, uint32_t mtu, uint16_t cntxt_id)
1290 q80_set_max_mtu_t *max_mtu;
1291 q80_set_max_mtu_rsp_t *max_mtu_rsp;
1296 max_mtu = (q80_set_max_mtu_t *)ha->hw.mbox;
1297 bzero(max_mtu, (sizeof (q80_set_max_mtu_t)));
1299 max_mtu->opcode = Q8_MBX_SET_MAX_MTU;
1300 max_mtu->count_version = (sizeof (q80_set_max_mtu_t) >> 2);
1301 max_mtu->count_version |= Q8_MBX_CMD_VERSION;
1303 max_mtu->cntxt_id = cntxt_id;
1306 if (qla_mbx_cmd(ha, (uint32_t *)max_mtu,
1307 (sizeof (q80_set_max_mtu_t) >> 2),
1308 ha->hw.mbox, (sizeof (q80_set_max_mtu_rsp_t) >> 2), 1)) {
1309 device_printf(dev, "%s: failed\n", __func__);
1313 max_mtu_rsp = (q80_set_max_mtu_rsp_t *)ha->hw.mbox;
1315 err = Q8_MBX_RSP_STATUS(max_mtu_rsp->regcnt_status);
1318 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
1325 qla_link_event_req(qla_host_t *ha, uint16_t cntxt_id)
1328 q80_link_event_t *lnk;
1329 q80_link_event_rsp_t *lnk_rsp;
1334 lnk = (q80_link_event_t *)ha->hw.mbox;
1335 bzero(lnk, (sizeof (q80_link_event_t)));
1337 lnk->opcode = Q8_MBX_LINK_EVENT_REQ;
1338 lnk->count_version = (sizeof (q80_link_event_t) >> 2);
1339 lnk->count_version |= Q8_MBX_CMD_VERSION;
1341 lnk->cntxt_id = cntxt_id;
1342 lnk->cmd = Q8_LINK_EVENT_CMD_ENABLE_ASYNC;
1344 if (qla_mbx_cmd(ha, (uint32_t *)lnk, (sizeof (q80_link_event_t) >> 2),
1345 ha->hw.mbox, (sizeof (q80_link_event_rsp_t) >> 2), 0)) {
1346 device_printf(dev, "%s: failed\n", __func__);
1350 lnk_rsp = (q80_link_event_rsp_t *)ha->hw.mbox;
1352 err = Q8_MBX_RSP_STATUS(lnk_rsp->regcnt_status);
1355 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
1362 qla_config_fw_lro(qla_host_t *ha, uint16_t cntxt_id)
1365 q80_config_fw_lro_t *fw_lro;
1366 q80_config_fw_lro_rsp_t *fw_lro_rsp;
1371 fw_lro = (q80_config_fw_lro_t *)ha->hw.mbox;
1372 bzero(fw_lro, sizeof(q80_config_fw_lro_t));
1374 fw_lro->opcode = Q8_MBX_CONFIG_FW_LRO;
1375 fw_lro->count_version = (sizeof (q80_config_fw_lro_t) >> 2);
1376 fw_lro->count_version |= Q8_MBX_CMD_VERSION;
1378 fw_lro->flags |= Q8_MBX_FW_LRO_IPV4 | Q8_MBX_FW_LRO_IPV4_WO_DST_IP_CHK;
1379 fw_lro->flags |= Q8_MBX_FW_LRO_IPV6 | Q8_MBX_FW_LRO_IPV6_WO_DST_IP_CHK;
1381 fw_lro->cntxt_id = cntxt_id;
1383 if (qla_mbx_cmd(ha, (uint32_t *)fw_lro,
1384 (sizeof (q80_config_fw_lro_t) >> 2),
1385 ha->hw.mbox, (sizeof (q80_config_fw_lro_rsp_t) >> 2), 0)) {
1386 device_printf(dev, "%s: failed\n", __func__);
1390 fw_lro_rsp = (q80_config_fw_lro_rsp_t *)ha->hw.mbox;
1392 err = Q8_MBX_RSP_STATUS(fw_lro_rsp->regcnt_status);
1395 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
1402 qla_set_cam_search_mode(qla_host_t *ha, uint32_t search_mode)
1405 q80_hw_config_t *hw_config;
1406 q80_hw_config_rsp_t *hw_config_rsp;
1411 hw_config = (q80_hw_config_t *)ha->hw.mbox;
1412 bzero(hw_config, sizeof (q80_hw_config_t));
1414 hw_config->opcode = Q8_MBX_HW_CONFIG;
1415 hw_config->count_version = Q8_HW_CONFIG_SET_CAM_SEARCH_MODE_COUNT;
1416 hw_config->count_version |= Q8_MBX_CMD_VERSION;
1418 hw_config->cmd = Q8_HW_CONFIG_SET_CAM_SEARCH_MODE;
1420 hw_config->u.set_cam_search_mode.mode = search_mode;
1422 if (qla_mbx_cmd(ha, (uint32_t *)hw_config,
1423 (sizeof (q80_hw_config_t) >> 2),
1424 ha->hw.mbox, (sizeof (q80_hw_config_rsp_t) >> 2), 0)) {
1425 device_printf(dev, "%s: failed\n", __func__);
1428 hw_config_rsp = (q80_hw_config_rsp_t *)ha->hw.mbox;
1430 err = Q8_MBX_RSP_STATUS(hw_config_rsp->regcnt_status);
1433 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
1440 qla_get_cam_search_mode(qla_host_t *ha)
1443 q80_hw_config_t *hw_config;
1444 q80_hw_config_rsp_t *hw_config_rsp;
1449 hw_config = (q80_hw_config_t *)ha->hw.mbox;
1450 bzero(hw_config, sizeof (q80_hw_config_t));
1452 hw_config->opcode = Q8_MBX_HW_CONFIG;
1453 hw_config->count_version = Q8_HW_CONFIG_GET_CAM_SEARCH_MODE_COUNT;
1454 hw_config->count_version |= Q8_MBX_CMD_VERSION;
1456 hw_config->cmd = Q8_HW_CONFIG_GET_CAM_SEARCH_MODE;
1458 if (qla_mbx_cmd(ha, (uint32_t *)hw_config,
1459 (sizeof (q80_hw_config_t) >> 2),
1460 ha->hw.mbox, (sizeof (q80_hw_config_rsp_t) >> 2), 0)) {
1461 device_printf(dev, "%s: failed\n", __func__);
1464 hw_config_rsp = (q80_hw_config_rsp_t *)ha->hw.mbox;
1466 err = Q8_MBX_RSP_STATUS(hw_config_rsp->regcnt_status);
1469 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
1471 device_printf(dev, "%s: cam search mode [0x%08x]\n", __func__,
1472 hw_config_rsp->u.get_cam_search_mode.mode);
1481 qla_xmt_stats(qla_host_t *ha, q80_xmt_stats_t *xstat, int i)
1483 device_t dev = ha->pci_dev;
1485 if (i < ha->hw.num_tx_rings) {
1486 device_printf(dev, "%s[%d]: total_bytes\t\t%" PRIu64 "\n",
1487 __func__, i, xstat->total_bytes);
1488 device_printf(dev, "%s[%d]: total_pkts\t\t%" PRIu64 "\n",
1489 __func__, i, xstat->total_pkts);
1490 device_printf(dev, "%s[%d]: errors\t\t%" PRIu64 "\n",
1491 __func__, i, xstat->errors);
1492 device_printf(dev, "%s[%d]: pkts_dropped\t%" PRIu64 "\n",
1493 __func__, i, xstat->pkts_dropped);
1494 device_printf(dev, "%s[%d]: switch_pkts\t\t%" PRIu64 "\n",
1495 __func__, i, xstat->switch_pkts);
1496 device_printf(dev, "%s[%d]: num_buffers\t\t%" PRIu64 "\n",
1497 __func__, i, xstat->num_buffers);
1499 device_printf(dev, "%s: total_bytes\t\t\t%" PRIu64 "\n",
1500 __func__, xstat->total_bytes);
1501 device_printf(dev, "%s: total_pkts\t\t\t%" PRIu64 "\n",
1502 __func__, xstat->total_pkts);
1503 device_printf(dev, "%s: errors\t\t\t%" PRIu64 "\n",
1504 __func__, xstat->errors);
1505 device_printf(dev, "%s: pkts_dropped\t\t\t%" PRIu64 "\n",
1506 __func__, xstat->pkts_dropped);
1507 device_printf(dev, "%s: switch_pkts\t\t\t%" PRIu64 "\n",
1508 __func__, xstat->switch_pkts);
1509 device_printf(dev, "%s: num_buffers\t\t\t%" PRIu64 "\n",
1510 __func__, xstat->num_buffers);
1515 qla_rcv_stats(qla_host_t *ha, q80_rcv_stats_t *rstat)
1517 device_t dev = ha->pci_dev;
1519 device_printf(dev, "%s: total_bytes\t\t\t%" PRIu64 "\n", __func__,
1520 rstat->total_bytes);
1521 device_printf(dev, "%s: total_pkts\t\t\t%" PRIu64 "\n", __func__,
1523 device_printf(dev, "%s: lro_pkt_count\t\t%" PRIu64 "\n", __func__,
1524 rstat->lro_pkt_count);
1525 device_printf(dev, "%s: sw_pkt_count\t\t\t%" PRIu64 "\n", __func__,
1526 rstat->sw_pkt_count);
1527 device_printf(dev, "%s: ip_chksum_err\t\t%" PRIu64 "\n", __func__,
1528 rstat->ip_chksum_err);
1529 device_printf(dev, "%s: pkts_wo_acntxts\t\t%" PRIu64 "\n", __func__,
1530 rstat->pkts_wo_acntxts);
1531 device_printf(dev, "%s: pkts_dropped_no_sds_card\t%" PRIu64 "\n",
1532 __func__, rstat->pkts_dropped_no_sds_card);
1533 device_printf(dev, "%s: pkts_dropped_no_sds_host\t%" PRIu64 "\n",
1534 __func__, rstat->pkts_dropped_no_sds_host);
1535 device_printf(dev, "%s: oversized_pkts\t\t%" PRIu64 "\n", __func__,
1536 rstat->oversized_pkts);
1537 device_printf(dev, "%s: pkts_dropped_no_rds\t\t%" PRIu64 "\n",
1538 __func__, rstat->pkts_dropped_no_rds);
1539 device_printf(dev, "%s: unxpctd_mcast_pkts\t\t%" PRIu64 "\n",
1540 __func__, rstat->unxpctd_mcast_pkts);
1541 device_printf(dev, "%s: re1_fbq_error\t\t%" PRIu64 "\n", __func__,
1542 rstat->re1_fbq_error);
1543 device_printf(dev, "%s: invalid_mac_addr\t\t%" PRIu64 "\n", __func__,
1544 rstat->invalid_mac_addr);
1545 device_printf(dev, "%s: rds_prime_trys\t\t%" PRIu64 "\n", __func__,
1546 rstat->rds_prime_trys);
1547 device_printf(dev, "%s: rds_prime_success\t\t%" PRIu64 "\n", __func__,
1548 rstat->rds_prime_success);
1549 device_printf(dev, "%s: lro_flows_added\t\t%" PRIu64 "\n", __func__,
1550 rstat->lro_flows_added);
1551 device_printf(dev, "%s: lro_flows_deleted\t\t%" PRIu64 "\n", __func__,
1552 rstat->lro_flows_deleted);
1553 device_printf(dev, "%s: lro_flows_active\t\t%" PRIu64 "\n", __func__,
1554 rstat->lro_flows_active);
1555 device_printf(dev, "%s: pkts_droped_unknown\t\t%" PRIu64 "\n",
1556 __func__, rstat->pkts_droped_unknown);
1560 qla_mac_stats(qla_host_t *ha, q80_mac_stats_t *mstat)
1562 device_t dev = ha->pci_dev;
1564 device_printf(dev, "%s: xmt_frames\t\t\t%" PRIu64 "\n", __func__,
1566 device_printf(dev, "%s: xmt_bytes\t\t\t%" PRIu64 "\n", __func__,
1568 device_printf(dev, "%s: xmt_mcast_pkts\t\t%" PRIu64 "\n", __func__,
1569 mstat->xmt_mcast_pkts);
1570 device_printf(dev, "%s: xmt_bcast_pkts\t\t%" PRIu64 "\n", __func__,
1571 mstat->xmt_bcast_pkts);
1572 device_printf(dev, "%s: xmt_pause_frames\t\t%" PRIu64 "\n", __func__,
1573 mstat->xmt_pause_frames);
1574 device_printf(dev, "%s: xmt_cntrl_pkts\t\t%" PRIu64 "\n", __func__,
1575 mstat->xmt_cntrl_pkts);
1576 device_printf(dev, "%s: xmt_pkt_lt_64bytes\t\t%" PRIu64 "\n",
1577 __func__, mstat->xmt_pkt_lt_64bytes);
1578 device_printf(dev, "%s: xmt_pkt_lt_127bytes\t\t%" PRIu64 "\n",
1579 __func__, mstat->xmt_pkt_lt_127bytes);
1580 device_printf(dev, "%s: xmt_pkt_lt_255bytes\t\t%" PRIu64 "\n",
1581 __func__, mstat->xmt_pkt_lt_255bytes);
1582 device_printf(dev, "%s: xmt_pkt_lt_511bytes\t\t%" PRIu64 "\n",
1583 __func__, mstat->xmt_pkt_lt_511bytes);
1584 device_printf(dev, "%s: xmt_pkt_lt_1023bytes\t\t%" PRIu64 "\n",
1585 __func__, mstat->xmt_pkt_lt_1023bytes);
1586 device_printf(dev, "%s: xmt_pkt_lt_1518bytes\t\t%" PRIu64 "\n",
1587 __func__, mstat->xmt_pkt_lt_1518bytes);
1588 device_printf(dev, "%s: xmt_pkt_gt_1518bytes\t\t%" PRIu64 "\n",
1589 __func__, mstat->xmt_pkt_gt_1518bytes);
1591 device_printf(dev, "%s: rcv_frames\t\t\t%" PRIu64 "\n", __func__,
1593 device_printf(dev, "%s: rcv_bytes\t\t\t%" PRIu64 "\n", __func__,
1595 device_printf(dev, "%s: rcv_mcast_pkts\t\t%" PRIu64 "\n", __func__,
1596 mstat->rcv_mcast_pkts);
1597 device_printf(dev, "%s: rcv_bcast_pkts\t\t%" PRIu64 "\n", __func__,
1598 mstat->rcv_bcast_pkts);
1599 device_printf(dev, "%s: rcv_pause_frames\t\t%" PRIu64 "\n", __func__,
1600 mstat->rcv_pause_frames);
1601 device_printf(dev, "%s: rcv_cntrl_pkts\t\t%" PRIu64 "\n", __func__,
1602 mstat->rcv_cntrl_pkts);
1603 device_printf(dev, "%s: rcv_pkt_lt_64bytes\t\t%" PRIu64 "\n",
1604 __func__, mstat->rcv_pkt_lt_64bytes);
1605 device_printf(dev, "%s: rcv_pkt_lt_127bytes\t\t%" PRIu64 "\n",
1606 __func__, mstat->rcv_pkt_lt_127bytes);
1607 device_printf(dev, "%s: rcv_pkt_lt_255bytes\t\t%" PRIu64 "\n",
1608 __func__, mstat->rcv_pkt_lt_255bytes);
1609 device_printf(dev, "%s: rcv_pkt_lt_511bytes\t\t%" PRIu64 "\n",
1610 __func__, mstat->rcv_pkt_lt_511bytes);
1611 device_printf(dev, "%s: rcv_pkt_lt_1023bytes\t\t%" PRIu64 "\n",
1612 __func__, mstat->rcv_pkt_lt_1023bytes);
1613 device_printf(dev, "%s: rcv_pkt_lt_1518bytes\t\t%" PRIu64 "\n",
1614 __func__, mstat->rcv_pkt_lt_1518bytes);
1615 device_printf(dev, "%s: rcv_pkt_gt_1518bytes\t\t%" PRIu64 "\n",
1616 __func__, mstat->rcv_pkt_gt_1518bytes);
1618 device_printf(dev, "%s: rcv_len_error\t\t%" PRIu64 "\n", __func__,
1619 mstat->rcv_len_error);
1620 device_printf(dev, "%s: rcv_len_small\t\t%" PRIu64 "\n", __func__,
1621 mstat->rcv_len_small);
1622 device_printf(dev, "%s: rcv_len_large\t\t%" PRIu64 "\n", __func__,
1623 mstat->rcv_len_large);
1624 device_printf(dev, "%s: rcv_jabber\t\t\t%" PRIu64 "\n", __func__,
1626 device_printf(dev, "%s: rcv_dropped\t\t\t%" PRIu64 "\n", __func__,
1627 mstat->rcv_dropped);
1628 device_printf(dev, "%s: fcs_error\t\t\t%" PRIu64 "\n", __func__,
1630 device_printf(dev, "%s: align_error\t\t\t%" PRIu64 "\n", __func__,
1631 mstat->align_error);
1636 qla_get_hw_stats(qla_host_t *ha, uint32_t cmd, uint32_t rsp_size)
1639 q80_get_stats_t *stat;
1640 q80_get_stats_rsp_t *stat_rsp;
1645 stat = (q80_get_stats_t *)ha->hw.mbox;
1646 bzero(stat, (sizeof (q80_get_stats_t)));
1648 stat->opcode = Q8_MBX_GET_STATS;
1649 stat->count_version = 2;
1650 stat->count_version |= Q8_MBX_CMD_VERSION;
1654 if (qla_mbx_cmd(ha, (uint32_t *)stat, 2,
1655 ha->hw.mbox, (rsp_size >> 2), 0)) {
1656 device_printf(dev, "%s: failed\n", __func__);
1660 stat_rsp = (q80_get_stats_rsp_t *)ha->hw.mbox;
1662 err = Q8_MBX_RSP_STATUS(stat_rsp->regcnt_status);
1672 ql_get_stats(qla_host_t *ha)
1674 q80_get_stats_rsp_t *stat_rsp;
1675 q80_mac_stats_t *mstat;
1676 q80_xmt_stats_t *xstat;
1677 q80_rcv_stats_t *rstat;
1681 stat_rsp = (q80_get_stats_rsp_t *)ha->hw.mbox;
1683 * Get MAC Statistics
1685 cmd = Q8_GET_STATS_CMD_TYPE_MAC;
1686 // cmd |= Q8_GET_STATS_CMD_CLEAR;
1688 cmd |= ((ha->pci_func & 0x1) << 16);
1690 if (qla_get_hw_stats(ha, cmd, sizeof (q80_get_stats_rsp_t)) == 0) {
1691 mstat = (q80_mac_stats_t *)&stat_rsp->u.mac;
1692 qla_mac_stats(ha, mstat);
1694 device_printf(ha->pci_dev, "%s: mac failed [0x%08x]\n",
1695 __func__, ha->hw.mbox[0]);
1698 * Get RCV Statistics
1700 cmd = Q8_GET_STATS_CMD_RCV | Q8_GET_STATS_CMD_TYPE_CNTXT;
1701 // cmd |= Q8_GET_STATS_CMD_CLEAR;
1702 cmd |= (ha->hw.rcv_cntxt_id << 16);
1704 if (qla_get_hw_stats(ha, cmd, sizeof (q80_get_stats_rsp_t)) == 0) {
1705 rstat = (q80_rcv_stats_t *)&stat_rsp->u.rcv;
1706 qla_rcv_stats(ha, rstat);
1708 device_printf(ha->pci_dev, "%s: rcv failed [0x%08x]\n",
1709 __func__, ha->hw.mbox[0]);
1712 * Get XMT Statistics
1714 for (i = 0 ; i < ha->hw.num_tx_rings; i++) {
1715 cmd = Q8_GET_STATS_CMD_XMT | Q8_GET_STATS_CMD_TYPE_CNTXT;
1716 // cmd |= Q8_GET_STATS_CMD_CLEAR;
1717 cmd |= (ha->hw.tx_cntxt[i].tx_cntxt_id << 16);
1719 if (qla_get_hw_stats(ha, cmd, sizeof(q80_get_stats_rsp_t))
1721 xstat = (q80_xmt_stats_t *)&stat_rsp->u.xmt;
1722 qla_xmt_stats(ha, xstat, i);
1724 device_printf(ha->pci_dev, "%s: xmt failed [0x%08x]\n",
1725 __func__, ha->hw.mbox[0]);
1732 qla_get_quick_stats(qla_host_t *ha)
1734 q80_get_mac_rcv_xmt_stats_rsp_t *stat_rsp;
1735 q80_mac_stats_t *mstat;
1736 q80_xmt_stats_t *xstat;
1737 q80_rcv_stats_t *rstat;
1740 stat_rsp = (q80_get_mac_rcv_xmt_stats_rsp_t *)ha->hw.mbox;
1742 cmd = Q8_GET_STATS_CMD_TYPE_ALL;
1743 // cmd |= Q8_GET_STATS_CMD_CLEAR;
1745 // cmd |= ((ha->pci_func & 0x3) << 16);
1746 cmd |= (0xFFFF << 16);
1748 if (qla_get_hw_stats(ha, cmd,
1749 sizeof (q80_get_mac_rcv_xmt_stats_rsp_t)) == 0) {
1751 mstat = (q80_mac_stats_t *)&stat_rsp->mac;
1752 rstat = (q80_rcv_stats_t *)&stat_rsp->rcv;
1753 xstat = (q80_xmt_stats_t *)&stat_rsp->xmt;
1754 qla_mac_stats(ha, mstat);
1755 qla_rcv_stats(ha, rstat);
1756 qla_xmt_stats(ha, xstat, ha->hw.num_tx_rings);
1758 device_printf(ha->pci_dev, "%s: failed [0x%08x]\n",
1759 __func__, ha->hw.mbox[0]);
1766 * Function: Checks if the packet to be transmitted is a candidate for
1767 * Large TCP Segment Offload. If yes, the appropriate fields in the Tx
1768 * Ring Structure are plugged in.
1771 qla_tx_tso(qla_host_t *ha, struct mbuf *mp, q80_tx_cmd_t *tx_cmd, uint8_t *hdr)
1773 struct ether_vlan_header *eh;
1774 struct ip *ip = NULL;
1775 struct ip6_hdr *ip6 = NULL;
1776 struct tcphdr *th = NULL;
1777 uint32_t ehdrlen, hdrlen, ip_hlen, tcp_hlen, tcp_opt_off;
1778 uint16_t etype, opcode, offload = 1;
1784 eh = mtod(mp, struct ether_vlan_header *);
1786 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
1787 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
1788 etype = ntohs(eh->evl_proto);
1790 ehdrlen = ETHER_HDR_LEN;
1791 etype = ntohs(eh->evl_encap_proto);
1799 tcp_opt_off = ehdrlen + sizeof(struct ip) +
1800 sizeof(struct tcphdr);
1802 if (mp->m_len < tcp_opt_off) {
1803 m_copydata(mp, 0, tcp_opt_off, hdr);
1804 ip = (struct ip *)(hdr + ehdrlen);
1806 ip = (struct ip *)(mp->m_data + ehdrlen);
1809 ip_hlen = ip->ip_hl << 2;
1810 opcode = Q8_TX_CMD_OP_XMT_TCP_LSO;
1813 if ((ip->ip_p != IPPROTO_TCP) ||
1814 (ip_hlen != sizeof (struct ip))){
1815 /* IP Options are not supported */
1819 th = (struct tcphdr *)((caddr_t)ip + ip_hlen);
1823 case ETHERTYPE_IPV6:
1825 tcp_opt_off = ehdrlen + sizeof(struct ip6_hdr) +
1826 sizeof (struct tcphdr);
1828 if (mp->m_len < tcp_opt_off) {
1829 m_copydata(mp, 0, tcp_opt_off, hdr);
1830 ip6 = (struct ip6_hdr *)(hdr + ehdrlen);
1832 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
1835 ip_hlen = sizeof(struct ip6_hdr);
1836 opcode = Q8_TX_CMD_OP_XMT_TCP_LSO_IPV6;
1838 if (ip6->ip6_nxt != IPPROTO_TCP) {
1839 //device_printf(dev, "%s: ipv6\n", __func__);
1842 th = (struct tcphdr *)((caddr_t)ip6 + ip_hlen);
1846 QL_DPRINT8(ha, (dev, "%s: type!=ip\n", __func__));
1854 tcp_hlen = th->th_off << 2;
1855 hdrlen = ehdrlen + ip_hlen + tcp_hlen;
1857 if (mp->m_len < hdrlen) {
1858 if (mp->m_len < tcp_opt_off) {
1859 if (tcp_hlen > sizeof(struct tcphdr)) {
1860 m_copydata(mp, tcp_opt_off,
1861 (tcp_hlen - sizeof(struct tcphdr)),
1865 m_copydata(mp, 0, hdrlen, hdr);
1869 tx_cmd->mss = mp->m_pkthdr.tso_segsz;
1871 tx_cmd->flags_opcode = opcode ;
1872 tx_cmd->tcp_hdr_off = ip_hlen + ehdrlen;
1873 tx_cmd->total_hdr_len = hdrlen;
1875 /* Check for Multicast least significant bit of MSB == 1 */
1876 if (eh->evl_dhost[0] & 0x01) {
1877 tx_cmd->flags_opcode |= Q8_TX_CMD_FLAGS_MULTICAST;
1880 if (mp->m_len < hdrlen) {
1881 printf("%d\n", hdrlen);
1889 * Name: qla_tx_chksum
1890 * Function: Checks if the packet to be transmitted is a candidate for
1891 * TCP/UDP Checksum offload. If yes, the appropriate fields in the Tx
1892 * Ring Structure are plugged in.
1895 qla_tx_chksum(qla_host_t *ha, struct mbuf *mp, uint32_t *op_code,
1896 uint32_t *tcp_hdr_off)
1898 struct ether_vlan_header *eh;
1900 struct ip6_hdr *ip6;
1901 uint32_t ehdrlen, ip_hlen;
1902 uint16_t etype, opcode, offload = 1;
1904 uint8_t buf[sizeof(struct ip6_hdr)];
1910 if ((mp->m_pkthdr.csum_flags & (CSUM_TCP|CSUM_UDP)) == 0)
1913 eh = mtod(mp, struct ether_vlan_header *);
1915 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
1916 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
1917 etype = ntohs(eh->evl_proto);
1919 ehdrlen = ETHER_HDR_LEN;
1920 etype = ntohs(eh->evl_encap_proto);
1926 ip = (struct ip *)(mp->m_data + ehdrlen);
1928 ip_hlen = sizeof (struct ip);
1930 if (mp->m_len < (ehdrlen + ip_hlen)) {
1931 m_copydata(mp, ehdrlen, sizeof(struct ip), buf);
1932 ip = (struct ip *)buf;
1935 if (ip->ip_p == IPPROTO_TCP)
1936 opcode = Q8_TX_CMD_OP_XMT_TCP_CHKSUM;
1937 else if (ip->ip_p == IPPROTO_UDP)
1938 opcode = Q8_TX_CMD_OP_XMT_UDP_CHKSUM;
1940 //device_printf(dev, "%s: ipv4\n", __func__);
1945 case ETHERTYPE_IPV6:
1946 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
1948 ip_hlen = sizeof(struct ip6_hdr);
1950 if (mp->m_len < (ehdrlen + ip_hlen)) {
1951 m_copydata(mp, ehdrlen, sizeof (struct ip6_hdr),
1953 ip6 = (struct ip6_hdr *)buf;
1956 if (ip6->ip6_nxt == IPPROTO_TCP)
1957 opcode = Q8_TX_CMD_OP_XMT_TCP_CHKSUM_IPV6;
1958 else if (ip6->ip6_nxt == IPPROTO_UDP)
1959 opcode = Q8_TX_CMD_OP_XMT_UDP_CHKSUM_IPV6;
1961 //device_printf(dev, "%s: ipv6\n", __func__);
1974 *tcp_hdr_off = (ip_hlen + ehdrlen);
1979 #define QLA_TX_MIN_FREE 2
1982 * Function: Transmits a packet. It first checks if the packet is a
1983 * candidate for Large TCP Segment Offload and then for UDP/TCP checksum
1984 * offload. If either of these creteria are not met, it is transmitted
1985 * as a regular ethernet frame.
1988 ql_hw_send(qla_host_t *ha, bus_dma_segment_t *segs, int nsegs,
1989 uint32_t tx_idx, struct mbuf *mp, uint32_t txr_idx, uint32_t iscsi_pdu)
1991 struct ether_vlan_header *eh;
1992 qla_hw_t *hw = &ha->hw;
1993 q80_tx_cmd_t *tx_cmd, tso_cmd;
1994 bus_dma_segment_t *c_seg;
1995 uint32_t num_tx_cmds, hdr_len = 0;
1996 uint32_t total_length = 0, bytes, tx_cmd_count = 0, txr_next;
1999 uint8_t *src = NULL, *dst = NULL;
2000 uint8_t frame_hdr[QL_FRAME_HDR_SIZE];
2001 uint32_t op_code = 0;
2002 uint32_t tcp_hdr_off = 0;
2007 * Always make sure there is atleast one empty slot in the tx_ring
2008 * tx_ring is considered full when there only one entry available
2010 num_tx_cmds = (nsegs + (Q8_TX_CMD_MAX_SEGMENTS - 1)) >> 2;
2012 total_length = mp->m_pkthdr.len;
2013 if (total_length > QLA_MAX_TSO_FRAME_SIZE) {
2014 device_printf(dev, "%s: total length exceeds maxlen(%d)\n",
2015 __func__, total_length);
2018 eh = mtod(mp, struct ether_vlan_header *);
2020 if (mp->m_pkthdr.csum_flags & CSUM_TSO) {
2022 bzero((void *)&tso_cmd, sizeof(q80_tx_cmd_t));
2025 ret = qla_tx_tso(ha, mp, &tso_cmd, src);
2028 /* find the additional tx_cmd descriptors required */
2030 if (mp->m_flags & M_VLANTAG)
2031 tso_cmd.total_hdr_len += ETHER_VLAN_ENCAP_LEN;
2033 hdr_len = tso_cmd.total_hdr_len;
2035 bytes = sizeof(q80_tx_cmd_t) - Q8_TX_CMD_TSO_ALIGN;
2036 bytes = QL_MIN(bytes, hdr_len);
2042 bytes = QL_MIN((sizeof(q80_tx_cmd_t)), hdr_len);
2046 hdr_len = tso_cmd.total_hdr_len;
2049 src = (uint8_t *)eh;
2053 (void)qla_tx_chksum(ha, mp, &op_code, &tcp_hdr_off);
2057 ha->hw.iscsi_pkt_count++;
2059 if (hw->tx_cntxt[txr_idx].txr_free <= (num_tx_cmds + QLA_TX_MIN_FREE)) {
2060 ql_hw_tx_done_locked(ha, txr_idx);
2061 if (hw->tx_cntxt[txr_idx].txr_free <=
2062 (num_tx_cmds + QLA_TX_MIN_FREE)) {
2063 QL_DPRINT8(ha, (dev, "%s: (hw->txr_free <= "
2064 "(num_tx_cmds + QLA_TX_MIN_FREE))\n",
2070 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[tx_idx];
2072 if (!(mp->m_pkthdr.csum_flags & CSUM_TSO)) {
2074 if (nsegs > ha->hw.max_tx_segs)
2075 ha->hw.max_tx_segs = nsegs;
2077 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t));
2080 tx_cmd->flags_opcode = op_code;
2081 tx_cmd->tcp_hdr_off = tcp_hdr_off;
2084 tx_cmd->flags_opcode = Q8_TX_CMD_OP_XMT_ETHER;
2087 bcopy(&tso_cmd, tx_cmd, sizeof(q80_tx_cmd_t));
2088 ha->tx_tso_frames++;
2091 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2092 tx_cmd->flags_opcode |= Q8_TX_CMD_FLAGS_VLAN_TAGGED;
2095 eh->evl_tag |= ha->hw.user_pri_iscsi << 13;
2097 } else if (mp->m_flags & M_VLANTAG) {
2099 if (hdr_len) { /* TSO */
2100 tx_cmd->flags_opcode |= (Q8_TX_CMD_FLAGS_VLAN_TAGGED |
2101 Q8_TX_CMD_FLAGS_HW_VLAN_ID);
2102 tx_cmd->tcp_hdr_off += ETHER_VLAN_ENCAP_LEN;
2104 tx_cmd->flags_opcode |= Q8_TX_CMD_FLAGS_HW_VLAN_ID;
2106 ha->hw_vlan_tx_frames++;
2107 tx_cmd->vlan_tci = mp->m_pkthdr.ether_vtag;
2110 tx_cmd->vlan_tci |= ha->hw.user_pri_iscsi << 13;
2111 mp->m_pkthdr.ether_vtag = tx_cmd->vlan_tci;
2116 tx_cmd->n_bufs = (uint8_t)nsegs;
2117 tx_cmd->data_len_lo = (uint8_t)(total_length & 0xFF);
2118 tx_cmd->data_len_hi = qla_host_to_le16(((uint16_t)(total_length >> 8)));
2119 tx_cmd->cntxtid = Q8_TX_CMD_PORT_CNXTID(ha->pci_func);
2124 for (i = 0; ((i < Q8_TX_CMD_MAX_SEGMENTS) && nsegs); i++) {
2128 tx_cmd->buf1_addr = c_seg->ds_addr;
2129 tx_cmd->buf1_len = c_seg->ds_len;
2133 tx_cmd->buf2_addr = c_seg->ds_addr;
2134 tx_cmd->buf2_len = c_seg->ds_len;
2138 tx_cmd->buf3_addr = c_seg->ds_addr;
2139 tx_cmd->buf3_len = c_seg->ds_len;
2143 tx_cmd->buf4_addr = c_seg->ds_addr;
2144 tx_cmd->buf4_len = c_seg->ds_len;
2152 txr_next = hw->tx_cntxt[txr_idx].txr_next =
2153 (hw->tx_cntxt[txr_idx].txr_next + 1) &
2154 (NUM_TX_DESCRIPTORS - 1);
2160 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[txr_next];
2161 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t));
2164 if (mp->m_pkthdr.csum_flags & CSUM_TSO) {
2166 /* TSO : Copy the header in the following tx cmd descriptors */
2168 txr_next = hw->tx_cntxt[txr_idx].txr_next;
2170 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[txr_next];
2171 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t));
2173 bytes = sizeof(q80_tx_cmd_t) - Q8_TX_CMD_TSO_ALIGN;
2174 bytes = QL_MIN(bytes, hdr_len);
2176 dst = (uint8_t *)tx_cmd + Q8_TX_CMD_TSO_ALIGN;
2178 if (mp->m_flags & M_VLANTAG) {
2179 /* first copy the src/dst MAC addresses */
2180 bcopy(src, dst, (ETHER_ADDR_LEN * 2));
2181 dst += (ETHER_ADDR_LEN * 2);
2182 src += (ETHER_ADDR_LEN * 2);
2184 *((uint16_t *)dst) = htons(ETHERTYPE_VLAN);
2186 *((uint16_t *)dst) = htons(mp->m_pkthdr.ether_vtag);
2189 /* bytes left in src header */
2190 hdr_len -= ((ETHER_ADDR_LEN * 2) +
2191 ETHER_VLAN_ENCAP_LEN);
2193 /* bytes left in TxCmd Entry */
2194 bytes -= ((ETHER_ADDR_LEN * 2) + ETHER_VLAN_ENCAP_LEN);
2197 bcopy(src, dst, bytes);
2201 bcopy(src, dst, bytes);
2206 txr_next = hw->tx_cntxt[txr_idx].txr_next =
2207 (hw->tx_cntxt[txr_idx].txr_next + 1) &
2208 (NUM_TX_DESCRIPTORS - 1);
2212 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[txr_next];
2213 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t));
2215 bytes = QL_MIN((sizeof(q80_tx_cmd_t)), hdr_len);
2217 bcopy(src, tx_cmd, bytes);
2221 txr_next = hw->tx_cntxt[txr_idx].txr_next =
2222 (hw->tx_cntxt[txr_idx].txr_next + 1) &
2223 (NUM_TX_DESCRIPTORS - 1);
2228 hw->tx_cntxt[txr_idx].txr_free =
2229 hw->tx_cntxt[txr_idx].txr_free - tx_cmd_count;
2231 QL_UPDATE_TX_PRODUCER_INDEX(ha, hw->tx_cntxt[txr_idx].txr_next,\
2233 QL_DPRINT8(ha, (dev, "%s: return\n", __func__));
2240 #define Q8_CONFIG_IND_TBL_SIZE 32 /* < Q8_RSS_IND_TBL_SIZE and power of 2 */
2242 qla_config_rss_ind_table(qla_host_t *ha)
2245 uint8_t rss_ind_tbl[Q8_CONFIG_IND_TBL_SIZE];
2248 for (i = 0; i < Q8_CONFIG_IND_TBL_SIZE; i++) {
2249 rss_ind_tbl[i] = i % ha->hw.num_sds_rings;
2252 for (i = 0; i <= Q8_RSS_IND_TBL_MAX_IDX ;
2253 i = i + Q8_CONFIG_IND_TBL_SIZE) {
2255 if ((i + Q8_CONFIG_IND_TBL_SIZE) > Q8_RSS_IND_TBL_MAX_IDX) {
2256 count = Q8_RSS_IND_TBL_MAX_IDX - i + 1;
2258 count = Q8_CONFIG_IND_TBL_SIZE;
2261 if (qla_set_rss_ind_table(ha, i, count, ha->hw.rcv_cntxt_id,
2270 qla_config_soft_lro(qla_host_t *ha)
2273 qla_hw_t *hw = &ha->hw;
2274 struct lro_ctrl *lro;
2276 for (i = 0; i < hw->num_sds_rings; i++) {
2277 lro = &hw->sds[i].lro;
2279 bzero(lro, sizeof(struct lro_ctrl));
2281 #if (__FreeBSD_version >= 1100101)
2282 if (tcp_lro_init_args(lro, ha->ifp, 0, NUM_RX_DESCRIPTORS)) {
2283 device_printf(ha->pci_dev,
2284 "%s: tcp_lro_init_args [%d] failed\n",
2289 if (tcp_lro_init(lro)) {
2290 device_printf(ha->pci_dev,
2291 "%s: tcp_lro_init [%d] failed\n",
2295 #endif /* #if (__FreeBSD_version >= 1100101) */
2300 QL_DPRINT2(ha, (ha->pci_dev, "%s: LRO initialized\n", __func__));
2305 qla_drain_soft_lro(qla_host_t *ha)
2308 qla_hw_t *hw = &ha->hw;
2309 struct lro_ctrl *lro;
2311 for (i = 0; i < hw->num_sds_rings; i++) {
2312 lro = &hw->sds[i].lro;
2314 #if (__FreeBSD_version >= 1100101)
2315 tcp_lro_flush_all(lro);
2317 struct lro_entry *queued;
2319 while ((!SLIST_EMPTY(&lro->lro_active))) {
2320 queued = SLIST_FIRST(&lro->lro_active);
2321 SLIST_REMOVE_HEAD(&lro->lro_active, next);
2322 tcp_lro_flush(lro, queued);
2324 #endif /* #if (__FreeBSD_version >= 1100101) */
2331 qla_free_soft_lro(qla_host_t *ha)
2334 qla_hw_t *hw = &ha->hw;
2335 struct lro_ctrl *lro;
2337 for (i = 0; i < hw->num_sds_rings; i++) {
2338 lro = &hw->sds[i].lro;
2347 * Name: ql_del_hw_if
2348 * Function: Destroys the hardware specific entities corresponding to an
2349 * Ethernet Interface
2352 ql_del_hw_if(qla_host_t *ha)
2357 (void)qla_stop_nic_func(ha);
2359 qla_del_rcv_cntxt(ha);
2361 qla_del_xmt_cntxt(ha);
2363 if (ha->hw.flags.init_intr_cnxt) {
2364 for (i = 0; i < ha->hw.num_sds_rings; ) {
2366 if ((i + Q8_MAX_INTR_VECTORS) < ha->hw.num_sds_rings)
2367 num_msix = Q8_MAX_INTR_VECTORS;
2369 num_msix = ha->hw.num_sds_rings - i;
2370 qla_config_intr_cntxt(ha, i, num_msix, 0);
2375 ha->hw.flags.init_intr_cnxt = 0;
2378 if (ha->hw.enable_soft_lro) {
2379 qla_drain_soft_lro(ha);
2380 qla_free_soft_lro(ha);
2387 qla_confirm_9kb_enable(qla_host_t *ha)
2389 uint32_t supports_9kb = 0;
2391 ha->hw.mbx_intr_mask_offset = READ_REG32(ha, Q8_MBOX_INT_MASK_MSIX);
2393 /* Use MSI-X vector 0; Enable Firmware Mailbox Interrupt */
2394 WRITE_REG32(ha, Q8_MBOX_INT_ENABLE, BIT_2);
2395 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
2397 qla_get_nic_partition(ha, &supports_9kb, NULL);
2400 ha->hw.enable_9kb = 0;
2406 * Name: ql_init_hw_if
2407 * Function: Creates the hardware specific entities corresponding to an
2408 * Ethernet Interface - Transmit and Receive Contexts. Sets the MAC Address
2409 * corresponding to the interface. Enables LRO if allowed.
2412 ql_init_hw_if(qla_host_t *ha)
2416 uint8_t bcast_mac[6];
2422 for (i = 0; i < ha->hw.num_sds_rings; i++) {
2423 bzero(ha->hw.dma_buf.sds_ring[i].dma_b,
2424 ha->hw.dma_buf.sds_ring[i].size);
2427 for (i = 0; i < ha->hw.num_sds_rings; ) {
2429 if ((i + Q8_MAX_INTR_VECTORS) < ha->hw.num_sds_rings)
2430 num_msix = Q8_MAX_INTR_VECTORS;
2432 num_msix = ha->hw.num_sds_rings - i;
2434 if (qla_config_intr_cntxt(ha, i, num_msix, 1)) {
2440 for (i = 0; i < num_msix; ) {
2441 qla_config_intr_cntxt(ha, i,
2442 Q8_MAX_INTR_VECTORS, 0);
2443 i += Q8_MAX_INTR_VECTORS;
2452 ha->hw.flags.init_intr_cnxt = 1;
2455 * Create Receive Context
2457 if (qla_init_rcv_cntxt(ha)) {
2461 for (i = 0; i < ha->hw.num_rds_rings; i++) {
2462 rdesc = &ha->hw.rds[i];
2463 rdesc->rx_next = NUM_RX_DESCRIPTORS - 2;
2465 /* Update the RDS Producer Indices */
2466 QL_UPDATE_RDS_PRODUCER_INDEX(ha, rdesc->prod_std,\
2472 * Create Transmit Context
2474 if (qla_init_xmt_cntxt(ha)) {
2475 qla_del_rcv_cntxt(ha);
2478 ha->hw.max_tx_segs = 0;
2480 if (qla_config_mac_addr(ha, ha->hw.mac_addr, 1, 1))
2483 ha->hw.flags.unicast_mac = 1;
2485 bcast_mac[0] = 0xFF; bcast_mac[1] = 0xFF; bcast_mac[2] = 0xFF;
2486 bcast_mac[3] = 0xFF; bcast_mac[4] = 0xFF; bcast_mac[5] = 0xFF;
2488 if (qla_config_mac_addr(ha, bcast_mac, 1, 1))
2491 ha->hw.flags.bcast_mac = 1;
2494 * program any cached multicast addresses
2496 if (qla_hw_add_all_mcast(ha))
2499 if (qla_config_rss(ha, ha->hw.rcv_cntxt_id))
2502 if (qla_config_rss_ind_table(ha))
2505 if (qla_config_intr_coalesce(ha, ha->hw.rcv_cntxt_id, 0, 1))
2508 if (qla_link_event_req(ha, ha->hw.rcv_cntxt_id))
2511 if (ha->ifp->if_capenable & IFCAP_LRO) {
2512 if (ha->hw.enable_hw_lro) {
2513 ha->hw.enable_soft_lro = 0;
2515 if (qla_config_fw_lro(ha, ha->hw.rcv_cntxt_id))
2518 ha->hw.enable_soft_lro = 1;
2520 if (qla_config_soft_lro(ha))
2525 if (qla_init_nic_func(ha))
2528 if (qla_query_fw_dcbx_caps(ha))
2531 for (i = 0; i < ha->hw.num_sds_rings; i++)
2532 QL_ENABLE_INTERRUPTS(ha, i);
2538 qla_map_sds_to_rds(qla_host_t *ha, uint32_t start_idx, uint32_t num_idx)
2540 device_t dev = ha->pci_dev;
2541 q80_rq_map_sds_to_rds_t *map_rings;
2542 q80_rsp_map_sds_to_rds_t *map_rings_rsp;
2544 qla_hw_t *hw = &ha->hw;
2546 map_rings = (q80_rq_map_sds_to_rds_t *)ha->hw.mbox;
2547 bzero(map_rings, sizeof(q80_rq_map_sds_to_rds_t));
2549 map_rings->opcode = Q8_MBX_MAP_SDS_TO_RDS;
2550 map_rings->count_version = (sizeof (q80_rq_map_sds_to_rds_t) >> 2);
2551 map_rings->count_version |= Q8_MBX_CMD_VERSION;
2553 map_rings->cntxt_id = hw->rcv_cntxt_id;
2554 map_rings->num_rings = num_idx;
2556 for (i = 0; i < num_idx; i++) {
2557 map_rings->sds_rds[i].sds_ring = i + start_idx;
2558 map_rings->sds_rds[i].rds_ring = i + start_idx;
2561 if (qla_mbx_cmd(ha, (uint32_t *)map_rings,
2562 (sizeof (q80_rq_map_sds_to_rds_t) >> 2),
2563 ha->hw.mbox, (sizeof(q80_rsp_add_rcv_rings_t) >> 2), 0)) {
2564 device_printf(dev, "%s: failed0\n", __func__);
2568 map_rings_rsp = (q80_rsp_map_sds_to_rds_t *)ha->hw.mbox;
2570 err = Q8_MBX_RSP_STATUS(map_rings_rsp->regcnt_status);
2573 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
2581 * Name: qla_init_rcv_cntxt
2582 * Function: Creates the Receive Context.
2585 qla_init_rcv_cntxt(qla_host_t *ha)
2587 q80_rq_rcv_cntxt_t *rcntxt;
2588 q80_rsp_rcv_cntxt_t *rcntxt_rsp;
2589 q80_stat_desc_t *sdesc;
2591 qla_hw_t *hw = &ha->hw;
2594 uint32_t rcntxt_sds_rings;
2595 uint32_t rcntxt_rds_rings;
2601 * Create Receive Context
2604 for (i = 0; i < hw->num_sds_rings; i++) {
2605 sdesc = (q80_stat_desc_t *)&hw->sds[i].sds_ring_base[0];
2607 for (j = 0; j < NUM_STATUS_DESCRIPTORS; j++) {
2608 sdesc->data[0] = 1ULL;
2609 sdesc->data[1] = 1ULL;
2613 rcntxt_sds_rings = hw->num_sds_rings;
2614 if (hw->num_sds_rings > MAX_RCNTXT_SDS_RINGS)
2615 rcntxt_sds_rings = MAX_RCNTXT_SDS_RINGS;
2617 rcntxt_rds_rings = hw->num_rds_rings;
2619 if (hw->num_rds_rings > MAX_RDS_RING_SETS)
2620 rcntxt_rds_rings = MAX_RDS_RING_SETS;
2622 rcntxt = (q80_rq_rcv_cntxt_t *)ha->hw.mbox;
2623 bzero(rcntxt, (sizeof (q80_rq_rcv_cntxt_t)));
2625 rcntxt->opcode = Q8_MBX_CREATE_RX_CNTXT;
2626 rcntxt->count_version = (sizeof (q80_rq_rcv_cntxt_t) >> 2);
2627 rcntxt->count_version |= Q8_MBX_CMD_VERSION;
2629 rcntxt->cap0 = Q8_RCV_CNTXT_CAP0_BASEFW |
2630 Q8_RCV_CNTXT_CAP0_LRO |
2631 Q8_RCV_CNTXT_CAP0_HW_LRO |
2632 Q8_RCV_CNTXT_CAP0_RSS |
2633 Q8_RCV_CNTXT_CAP0_SGL_LRO;
2635 if (ha->hw.enable_9kb)
2636 rcntxt->cap0 |= Q8_RCV_CNTXT_CAP0_SINGLE_JUMBO;
2638 rcntxt->cap0 |= Q8_RCV_CNTXT_CAP0_SGL_JUMBO;
2640 if (ha->hw.num_rds_rings > 1) {
2641 rcntxt->nrds_sets_rings = rcntxt_rds_rings | (1 << 5);
2642 rcntxt->cap0 |= Q8_RCV_CNTXT_CAP0_MULTI_RDS;
2644 rcntxt->nrds_sets_rings = 0x1 | (1 << 5);
2646 rcntxt->nsds_rings = rcntxt_sds_rings;
2648 rcntxt->rds_producer_mode = Q8_RCV_CNTXT_RDS_PROD_MODE_UNIQUE;
2650 rcntxt->rcv_vpid = 0;
2652 for (i = 0; i < rcntxt_sds_rings; i++) {
2653 rcntxt->sds[i].paddr =
2654 qla_host_to_le64(hw->dma_buf.sds_ring[i].dma_addr);
2655 rcntxt->sds[i].size =
2656 qla_host_to_le32(NUM_STATUS_DESCRIPTORS);
2657 rcntxt->sds[i].intr_id = qla_host_to_le16(hw->intr_id[i]);
2658 rcntxt->sds[i].intr_src_bit = qla_host_to_le16(0);
2661 for (i = 0; i < rcntxt_rds_rings; i++) {
2662 rcntxt->rds[i].paddr_std =
2663 qla_host_to_le64(hw->dma_buf.rds_ring[i].dma_addr);
2665 if (ha->hw.enable_9kb)
2666 rcntxt->rds[i].std_bsize =
2667 qla_host_to_le64(MJUM9BYTES);
2669 rcntxt->rds[i].std_bsize = qla_host_to_le64(MCLBYTES);
2671 rcntxt->rds[i].std_nentries =
2672 qla_host_to_le32(NUM_RX_DESCRIPTORS);
2675 if (qla_mbx_cmd(ha, (uint32_t *)rcntxt,
2676 (sizeof (q80_rq_rcv_cntxt_t) >> 2),
2677 ha->hw.mbox, (sizeof(q80_rsp_rcv_cntxt_t) >> 2), 0)) {
2678 device_printf(dev, "%s: failed0\n", __func__);
2682 rcntxt_rsp = (q80_rsp_rcv_cntxt_t *)ha->hw.mbox;
2684 err = Q8_MBX_RSP_STATUS(rcntxt_rsp->regcnt_status);
2687 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
2691 for (i = 0; i < rcntxt_sds_rings; i++) {
2692 hw->sds[i].sds_consumer = rcntxt_rsp->sds_cons[i];
2695 for (i = 0; i < rcntxt_rds_rings; i++) {
2696 hw->rds[i].prod_std = rcntxt_rsp->rds[i].prod_std;
2699 hw->rcv_cntxt_id = rcntxt_rsp->cntxt_id;
2701 ha->hw.flags.init_rx_cnxt = 1;
2703 if (hw->num_sds_rings > MAX_RCNTXT_SDS_RINGS) {
2705 for (i = MAX_RCNTXT_SDS_RINGS; i < hw->num_sds_rings;) {
2707 if ((i + MAX_RCNTXT_SDS_RINGS) < hw->num_sds_rings)
2708 max_idx = MAX_RCNTXT_SDS_RINGS;
2710 max_idx = hw->num_sds_rings - i;
2712 err = qla_add_rcv_rings(ha, i, max_idx);
2720 if (hw->num_rds_rings > 1) {
2722 for (i = 0; i < hw->num_rds_rings; ) {
2724 if ((i + MAX_SDS_TO_RDS_MAP) < hw->num_rds_rings)
2725 max_idx = MAX_SDS_TO_RDS_MAP;
2727 max_idx = hw->num_rds_rings - i;
2729 err = qla_map_sds_to_rds(ha, i, max_idx);
2741 qla_add_rcv_rings(qla_host_t *ha, uint32_t sds_idx, uint32_t nsds)
2743 device_t dev = ha->pci_dev;
2744 q80_rq_add_rcv_rings_t *add_rcv;
2745 q80_rsp_add_rcv_rings_t *add_rcv_rsp;
2747 qla_hw_t *hw = &ha->hw;
2749 add_rcv = (q80_rq_add_rcv_rings_t *)ha->hw.mbox;
2750 bzero(add_rcv, sizeof (q80_rq_add_rcv_rings_t));
2752 add_rcv->opcode = Q8_MBX_ADD_RX_RINGS;
2753 add_rcv->count_version = (sizeof (q80_rq_add_rcv_rings_t) >> 2);
2754 add_rcv->count_version |= Q8_MBX_CMD_VERSION;
2756 add_rcv->nrds_sets_rings = nsds | (1 << 5);
2757 add_rcv->nsds_rings = nsds;
2758 add_rcv->cntxt_id = hw->rcv_cntxt_id;
2760 for (i = 0; i < nsds; i++) {
2764 add_rcv->sds[i].paddr =
2765 qla_host_to_le64(hw->dma_buf.sds_ring[j].dma_addr);
2767 add_rcv->sds[i].size =
2768 qla_host_to_le32(NUM_STATUS_DESCRIPTORS);
2770 add_rcv->sds[i].intr_id = qla_host_to_le16(hw->intr_id[j]);
2771 add_rcv->sds[i].intr_src_bit = qla_host_to_le16(0);
2775 for (i = 0; (i < nsds); i++) {
2778 add_rcv->rds[i].paddr_std =
2779 qla_host_to_le64(hw->dma_buf.rds_ring[j].dma_addr);
2781 if (ha->hw.enable_9kb)
2782 add_rcv->rds[i].std_bsize =
2783 qla_host_to_le64(MJUM9BYTES);
2785 add_rcv->rds[i].std_bsize = qla_host_to_le64(MCLBYTES);
2787 add_rcv->rds[i].std_nentries =
2788 qla_host_to_le32(NUM_RX_DESCRIPTORS);
2792 if (qla_mbx_cmd(ha, (uint32_t *)add_rcv,
2793 (sizeof (q80_rq_add_rcv_rings_t) >> 2),
2794 ha->hw.mbox, (sizeof(q80_rsp_add_rcv_rings_t) >> 2), 0)) {
2795 device_printf(dev, "%s: failed0\n", __func__);
2799 add_rcv_rsp = (q80_rsp_add_rcv_rings_t *)ha->hw.mbox;
2801 err = Q8_MBX_RSP_STATUS(add_rcv_rsp->regcnt_status);
2804 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
2808 for (i = 0; i < nsds; i++) {
2809 hw->sds[(i + sds_idx)].sds_consumer = add_rcv_rsp->sds_cons[i];
2812 for (i = 0; i < nsds; i++) {
2813 hw->rds[(i + sds_idx)].prod_std = add_rcv_rsp->rds[i].prod_std;
2820 * Name: qla_del_rcv_cntxt
2821 * Function: Destroys the Receive Context.
2824 qla_del_rcv_cntxt(qla_host_t *ha)
2826 device_t dev = ha->pci_dev;
2827 q80_rcv_cntxt_destroy_t *rcntxt;
2828 q80_rcv_cntxt_destroy_rsp_t *rcntxt_rsp;
2830 uint8_t bcast_mac[6];
2832 if (!ha->hw.flags.init_rx_cnxt)
2835 if (qla_hw_del_all_mcast(ha))
2838 if (ha->hw.flags.bcast_mac) {
2840 bcast_mac[0] = 0xFF; bcast_mac[1] = 0xFF; bcast_mac[2] = 0xFF;
2841 bcast_mac[3] = 0xFF; bcast_mac[4] = 0xFF; bcast_mac[5] = 0xFF;
2843 if (qla_config_mac_addr(ha, bcast_mac, 0, 1))
2845 ha->hw.flags.bcast_mac = 0;
2849 if (ha->hw.flags.unicast_mac) {
2850 if (qla_config_mac_addr(ha, ha->hw.mac_addr, 0, 1))
2852 ha->hw.flags.unicast_mac = 0;
2855 rcntxt = (q80_rcv_cntxt_destroy_t *)ha->hw.mbox;
2856 bzero(rcntxt, (sizeof (q80_rcv_cntxt_destroy_t)));
2858 rcntxt->opcode = Q8_MBX_DESTROY_RX_CNTXT;
2859 rcntxt->count_version = (sizeof (q80_rcv_cntxt_destroy_t) >> 2);
2860 rcntxt->count_version |= Q8_MBX_CMD_VERSION;
2862 rcntxt->cntxt_id = ha->hw.rcv_cntxt_id;
2864 if (qla_mbx_cmd(ha, (uint32_t *)rcntxt,
2865 (sizeof (q80_rcv_cntxt_destroy_t) >> 2),
2866 ha->hw.mbox, (sizeof(q80_rcv_cntxt_destroy_rsp_t) >> 2), 0)) {
2867 device_printf(dev, "%s: failed0\n", __func__);
2870 rcntxt_rsp = (q80_rcv_cntxt_destroy_rsp_t *)ha->hw.mbox;
2872 err = Q8_MBX_RSP_STATUS(rcntxt_rsp->regcnt_status);
2875 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
2878 ha->hw.flags.init_rx_cnxt = 0;
2883 * Name: qla_init_xmt_cntxt
2884 * Function: Creates the Transmit Context.
2887 qla_init_xmt_cntxt_i(qla_host_t *ha, uint32_t txr_idx)
2890 qla_hw_t *hw = &ha->hw;
2891 q80_rq_tx_cntxt_t *tcntxt;
2892 q80_rsp_tx_cntxt_t *tcntxt_rsp;
2894 qla_hw_tx_cntxt_t *hw_tx_cntxt;
2897 hw_tx_cntxt = &hw->tx_cntxt[txr_idx];
2902 * Create Transmit Context
2904 tcntxt = (q80_rq_tx_cntxt_t *)ha->hw.mbox;
2905 bzero(tcntxt, (sizeof (q80_rq_tx_cntxt_t)));
2907 tcntxt->opcode = Q8_MBX_CREATE_TX_CNTXT;
2908 tcntxt->count_version = (sizeof (q80_rq_tx_cntxt_t) >> 2);
2909 tcntxt->count_version |= Q8_MBX_CMD_VERSION;
2913 #ifdef QL_ENABLE_ISCSI_TLV
2915 tcntxt->cap0 = Q8_TX_CNTXT_CAP0_BASEFW | Q8_TX_CNTXT_CAP0_LSO |
2916 Q8_TX_CNTXT_CAP0_TC;
2918 if (txr_idx >= (ha->hw.num_tx_rings >> 1)) {
2919 tcntxt->traffic_class = 1;
2922 intr_idx = txr_idx % (ha->hw.num_tx_rings >> 1);
2925 tcntxt->cap0 = Q8_TX_CNTXT_CAP0_BASEFW | Q8_TX_CNTXT_CAP0_LSO;
2927 #endif /* #ifdef QL_ENABLE_ISCSI_TLV */
2929 tcntxt->ntx_rings = 1;
2931 tcntxt->tx_ring[0].paddr =
2932 qla_host_to_le64(hw_tx_cntxt->tx_ring_paddr);
2933 tcntxt->tx_ring[0].tx_consumer =
2934 qla_host_to_le64(hw_tx_cntxt->tx_cons_paddr);
2935 tcntxt->tx_ring[0].nentries = qla_host_to_le16(NUM_TX_DESCRIPTORS);
2937 tcntxt->tx_ring[0].intr_id = qla_host_to_le16(hw->intr_id[intr_idx]);
2938 tcntxt->tx_ring[0].intr_src_bit = qla_host_to_le16(0);
2940 hw_tx_cntxt->txr_free = NUM_TX_DESCRIPTORS;
2941 hw_tx_cntxt->txr_next = hw_tx_cntxt->txr_comp = 0;
2943 if (qla_mbx_cmd(ha, (uint32_t *)tcntxt,
2944 (sizeof (q80_rq_tx_cntxt_t) >> 2),
2946 (sizeof(q80_rsp_tx_cntxt_t) >> 2), 0)) {
2947 device_printf(dev, "%s: failed0\n", __func__);
2950 tcntxt_rsp = (q80_rsp_tx_cntxt_t *)ha->hw.mbox;
2952 err = Q8_MBX_RSP_STATUS(tcntxt_rsp->regcnt_status);
2955 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
2959 hw_tx_cntxt->tx_prod_reg = tcntxt_rsp->tx_ring[0].prod_index;
2960 hw_tx_cntxt->tx_cntxt_id = tcntxt_rsp->tx_ring[0].cntxt_id;
2962 if (qla_config_intr_coalesce(ha, hw_tx_cntxt->tx_cntxt_id, 0, 0))
2970 * Name: qla_del_xmt_cntxt
2971 * Function: Destroys the Transmit Context.
2974 qla_del_xmt_cntxt_i(qla_host_t *ha, uint32_t txr_idx)
2976 device_t dev = ha->pci_dev;
2977 q80_tx_cntxt_destroy_t *tcntxt;
2978 q80_tx_cntxt_destroy_rsp_t *tcntxt_rsp;
2981 tcntxt = (q80_tx_cntxt_destroy_t *)ha->hw.mbox;
2982 bzero(tcntxt, (sizeof (q80_tx_cntxt_destroy_t)));
2984 tcntxt->opcode = Q8_MBX_DESTROY_TX_CNTXT;
2985 tcntxt->count_version = (sizeof (q80_tx_cntxt_destroy_t) >> 2);
2986 tcntxt->count_version |= Q8_MBX_CMD_VERSION;
2988 tcntxt->cntxt_id = ha->hw.tx_cntxt[txr_idx].tx_cntxt_id;
2990 if (qla_mbx_cmd(ha, (uint32_t *)tcntxt,
2991 (sizeof (q80_tx_cntxt_destroy_t) >> 2),
2992 ha->hw.mbox, (sizeof (q80_tx_cntxt_destroy_rsp_t) >> 2), 0)) {
2993 device_printf(dev, "%s: failed0\n", __func__);
2996 tcntxt_rsp = (q80_tx_cntxt_destroy_rsp_t *)ha->hw.mbox;
2998 err = Q8_MBX_RSP_STATUS(tcntxt_rsp->regcnt_status);
3001 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
3008 qla_del_xmt_cntxt(qla_host_t *ha)
3012 if (!ha->hw.flags.init_tx_cnxt)
3015 for (i = 0; i < ha->hw.num_tx_rings; i++) {
3016 if (qla_del_xmt_cntxt_i(ha, i))
3019 ha->hw.flags.init_tx_cnxt = 0;
3023 qla_init_xmt_cntxt(qla_host_t *ha)
3027 for (i = 0; i < ha->hw.num_tx_rings; i++) {
3028 if (qla_init_xmt_cntxt_i(ha, i) != 0) {
3029 for (j = 0; j < i; j++)
3030 qla_del_xmt_cntxt_i(ha, j);
3034 ha->hw.flags.init_tx_cnxt = 1;
3039 qla_hw_all_mcast(qla_host_t *ha, uint32_t add_mcast)
3045 nmcast = ha->hw.nmcast;
3047 QL_DPRINT2(ha, (ha->pci_dev,
3048 "%s:[0x%x] enter nmcast = %d \n", __func__, add_mcast, nmcast));
3050 mcast = ha->hw.mac_addr_arr;
3051 memset(mcast, 0, (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN));
3053 for (i = 0 ; ((i < Q8_MAX_NUM_MULTICAST_ADDRS) && nmcast); i++) {
3054 if ((ha->hw.mcast[i].addr[0] != 0) ||
3055 (ha->hw.mcast[i].addr[1] != 0) ||
3056 (ha->hw.mcast[i].addr[2] != 0) ||
3057 (ha->hw.mcast[i].addr[3] != 0) ||
3058 (ha->hw.mcast[i].addr[4] != 0) ||
3059 (ha->hw.mcast[i].addr[5] != 0)) {
3061 bcopy(ha->hw.mcast[i].addr, mcast, ETHER_ADDR_LEN);
3062 mcast = mcast + ETHER_ADDR_LEN;
3065 if (count == Q8_MAX_MAC_ADDRS) {
3066 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr,
3067 add_mcast, count)) {
3068 device_printf(ha->pci_dev,
3069 "%s: failed\n", __func__);
3074 mcast = ha->hw.mac_addr_arr;
3076 (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN));
3084 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr, add_mcast,
3086 device_printf(ha->pci_dev, "%s: failed\n", __func__);
3090 QL_DPRINT2(ha, (ha->pci_dev,
3091 "%s:[0x%x] exit nmcast = %d \n", __func__, add_mcast, nmcast));
3097 qla_hw_add_all_mcast(qla_host_t *ha)
3101 ret = qla_hw_all_mcast(ha, 1);
3107 qla_hw_del_all_mcast(qla_host_t *ha)
3111 ret = qla_hw_all_mcast(ha, 0);
3113 bzero(ha->hw.mcast, (sizeof (qla_mcast_t) * Q8_MAX_NUM_MULTICAST_ADDRS));
3120 qla_hw_mac_addr_present(qla_host_t *ha, uint8_t *mta)
3124 for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) {
3125 if (QL_MAC_CMP(ha->hw.mcast[i].addr, mta) == 0)
3126 return (0); /* its been already added */
3132 qla_hw_add_mcast(qla_host_t *ha, uint8_t *mta, uint32_t nmcast)
3136 for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) {
3138 if ((ha->hw.mcast[i].addr[0] == 0) &&
3139 (ha->hw.mcast[i].addr[1] == 0) &&
3140 (ha->hw.mcast[i].addr[2] == 0) &&
3141 (ha->hw.mcast[i].addr[3] == 0) &&
3142 (ha->hw.mcast[i].addr[4] == 0) &&
3143 (ha->hw.mcast[i].addr[5] == 0)) {
3145 bcopy(mta, ha->hw.mcast[i].addr, Q8_MAC_ADDR_LEN);
3148 mta = mta + ETHER_ADDR_LEN;
3160 qla_hw_del_mcast(qla_host_t *ha, uint8_t *mta, uint32_t nmcast)
3164 for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) {
3165 if (QL_MAC_CMP(ha->hw.mcast[i].addr, mta) == 0) {
3167 ha->hw.mcast[i].addr[0] = 0;
3168 ha->hw.mcast[i].addr[1] = 0;
3169 ha->hw.mcast[i].addr[2] = 0;
3170 ha->hw.mcast[i].addr[3] = 0;
3171 ha->hw.mcast[i].addr[4] = 0;
3172 ha->hw.mcast[i].addr[5] = 0;
3176 mta = mta + ETHER_ADDR_LEN;
3187 * Name: ql_hw_set_multi
3188 * Function: Sets the Multicast Addresses provided by the host O.S into the
3189 * hardware (for the given interface)
3192 ql_hw_set_multi(qla_host_t *ha, uint8_t *mcast_addr, uint32_t mcnt,
3195 uint8_t *mta = mcast_addr;
3201 mcast = ha->hw.mac_addr_arr;
3202 memset(mcast, 0, (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN));
3204 for (i = 0; i < mcnt; i++) {
3205 if (mta[0] || mta[1] || mta[2] || mta[3] || mta[4] || mta[5]) {
3207 if (qla_hw_mac_addr_present(ha, mta) != 0) {
3208 bcopy(mta, mcast, ETHER_ADDR_LEN);
3209 mcast = mcast + ETHER_ADDR_LEN;
3213 if (qla_hw_mac_addr_present(ha, mta) == 0) {
3214 bcopy(mta, mcast, ETHER_ADDR_LEN);
3215 mcast = mcast + ETHER_ADDR_LEN;
3220 if (count == Q8_MAX_MAC_ADDRS) {
3221 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr,
3223 device_printf(ha->pci_dev, "%s: failed\n",
3229 qla_hw_add_mcast(ha, ha->hw.mac_addr_arr,
3232 qla_hw_del_mcast(ha, ha->hw.mac_addr_arr,
3237 mcast = ha->hw.mac_addr_arr;
3238 memset(mcast, 0, (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN));
3241 mta += Q8_MAC_ADDR_LEN;
3245 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr, add_mac,
3247 device_printf(ha->pci_dev, "%s: failed\n", __func__);
3251 qla_hw_add_mcast(ha, ha->hw.mac_addr_arr, count);
3253 qla_hw_del_mcast(ha, ha->hw.mac_addr_arr, count);
3261 * Name: ql_hw_tx_done_locked
3262 * Function: Handle Transmit Completions
3265 ql_hw_tx_done_locked(qla_host_t *ha, uint32_t txr_idx)
3268 qla_hw_t *hw = &ha->hw;
3269 uint32_t comp_idx, comp_count = 0;
3270 qla_hw_tx_cntxt_t *hw_tx_cntxt;
3272 hw_tx_cntxt = &hw->tx_cntxt[txr_idx];
3274 /* retrieve index of last entry in tx ring completed */
3275 comp_idx = qla_le32_to_host(*(hw_tx_cntxt->tx_cons));
3277 while (comp_idx != hw_tx_cntxt->txr_comp) {
3279 txb = &ha->tx_ring[txr_idx].tx_buf[hw_tx_cntxt->txr_comp];
3281 hw_tx_cntxt->txr_comp++;
3282 if (hw_tx_cntxt->txr_comp == NUM_TX_DESCRIPTORS)
3283 hw_tx_cntxt->txr_comp = 0;
3288 ha->ifp->if_opackets++;
3290 bus_dmamap_sync(ha->tx_tag, txb->map,
3291 BUS_DMASYNC_POSTWRITE);
3292 bus_dmamap_unload(ha->tx_tag, txb->map);
3293 m_freem(txb->m_head);
3299 hw_tx_cntxt->txr_free += comp_count;
3304 ql_update_link_state(qla_host_t *ha)
3306 uint32_t link_state;
3307 uint32_t prev_link_state;
3309 if (!(ha->ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3313 link_state = READ_REG32(ha, Q8_LINK_STATE);
3315 prev_link_state = ha->hw.link_up;
3317 if (ha->pci_func == 0)
3318 ha->hw.link_up = (((link_state & 0xF) == 1)? 1 : 0);
3320 ha->hw.link_up = ((((link_state >> 4)& 0xF) == 1)? 1 : 0);
3322 if (prev_link_state != ha->hw.link_up) {
3323 if (ha->hw.link_up) {
3324 if_link_state_change(ha->ifp, LINK_STATE_UP);
3326 if_link_state_change(ha->ifp, LINK_STATE_DOWN);
3333 ql_hw_stop_rcv(qla_host_t *ha)
3335 int i, done, count = 100;
3337 ha->flags.stop_rcv = 1;
3341 for (i = 0; i < ha->hw.num_sds_rings; i++) {
3342 if (ha->hw.sds[i].rcv_active)
3348 qla_mdelay(__func__, 10);
3352 device_printf(ha->pci_dev, "%s: Counter expired.\n", __func__);
3358 ql_hw_check_health(qla_host_t *ha)
3362 ha->hw.health_count++;
3364 if (ha->hw.health_count < 1000)
3367 ha->hw.health_count = 0;
3369 val = READ_REG32(ha, Q8_ASIC_TEMPERATURE);
3371 if (((val & 0xFFFF) == 2) || ((val & 0xFFFF) == 3) ||
3372 (QL_ERR_INJECT(ha, INJCT_TEMPERATURE_FAILURE))) {
3373 device_printf(ha->pci_dev, "%s: Temperature Alert [0x%08x]\n",
3378 val = READ_REG32(ha, Q8_FIRMWARE_HEARTBEAT);
3380 if ((val != ha->hw.hbeat_value) &&
3381 (!(QL_ERR_INJECT(ha, INJCT_HEARTBEAT_FAILURE)))) {
3382 ha->hw.hbeat_value = val;
3385 device_printf(ha->pci_dev, "%s: Heartbeat Failue [0x%08x]\n",
3392 qla_init_nic_func(qla_host_t *ha)
3395 q80_init_nic_func_t *init_nic;
3396 q80_init_nic_func_rsp_t *init_nic_rsp;
3401 init_nic = (q80_init_nic_func_t *)ha->hw.mbox;
3402 bzero(init_nic, sizeof(q80_init_nic_func_t));
3404 init_nic->opcode = Q8_MBX_INIT_NIC_FUNC;
3405 init_nic->count_version = (sizeof (q80_init_nic_func_t) >> 2);
3406 init_nic->count_version |= Q8_MBX_CMD_VERSION;
3408 init_nic->options = Q8_INIT_NIC_REG_DCBX_CHNG_AEN;
3409 init_nic->options |= Q8_INIT_NIC_REG_SFP_CHNG_AEN;
3410 init_nic->options |= Q8_INIT_NIC_REG_IDC_AEN;
3412 //qla_dump_buf8(ha, __func__, init_nic, sizeof (q80_init_nic_func_t));
3413 if (qla_mbx_cmd(ha, (uint32_t *)init_nic,
3414 (sizeof (q80_init_nic_func_t) >> 2),
3415 ha->hw.mbox, (sizeof (q80_init_nic_func_rsp_t) >> 2), 0)) {
3416 device_printf(dev, "%s: failed\n", __func__);
3420 init_nic_rsp = (q80_init_nic_func_rsp_t *)ha->hw.mbox;
3421 // qla_dump_buf8(ha, __func__, init_nic_rsp, sizeof (q80_init_nic_func_rsp_t));
3423 err = Q8_MBX_RSP_STATUS(init_nic_rsp->regcnt_status);
3426 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
3433 qla_stop_nic_func(qla_host_t *ha)
3436 q80_stop_nic_func_t *stop_nic;
3437 q80_stop_nic_func_rsp_t *stop_nic_rsp;
3442 stop_nic = (q80_stop_nic_func_t *)ha->hw.mbox;
3443 bzero(stop_nic, sizeof(q80_stop_nic_func_t));
3445 stop_nic->opcode = Q8_MBX_STOP_NIC_FUNC;
3446 stop_nic->count_version = (sizeof (q80_stop_nic_func_t) >> 2);
3447 stop_nic->count_version |= Q8_MBX_CMD_VERSION;
3449 stop_nic->options = Q8_STOP_NIC_DEREG_DCBX_CHNG_AEN;
3450 stop_nic->options |= Q8_STOP_NIC_DEREG_SFP_CHNG_AEN;
3452 //qla_dump_buf8(ha, __func__, stop_nic, sizeof (q80_stop_nic_func_t));
3453 if (qla_mbx_cmd(ha, (uint32_t *)stop_nic,
3454 (sizeof (q80_stop_nic_func_t) >> 2),
3455 ha->hw.mbox, (sizeof (q80_stop_nic_func_rsp_t) >> 2), 0)) {
3456 device_printf(dev, "%s: failed\n", __func__);
3460 stop_nic_rsp = (q80_stop_nic_func_rsp_t *)ha->hw.mbox;
3461 //qla_dump_buf8(ha, __func__, stop_nic_rsp, sizeof (q80_stop_nic_func_rsp_ t));
3463 err = Q8_MBX_RSP_STATUS(stop_nic_rsp->regcnt_status);
3466 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
3473 qla_query_fw_dcbx_caps(qla_host_t *ha)
3476 q80_query_fw_dcbx_caps_t *fw_dcbx;
3477 q80_query_fw_dcbx_caps_rsp_t *fw_dcbx_rsp;
3482 fw_dcbx = (q80_query_fw_dcbx_caps_t *)ha->hw.mbox;
3483 bzero(fw_dcbx, sizeof(q80_query_fw_dcbx_caps_t));
3485 fw_dcbx->opcode = Q8_MBX_GET_FW_DCBX_CAPS;
3486 fw_dcbx->count_version = (sizeof (q80_query_fw_dcbx_caps_t) >> 2);
3487 fw_dcbx->count_version |= Q8_MBX_CMD_VERSION;
3489 ql_dump_buf8(ha, __func__, fw_dcbx, sizeof (q80_query_fw_dcbx_caps_t));
3490 if (qla_mbx_cmd(ha, (uint32_t *)fw_dcbx,
3491 (sizeof (q80_query_fw_dcbx_caps_t) >> 2),
3492 ha->hw.mbox, (sizeof (q80_query_fw_dcbx_caps_rsp_t) >> 2), 0)) {
3493 device_printf(dev, "%s: failed\n", __func__);
3497 fw_dcbx_rsp = (q80_query_fw_dcbx_caps_rsp_t *)ha->hw.mbox;
3498 ql_dump_buf8(ha, __func__, fw_dcbx_rsp,
3499 sizeof (q80_query_fw_dcbx_caps_rsp_t));
3501 err = Q8_MBX_RSP_STATUS(fw_dcbx_rsp->regcnt_status);
3504 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
3511 qla_idc_ack(qla_host_t *ha, uint32_t aen_mb1, uint32_t aen_mb2,
3512 uint32_t aen_mb3, uint32_t aen_mb4)
3515 q80_idc_ack_t *idc_ack;
3516 q80_idc_ack_rsp_t *idc_ack_rsp;
3522 idc_ack = (q80_idc_ack_t *)ha->hw.mbox;
3523 bzero(idc_ack, sizeof(q80_idc_ack_t));
3525 idc_ack->opcode = Q8_MBX_IDC_ACK;
3526 idc_ack->count_version = (sizeof (q80_idc_ack_t) >> 2);
3527 idc_ack->count_version |= Q8_MBX_CMD_VERSION;
3529 idc_ack->aen_mb1 = aen_mb1;
3530 idc_ack->aen_mb2 = aen_mb2;
3531 idc_ack->aen_mb3 = aen_mb3;
3532 idc_ack->aen_mb4 = aen_mb4;
3534 ha->hw.imd_compl= 0;
3536 if (qla_mbx_cmd(ha, (uint32_t *)idc_ack,
3537 (sizeof (q80_idc_ack_t) >> 2),
3538 ha->hw.mbox, (sizeof (q80_idc_ack_rsp_t) >> 2), 0)) {
3539 device_printf(dev, "%s: failed\n", __func__);
3543 idc_ack_rsp = (q80_idc_ack_rsp_t *)ha->hw.mbox;
3545 err = Q8_MBX_RSP_STATUS(idc_ack_rsp->regcnt_status);
3548 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
3552 while (count && !ha->hw.imd_compl) {
3553 qla_mdelay(__func__, 100);
3560 device_printf(dev, "%s: count %d\n", __func__, count);
3566 qla_set_port_config(qla_host_t *ha, uint32_t cfg_bits)
3569 q80_set_port_cfg_t *pcfg;
3570 q80_set_port_cfg_rsp_t *pfg_rsp;
3576 pcfg = (q80_set_port_cfg_t *)ha->hw.mbox;
3577 bzero(pcfg, sizeof(q80_set_port_cfg_t));
3579 pcfg->opcode = Q8_MBX_SET_PORT_CONFIG;
3580 pcfg->count_version = (sizeof (q80_set_port_cfg_t) >> 2);
3581 pcfg->count_version |= Q8_MBX_CMD_VERSION;
3583 pcfg->cfg_bits = cfg_bits;
3585 device_printf(dev, "%s: cfg_bits"
3586 " [STD_PAUSE_DIR, PAUSE_TYPE, DCBX]"
3587 " [0x%x, 0x%x, 0x%x]\n", __func__,
3588 ((cfg_bits & Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK)>>20),
3589 ((cfg_bits & Q8_PORT_CFG_BITS_PAUSE_CFG_MASK) >> 5),
3590 ((cfg_bits & Q8_PORT_CFG_BITS_DCBX_ENABLE) ? 1: 0));
3592 ha->hw.imd_compl= 0;
3594 if (qla_mbx_cmd(ha, (uint32_t *)pcfg,
3595 (sizeof (q80_set_port_cfg_t) >> 2),
3596 ha->hw.mbox, (sizeof (q80_set_port_cfg_rsp_t) >> 2), 0)) {
3597 device_printf(dev, "%s: failed\n", __func__);
3601 pfg_rsp = (q80_set_port_cfg_rsp_t *)ha->hw.mbox;
3603 err = Q8_MBX_RSP_STATUS(pfg_rsp->regcnt_status);
3605 if (err == Q8_MBX_RSP_IDC_INTRMD_RSP) {
3606 while (count && !ha->hw.imd_compl) {
3607 qla_mdelay(__func__, 100);
3611 device_printf(dev, "%s: count %d\n", __func__, count);
3618 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
3627 qla_get_minidump_tmplt_size(qla_host_t *ha, uint32_t *size)
3630 device_t dev = ha->pci_dev;
3631 q80_config_md_templ_size_t *md_size;
3632 q80_config_md_templ_size_rsp_t *md_size_rsp;
3634 #ifndef QL_LDFLASH_FW
3636 ql_minidump_template_hdr_t *hdr;
3638 hdr = (ql_minidump_template_hdr_t *)ql83xx_minidump;
3639 *size = hdr->size_of_template;
3642 #endif /* #ifdef QL_LDFLASH_FW */
3644 md_size = (q80_config_md_templ_size_t *) ha->hw.mbox;
3645 bzero(md_size, sizeof(q80_config_md_templ_size_t));
3647 md_size->opcode = Q8_MBX_GET_MINIDUMP_TMPLT_SIZE;
3648 md_size->count_version = (sizeof (q80_config_md_templ_size_t) >> 2);
3649 md_size->count_version |= Q8_MBX_CMD_VERSION;
3651 if (qla_mbx_cmd(ha, (uint32_t *) md_size,
3652 (sizeof(q80_config_md_templ_size_t) >> 2), ha->hw.mbox,
3653 (sizeof(q80_config_md_templ_size_rsp_t) >> 2), 0)) {
3655 device_printf(dev, "%s: failed\n", __func__);
3660 md_size_rsp = (q80_config_md_templ_size_rsp_t *) ha->hw.mbox;
3662 err = Q8_MBX_RSP_STATUS(md_size_rsp->regcnt_status);
3665 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
3669 *size = md_size_rsp->templ_size;
3675 qla_get_port_config(qla_host_t *ha, uint32_t *cfg_bits)
3678 q80_get_port_cfg_t *pcfg;
3679 q80_get_port_cfg_rsp_t *pcfg_rsp;
3684 pcfg = (q80_get_port_cfg_t *)ha->hw.mbox;
3685 bzero(pcfg, sizeof(q80_get_port_cfg_t));
3687 pcfg->opcode = Q8_MBX_GET_PORT_CONFIG;
3688 pcfg->count_version = (sizeof (q80_get_port_cfg_t) >> 2);
3689 pcfg->count_version |= Q8_MBX_CMD_VERSION;
3691 if (qla_mbx_cmd(ha, (uint32_t *)pcfg,
3692 (sizeof (q80_get_port_cfg_t) >> 2),
3693 ha->hw.mbox, (sizeof (q80_get_port_cfg_rsp_t) >> 2), 0)) {
3694 device_printf(dev, "%s: failed\n", __func__);
3698 pcfg_rsp = (q80_get_port_cfg_rsp_t *)ha->hw.mbox;
3700 err = Q8_MBX_RSP_STATUS(pcfg_rsp->regcnt_status);
3703 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
3707 device_printf(dev, "%s: [cfg_bits, port type]"
3708 " [0x%08x, 0x%02x] [STD_PAUSE_DIR, PAUSE_TYPE, DCBX]"
3709 " [0x%x, 0x%x, 0x%x]\n", __func__,
3710 pcfg_rsp->cfg_bits, pcfg_rsp->phys_port_type,
3711 ((pcfg_rsp->cfg_bits & Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK)>>20),
3712 ((pcfg_rsp->cfg_bits & Q8_PORT_CFG_BITS_PAUSE_CFG_MASK) >> 5),
3713 ((pcfg_rsp->cfg_bits & Q8_PORT_CFG_BITS_DCBX_ENABLE) ? 1: 0)
3716 *cfg_bits = pcfg_rsp->cfg_bits;
3722 ql_iscsi_pdu(qla_host_t *ha, struct mbuf *mp)
3724 struct ether_vlan_header *eh;
3726 struct ip *ip = NULL;
3727 struct ip6_hdr *ip6 = NULL;
3728 struct tcphdr *th = NULL;
3731 uint8_t buf[sizeof(struct ip6_hdr)];
3733 eh = mtod(mp, struct ether_vlan_header *);
3735 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3736 hdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3737 etype = ntohs(eh->evl_proto);
3739 hdrlen = ETHER_HDR_LEN;
3740 etype = ntohs(eh->evl_encap_proto);
3743 if (etype == ETHERTYPE_IP) {
3745 offset = (hdrlen + sizeof (struct ip));
3747 if (mp->m_len >= offset) {
3748 ip = (struct ip *)(mp->m_data + hdrlen);
3750 m_copydata(mp, hdrlen, sizeof (struct ip), buf);
3751 ip = (struct ip *)buf;
3754 if (ip->ip_p == IPPROTO_TCP) {
3756 hdrlen += ip->ip_hl << 2;
3757 offset = hdrlen + 4;
3759 if (mp->m_len >= offset) {
3760 th = (struct tcphdr *)(mp->m_data + hdrlen);;
3762 m_copydata(mp, hdrlen, 4, buf);
3763 th = (struct tcphdr *)buf;
3767 } else if (etype == ETHERTYPE_IPV6) {
3769 offset = (hdrlen + sizeof (struct ip6_hdr));
3771 if (mp->m_len >= offset) {
3772 ip6 = (struct ip6_hdr *)(mp->m_data + hdrlen);
3774 m_copydata(mp, hdrlen, sizeof (struct ip6_hdr), buf);
3775 ip6 = (struct ip6_hdr *)buf;
3778 if (ip6->ip6_nxt == IPPROTO_TCP) {
3780 hdrlen += sizeof(struct ip6_hdr);
3781 offset = hdrlen + 4;
3783 if (mp->m_len >= offset) {
3784 th = (struct tcphdr *)(mp->m_data + hdrlen);;
3786 m_copydata(mp, hdrlen, 4, buf);
3787 th = (struct tcphdr *)buf;
3793 if ((th->th_sport == htons(3260)) ||
3794 (th->th_dport == htons(3260)))
3801 qla_hw_async_event(qla_host_t *ha)
3803 switch (ha->hw.aen_mb0) {
3805 (void)qla_idc_ack(ha, ha->hw.aen_mb1, ha->hw.aen_mb2,
3806 ha->hw.aen_mb3, ha->hw.aen_mb4);
3817 #ifdef QL_LDFLASH_FW
3819 ql_get_minidump_template(qla_host_t *ha)
3822 device_t dev = ha->pci_dev;
3823 q80_config_md_templ_cmd_t *md_templ;
3824 q80_config_md_templ_cmd_rsp_t *md_templ_rsp;
3826 md_templ = (q80_config_md_templ_cmd_t *) ha->hw.mbox;
3827 bzero(md_templ, (sizeof (q80_config_md_templ_cmd_t)));
3829 md_templ->opcode = Q8_MBX_GET_MINIDUMP_TMPLT;
3830 md_templ->count_version = ( sizeof(q80_config_md_templ_cmd_t) >> 2);
3831 md_templ->count_version |= Q8_MBX_CMD_VERSION;
3833 md_templ->buf_addr = ha->hw.dma_buf.minidump.dma_addr;
3834 md_templ->buff_size = ha->hw.dma_buf.minidump.size;
3836 if (qla_mbx_cmd(ha, (uint32_t *) md_templ,
3837 (sizeof(q80_config_md_templ_cmd_t) >> 2),
3839 (sizeof(q80_config_md_templ_cmd_rsp_t) >> 2), 0)) {
3841 device_printf(dev, "%s: failed\n", __func__);
3846 md_templ_rsp = (q80_config_md_templ_cmd_rsp_t *) ha->hw.mbox;
3848 err = Q8_MBX_RSP_STATUS(md_templ_rsp->regcnt_status);
3851 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
3858 #endif /* #ifdef QL_LDFLASH_FW */
3861 * Minidump related functionality
3864 static int ql_parse_template(qla_host_t *ha);
3866 static uint32_t ql_rdcrb(qla_host_t *ha,
3867 ql_minidump_entry_rdcrb_t *crb_entry,
3868 uint32_t * data_buff);
3870 static uint32_t ql_pollrd(qla_host_t *ha,
3871 ql_minidump_entry_pollrd_t *entry,
3872 uint32_t * data_buff);
3874 static uint32_t ql_pollrd_modify_write(qla_host_t *ha,
3875 ql_minidump_entry_rd_modify_wr_with_poll_t *entry,
3876 uint32_t *data_buff);
3878 static uint32_t ql_L2Cache(qla_host_t *ha,
3879 ql_minidump_entry_cache_t *cacheEntry,
3880 uint32_t * data_buff);
3882 static uint32_t ql_L1Cache(qla_host_t *ha,
3883 ql_minidump_entry_cache_t *cacheEntry,
3884 uint32_t *data_buff);
3886 static uint32_t ql_rdocm(qla_host_t *ha,
3887 ql_minidump_entry_rdocm_t *ocmEntry,
3888 uint32_t *data_buff);
3890 static uint32_t ql_rdmem(qla_host_t *ha,
3891 ql_minidump_entry_rdmem_t *mem_entry,
3892 uint32_t *data_buff);
3894 static uint32_t ql_rdrom(qla_host_t *ha,
3895 ql_minidump_entry_rdrom_t *romEntry,
3896 uint32_t *data_buff);
3898 static uint32_t ql_rdmux(qla_host_t *ha,
3899 ql_minidump_entry_mux_t *muxEntry,
3900 uint32_t *data_buff);
3902 static uint32_t ql_rdmux2(qla_host_t *ha,
3903 ql_minidump_entry_mux2_t *muxEntry,
3904 uint32_t *data_buff);
3906 static uint32_t ql_rdqueue(qla_host_t *ha,
3907 ql_minidump_entry_queue_t *queueEntry,
3908 uint32_t *data_buff);
3910 static uint32_t ql_cntrl(qla_host_t *ha,
3911 ql_minidump_template_hdr_t *template_hdr,
3912 ql_minidump_entry_cntrl_t *crbEntry);
3916 ql_minidump_size(qla_host_t *ha)
3920 ql_minidump_template_hdr_t *hdr;
3922 hdr = (ql_minidump_template_hdr_t *)ha->hw.dma_buf.minidump.dma_b;
3926 for (k = 1; k < QL_DBG_CAP_SIZE_ARRAY_LEN; k++) {
3927 if (i & ha->hw.mdump_capture_mask)
3928 size += hdr->capture_size_array[k];
3935 ql_free_minidump_buffer(qla_host_t *ha)
3937 if (ha->hw.mdump_buffer != NULL) {
3938 free(ha->hw.mdump_buffer, M_QLA83XXBUF);
3939 ha->hw.mdump_buffer = NULL;
3940 ha->hw.mdump_buffer_size = 0;
3946 ql_alloc_minidump_buffer(qla_host_t *ha)
3948 ha->hw.mdump_buffer_size = ql_minidump_size(ha);
3950 if (!ha->hw.mdump_buffer_size)
3953 ha->hw.mdump_buffer = malloc(ha->hw.mdump_buffer_size, M_QLA83XXBUF,
3956 if (ha->hw.mdump_buffer == NULL)
3963 ql_free_minidump_template_buffer(qla_host_t *ha)
3965 if (ha->hw.mdump_template != NULL) {
3966 free(ha->hw.mdump_template, M_QLA83XXBUF);
3967 ha->hw.mdump_template = NULL;
3968 ha->hw.mdump_template_size = 0;
3974 ql_alloc_minidump_template_buffer(qla_host_t *ha)
3976 ha->hw.mdump_template_size = ha->hw.dma_buf.minidump.size;
3978 ha->hw.mdump_template = malloc(ha->hw.mdump_template_size,
3979 M_QLA83XXBUF, M_NOWAIT);
3981 if (ha->hw.mdump_template == NULL)
3988 ql_alloc_minidump_buffers(qla_host_t *ha)
3992 ret = ql_alloc_minidump_template_buffer(ha);
3997 ret = ql_alloc_minidump_buffer(ha);
4000 ql_free_minidump_template_buffer(ha);
4007 ql_validate_minidump_checksum(qla_host_t *ha)
4011 uint32_t *template_buff;
4013 count = ha->hw.dma_buf.minidump.size / sizeof (uint32_t);
4014 template_buff = ha->hw.dma_buf.minidump.dma_b;
4016 while (count-- > 0) {
4017 sum += *template_buff++;
4021 sum = (sum & 0xFFFFFFFF) + (sum >> 32);
4028 ql_minidump_init(qla_host_t *ha)
4031 uint32_t template_size = 0;
4032 device_t dev = ha->pci_dev;
4035 * Get Minidump Template Size
4037 ret = qla_get_minidump_tmplt_size(ha, &template_size);
4039 if (ret || (template_size == 0)) {
4040 device_printf(dev, "%s: failed [%d, %d]\n", __func__, ret,
4046 * Allocate Memory for Minidump Template
4049 ha->hw.dma_buf.minidump.alignment = 8;
4050 ha->hw.dma_buf.minidump.size = template_size;
4052 #ifdef QL_LDFLASH_FW
4053 if (ql_alloc_dmabuf(ha, &ha->hw.dma_buf.minidump)) {
4055 device_printf(dev, "%s: minidump dma alloc failed\n", __func__);
4059 ha->hw.dma_buf.flags.minidump = 1;
4062 * Retrieve Minidump Template
4064 ret = ql_get_minidump_template(ha);
4066 ha->hw.dma_buf.minidump.dma_b = ql83xx_minidump;
4068 #endif /* #ifdef QL_LDFLASH_FW */
4072 ret = ql_validate_minidump_checksum(ha);
4076 ret = ql_alloc_minidump_buffers(ha);
4079 ha->hw.mdump_init = 1;
4082 "%s: ql_alloc_minidump_buffers"
4083 " failed\n", __func__);
4085 device_printf(dev, "%s: ql_validate_minidump_checksum"
4086 " failed\n", __func__);
4089 device_printf(dev, "%s: ql_get_minidump_template failed\n",
4094 ql_minidump_free(ha);
4100 ql_minidump_free(qla_host_t *ha)
4102 ha->hw.mdump_init = 0;
4103 if (ha->hw.dma_buf.flags.minidump) {
4104 ha->hw.dma_buf.flags.minidump = 0;
4105 ql_free_dmabuf(ha, &ha->hw.dma_buf.minidump);
4108 ql_free_minidump_template_buffer(ha);
4109 ql_free_minidump_buffer(ha);
4115 ql_minidump(qla_host_t *ha)
4117 if (!ha->hw.mdump_init)
4120 if (ha->hw.mdump_done)
4123 ha->hw.mdump_start_seq_index = ql_stop_sequence(ha);
4125 bzero(ha->hw.mdump_buffer, ha->hw.mdump_buffer_size);
4126 bzero(ha->hw.mdump_template, ha->hw.mdump_template_size);
4128 bcopy(ha->hw.dma_buf.minidump.dma_b, ha->hw.mdump_template,
4129 ha->hw.mdump_template_size);
4131 ql_parse_template(ha);
4133 ql_start_sequence(ha, ha->hw.mdump_start_seq_index);
4135 ha->hw.mdump_done = 1;
4145 ql_entry_err_chk(ql_minidump_entry_t *entry, uint32_t esize)
4147 if (esize != entry->hdr.entry_capture_size) {
4148 entry->hdr.entry_capture_size = esize;
4149 entry->hdr.driver_flags |= QL_DBG_SIZE_ERR_FLAG;
4156 ql_parse_template(qla_host_t *ha)
4158 uint32_t num_of_entries, buff_level, e_cnt, esize;
4159 uint32_t end_cnt, rv = 0;
4160 char *dump_buff, *dbuff;
4161 int sane_start = 0, sane_end = 0;
4162 ql_minidump_template_hdr_t *template_hdr;
4163 ql_minidump_entry_t *entry;
4164 uint32_t capture_mask;
4167 /* Setup parameters */
4168 template_hdr = (ql_minidump_template_hdr_t *)ha->hw.mdump_template;
4170 if (template_hdr->entry_type == TLHDR)
4173 dump_buff = (char *) ha->hw.mdump_buffer;
4175 num_of_entries = template_hdr->num_of_entries;
4177 entry = (ql_minidump_entry_t *) ((char *)template_hdr
4178 + template_hdr->first_entry_offset );
4180 template_hdr->saved_state_array[QL_OCM0_ADDR_INDX] =
4181 template_hdr->ocm_window_array[ha->pci_func];
4182 template_hdr->saved_state_array[QL_PCIE_FUNC_INDX] = ha->pci_func;
4184 capture_mask = ha->hw.mdump_capture_mask;
4185 dump_size = ha->hw.mdump_buffer_size;
4187 template_hdr->driver_capture_mask = capture_mask;
4189 QL_DPRINT80(ha, (ha->pci_dev,
4190 "%s: sane_start = %d num_of_entries = %d "
4191 "capture_mask = 0x%x dump_size = %d \n",
4192 __func__, sane_start, num_of_entries, capture_mask, dump_size));
4194 for (buff_level = 0, e_cnt = 0; e_cnt < num_of_entries; e_cnt++) {
4197 * If the capture_mask of the entry does not match capture mask
4198 * skip the entry after marking the driver_flags indicator.
4201 if (!(entry->hdr.entry_capture_mask & capture_mask)) {
4203 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG;
4204 entry = (ql_minidump_entry_t *) ((char *) entry
4205 + entry->hdr.entry_size);
4210 * This is ONLY needed in implementations where
4211 * the capture buffer allocated is too small to capture
4212 * all of the required entries for a given capture mask.
4213 * We need to empty the buffer contents to a file
4214 * if possible, before processing the next entry
4215 * If the buff_full_flag is set, no further capture will happen
4216 * and all remaining non-control entries will be skipped.
4218 if (entry->hdr.entry_capture_size != 0) {
4219 if ((buff_level + entry->hdr.entry_capture_size) >
4221 /* Try to recover by emptying buffer to file */
4222 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG;
4223 entry = (ql_minidump_entry_t *) ((char *) entry
4224 + entry->hdr.entry_size);
4230 * Decode the entry type and process it accordingly
4233 switch (entry->hdr.entry_type) {
4238 if (sane_end == 0) {
4245 dbuff = dump_buff + buff_level;
4246 esize = ql_rdcrb(ha, (void *)entry, (void *)dbuff);
4247 ql_entry_err_chk(entry, esize);
4248 buff_level += esize;
4252 dbuff = dump_buff + buff_level;
4253 esize = ql_pollrd(ha, (void *)entry, (void *)dbuff);
4254 ql_entry_err_chk(entry, esize);
4255 buff_level += esize;
4259 dbuff = dump_buff + buff_level;
4260 esize = ql_pollrd_modify_write(ha, (void *)entry,
4262 ql_entry_err_chk(entry, esize);
4263 buff_level += esize;
4270 dbuff = dump_buff + buff_level;
4271 esize = ql_L2Cache(ha, (void *)entry, (void *)dbuff);
4273 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG;
4275 ql_entry_err_chk(entry, esize);
4276 buff_level += esize;
4282 dbuff = dump_buff + buff_level;
4283 esize = ql_L1Cache(ha, (void *)entry, (void *)dbuff);
4284 ql_entry_err_chk(entry, esize);
4285 buff_level += esize;
4289 dbuff = dump_buff + buff_level;
4290 esize = ql_rdocm(ha, (void *)entry, (void *)dbuff);
4291 ql_entry_err_chk(entry, esize);
4292 buff_level += esize;
4296 dbuff = dump_buff + buff_level;
4297 esize = ql_rdmem(ha, (void *)entry, (void *)dbuff);
4298 ql_entry_err_chk(entry, esize);
4299 buff_level += esize;
4304 dbuff = dump_buff + buff_level;
4305 esize = ql_rdrom(ha, (void *)entry, (void *)dbuff);
4306 ql_entry_err_chk(entry, esize);
4307 buff_level += esize;
4311 dbuff = dump_buff + buff_level;
4312 esize = ql_rdmux(ha, (void *)entry, (void *)dbuff);
4313 ql_entry_err_chk(entry, esize);
4314 buff_level += esize;
4318 dbuff = dump_buff + buff_level;
4319 esize = ql_rdmux2(ha, (void *)entry, (void *)dbuff);
4320 ql_entry_err_chk(entry, esize);
4321 buff_level += esize;
4325 dbuff = dump_buff + buff_level;
4326 esize = ql_rdqueue(ha, (void *)entry, (void *)dbuff);
4327 ql_entry_err_chk(entry, esize);
4328 buff_level += esize;
4332 if ((rv = ql_cntrl(ha, template_hdr, (void *)entry))) {
4333 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG;
4337 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG;
4340 /* next entry in the template */
4341 entry = (ql_minidump_entry_t *) ((char *) entry
4342 + entry->hdr.entry_size);
4345 if (!sane_start || (sane_end > 1)) {
4346 device_printf(ha->pci_dev,
4347 "\n%s: Template configuration error. Check Template\n",
4351 QL_DPRINT80(ha, (ha->pci_dev, "%s: Minidump num of entries = %d\n",
4352 __func__, template_hdr->num_of_entries));
4358 * Read CRB operation.
4361 ql_rdcrb(qla_host_t *ha, ql_minidump_entry_rdcrb_t * crb_entry,
4362 uint32_t * data_buff)
4366 uint32_t op_count, addr, stride, value = 0;
4368 addr = crb_entry->addr;
4369 op_count = crb_entry->op_count;
4370 stride = crb_entry->addr_stride;
4372 for (loop_cnt = 0; loop_cnt < op_count; loop_cnt++) {
4374 ret = ql_rdwr_indreg32(ha, addr, &value, 1);
4379 *data_buff++ = addr;
4380 *data_buff++ = value;
4381 addr = addr + stride;
4385 * for testing purpose we return amount of data written
4387 return (op_count * (2 * sizeof(uint32_t)));
4395 ql_L2Cache(qla_host_t *ha, ql_minidump_entry_cache_t *cacheEntry,
4396 uint32_t * data_buff)
4402 uint32_t read_value;
4403 uint32_t addr, read_addr, cntrl_addr, tag_reg_addr, cntl_value_w;
4404 uint32_t tag_value, read_cnt;
4405 volatile uint8_t cntl_value_r;
4409 loop_cnt = cacheEntry->op_count;
4411 read_addr = cacheEntry->read_addr;
4412 cntrl_addr = cacheEntry->control_addr;
4413 cntl_value_w = (uint32_t) cacheEntry->write_value;
4415 tag_reg_addr = cacheEntry->tag_reg_addr;
4417 tag_value = cacheEntry->init_tag_value;
4418 read_cnt = cacheEntry->read_addr_cnt;
4420 for (i = 0; i < loop_cnt; i++) {
4422 ret = ql_rdwr_indreg32(ha, tag_reg_addr, &tag_value, 0);
4426 if (cacheEntry->write_value != 0) {
4428 ret = ql_rdwr_indreg32(ha, cntrl_addr,
4434 if (cacheEntry->poll_mask != 0) {
4436 timeout = cacheEntry->poll_wait;
4438 ret = ql_rdwr_indreg32(ha, cntrl_addr, &data, 1);
4442 cntl_value_r = (uint8_t)data;
4444 while ((cntl_value_r & cacheEntry->poll_mask) != 0) {
4447 qla_mdelay(__func__, 1);
4452 ret = ql_rdwr_indreg32(ha, cntrl_addr,
4457 cntl_value_r = (uint8_t)data;
4460 /* Report timeout error.
4461 * core dump capture failed
4462 * Skip remaining entries.
4463 * Write buffer out to file
4464 * Use driver specific fields in template header
4465 * to report this error.
4472 for (k = 0; k < read_cnt; k++) {
4474 ret = ql_rdwr_indreg32(ha, addr, &read_value, 1);
4478 *data_buff++ = read_value;
4479 addr += cacheEntry->read_addr_stride;
4482 tag_value += cacheEntry->tag_value_stride;
4485 return (read_cnt * loop_cnt * sizeof(uint32_t));
4493 ql_L1Cache(qla_host_t *ha,
4494 ql_minidump_entry_cache_t *cacheEntry,
4495 uint32_t *data_buff)
4501 uint32_t read_value;
4502 uint32_t addr, read_addr, cntrl_addr, tag_reg_addr;
4503 uint32_t tag_value, read_cnt;
4504 uint32_t cntl_value_w;
4506 loop_cnt = cacheEntry->op_count;
4508 read_addr = cacheEntry->read_addr;
4509 cntrl_addr = cacheEntry->control_addr;
4510 cntl_value_w = (uint32_t) cacheEntry->write_value;
4512 tag_reg_addr = cacheEntry->tag_reg_addr;
4514 tag_value = cacheEntry->init_tag_value;
4515 read_cnt = cacheEntry->read_addr_cnt;
4517 for (i = 0; i < loop_cnt; i++) {
4519 ret = ql_rdwr_indreg32(ha, tag_reg_addr, &tag_value, 0);
4523 ret = ql_rdwr_indreg32(ha, cntrl_addr, &cntl_value_w, 0);
4528 for (k = 0; k < read_cnt; k++) {
4530 ret = ql_rdwr_indreg32(ha, addr, &read_value, 1);
4534 *data_buff++ = read_value;
4535 addr += cacheEntry->read_addr_stride;
4538 tag_value += cacheEntry->tag_value_stride;
4541 return (read_cnt * loop_cnt * sizeof(uint32_t));
4545 * Reading OCM memory
4549 ql_rdocm(qla_host_t *ha,
4550 ql_minidump_entry_rdocm_t *ocmEntry,
4551 uint32_t *data_buff)
4554 volatile uint32_t addr;
4555 volatile uint32_t value;
4557 addr = ocmEntry->read_addr;
4558 loop_cnt = ocmEntry->op_count;
4560 for (i = 0; i < loop_cnt; i++) {
4561 value = READ_REG32(ha, addr);
4562 *data_buff++ = value;
4563 addr += ocmEntry->read_addr_stride;
4565 return (loop_cnt * sizeof(value));
4573 ql_rdmem(qla_host_t *ha,
4574 ql_minidump_entry_rdmem_t *mem_entry,
4575 uint32_t *data_buff)
4579 volatile uint32_t addr;
4580 q80_offchip_mem_val_t val;
4582 addr = mem_entry->read_addr;
4584 /* size in bytes / 16 */
4585 loop_cnt = mem_entry->read_data_size / (sizeof(uint32_t) * 4);
4587 for (i = 0; i < loop_cnt; i++) {
4589 ret = ql_rdwr_offchip_mem(ha, (addr & 0x0ffffffff), &val, 1);
4593 *data_buff++ = val.data_lo;
4594 *data_buff++ = val.data_hi;
4595 *data_buff++ = val.data_ulo;
4596 *data_buff++ = val.data_uhi;
4598 addr += (sizeof(uint32_t) * 4);
4601 return (loop_cnt * (sizeof(uint32_t) * 4));
4609 ql_rdrom(qla_host_t *ha,
4610 ql_minidump_entry_rdrom_t *romEntry,
4611 uint32_t *data_buff)
4618 addr = romEntry->read_addr;
4619 loop_cnt = romEntry->read_data_size; /* This is size in bytes */
4620 loop_cnt /= sizeof(value);
4622 for (i = 0; i < loop_cnt; i++) {
4624 ret = ql_rd_flash32(ha, addr, &value);
4628 *data_buff++ = value;
4629 addr += sizeof(value);
4632 return (loop_cnt * sizeof(value));
4640 ql_rdmux(qla_host_t *ha,
4641 ql_minidump_entry_mux_t *muxEntry,
4642 uint32_t *data_buff)
4646 uint32_t read_value, sel_value;
4647 uint32_t read_addr, select_addr;
4649 select_addr = muxEntry->select_addr;
4650 sel_value = muxEntry->select_value;
4651 read_addr = muxEntry->read_addr;
4653 for (loop_cnt = 0; loop_cnt < muxEntry->op_count; loop_cnt++) {
4655 ret = ql_rdwr_indreg32(ha, select_addr, &sel_value, 0);
4659 ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1);
4663 *data_buff++ = sel_value;
4664 *data_buff++ = read_value;
4666 sel_value += muxEntry->select_value_stride;
4669 return (loop_cnt * (2 * sizeof(uint32_t)));
4673 ql_rdmux2(qla_host_t *ha,
4674 ql_minidump_entry_mux2_t *muxEntry,
4675 uint32_t *data_buff)
4680 uint32_t select_addr_1, select_addr_2;
4681 uint32_t select_value_1, select_value_2;
4682 uint32_t select_value_count, select_value_mask;
4683 uint32_t read_addr, read_value;
4685 select_addr_1 = muxEntry->select_addr_1;
4686 select_addr_2 = muxEntry->select_addr_2;
4687 select_value_1 = muxEntry->select_value_1;
4688 select_value_2 = muxEntry->select_value_2;
4689 select_value_count = muxEntry->select_value_count;
4690 select_value_mask = muxEntry->select_value_mask;
4692 read_addr = muxEntry->read_addr;
4694 for (loop_cnt = 0; loop_cnt < muxEntry->select_value_count;
4697 uint32_t temp_sel_val;
4699 ret = ql_rdwr_indreg32(ha, select_addr_1, &select_value_1, 0);
4703 temp_sel_val = select_value_1 & select_value_mask;
4705 ret = ql_rdwr_indreg32(ha, select_addr_2, &temp_sel_val, 0);
4709 ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1);
4713 *data_buff++ = temp_sel_val;
4714 *data_buff++ = read_value;
4716 ret = ql_rdwr_indreg32(ha, select_addr_1, &select_value_2, 0);
4720 temp_sel_val = select_value_2 & select_value_mask;
4722 ret = ql_rdwr_indreg32(ha, select_addr_2, &temp_sel_val, 0);
4726 ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1);
4730 *data_buff++ = temp_sel_val;
4731 *data_buff++ = read_value;
4733 select_value_1 += muxEntry->select_value_stride;
4734 select_value_2 += muxEntry->select_value_stride;
4737 return (loop_cnt * (4 * sizeof(uint32_t)));
4741 * Handling Queue State Reads.
4745 ql_rdqueue(qla_host_t *ha,
4746 ql_minidump_entry_queue_t *queueEntry,
4747 uint32_t *data_buff)
4751 uint32_t read_value;
4752 uint32_t read_addr, read_stride, select_addr;
4753 uint32_t queue_id, read_cnt;
4755 read_cnt = queueEntry->read_addr_cnt;
4756 read_stride = queueEntry->read_addr_stride;
4757 select_addr = queueEntry->select_addr;
4759 for (loop_cnt = 0, queue_id = 0; loop_cnt < queueEntry->op_count;
4762 ret = ql_rdwr_indreg32(ha, select_addr, &queue_id, 0);
4766 read_addr = queueEntry->read_addr;
4768 for (k = 0; k < read_cnt; k++) {
4770 ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1);
4774 *data_buff++ = read_value;
4775 read_addr += read_stride;
4778 queue_id += queueEntry->queue_id_stride;
4781 return (loop_cnt * (read_cnt * sizeof(uint32_t)));
4785 * Handling control entries.
4789 ql_cntrl(qla_host_t *ha,
4790 ql_minidump_template_hdr_t *template_hdr,
4791 ql_minidump_entry_cntrl_t *crbEntry)
4795 uint32_t opcode, read_value, addr, entry_addr;
4798 entry_addr = crbEntry->addr;
4800 for (count = 0; count < crbEntry->op_count; count++) {
4801 opcode = crbEntry->opcode;
4803 if (opcode & QL_DBG_OPCODE_WR) {
4805 ret = ql_rdwr_indreg32(ha, entry_addr,
4806 &crbEntry->value_1, 0);
4810 opcode &= ~QL_DBG_OPCODE_WR;
4813 if (opcode & QL_DBG_OPCODE_RW) {
4815 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 1);
4819 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 0);
4823 opcode &= ~QL_DBG_OPCODE_RW;
4826 if (opcode & QL_DBG_OPCODE_AND) {
4828 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 1);
4832 read_value &= crbEntry->value_2;
4833 opcode &= ~QL_DBG_OPCODE_AND;
4835 if (opcode & QL_DBG_OPCODE_OR) {
4836 read_value |= crbEntry->value_3;
4837 opcode &= ~QL_DBG_OPCODE_OR;
4840 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 0);
4845 if (opcode & QL_DBG_OPCODE_OR) {
4847 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 1);
4851 read_value |= crbEntry->value_3;
4853 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 0);
4857 opcode &= ~QL_DBG_OPCODE_OR;
4860 if (opcode & QL_DBG_OPCODE_POLL) {
4862 opcode &= ~QL_DBG_OPCODE_POLL;
4863 timeout = crbEntry->poll_timeout;
4866 ret = ql_rdwr_indreg32(ha, addr, &read_value, 1);
4870 while ((read_value & crbEntry->value_2)
4871 != crbEntry->value_1) {
4874 qla_mdelay(__func__, 1);
4879 ret = ql_rdwr_indreg32(ha, addr,
4887 * Report timeout error.
4888 * core dump capture failed
4889 * Skip remaining entries.
4890 * Write buffer out to file
4891 * Use driver specific fields in template header
4892 * to report this error.
4898 if (opcode & QL_DBG_OPCODE_RDSTATE) {
4900 * decide which address to use.
4902 if (crbEntry->state_index_a) {
4903 addr = template_hdr->saved_state_array[
4904 crbEntry-> state_index_a];
4909 ret = ql_rdwr_indreg32(ha, addr, &read_value, 1);
4913 template_hdr->saved_state_array[crbEntry->state_index_v]
4915 opcode &= ~QL_DBG_OPCODE_RDSTATE;
4918 if (opcode & QL_DBG_OPCODE_WRSTATE) {
4920 * decide which value to use.
4922 if (crbEntry->state_index_v) {
4923 read_value = template_hdr->saved_state_array[
4924 crbEntry->state_index_v];
4926 read_value = crbEntry->value_1;
4929 * decide which address to use.
4931 if (crbEntry->state_index_a) {
4932 addr = template_hdr->saved_state_array[
4933 crbEntry-> state_index_a];
4938 ret = ql_rdwr_indreg32(ha, addr, &read_value, 0);
4942 opcode &= ~QL_DBG_OPCODE_WRSTATE;
4945 if (opcode & QL_DBG_OPCODE_MDSTATE) {
4946 /* Read value from saved state using index */
4947 read_value = template_hdr->saved_state_array[
4948 crbEntry->state_index_v];
4950 read_value <<= crbEntry->shl; /*Shift left operation */
4951 read_value >>= crbEntry->shr; /*Shift right operation */
4953 if (crbEntry->value_2) {
4954 /* check if AND mask is provided */
4955 read_value &= crbEntry->value_2;
4958 read_value |= crbEntry->value_3; /* OR operation */
4959 read_value += crbEntry->value_1; /* increment op */
4961 /* Write value back to state area. */
4963 template_hdr->saved_state_array[crbEntry->state_index_v]
4965 opcode &= ~QL_DBG_OPCODE_MDSTATE;
4968 entry_addr += crbEntry->addr_stride;
4975 * Handling rd poll entry.
4979 ql_pollrd(qla_host_t *ha, ql_minidump_entry_pollrd_t *entry,
4980 uint32_t *data_buff)
4984 uint32_t op_count, select_addr, select_value_stride, select_value;
4985 uint32_t read_addr, poll, mask, data_size, data;
4986 uint32_t wait_count = 0;
4988 select_addr = entry->select_addr;
4989 read_addr = entry->read_addr;
4990 select_value = entry->select_value;
4991 select_value_stride = entry->select_value_stride;
4992 op_count = entry->op_count;
4995 data_size = entry->data_size;
4997 for (loop_cnt = 0; loop_cnt < op_count; loop_cnt++) {
4999 ret = ql_rdwr_indreg32(ha, select_addr, &select_value, 0);
5005 while (wait_count < poll) {
5009 ret = ql_rdwr_indreg32(ha, select_addr, &temp, 1);
5013 if ( (temp & mask) != 0 ) {
5019 if (wait_count == poll) {
5020 device_printf(ha->pci_dev,
5021 "%s: Error in processing entry\n", __func__);
5022 device_printf(ha->pci_dev,
5023 "%s: wait_count <0x%x> poll <0x%x>\n",
5024 __func__, wait_count, poll);
5028 ret = ql_rdwr_indreg32(ha, read_addr, &data, 1);
5032 *data_buff++ = select_value;
5033 *data_buff++ = data;
5034 select_value = select_value + select_value_stride;
5038 * for testing purpose we return amount of data written
5040 return (loop_cnt * (2 * sizeof(uint32_t)));
5045 * Handling rd modify write poll entry.
5049 ql_pollrd_modify_write(qla_host_t *ha,
5050 ql_minidump_entry_rd_modify_wr_with_poll_t *entry,
5051 uint32_t *data_buff)
5054 uint32_t addr_1, addr_2, value_1, value_2, data;
5055 uint32_t poll, mask, data_size, modify_mask;
5056 uint32_t wait_count = 0;
5058 addr_1 = entry->addr_1;
5059 addr_2 = entry->addr_2;
5060 value_1 = entry->value_1;
5061 value_2 = entry->value_2;
5065 modify_mask = entry->modify_mask;
5066 data_size = entry->data_size;
5069 ret = ql_rdwr_indreg32(ha, addr_1, &value_1, 0);
5074 while (wait_count < poll) {
5078 ret = ql_rdwr_indreg32(ha, addr_1, &temp, 1);
5082 if ( (temp & mask) != 0 ) {
5088 if (wait_count == poll) {
5089 device_printf(ha->pci_dev, "%s Error in processing entry\n",
5093 ret = ql_rdwr_indreg32(ha, addr_2, &data, 1);
5097 data = (data & modify_mask);
5099 ret = ql_rdwr_indreg32(ha, addr_2, &data, 0);
5103 ret = ql_rdwr_indreg32(ha, addr_1, &value_2, 0);
5109 while (wait_count < poll) {
5113 ret = ql_rdwr_indreg32(ha, addr_1, &temp, 1);
5117 if ( (temp & mask) != 0 ) {
5122 *data_buff++ = addr_2;
5123 *data_buff++ = data;
5127 * for testing purpose we return amount of data written
5129 return (2 * sizeof(uint32_t));