2 * Copyright (c) 2013-2016 Qlogic Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
30 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
31 * Content: Contains Hardware dependant functions
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
40 #include "ql_inline.h"
44 #include "ql_minidump.h"
50 static void qla_del_rcv_cntxt(qla_host_t *ha);
51 static int qla_init_rcv_cntxt(qla_host_t *ha);
52 static int qla_del_xmt_cntxt(qla_host_t *ha);
53 static int qla_init_xmt_cntxt(qla_host_t *ha);
54 static int qla_mbx_cmd(qla_host_t *ha, uint32_t *h_mbox, uint32_t n_hmbox,
55 uint32_t *fw_mbox, uint32_t n_fwmbox, uint32_t no_pause);
56 static int qla_config_intr_cntxt(qla_host_t *ha, uint32_t start_idx,
57 uint32_t num_intrs, uint32_t create);
58 static int qla_config_rss(qla_host_t *ha, uint16_t cntxt_id);
59 static int qla_config_intr_coalesce(qla_host_t *ha, uint16_t cntxt_id,
60 int tenable, int rcv);
61 static int qla_set_mac_rcv_mode(qla_host_t *ha, uint32_t mode);
62 static int qla_link_event_req(qla_host_t *ha, uint16_t cntxt_id);
64 static int qla_tx_tso(qla_host_t *ha, struct mbuf *mp, q80_tx_cmd_t *tx_cmd,
66 static int qla_hw_add_all_mcast(qla_host_t *ha);
67 static int qla_add_rcv_rings(qla_host_t *ha, uint32_t sds_idx, uint32_t nsds);
69 static int qla_init_nic_func(qla_host_t *ha);
70 static int qla_stop_nic_func(qla_host_t *ha);
71 static int qla_query_fw_dcbx_caps(qla_host_t *ha);
72 static int qla_set_port_config(qla_host_t *ha, uint32_t cfg_bits);
73 static int qla_get_port_config(qla_host_t *ha, uint32_t *cfg_bits);
74 static int qla_set_cam_search_mode(qla_host_t *ha, uint32_t search_mode);
75 static int qla_get_cam_search_mode(qla_host_t *ha);
77 static void ql_minidump_free(qla_host_t *ha);
82 qla_stop_pegs(qla_host_t *ha)
86 ql_rdwr_indreg32(ha, Q8_CRB_PEG_0, &val, 0);
87 ql_rdwr_indreg32(ha, Q8_CRB_PEG_1, &val, 0);
88 ql_rdwr_indreg32(ha, Q8_CRB_PEG_2, &val, 0);
89 ql_rdwr_indreg32(ha, Q8_CRB_PEG_3, &val, 0);
90 ql_rdwr_indreg32(ha, Q8_CRB_PEG_4, &val, 0);
91 device_printf(ha->pci_dev, "%s PEGS HALTED!!!!!\n", __func__);
95 qla_sysctl_stop_pegs(SYSCTL_HANDLER_ARGS)
100 err = sysctl_handle_int(oidp, &ret, 0, req);
103 if (err || !req->newptr)
107 ha = (qla_host_t *)arg1;
108 if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) {
110 QLA_UNLOCK(ha, __func__);
116 #endif /* #ifdef QL_DBG */
119 qla_validate_set_port_cfg_bit(uint32_t bits)
121 if ((bits & 0xF) > 1)
124 if (((bits >> 4) & 0xF) > 2)
127 if (((bits >> 8) & 0xF) > 2)
134 qla_sysctl_port_cfg(SYSCTL_HANDLER_ARGS)
140 err = sysctl_handle_int(oidp, &ret, 0, req);
142 if (err || !req->newptr)
145 ha = (qla_host_t *)arg1;
147 if ((qla_validate_set_port_cfg_bit((uint32_t)ret) == 0)) {
149 err = qla_get_port_config(ha, &cfg_bits);
152 goto qla_sysctl_set_port_cfg_exit;
155 cfg_bits |= Q8_PORT_CFG_BITS_DCBX_ENABLE;
157 cfg_bits &= ~Q8_PORT_CFG_BITS_DCBX_ENABLE;
161 cfg_bits &= ~Q8_PORT_CFG_BITS_PAUSE_CFG_MASK;
163 if ((ret & 0xF) == 0) {
164 cfg_bits |= Q8_PORT_CFG_BITS_PAUSE_DISABLED;
165 } else if ((ret & 0xF) == 1){
166 cfg_bits |= Q8_PORT_CFG_BITS_PAUSE_STD;
168 cfg_bits |= Q8_PORT_CFG_BITS_PAUSE_PPM;
172 cfg_bits &= ~Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK;
175 cfg_bits |= Q8_PORT_CFG_BITS_STDPAUSE_XMT_RCV;
176 } else if (ret == 1){
177 cfg_bits |= Q8_PORT_CFG_BITS_STDPAUSE_XMT;
179 cfg_bits |= Q8_PORT_CFG_BITS_STDPAUSE_RCV;
182 if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) {
183 err = qla_set_port_config(ha, cfg_bits);
184 QLA_UNLOCK(ha, __func__);
186 device_printf(ha->pci_dev, "%s: failed\n", __func__);
189 if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) {
190 err = qla_get_port_config(ha, &cfg_bits);
191 QLA_UNLOCK(ha, __func__);
193 device_printf(ha->pci_dev, "%s: failed\n", __func__);
197 qla_sysctl_set_port_cfg_exit:
202 qla_sysctl_set_cam_search_mode(SYSCTL_HANDLER_ARGS)
207 err = sysctl_handle_int(oidp, &ret, 0, req);
209 if (err || !req->newptr)
212 ha = (qla_host_t *)arg1;
214 if ((ret == Q8_HW_CONFIG_CAM_SEARCH_MODE_INTERNAL) ||
215 (ret == Q8_HW_CONFIG_CAM_SEARCH_MODE_AUTO)) {
217 if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) {
218 err = qla_set_cam_search_mode(ha, (uint32_t)ret);
219 QLA_UNLOCK(ha, __func__);
221 device_printf(ha->pci_dev, "%s: failed\n", __func__);
225 device_printf(ha->pci_dev, "%s: ret = %d\n", __func__, ret);
232 qla_sysctl_get_cam_search_mode(SYSCTL_HANDLER_ARGS)
237 err = sysctl_handle_int(oidp, &ret, 0, req);
239 if (err || !req->newptr)
242 ha = (qla_host_t *)arg1;
243 if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) {
244 err = qla_get_cam_search_mode(ha);
245 QLA_UNLOCK(ha, __func__);
247 device_printf(ha->pci_dev, "%s: failed\n", __func__);
254 qlnx_add_hw_mac_stats_sysctls(qla_host_t *ha)
256 struct sysctl_ctx_list *ctx;
257 struct sysctl_oid_list *children;
258 struct sysctl_oid *ctx_oid;
260 ctx = device_get_sysctl_ctx(ha->pci_dev);
261 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev));
263 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_hw_mac",
264 CTLFLAG_RD, NULL, "stats_hw_mac");
265 children = SYSCTL_CHILDREN(ctx_oid);
267 SYSCTL_ADD_QUAD(ctx, children,
268 OID_AUTO, "xmt_frames",
269 CTLFLAG_RD, &ha->hw.mac.xmt_frames,
272 SYSCTL_ADD_QUAD(ctx, children,
273 OID_AUTO, "xmt_bytes",
274 CTLFLAG_RD, &ha->hw.mac.xmt_bytes,
277 SYSCTL_ADD_QUAD(ctx, children,
278 OID_AUTO, "xmt_mcast_pkts",
279 CTLFLAG_RD, &ha->hw.mac.xmt_mcast_pkts,
282 SYSCTL_ADD_QUAD(ctx, children,
283 OID_AUTO, "xmt_bcast_pkts",
284 CTLFLAG_RD, &ha->hw.mac.xmt_bcast_pkts,
287 SYSCTL_ADD_QUAD(ctx, children,
288 OID_AUTO, "xmt_pause_frames",
289 CTLFLAG_RD, &ha->hw.mac.xmt_pause_frames,
292 SYSCTL_ADD_QUAD(ctx, children,
293 OID_AUTO, "xmt_cntrl_pkts",
294 CTLFLAG_RD, &ha->hw.mac.xmt_cntrl_pkts,
297 SYSCTL_ADD_QUAD(ctx, children,
298 OID_AUTO, "xmt_pkt_lt_64bytes",
299 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_64bytes,
300 "xmt_pkt_lt_64bytes");
302 SYSCTL_ADD_QUAD(ctx, children,
303 OID_AUTO, "xmt_pkt_lt_127bytes",
304 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_127bytes,
305 "xmt_pkt_lt_127bytes");
307 SYSCTL_ADD_QUAD(ctx, children,
308 OID_AUTO, "xmt_pkt_lt_255bytes",
309 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_255bytes,
310 "xmt_pkt_lt_255bytes");
312 SYSCTL_ADD_QUAD(ctx, children,
313 OID_AUTO, "xmt_pkt_lt_511bytes",
314 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_511bytes,
315 "xmt_pkt_lt_511bytes");
317 SYSCTL_ADD_QUAD(ctx, children,
318 OID_AUTO, "xmt_pkt_lt_1023bytes",
319 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_1023bytes,
320 "xmt_pkt_lt_1023bytes");
322 SYSCTL_ADD_QUAD(ctx, children,
323 OID_AUTO, "xmt_pkt_lt_1518bytes",
324 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_1518bytes,
325 "xmt_pkt_lt_1518bytes");
327 SYSCTL_ADD_QUAD(ctx, children,
328 OID_AUTO, "xmt_pkt_gt_1518bytes",
329 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_gt_1518bytes,
330 "xmt_pkt_gt_1518bytes");
332 SYSCTL_ADD_QUAD(ctx, children,
333 OID_AUTO, "rcv_frames",
334 CTLFLAG_RD, &ha->hw.mac.rcv_frames,
337 SYSCTL_ADD_QUAD(ctx, children,
338 OID_AUTO, "rcv_bytes",
339 CTLFLAG_RD, &ha->hw.mac.rcv_bytes,
342 SYSCTL_ADD_QUAD(ctx, children,
343 OID_AUTO, "rcv_mcast_pkts",
344 CTLFLAG_RD, &ha->hw.mac.rcv_mcast_pkts,
347 SYSCTL_ADD_QUAD(ctx, children,
348 OID_AUTO, "rcv_bcast_pkts",
349 CTLFLAG_RD, &ha->hw.mac.rcv_bcast_pkts,
352 SYSCTL_ADD_QUAD(ctx, children,
353 OID_AUTO, "rcv_pause_frames",
354 CTLFLAG_RD, &ha->hw.mac.rcv_pause_frames,
357 SYSCTL_ADD_QUAD(ctx, children,
358 OID_AUTO, "rcv_cntrl_pkts",
359 CTLFLAG_RD, &ha->hw.mac.rcv_cntrl_pkts,
362 SYSCTL_ADD_QUAD(ctx, children,
363 OID_AUTO, "rcv_pkt_lt_64bytes",
364 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_64bytes,
365 "rcv_pkt_lt_64bytes");
367 SYSCTL_ADD_QUAD(ctx, children,
368 OID_AUTO, "rcv_pkt_lt_127bytes",
369 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_127bytes,
370 "rcv_pkt_lt_127bytes");
372 SYSCTL_ADD_QUAD(ctx, children,
373 OID_AUTO, "rcv_pkt_lt_255bytes",
374 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_255bytes,
375 "rcv_pkt_lt_255bytes");
377 SYSCTL_ADD_QUAD(ctx, children,
378 OID_AUTO, "rcv_pkt_lt_511bytes",
379 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_511bytes,
380 "rcv_pkt_lt_511bytes");
382 SYSCTL_ADD_QUAD(ctx, children,
383 OID_AUTO, "rcv_pkt_lt_1023bytes",
384 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_1023bytes,
385 "rcv_pkt_lt_1023bytes");
387 SYSCTL_ADD_QUAD(ctx, children,
388 OID_AUTO, "rcv_pkt_lt_1518bytes",
389 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_1518bytes,
390 "rcv_pkt_lt_1518bytes");
392 SYSCTL_ADD_QUAD(ctx, children,
393 OID_AUTO, "rcv_pkt_gt_1518bytes",
394 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_gt_1518bytes,
395 "rcv_pkt_gt_1518bytes");
397 SYSCTL_ADD_QUAD(ctx, children,
398 OID_AUTO, "rcv_len_error",
399 CTLFLAG_RD, &ha->hw.mac.rcv_len_error,
402 SYSCTL_ADD_QUAD(ctx, children,
403 OID_AUTO, "rcv_len_small",
404 CTLFLAG_RD, &ha->hw.mac.rcv_len_small,
407 SYSCTL_ADD_QUAD(ctx, children,
408 OID_AUTO, "rcv_len_large",
409 CTLFLAG_RD, &ha->hw.mac.rcv_len_large,
412 SYSCTL_ADD_QUAD(ctx, children,
413 OID_AUTO, "rcv_jabber",
414 CTLFLAG_RD, &ha->hw.mac.rcv_jabber,
417 SYSCTL_ADD_QUAD(ctx, children,
418 OID_AUTO, "rcv_dropped",
419 CTLFLAG_RD, &ha->hw.mac.rcv_dropped,
422 SYSCTL_ADD_QUAD(ctx, children,
423 OID_AUTO, "fcs_error",
424 CTLFLAG_RD, &ha->hw.mac.fcs_error,
427 SYSCTL_ADD_QUAD(ctx, children,
428 OID_AUTO, "align_error",
429 CTLFLAG_RD, &ha->hw.mac.align_error,
432 SYSCTL_ADD_QUAD(ctx, children,
433 OID_AUTO, "eswitched_frames",
434 CTLFLAG_RD, &ha->hw.mac.eswitched_frames,
437 SYSCTL_ADD_QUAD(ctx, children,
438 OID_AUTO, "eswitched_bytes",
439 CTLFLAG_RD, &ha->hw.mac.eswitched_bytes,
442 SYSCTL_ADD_QUAD(ctx, children,
443 OID_AUTO, "eswitched_mcast_frames",
444 CTLFLAG_RD, &ha->hw.mac.eswitched_mcast_frames,
445 "eswitched_mcast_frames");
447 SYSCTL_ADD_QUAD(ctx, children,
448 OID_AUTO, "eswitched_bcast_frames",
449 CTLFLAG_RD, &ha->hw.mac.eswitched_bcast_frames,
450 "eswitched_bcast_frames");
452 SYSCTL_ADD_QUAD(ctx, children,
453 OID_AUTO, "eswitched_ucast_frames",
454 CTLFLAG_RD, &ha->hw.mac.eswitched_ucast_frames,
455 "eswitched_ucast_frames");
457 SYSCTL_ADD_QUAD(ctx, children,
458 OID_AUTO, "eswitched_err_free_frames",
459 CTLFLAG_RD, &ha->hw.mac.eswitched_err_free_frames,
460 "eswitched_err_free_frames");
462 SYSCTL_ADD_QUAD(ctx, children,
463 OID_AUTO, "eswitched_err_free_bytes",
464 CTLFLAG_RD, &ha->hw.mac.eswitched_err_free_bytes,
465 "eswitched_err_free_bytes");
471 qlnx_add_hw_rcv_stats_sysctls(qla_host_t *ha)
473 struct sysctl_ctx_list *ctx;
474 struct sysctl_oid_list *children;
475 struct sysctl_oid *ctx_oid;
477 ctx = device_get_sysctl_ctx(ha->pci_dev);
478 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev));
480 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_hw_rcv",
481 CTLFLAG_RD, NULL, "stats_hw_rcv");
482 children = SYSCTL_CHILDREN(ctx_oid);
484 SYSCTL_ADD_QUAD(ctx, children,
485 OID_AUTO, "total_bytes",
486 CTLFLAG_RD, &ha->hw.rcv.total_bytes,
489 SYSCTL_ADD_QUAD(ctx, children,
490 OID_AUTO, "total_pkts",
491 CTLFLAG_RD, &ha->hw.rcv.total_pkts,
494 SYSCTL_ADD_QUAD(ctx, children,
495 OID_AUTO, "lro_pkt_count",
496 CTLFLAG_RD, &ha->hw.rcv.lro_pkt_count,
499 SYSCTL_ADD_QUAD(ctx, children,
500 OID_AUTO, "sw_pkt_count",
501 CTLFLAG_RD, &ha->hw.rcv.sw_pkt_count,
504 SYSCTL_ADD_QUAD(ctx, children,
505 OID_AUTO, "ip_chksum_err",
506 CTLFLAG_RD, &ha->hw.rcv.ip_chksum_err,
509 SYSCTL_ADD_QUAD(ctx, children,
510 OID_AUTO, "pkts_wo_acntxts",
511 CTLFLAG_RD, &ha->hw.rcv.pkts_wo_acntxts,
514 SYSCTL_ADD_QUAD(ctx, children,
515 OID_AUTO, "pkts_dropped_no_sds_card",
516 CTLFLAG_RD, &ha->hw.rcv.pkts_dropped_no_sds_card,
517 "pkts_dropped_no_sds_card");
519 SYSCTL_ADD_QUAD(ctx, children,
520 OID_AUTO, "pkts_dropped_no_sds_host",
521 CTLFLAG_RD, &ha->hw.rcv.pkts_dropped_no_sds_host,
522 "pkts_dropped_no_sds_host");
524 SYSCTL_ADD_QUAD(ctx, children,
525 OID_AUTO, "oversized_pkts",
526 CTLFLAG_RD, &ha->hw.rcv.oversized_pkts,
529 SYSCTL_ADD_QUAD(ctx, children,
530 OID_AUTO, "pkts_dropped_no_rds",
531 CTLFLAG_RD, &ha->hw.rcv.pkts_dropped_no_rds,
532 "pkts_dropped_no_rds");
534 SYSCTL_ADD_QUAD(ctx, children,
535 OID_AUTO, "unxpctd_mcast_pkts",
536 CTLFLAG_RD, &ha->hw.rcv.unxpctd_mcast_pkts,
537 "unxpctd_mcast_pkts");
539 SYSCTL_ADD_QUAD(ctx, children,
540 OID_AUTO, "re1_fbq_error",
541 CTLFLAG_RD, &ha->hw.rcv.re1_fbq_error,
544 SYSCTL_ADD_QUAD(ctx, children,
545 OID_AUTO, "invalid_mac_addr",
546 CTLFLAG_RD, &ha->hw.rcv.invalid_mac_addr,
549 SYSCTL_ADD_QUAD(ctx, children,
550 OID_AUTO, "rds_prime_trys",
551 CTLFLAG_RD, &ha->hw.rcv.rds_prime_trys,
554 SYSCTL_ADD_QUAD(ctx, children,
555 OID_AUTO, "rds_prime_success",
556 CTLFLAG_RD, &ha->hw.rcv.rds_prime_success,
557 "rds_prime_success");
559 SYSCTL_ADD_QUAD(ctx, children,
560 OID_AUTO, "lro_flows_added",
561 CTLFLAG_RD, &ha->hw.rcv.lro_flows_added,
564 SYSCTL_ADD_QUAD(ctx, children,
565 OID_AUTO, "lro_flows_deleted",
566 CTLFLAG_RD, &ha->hw.rcv.lro_flows_deleted,
567 "lro_flows_deleted");
569 SYSCTL_ADD_QUAD(ctx, children,
570 OID_AUTO, "lro_flows_active",
571 CTLFLAG_RD, &ha->hw.rcv.lro_flows_active,
574 SYSCTL_ADD_QUAD(ctx, children,
575 OID_AUTO, "pkts_droped_unknown",
576 CTLFLAG_RD, &ha->hw.rcv.pkts_droped_unknown,
577 "pkts_droped_unknown");
579 SYSCTL_ADD_QUAD(ctx, children,
580 OID_AUTO, "pkts_cnt_oversized",
581 CTLFLAG_RD, &ha->hw.rcv.pkts_cnt_oversized,
582 "pkts_cnt_oversized");
588 qlnx_add_hw_xmt_stats_sysctls(qla_host_t *ha)
590 struct sysctl_ctx_list *ctx;
591 struct sysctl_oid_list *children;
592 struct sysctl_oid_list *node_children;
593 struct sysctl_oid *ctx_oid;
595 uint8_t name_str[16];
597 ctx = device_get_sysctl_ctx(ha->pci_dev);
598 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev));
600 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_hw_xmt",
601 CTLFLAG_RD, NULL, "stats_hw_xmt");
602 children = SYSCTL_CHILDREN(ctx_oid);
604 for (i = 0; i < ha->hw.num_tx_rings; i++) {
606 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str)));
607 snprintf(name_str, sizeof(name_str), "%d", i);
609 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name_str,
610 CTLFLAG_RD, NULL, name_str);
611 node_children = SYSCTL_CHILDREN(ctx_oid);
615 SYSCTL_ADD_QUAD(ctx, node_children,
616 OID_AUTO, "total_bytes",
617 CTLFLAG_RD, &ha->hw.xmt[i].total_bytes,
620 SYSCTL_ADD_QUAD(ctx, node_children,
621 OID_AUTO, "total_pkts",
622 CTLFLAG_RD, &ha->hw.xmt[i].total_pkts,
625 SYSCTL_ADD_QUAD(ctx, node_children,
627 CTLFLAG_RD, &ha->hw.xmt[i].errors,
630 SYSCTL_ADD_QUAD(ctx, node_children,
631 OID_AUTO, "pkts_dropped",
632 CTLFLAG_RD, &ha->hw.xmt[i].pkts_dropped,
635 SYSCTL_ADD_QUAD(ctx, node_children,
636 OID_AUTO, "switch_pkts",
637 CTLFLAG_RD, &ha->hw.xmt[i].switch_pkts,
640 SYSCTL_ADD_QUAD(ctx, node_children,
641 OID_AUTO, "num_buffers",
642 CTLFLAG_RD, &ha->hw.xmt[i].num_buffers,
650 qlnx_add_hw_mbx_cmpl_stats_sysctls(qla_host_t *ha)
652 struct sysctl_ctx_list *ctx;
653 struct sysctl_oid_list *node_children;
655 ctx = device_get_sysctl_ctx(ha->pci_dev);
656 node_children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev));
658 SYSCTL_ADD_QUAD(ctx, node_children,
659 OID_AUTO, "mbx_completion_time_lt_200ms",
660 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[0],
661 "mbx_completion_time_lt_200ms");
663 SYSCTL_ADD_QUAD(ctx, node_children,
664 OID_AUTO, "mbx_completion_time_200ms_400ms",
665 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[1],
666 "mbx_completion_time_200ms_400ms");
668 SYSCTL_ADD_QUAD(ctx, node_children,
669 OID_AUTO, "mbx_completion_time_400ms_600ms",
670 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[2],
671 "mbx_completion_time_400ms_600ms");
673 SYSCTL_ADD_QUAD(ctx, node_children,
674 OID_AUTO, "mbx_completion_time_600ms_800ms",
675 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[3],
676 "mbx_completion_time_600ms_800ms");
678 SYSCTL_ADD_QUAD(ctx, node_children,
679 OID_AUTO, "mbx_completion_time_800ms_1000ms",
680 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[4],
681 "mbx_completion_time_800ms_1000ms");
683 SYSCTL_ADD_QUAD(ctx, node_children,
684 OID_AUTO, "mbx_completion_time_1000ms_1200ms",
685 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[5],
686 "mbx_completion_time_1000ms_1200ms");
688 SYSCTL_ADD_QUAD(ctx, node_children,
689 OID_AUTO, "mbx_completion_time_1200ms_1400ms",
690 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[6],
691 "mbx_completion_time_1200ms_1400ms");
693 SYSCTL_ADD_QUAD(ctx, node_children,
694 OID_AUTO, "mbx_completion_time_1400ms_1600ms",
695 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[7],
696 "mbx_completion_time_1400ms_1600ms");
698 SYSCTL_ADD_QUAD(ctx, node_children,
699 OID_AUTO, "mbx_completion_time_1600ms_1800ms",
700 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[8],
701 "mbx_completion_time_1600ms_1800ms");
703 SYSCTL_ADD_QUAD(ctx, node_children,
704 OID_AUTO, "mbx_completion_time_1800ms_2000ms",
705 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[9],
706 "mbx_completion_time_1800ms_2000ms");
708 SYSCTL_ADD_QUAD(ctx, node_children,
709 OID_AUTO, "mbx_completion_time_2000ms_2200ms",
710 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[10],
711 "mbx_completion_time_2000ms_2200ms");
713 SYSCTL_ADD_QUAD(ctx, node_children,
714 OID_AUTO, "mbx_completion_time_2200ms_2400ms",
715 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[11],
716 "mbx_completion_time_2200ms_2400ms");
718 SYSCTL_ADD_QUAD(ctx, node_children,
719 OID_AUTO, "mbx_completion_time_2400ms_2600ms",
720 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[12],
721 "mbx_completion_time_2400ms_2600ms");
723 SYSCTL_ADD_QUAD(ctx, node_children,
724 OID_AUTO, "mbx_completion_time_2600ms_2800ms",
725 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[13],
726 "mbx_completion_time_2600ms_2800ms");
728 SYSCTL_ADD_QUAD(ctx, node_children,
729 OID_AUTO, "mbx_completion_time_2800ms_3000ms",
730 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[14],
731 "mbx_completion_time_2800ms_3000ms");
733 SYSCTL_ADD_QUAD(ctx, node_children,
734 OID_AUTO, "mbx_completion_time_3000ms_4000ms",
735 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[15],
736 "mbx_completion_time_3000ms_4000ms");
738 SYSCTL_ADD_QUAD(ctx, node_children,
739 OID_AUTO, "mbx_completion_time_4000ms_5000ms",
740 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[16],
741 "mbx_completion_time_4000ms_5000ms");
743 SYSCTL_ADD_QUAD(ctx, node_children,
744 OID_AUTO, "mbx_completion_host_mbx_cntrl_timeout",
745 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[17],
746 "mbx_completion_host_mbx_cntrl_timeout");
748 SYSCTL_ADD_QUAD(ctx, node_children,
749 OID_AUTO, "mbx_completion_fw_mbx_cntrl_timeout",
750 CTLFLAG_RD, &ha->hw.mbx_comp_msecs[18],
751 "mbx_completion_fw_mbx_cntrl_timeout");
756 qlnx_add_hw_stats_sysctls(qla_host_t *ha)
758 qlnx_add_hw_mac_stats_sysctls(ha);
759 qlnx_add_hw_rcv_stats_sysctls(ha);
760 qlnx_add_hw_xmt_stats_sysctls(ha);
761 qlnx_add_hw_mbx_cmpl_stats_sysctls(ha);
767 qlnx_add_drvr_sds_stats(qla_host_t *ha)
769 struct sysctl_ctx_list *ctx;
770 struct sysctl_oid_list *children;
771 struct sysctl_oid_list *node_children;
772 struct sysctl_oid *ctx_oid;
774 uint8_t name_str[16];
776 ctx = device_get_sysctl_ctx(ha->pci_dev);
777 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev));
779 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_drvr_sds",
780 CTLFLAG_RD, NULL, "stats_drvr_sds");
781 children = SYSCTL_CHILDREN(ctx_oid);
783 for (i = 0; i < ha->hw.num_sds_rings; i++) {
785 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str)));
786 snprintf(name_str, sizeof(name_str), "%d", i);
788 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name_str,
789 CTLFLAG_RD, NULL, name_str);
790 node_children = SYSCTL_CHILDREN(ctx_oid);
792 SYSCTL_ADD_QUAD(ctx, node_children,
793 OID_AUTO, "intr_count",
794 CTLFLAG_RD, &ha->hw.sds[i].intr_count,
797 SYSCTL_ADD_UINT(ctx, node_children,
799 CTLFLAG_RD, &ha->hw.sds[i].rx_free,
800 ha->hw.sds[i].rx_free, "rx_free");
806 qlnx_add_drvr_rds_stats(qla_host_t *ha)
808 struct sysctl_ctx_list *ctx;
809 struct sysctl_oid_list *children;
810 struct sysctl_oid_list *node_children;
811 struct sysctl_oid *ctx_oid;
813 uint8_t name_str[16];
815 ctx = device_get_sysctl_ctx(ha->pci_dev);
816 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev));
818 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_drvr_rds",
819 CTLFLAG_RD, NULL, "stats_drvr_rds");
820 children = SYSCTL_CHILDREN(ctx_oid);
822 for (i = 0; i < ha->hw.num_rds_rings; i++) {
824 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str)));
825 snprintf(name_str, sizeof(name_str), "%d", i);
827 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name_str,
828 CTLFLAG_RD, NULL, name_str);
829 node_children = SYSCTL_CHILDREN(ctx_oid);
831 SYSCTL_ADD_QUAD(ctx, node_children,
833 CTLFLAG_RD, &ha->hw.rds[i].count,
836 SYSCTL_ADD_QUAD(ctx, node_children,
837 OID_AUTO, "lro_pkt_count",
838 CTLFLAG_RD, &ha->hw.rds[i].lro_pkt_count,
841 SYSCTL_ADD_QUAD(ctx, node_children,
842 OID_AUTO, "lro_bytes",
843 CTLFLAG_RD, &ha->hw.rds[i].lro_bytes,
851 qlnx_add_drvr_tx_stats(qla_host_t *ha)
853 struct sysctl_ctx_list *ctx;
854 struct sysctl_oid_list *children;
855 struct sysctl_oid_list *node_children;
856 struct sysctl_oid *ctx_oid;
858 uint8_t name_str[16];
860 ctx = device_get_sysctl_ctx(ha->pci_dev);
861 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev));
863 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_drvr_xmt",
864 CTLFLAG_RD, NULL, "stats_drvr_xmt");
865 children = SYSCTL_CHILDREN(ctx_oid);
867 for (i = 0; i < ha->hw.num_tx_rings; i++) {
869 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str)));
870 snprintf(name_str, sizeof(name_str), "%d", i);
872 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name_str,
873 CTLFLAG_RD, NULL, name_str);
874 node_children = SYSCTL_CHILDREN(ctx_oid);
876 SYSCTL_ADD_QUAD(ctx, node_children,
878 CTLFLAG_RD, &ha->tx_ring[i].count,
881 #ifdef QL_ENABLE_ISCSI_TLV
882 SYSCTL_ADD_QUAD(ctx, node_children,
883 OID_AUTO, "iscsi_pkt_count",
884 CTLFLAG_RD, &ha->tx_ring[i].iscsi_pkt_count,
886 #endif /* #ifdef QL_ENABLE_ISCSI_TLV */
893 qlnx_add_drvr_stats_sysctls(qla_host_t *ha)
895 qlnx_add_drvr_sds_stats(ha);
896 qlnx_add_drvr_rds_stats(ha);
897 qlnx_add_drvr_tx_stats(ha);
902 * Name: ql_hw_add_sysctls
903 * Function: Add P3Plus specific sysctls
906 ql_hw_add_sysctls(qla_host_t *ha)
912 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
913 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
914 OID_AUTO, "num_rds_rings", CTLFLAG_RD, &ha->hw.num_rds_rings,
915 ha->hw.num_rds_rings, "Number of Rcv Descriptor Rings");
917 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
918 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
919 OID_AUTO, "num_sds_rings", CTLFLAG_RD, &ha->hw.num_sds_rings,
920 ha->hw.num_sds_rings, "Number of Status Descriptor Rings");
922 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
923 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
924 OID_AUTO, "num_tx_rings", CTLFLAG_RD, &ha->hw.num_tx_rings,
925 ha->hw.num_tx_rings, "Number of Transmit Rings");
927 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
928 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
929 OID_AUTO, "tx_ring_index", CTLFLAG_RW, &ha->txr_idx,
930 ha->txr_idx, "Tx Ring Used");
932 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
933 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
934 OID_AUTO, "max_tx_segs", CTLFLAG_RD, &ha->hw.max_tx_segs,
935 ha->hw.max_tx_segs, "Max # of Segments in a non-TSO pkt");
937 ha->hw.sds_cidx_thres = 32;
938 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
939 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
940 OID_AUTO, "sds_cidx_thres", CTLFLAG_RW, &ha->hw.sds_cidx_thres,
941 ha->hw.sds_cidx_thres,
942 "Number of SDS entries to process before updating"
943 " SDS Ring Consumer Index");
945 ha->hw.rds_pidx_thres = 32;
946 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
947 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
948 OID_AUTO, "rds_pidx_thres", CTLFLAG_RW, &ha->hw.rds_pidx_thres,
949 ha->hw.rds_pidx_thres,
950 "Number of Rcv Rings Entries to post before updating"
951 " RDS Ring Producer Index");
953 ha->hw.rcv_intr_coalesce = (3 << 16) | 256;
954 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
955 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
956 OID_AUTO, "rcv_intr_coalesce", CTLFLAG_RW,
957 &ha->hw.rcv_intr_coalesce,
958 ha->hw.rcv_intr_coalesce,
959 "Rcv Intr Coalescing Parameters\n"
960 "\tbits 15:0 max packets\n"
961 "\tbits 31:16 max micro-seconds to wait\n"
963 "\tifconfig <if> down && ifconfig <if> up\n"
964 "\tto take effect \n");
966 ha->hw.xmt_intr_coalesce = (64 << 16) | 64;
967 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
968 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
969 OID_AUTO, "xmt_intr_coalesce", CTLFLAG_RW,
970 &ha->hw.xmt_intr_coalesce,
971 ha->hw.xmt_intr_coalesce,
972 "Xmt Intr Coalescing Parameters\n"
973 "\tbits 15:0 max packets\n"
974 "\tbits 31:16 max micro-seconds to wait\n"
976 "\tifconfig <if> down && ifconfig <if> up\n"
977 "\tto take effect \n");
979 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
980 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
981 OID_AUTO, "port_cfg", CTLTYPE_INT | CTLFLAG_RW,
983 qla_sysctl_port_cfg, "I",
984 "Set Port Configuration if values below "
985 "otherwise Get Port Configuration\n"
986 "\tBits 0-3 ; 1 = DCBX Enable; 0 = DCBX Disable\n"
987 "\tBits 4-7 : 0 = no pause; 1 = std ; 2 = ppm \n"
988 "\tBits 8-11: std pause cfg; 0 = xmt and rcv;"
989 " 1 = xmt only; 2 = rcv only;\n"
992 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
993 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
994 OID_AUTO, "set_cam_search_mode", CTLTYPE_INT | CTLFLAG_RW,
996 qla_sysctl_set_cam_search_mode, "I",
997 "Set CAM Search Mode"
998 "\t 1 = search mode internal\n"
999 "\t 2 = search mode auto\n");
1001 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1002 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1003 OID_AUTO, "get_cam_search_mode", CTLTYPE_INT | CTLFLAG_RW,
1005 qla_sysctl_get_cam_search_mode, "I",
1006 "Get CAM Search Mode"
1007 "\t 1 = search mode internal\n"
1008 "\t 2 = search mode auto\n");
1010 ha->hw.enable_9kb = 1;
1012 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
1013 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1014 OID_AUTO, "enable_9kb", CTLFLAG_RW, &ha->hw.enable_9kb,
1015 ha->hw.enable_9kb, "Enable 9Kbyte Buffers when MTU = 9000");
1017 ha->hw.enable_hw_lro = 1;
1019 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
1020 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1021 OID_AUTO, "enable_hw_lro", CTLFLAG_RW, &ha->hw.enable_hw_lro,
1022 ha->hw.enable_hw_lro, "Enable Hardware LRO; Default is true \n"
1023 "\t 1 : Hardware LRO if LRO is enabled\n"
1024 "\t 0 : Software LRO if LRO is enabled\n"
1025 "\t Any change requires ifconfig down/up to take effect\n"
1026 "\t Note that LRO may be turned off/on via ifconfig\n");
1028 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
1029 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1030 OID_AUTO, "sp_log_index", CTLFLAG_RW, &ha->hw.sp_log_index,
1031 ha->hw.sp_log_index, "sp_log_index");
1033 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
1034 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1035 OID_AUTO, "sp_log_stop", CTLFLAG_RW, &ha->hw.sp_log_stop,
1036 ha->hw.sp_log_stop, "sp_log_stop");
1038 ha->hw.sp_log_stop_events = 0;
1040 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
1041 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1042 OID_AUTO, "sp_log_stop_events", CTLFLAG_RW,
1043 &ha->hw.sp_log_stop_events,
1044 ha->hw.sp_log_stop_events, "Slow path event log is stopped"
1045 " when OR of the following events occur \n"
1046 "\t 0x01 : Heart beat Failure\n"
1047 "\t 0x02 : Temperature Failure\n"
1048 "\t 0x04 : HW Initialization Failure\n"
1049 "\t 0x08 : Interface Initialization Failure\n"
1050 "\t 0x10 : Error Recovery Failure\n");
1052 ha->hw.mdump_active = 0;
1053 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
1054 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1055 OID_AUTO, "minidump_active", CTLFLAG_RW, &ha->hw.mdump_active,
1056 ha->hw.mdump_active,
1057 "Minidump retrieval is Active");
1059 ha->hw.mdump_done = 0;
1060 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
1061 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1062 OID_AUTO, "mdump_done", CTLFLAG_RW,
1063 &ha->hw.mdump_done, ha->hw.mdump_done,
1064 "Minidump has been done and available for retrieval");
1066 ha->hw.mdump_capture_mask = 0xF;
1067 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
1068 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1069 OID_AUTO, "minidump_capture_mask", CTLFLAG_RW,
1070 &ha->hw.mdump_capture_mask, ha->hw.mdump_capture_mask,
1071 "Minidump capture mask");
1075 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
1076 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1077 OID_AUTO, "err_inject",
1078 CTLFLAG_RW, &ha->err_inject, ha->err_inject,
1079 "Error to be injected\n"
1080 "\t\t\t 0: No Errors\n"
1081 "\t\t\t 1: rcv: rxb struct invalid\n"
1082 "\t\t\t 2: rcv: mp == NULL\n"
1083 "\t\t\t 3: lro: rxb struct invalid\n"
1084 "\t\t\t 4: lro: mp == NULL\n"
1085 "\t\t\t 5: rcv: num handles invalid\n"
1086 "\t\t\t 6: reg: indirect reg rd_wr failure\n"
1087 "\t\t\t 7: ocm: offchip memory rd_wr failure\n"
1088 "\t\t\t 8: mbx: mailbox command failure\n"
1089 "\t\t\t 9: heartbeat failure\n"
1090 "\t\t\t A: temperature failure\n"
1091 "\t\t\t 11: m_getcl or m_getjcl failure\n"
1092 "\t\t\t 13: Invalid Descriptor Count in SGL Receive\n"
1093 "\t\t\t 14: Invalid Descriptor Count in LRO Receive\n"
1094 "\t\t\t 15: peer port error recovery failure\n"
1095 "\t\t\t 16: tx_buf[next_prod_index].mbuf != NULL\n" );
1097 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1098 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1099 OID_AUTO, "peg_stop", CTLTYPE_INT | CTLFLAG_RW,
1101 qla_sysctl_stop_pegs, "I", "Peg Stop");
1103 #endif /* #ifdef QL_DBG */
1105 ha->hw.user_pri_nic = 0;
1106 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
1107 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1108 OID_AUTO, "user_pri_nic", CTLFLAG_RW, &ha->hw.user_pri_nic,
1109 ha->hw.user_pri_nic,
1110 "VLAN Tag User Priority for Normal Ethernet Packets");
1112 ha->hw.user_pri_iscsi = 4;
1113 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
1114 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1115 OID_AUTO, "user_pri_iscsi", CTLFLAG_RW, &ha->hw.user_pri_iscsi,
1116 ha->hw.user_pri_iscsi,
1117 "VLAN Tag User Priority for iSCSI Packets");
1119 qlnx_add_hw_stats_sysctls(ha);
1120 qlnx_add_drvr_stats_sysctls(ha);
1126 ql_hw_link_status(qla_host_t *ha)
1128 device_printf(ha->pci_dev, "cable_oui\t\t 0x%08x\n", ha->hw.cable_oui);
1130 if (ha->hw.link_up) {
1131 device_printf(ha->pci_dev, "link Up\n");
1133 device_printf(ha->pci_dev, "link Down\n");
1136 if (ha->hw.fduplex) {
1137 device_printf(ha->pci_dev, "Full Duplex\n");
1139 device_printf(ha->pci_dev, "Half Duplex\n");
1142 if (ha->hw.autoneg) {
1143 device_printf(ha->pci_dev, "Auto Negotiation Enabled\n");
1145 device_printf(ha->pci_dev, "Auto Negotiation Disabled\n");
1148 switch (ha->hw.link_speed) {
1150 device_printf(ha->pci_dev, "link speed\t\t 10Gps\n");
1154 device_printf(ha->pci_dev, "link speed\t\t 1Gps\n");
1158 device_printf(ha->pci_dev, "link speed\t\t 100Mbps\n");
1162 device_printf(ha->pci_dev, "link speed\t\t Unknown\n");
1166 switch (ha->hw.module_type) {
1169 device_printf(ha->pci_dev, "Module Type 10GBase-LRM\n");
1173 device_printf(ha->pci_dev, "Module Type 10GBase-LR\n");
1177 device_printf(ha->pci_dev, "Module Type 10GBase-SR\n");
1181 device_printf(ha->pci_dev,
1182 "Module Type 10GE Passive Copper(Compliant)[%d m]\n",
1183 ha->hw.cable_length);
1187 device_printf(ha->pci_dev, "Module Type 10GE Active"
1188 " Limiting Copper(Compliant)[%d m]\n",
1189 ha->hw.cable_length);
1193 device_printf(ha->pci_dev,
1194 "Module Type 10GE Passive Copper"
1195 " (Legacy, Best Effort)[%d m]\n",
1196 ha->hw.cable_length);
1200 device_printf(ha->pci_dev, "Module Type 1000Base-SX\n");
1204 device_printf(ha->pci_dev, "Module Type 1000Base-LX\n");
1208 device_printf(ha->pci_dev, "Module Type 1000Base-CX\n");
1212 device_printf(ha->pci_dev, "Module Type 1000Base-T\n");
1216 device_printf(ha->pci_dev, "Module Type 1GE Passive Copper"
1217 "(Legacy, Best Effort)\n");
1221 device_printf(ha->pci_dev, "Unknown Module Type 0x%x\n",
1222 ha->hw.module_type);
1226 if (ha->hw.link_faults == 1)
1227 device_printf(ha->pci_dev, "SFP Power Fault\n");
1232 * Function: Frees the DMA'able memory allocated in ql_alloc_dma()
1235 ql_free_dma(qla_host_t *ha)
1239 if (ha->hw.dma_buf.flags.sds_ring) {
1240 for (i = 0; i < ha->hw.num_sds_rings; i++) {
1241 ql_free_dmabuf(ha, &ha->hw.dma_buf.sds_ring[i]);
1243 ha->hw.dma_buf.flags.sds_ring = 0;
1246 if (ha->hw.dma_buf.flags.rds_ring) {
1247 for (i = 0; i < ha->hw.num_rds_rings; i++) {
1248 ql_free_dmabuf(ha, &ha->hw.dma_buf.rds_ring[i]);
1250 ha->hw.dma_buf.flags.rds_ring = 0;
1253 if (ha->hw.dma_buf.flags.tx_ring) {
1254 ql_free_dmabuf(ha, &ha->hw.dma_buf.tx_ring);
1255 ha->hw.dma_buf.flags.tx_ring = 0;
1257 ql_minidump_free(ha);
1261 * Name: ql_alloc_dma
1262 * Function: Allocates DMA'able memory for Tx/Rx Rings, Tx/Rx Contexts.
1265 ql_alloc_dma(qla_host_t *ha)
1268 uint32_t i, j, size, tx_ring_size;
1270 qla_hw_tx_cntxt_t *tx_cntxt;
1276 QL_DPRINT2(ha, (dev, "%s: enter\n", __func__));
1280 * Allocate Transmit Ring
1282 tx_ring_size = (sizeof(q80_tx_cmd_t) * NUM_TX_DESCRIPTORS);
1283 size = (tx_ring_size * ha->hw.num_tx_rings);
1285 hw->dma_buf.tx_ring.alignment = 8;
1286 hw->dma_buf.tx_ring.size = size + PAGE_SIZE;
1288 if (ql_alloc_dmabuf(ha, &hw->dma_buf.tx_ring)) {
1289 device_printf(dev, "%s: tx ring alloc failed\n", __func__);
1290 goto ql_alloc_dma_exit;
1293 vaddr = (uint8_t *)hw->dma_buf.tx_ring.dma_b;
1294 paddr = hw->dma_buf.tx_ring.dma_addr;
1296 for (i = 0; i < ha->hw.num_tx_rings; i++) {
1297 tx_cntxt = (qla_hw_tx_cntxt_t *)&hw->tx_cntxt[i];
1299 tx_cntxt->tx_ring_base = (q80_tx_cmd_t *)vaddr;
1300 tx_cntxt->tx_ring_paddr = paddr;
1302 vaddr += tx_ring_size;
1303 paddr += tx_ring_size;
1306 for (i = 0; i < ha->hw.num_tx_rings; i++) {
1307 tx_cntxt = (qla_hw_tx_cntxt_t *)&hw->tx_cntxt[i];
1309 tx_cntxt->tx_cons = (uint32_t *)vaddr;
1310 tx_cntxt->tx_cons_paddr = paddr;
1312 vaddr += sizeof (uint32_t);
1313 paddr += sizeof (uint32_t);
1316 ha->hw.dma_buf.flags.tx_ring = 1;
1318 QL_DPRINT2(ha, (dev, "%s: tx_ring phys %p virt %p\n",
1319 __func__, (void *)(hw->dma_buf.tx_ring.dma_addr),
1320 hw->dma_buf.tx_ring.dma_b));
1322 * Allocate Receive Descriptor Rings
1325 for (i = 0; i < hw->num_rds_rings; i++) {
1327 hw->dma_buf.rds_ring[i].alignment = 8;
1328 hw->dma_buf.rds_ring[i].size =
1329 (sizeof(q80_recv_desc_t)) * NUM_RX_DESCRIPTORS;
1331 if (ql_alloc_dmabuf(ha, &hw->dma_buf.rds_ring[i])) {
1332 device_printf(dev, "%s: rds ring[%d] alloc failed\n",
1335 for (j = 0; j < i; j++)
1336 ql_free_dmabuf(ha, &hw->dma_buf.rds_ring[j]);
1338 goto ql_alloc_dma_exit;
1340 QL_DPRINT4(ha, (dev, "%s: rx_ring[%d] phys %p virt %p\n",
1341 __func__, i, (void *)(hw->dma_buf.rds_ring[i].dma_addr),
1342 hw->dma_buf.rds_ring[i].dma_b));
1345 hw->dma_buf.flags.rds_ring = 1;
1348 * Allocate Status Descriptor Rings
1351 for (i = 0; i < hw->num_sds_rings; i++) {
1352 hw->dma_buf.sds_ring[i].alignment = 8;
1353 hw->dma_buf.sds_ring[i].size =
1354 (sizeof(q80_stat_desc_t)) * NUM_STATUS_DESCRIPTORS;
1356 if (ql_alloc_dmabuf(ha, &hw->dma_buf.sds_ring[i])) {
1357 device_printf(dev, "%s: sds ring alloc failed\n",
1360 for (j = 0; j < i; j++)
1361 ql_free_dmabuf(ha, &hw->dma_buf.sds_ring[j]);
1363 goto ql_alloc_dma_exit;
1365 QL_DPRINT4(ha, (dev, "%s: sds_ring[%d] phys %p virt %p\n",
1367 (void *)(hw->dma_buf.sds_ring[i].dma_addr),
1368 hw->dma_buf.sds_ring[i].dma_b));
1370 for (i = 0; i < hw->num_sds_rings; i++) {
1371 hw->sds[i].sds_ring_base =
1372 (q80_stat_desc_t *)hw->dma_buf.sds_ring[i].dma_b;
1375 hw->dma_buf.flags.sds_ring = 1;
1384 #define Q8_MBX_MSEC_DELAY 5000
1387 qla_mbx_cmd(qla_host_t *ha, uint32_t *h_mbox, uint32_t n_hmbox,
1388 uint32_t *fw_mbox, uint32_t n_fwmbox, uint32_t no_pause)
1393 uint64_t start_usecs;
1397 ql_sp_log(ha, 0, 5, no_pause, h_mbox[0], h_mbox[1], h_mbox[2], h_mbox[3]);
1399 if (ha->offline || ha->qla_initiate_recovery) {
1400 ql_sp_log(ha, 1, 2, ha->offline, ha->qla_initiate_recovery, 0, 0, 0);
1401 goto exit_qla_mbx_cmd;
1404 if (((ha->err_inject & 0xFFFF) == INJCT_MBX_CMD_FAILURE) &&
1405 (((ha->err_inject & ~0xFFFF) == ((h_mbox[0] & 0xFFFF) << 16))||
1406 !(ha->err_inject & ~0xFFFF))) {
1408 QL_INITIATE_RECOVERY(ha);
1409 goto exit_qla_mbx_cmd;
1412 start_usecs = qla_get_usec_timestamp();
1417 i = Q8_MBX_MSEC_DELAY;
1421 if (ha->qla_initiate_recovery) {
1422 ql_sp_log(ha, 2, 1, ha->qla_initiate_recovery, 0, 0, 0, 0);
1426 data = READ_REG32(ha, Q8_HOST_MBOX_CNTRL);
1432 qla_mdelay(__func__, 1);
1438 device_printf(ha->pci_dev, "%s: host_mbx_cntrl 0x%08x\n",
1440 ql_sp_log(ha, 3, 1, data, 0, 0, 0, 0);
1442 ha->hw.mbx_comp_msecs[(Q8_MBX_COMP_MSECS - 2)]++;
1443 QL_INITIATE_RECOVERY(ha);
1444 goto exit_qla_mbx_cmd;
1447 for (i = 0; i < n_hmbox; i++) {
1448 WRITE_REG32(ha, (Q8_HOST_MBOX0 + (i << 2)), *h_mbox);
1452 WRITE_REG32(ha, Q8_HOST_MBOX_CNTRL, 0x1);
1455 i = Q8_MBX_MSEC_DELAY;
1458 if (ha->qla_initiate_recovery) {
1459 ql_sp_log(ha, 4, 1, ha->qla_initiate_recovery, 0, 0, 0, 0);
1463 data = READ_REG32(ha, Q8_FW_MBOX_CNTRL);
1465 if ((data & 0x3) == 1) {
1466 data = READ_REG32(ha, Q8_FW_MBOX0);
1467 if ((data & 0xF000) != 0x8000)
1473 qla_mdelay(__func__, 1);
1478 device_printf(ha->pci_dev, "%s: fw_mbx_cntrl 0x%08x\n",
1480 ql_sp_log(ha, 5, 1, data, 0, 0, 0, 0);
1482 ha->hw.mbx_comp_msecs[(Q8_MBX_COMP_MSECS - 1)]++;
1483 QL_INITIATE_RECOVERY(ha);
1484 goto exit_qla_mbx_cmd;
1487 for (i = 0; i < n_fwmbox; i++) {
1489 if (ha->qla_initiate_recovery) {
1490 ql_sp_log(ha, 6, 1, ha->qla_initiate_recovery, 0, 0, 0, 0);
1494 *fw_mbox++ = READ_REG32(ha, (Q8_FW_MBOX0 + (i << 2)));
1497 WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0);
1498 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
1500 end_usecs = qla_get_usec_timestamp();
1502 if (end_usecs > start_usecs) {
1503 msecs_200 = (end_usecs - start_usecs)/(1000 * 200);
1506 ha->hw.mbx_comp_msecs[msecs_200]++;
1507 else if (msecs_200 < 20)
1508 ha->hw.mbx_comp_msecs[15]++;
1510 device_printf(ha->pci_dev, "%s: [%ld, %ld] %ld\n", __func__,
1511 start_usecs, end_usecs, msecs_200);
1512 ha->hw.mbx_comp_msecs[16]++;
1515 ql_sp_log(ha, 7, 5, fw_mbox[0], fw_mbox[1], fw_mbox[2], fw_mbox[3], fw_mbox[4]);
1523 qla_get_nic_partition(qla_host_t *ha, uint32_t *supports_9kb,
1526 uint32_t *mbox, err;
1527 device_t dev = ha->pci_dev;
1529 bzero(ha->hw.mbox, (sizeof (uint32_t) * Q8_NUM_MBOX));
1533 mbox[0] = Q8_MBX_GET_NIC_PARTITION | (0x2 << 16) | (0x2 << 29);
1535 if (qla_mbx_cmd(ha, mbox, 2, mbox, 19, 0)) {
1536 device_printf(dev, "%s: failed0\n", __func__);
1539 err = mbox[0] >> 25;
1541 if (supports_9kb != NULL) {
1542 if (mbox[16] & 0x80) /* bit 7 of mbox 16 */
1548 if (num_rcvq != NULL)
1549 *num_rcvq = ((mbox[6] >> 16) & 0xFFFF);
1551 if ((err != 1) && (err != 0)) {
1552 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
1559 qla_config_intr_cntxt(qla_host_t *ha, uint32_t start_idx, uint32_t num_intrs,
1563 device_t dev = ha->pci_dev;
1564 q80_config_intr_t *c_intr;
1565 q80_config_intr_rsp_t *c_intr_rsp;
1567 c_intr = (q80_config_intr_t *)ha->hw.mbox;
1568 bzero(c_intr, (sizeof (q80_config_intr_t)));
1570 c_intr->opcode = Q8_MBX_CONFIG_INTR;
1572 c_intr->count_version = (sizeof (q80_config_intr_t) >> 2);
1573 c_intr->count_version |= Q8_MBX_CMD_VERSION;
1575 c_intr->nentries = num_intrs;
1577 for (i = 0; i < num_intrs; i++) {
1579 c_intr->intr[i].cmd_type = Q8_MBX_CONFIG_INTR_CREATE;
1580 c_intr->intr[i].msix_index = start_idx + 1 + i;
1582 c_intr->intr[i].cmd_type = Q8_MBX_CONFIG_INTR_DELETE;
1583 c_intr->intr[i].msix_index =
1584 ha->hw.intr_id[(start_idx + i)];
1587 c_intr->intr[i].cmd_type |= Q8_MBX_CONFIG_INTR_TYPE_MSI_X;
1590 if (qla_mbx_cmd(ha, (uint32_t *)c_intr,
1591 (sizeof (q80_config_intr_t) >> 2),
1592 ha->hw.mbox, (sizeof (q80_config_intr_rsp_t) >> 2), 0)) {
1593 device_printf(dev, "%s: %s failed0\n", __func__,
1594 (create ? "create" : "delete"));
1598 c_intr_rsp = (q80_config_intr_rsp_t *)ha->hw.mbox;
1600 err = Q8_MBX_RSP_STATUS(c_intr_rsp->regcnt_status);
1603 device_printf(dev, "%s: %s failed1 [0x%08x, %d]\n", __func__,
1604 (create ? "create" : "delete"), err, c_intr_rsp->nentries);
1606 for (i = 0; i < c_intr_rsp->nentries; i++) {
1607 device_printf(dev, "%s: [%d]:[0x%x 0x%x 0x%x]\n",
1609 c_intr_rsp->intr[i].status,
1610 c_intr_rsp->intr[i].intr_id,
1611 c_intr_rsp->intr[i].intr_src);
1617 for (i = 0; ((i < num_intrs) && create); i++) {
1618 if (!c_intr_rsp->intr[i].status) {
1619 ha->hw.intr_id[(start_idx + i)] =
1620 c_intr_rsp->intr[i].intr_id;
1621 ha->hw.intr_src[(start_idx + i)] =
1622 c_intr_rsp->intr[i].intr_src;
1630 * Name: qla_config_rss
1631 * Function: Configure RSS for the context/interface.
1633 static const uint64_t rss_key[] = { 0xbeac01fa6a42b73bULL,
1634 0x8030f20c77cb2da3ULL,
1635 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
1636 0x255b0ec26d5a56daULL };
1639 qla_config_rss(qla_host_t *ha, uint16_t cntxt_id)
1641 q80_config_rss_t *c_rss;
1642 q80_config_rss_rsp_t *c_rss_rsp;
1644 device_t dev = ha->pci_dev;
1646 c_rss = (q80_config_rss_t *)ha->hw.mbox;
1647 bzero(c_rss, (sizeof (q80_config_rss_t)));
1649 c_rss->opcode = Q8_MBX_CONFIG_RSS;
1651 c_rss->count_version = (sizeof (q80_config_rss_t) >> 2);
1652 c_rss->count_version |= Q8_MBX_CMD_VERSION;
1654 c_rss->hash_type = (Q8_MBX_RSS_HASH_TYPE_IPV4_TCP_IP |
1655 Q8_MBX_RSS_HASH_TYPE_IPV6_TCP_IP);
1656 //c_rss->hash_type = (Q8_MBX_RSS_HASH_TYPE_IPV4_TCP |
1657 // Q8_MBX_RSS_HASH_TYPE_IPV6_TCP);
1659 c_rss->flags = Q8_MBX_RSS_FLAGS_ENABLE_RSS;
1660 c_rss->flags |= Q8_MBX_RSS_FLAGS_USE_IND_TABLE;
1662 c_rss->indtbl_mask = Q8_MBX_RSS_INDTBL_MASK;
1664 c_rss->indtbl_mask |= Q8_MBX_RSS_FLAGS_MULTI_RSS_VALID;
1665 c_rss->flags |= Q8_MBX_RSS_FLAGS_TYPE_CRSS;
1667 c_rss->cntxt_id = cntxt_id;
1669 for (i = 0; i < 5; i++) {
1670 c_rss->rss_key[i] = rss_key[i];
1673 if (qla_mbx_cmd(ha, (uint32_t *)c_rss,
1674 (sizeof (q80_config_rss_t) >> 2),
1675 ha->hw.mbox, (sizeof(q80_config_rss_rsp_t) >> 2), 0)) {
1676 device_printf(dev, "%s: failed0\n", __func__);
1679 c_rss_rsp = (q80_config_rss_rsp_t *)ha->hw.mbox;
1681 err = Q8_MBX_RSP_STATUS(c_rss_rsp->regcnt_status);
1684 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
1691 qla_set_rss_ind_table(qla_host_t *ha, uint32_t start_idx, uint32_t count,
1692 uint16_t cntxt_id, uint8_t *ind_table)
1694 q80_config_rss_ind_table_t *c_rss_ind;
1695 q80_config_rss_ind_table_rsp_t *c_rss_ind_rsp;
1697 device_t dev = ha->pci_dev;
1699 if ((count > Q8_RSS_IND_TBL_SIZE) ||
1700 ((start_idx + count - 1) > Q8_RSS_IND_TBL_MAX_IDX)) {
1701 device_printf(dev, "%s: illegal count [%d, %d]\n", __func__,
1706 c_rss_ind = (q80_config_rss_ind_table_t *)ha->hw.mbox;
1707 bzero(c_rss_ind, sizeof (q80_config_rss_ind_table_t));
1709 c_rss_ind->opcode = Q8_MBX_CONFIG_RSS_TABLE;
1710 c_rss_ind->count_version = (sizeof (q80_config_rss_ind_table_t) >> 2);
1711 c_rss_ind->count_version |= Q8_MBX_CMD_VERSION;
1713 c_rss_ind->start_idx = start_idx;
1714 c_rss_ind->end_idx = start_idx + count - 1;
1715 c_rss_ind->cntxt_id = cntxt_id;
1716 bcopy(ind_table, c_rss_ind->ind_table, count);
1718 if (qla_mbx_cmd(ha, (uint32_t *)c_rss_ind,
1719 (sizeof (q80_config_rss_ind_table_t) >> 2), ha->hw.mbox,
1720 (sizeof(q80_config_rss_ind_table_rsp_t) >> 2), 0)) {
1721 device_printf(dev, "%s: failed0\n", __func__);
1725 c_rss_ind_rsp = (q80_config_rss_ind_table_rsp_t *)ha->hw.mbox;
1726 err = Q8_MBX_RSP_STATUS(c_rss_ind_rsp->regcnt_status);
1729 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
1736 * Name: qla_config_intr_coalesce
1737 * Function: Configure Interrupt Coalescing.
1740 qla_config_intr_coalesce(qla_host_t *ha, uint16_t cntxt_id, int tenable,
1743 q80_config_intr_coalesc_t *intrc;
1744 q80_config_intr_coalesc_rsp_t *intrc_rsp;
1746 device_t dev = ha->pci_dev;
1748 intrc = (q80_config_intr_coalesc_t *)ha->hw.mbox;
1749 bzero(intrc, (sizeof (q80_config_intr_coalesc_t)));
1751 intrc->opcode = Q8_MBX_CONFIG_INTR_COALESCE;
1752 intrc->count_version = (sizeof (q80_config_intr_coalesc_t) >> 2);
1753 intrc->count_version |= Q8_MBX_CMD_VERSION;
1756 intrc->flags = Q8_MBX_INTRC_FLAGS_RCV;
1757 intrc->max_pkts = ha->hw.rcv_intr_coalesce & 0xFFFF;
1758 intrc->max_mswait = (ha->hw.rcv_intr_coalesce >> 16) & 0xFFFF;
1760 intrc->flags = Q8_MBX_INTRC_FLAGS_XMT;
1761 intrc->max_pkts = ha->hw.xmt_intr_coalesce & 0xFFFF;
1762 intrc->max_mswait = (ha->hw.xmt_intr_coalesce >> 16) & 0xFFFF;
1765 intrc->cntxt_id = cntxt_id;
1768 intrc->flags |= Q8_MBX_INTRC_FLAGS_PERIODIC;
1769 intrc->timer_type = Q8_MBX_INTRC_TIMER_PERIODIC;
1771 for (i = 0; i < ha->hw.num_sds_rings; i++) {
1772 intrc->sds_ring_mask |= (1 << i);
1774 intrc->ms_timeout = 1000;
1777 if (qla_mbx_cmd(ha, (uint32_t *)intrc,
1778 (sizeof (q80_config_intr_coalesc_t) >> 2),
1779 ha->hw.mbox, (sizeof(q80_config_intr_coalesc_rsp_t) >> 2), 0)) {
1780 device_printf(dev, "%s: failed0\n", __func__);
1783 intrc_rsp = (q80_config_intr_coalesc_rsp_t *)ha->hw.mbox;
1785 err = Q8_MBX_RSP_STATUS(intrc_rsp->regcnt_status);
1788 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
1797 * Name: qla_config_mac_addr
1798 * Function: binds a MAC address to the context/interface.
1799 * Can be unicast, multicast or broadcast.
1802 qla_config_mac_addr(qla_host_t *ha, uint8_t *mac_addr, uint32_t add_mac,
1805 q80_config_mac_addr_t *cmac;
1806 q80_config_mac_addr_rsp_t *cmac_rsp;
1808 device_t dev = ha->pci_dev;
1810 uint8_t *mac_cpy = mac_addr;
1812 if (num_mac > Q8_MAX_MAC_ADDRS) {
1813 device_printf(dev, "%s: %s num_mac [0x%x] > Q8_MAX_MAC_ADDRS\n",
1814 __func__, (add_mac ? "Add" : "Del"), num_mac);
1818 cmac = (q80_config_mac_addr_t *)ha->hw.mbox;
1819 bzero(cmac, (sizeof (q80_config_mac_addr_t)));
1821 cmac->opcode = Q8_MBX_CONFIG_MAC_ADDR;
1822 cmac->count_version = sizeof (q80_config_mac_addr_t) >> 2;
1823 cmac->count_version |= Q8_MBX_CMD_VERSION;
1826 cmac->cmd = Q8_MBX_CMAC_CMD_ADD_MAC_ADDR;
1828 cmac->cmd = Q8_MBX_CMAC_CMD_DEL_MAC_ADDR;
1830 cmac->cmd |= Q8_MBX_CMAC_CMD_CAM_INGRESS;
1832 cmac->nmac_entries = num_mac;
1833 cmac->cntxt_id = ha->hw.rcv_cntxt_id;
1835 for (i = 0; i < num_mac; i++) {
1836 bcopy(mac_addr, cmac->mac_addr[i].addr, Q8_ETHER_ADDR_LEN);
1837 mac_addr = mac_addr + ETHER_ADDR_LEN;
1840 if (qla_mbx_cmd(ha, (uint32_t *)cmac,
1841 (sizeof (q80_config_mac_addr_t) >> 2),
1842 ha->hw.mbox, (sizeof(q80_config_mac_addr_rsp_t) >> 2), 1)) {
1843 device_printf(dev, "%s: %s failed0\n", __func__,
1844 (add_mac ? "Add" : "Del"));
1847 cmac_rsp = (q80_config_mac_addr_rsp_t *)ha->hw.mbox;
1849 err = Q8_MBX_RSP_STATUS(cmac_rsp->regcnt_status);
1852 device_printf(dev, "%s: %s failed1 [0x%08x]\n", __func__,
1853 (add_mac ? "Add" : "Del"), err);
1854 for (i = 0; i < num_mac; i++) {
1855 device_printf(dev, "%s: %02x:%02x:%02x:%02x:%02x:%02x\n",
1856 __func__, mac_cpy[0], mac_cpy[1], mac_cpy[2],
1857 mac_cpy[3], mac_cpy[4], mac_cpy[5]);
1858 mac_cpy += ETHER_ADDR_LEN;
1868 * Name: qla_set_mac_rcv_mode
1869 * Function: Enable/Disable AllMulticast and Promiscous Modes.
1872 qla_set_mac_rcv_mode(qla_host_t *ha, uint32_t mode)
1874 q80_config_mac_rcv_mode_t *rcv_mode;
1876 q80_config_mac_rcv_mode_rsp_t *rcv_mode_rsp;
1877 device_t dev = ha->pci_dev;
1879 rcv_mode = (q80_config_mac_rcv_mode_t *)ha->hw.mbox;
1880 bzero(rcv_mode, (sizeof (q80_config_mac_rcv_mode_t)));
1882 rcv_mode->opcode = Q8_MBX_CONFIG_MAC_RX_MODE;
1883 rcv_mode->count_version = sizeof (q80_config_mac_rcv_mode_t) >> 2;
1884 rcv_mode->count_version |= Q8_MBX_CMD_VERSION;
1886 rcv_mode->mode = mode;
1888 rcv_mode->cntxt_id = ha->hw.rcv_cntxt_id;
1890 if (qla_mbx_cmd(ha, (uint32_t *)rcv_mode,
1891 (sizeof (q80_config_mac_rcv_mode_t) >> 2),
1892 ha->hw.mbox, (sizeof(q80_config_mac_rcv_mode_rsp_t) >> 2), 1)) {
1893 device_printf(dev, "%s: failed0\n", __func__);
1896 rcv_mode_rsp = (q80_config_mac_rcv_mode_rsp_t *)ha->hw.mbox;
1898 err = Q8_MBX_RSP_STATUS(rcv_mode_rsp->regcnt_status);
1901 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
1909 ql_set_promisc(qla_host_t *ha)
1913 ha->hw.mac_rcv_mode |= Q8_MBX_MAC_RCV_PROMISC_ENABLE;
1914 ret = qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode);
1919 qla_reset_promisc(qla_host_t *ha)
1921 ha->hw.mac_rcv_mode &= ~Q8_MBX_MAC_RCV_PROMISC_ENABLE;
1922 (void)qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode);
1926 ql_set_allmulti(qla_host_t *ha)
1930 ha->hw.mac_rcv_mode |= Q8_MBX_MAC_ALL_MULTI_ENABLE;
1931 ret = qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode);
1936 qla_reset_allmulti(qla_host_t *ha)
1938 ha->hw.mac_rcv_mode &= ~Q8_MBX_MAC_ALL_MULTI_ENABLE;
1939 (void)qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode);
1943 * Name: ql_set_max_mtu
1945 * Sets the maximum transfer unit size for the specified rcv context.
1948 ql_set_max_mtu(qla_host_t *ha, uint32_t mtu, uint16_t cntxt_id)
1951 q80_set_max_mtu_t *max_mtu;
1952 q80_set_max_mtu_rsp_t *max_mtu_rsp;
1957 max_mtu = (q80_set_max_mtu_t *)ha->hw.mbox;
1958 bzero(max_mtu, (sizeof (q80_set_max_mtu_t)));
1960 max_mtu->opcode = Q8_MBX_SET_MAX_MTU;
1961 max_mtu->count_version = (sizeof (q80_set_max_mtu_t) >> 2);
1962 max_mtu->count_version |= Q8_MBX_CMD_VERSION;
1964 max_mtu->cntxt_id = cntxt_id;
1967 if (qla_mbx_cmd(ha, (uint32_t *)max_mtu,
1968 (sizeof (q80_set_max_mtu_t) >> 2),
1969 ha->hw.mbox, (sizeof (q80_set_max_mtu_rsp_t) >> 2), 1)) {
1970 device_printf(dev, "%s: failed\n", __func__);
1974 max_mtu_rsp = (q80_set_max_mtu_rsp_t *)ha->hw.mbox;
1976 err = Q8_MBX_RSP_STATUS(max_mtu_rsp->regcnt_status);
1979 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
1986 qla_link_event_req(qla_host_t *ha, uint16_t cntxt_id)
1989 q80_link_event_t *lnk;
1990 q80_link_event_rsp_t *lnk_rsp;
1995 lnk = (q80_link_event_t *)ha->hw.mbox;
1996 bzero(lnk, (sizeof (q80_link_event_t)));
1998 lnk->opcode = Q8_MBX_LINK_EVENT_REQ;
1999 lnk->count_version = (sizeof (q80_link_event_t) >> 2);
2000 lnk->count_version |= Q8_MBX_CMD_VERSION;
2002 lnk->cntxt_id = cntxt_id;
2003 lnk->cmd = Q8_LINK_EVENT_CMD_ENABLE_ASYNC;
2005 if (qla_mbx_cmd(ha, (uint32_t *)lnk, (sizeof (q80_link_event_t) >> 2),
2006 ha->hw.mbox, (sizeof (q80_link_event_rsp_t) >> 2), 0)) {
2007 device_printf(dev, "%s: failed\n", __func__);
2011 lnk_rsp = (q80_link_event_rsp_t *)ha->hw.mbox;
2013 err = Q8_MBX_RSP_STATUS(lnk_rsp->regcnt_status);
2016 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
2023 qla_config_fw_lro(qla_host_t *ha, uint16_t cntxt_id)
2026 q80_config_fw_lro_t *fw_lro;
2027 q80_config_fw_lro_rsp_t *fw_lro_rsp;
2032 fw_lro = (q80_config_fw_lro_t *)ha->hw.mbox;
2033 bzero(fw_lro, sizeof(q80_config_fw_lro_t));
2035 fw_lro->opcode = Q8_MBX_CONFIG_FW_LRO;
2036 fw_lro->count_version = (sizeof (q80_config_fw_lro_t) >> 2);
2037 fw_lro->count_version |= Q8_MBX_CMD_VERSION;
2039 fw_lro->flags |= Q8_MBX_FW_LRO_IPV4 | Q8_MBX_FW_LRO_IPV4_WO_DST_IP_CHK;
2040 fw_lro->flags |= Q8_MBX_FW_LRO_IPV6 | Q8_MBX_FW_LRO_IPV6_WO_DST_IP_CHK;
2042 fw_lro->cntxt_id = cntxt_id;
2044 if (qla_mbx_cmd(ha, (uint32_t *)fw_lro,
2045 (sizeof (q80_config_fw_lro_t) >> 2),
2046 ha->hw.mbox, (sizeof (q80_config_fw_lro_rsp_t) >> 2), 0)) {
2047 device_printf(dev, "%s: failed\n", __func__);
2051 fw_lro_rsp = (q80_config_fw_lro_rsp_t *)ha->hw.mbox;
2053 err = Q8_MBX_RSP_STATUS(fw_lro_rsp->regcnt_status);
2056 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
2063 qla_set_cam_search_mode(qla_host_t *ha, uint32_t search_mode)
2066 q80_hw_config_t *hw_config;
2067 q80_hw_config_rsp_t *hw_config_rsp;
2072 hw_config = (q80_hw_config_t *)ha->hw.mbox;
2073 bzero(hw_config, sizeof (q80_hw_config_t));
2075 hw_config->opcode = Q8_MBX_HW_CONFIG;
2076 hw_config->count_version = Q8_HW_CONFIG_SET_CAM_SEARCH_MODE_COUNT;
2077 hw_config->count_version |= Q8_MBX_CMD_VERSION;
2079 hw_config->cmd = Q8_HW_CONFIG_SET_CAM_SEARCH_MODE;
2081 hw_config->u.set_cam_search_mode.mode = search_mode;
2083 if (qla_mbx_cmd(ha, (uint32_t *)hw_config,
2084 (sizeof (q80_hw_config_t) >> 2),
2085 ha->hw.mbox, (sizeof (q80_hw_config_rsp_t) >> 2), 0)) {
2086 device_printf(dev, "%s: failed\n", __func__);
2089 hw_config_rsp = (q80_hw_config_rsp_t *)ha->hw.mbox;
2091 err = Q8_MBX_RSP_STATUS(hw_config_rsp->regcnt_status);
2094 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
2101 qla_get_cam_search_mode(qla_host_t *ha)
2104 q80_hw_config_t *hw_config;
2105 q80_hw_config_rsp_t *hw_config_rsp;
2110 hw_config = (q80_hw_config_t *)ha->hw.mbox;
2111 bzero(hw_config, sizeof (q80_hw_config_t));
2113 hw_config->opcode = Q8_MBX_HW_CONFIG;
2114 hw_config->count_version = Q8_HW_CONFIG_GET_CAM_SEARCH_MODE_COUNT;
2115 hw_config->count_version |= Q8_MBX_CMD_VERSION;
2117 hw_config->cmd = Q8_HW_CONFIG_GET_CAM_SEARCH_MODE;
2119 if (qla_mbx_cmd(ha, (uint32_t *)hw_config,
2120 (sizeof (q80_hw_config_t) >> 2),
2121 ha->hw.mbox, (sizeof (q80_hw_config_rsp_t) >> 2), 0)) {
2122 device_printf(dev, "%s: failed\n", __func__);
2125 hw_config_rsp = (q80_hw_config_rsp_t *)ha->hw.mbox;
2127 err = Q8_MBX_RSP_STATUS(hw_config_rsp->regcnt_status);
2130 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
2132 device_printf(dev, "%s: cam search mode [0x%08x]\n", __func__,
2133 hw_config_rsp->u.get_cam_search_mode.mode);
2140 qla_get_hw_stats(qla_host_t *ha, uint32_t cmd, uint32_t rsp_size)
2143 q80_get_stats_t *stat;
2144 q80_get_stats_rsp_t *stat_rsp;
2149 stat = (q80_get_stats_t *)ha->hw.mbox;
2150 bzero(stat, (sizeof (q80_get_stats_t)));
2152 stat->opcode = Q8_MBX_GET_STATS;
2153 stat->count_version = 2;
2154 stat->count_version |= Q8_MBX_CMD_VERSION;
2158 if (qla_mbx_cmd(ha, (uint32_t *)stat, 2,
2159 ha->hw.mbox, (rsp_size >> 2), 0)) {
2160 device_printf(dev, "%s: failed\n", __func__);
2164 stat_rsp = (q80_get_stats_rsp_t *)ha->hw.mbox;
2166 err = Q8_MBX_RSP_STATUS(stat_rsp->regcnt_status);
2176 ql_get_stats(qla_host_t *ha)
2178 q80_get_stats_rsp_t *stat_rsp;
2179 q80_mac_stats_t *mstat;
2180 q80_xmt_stats_t *xstat;
2181 q80_rcv_stats_t *rstat;
2184 struct ifnet *ifp = ha->ifp;
2189 if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) != 0) {
2190 device_printf(ha->pci_dev, "%s: failed\n", __func__);
2194 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2195 QLA_UNLOCK(ha, __func__);
2199 stat_rsp = (q80_get_stats_rsp_t *)ha->hw.mbox;
2201 * Get MAC Statistics
2203 cmd = Q8_GET_STATS_CMD_TYPE_MAC;
2204 // cmd |= Q8_GET_STATS_CMD_CLEAR;
2206 cmd |= ((ha->pci_func & 0x1) << 16);
2208 if (ha->qla_watchdog_pause || (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) ||
2210 goto ql_get_stats_exit;
2212 if (qla_get_hw_stats(ha, cmd, sizeof (q80_get_stats_rsp_t)) == 0) {
2213 mstat = (q80_mac_stats_t *)&stat_rsp->u.mac;
2214 bcopy(mstat, &ha->hw.mac, sizeof(q80_mac_stats_t));
2216 device_printf(ha->pci_dev, "%s: mac failed [0x%08x]\n",
2217 __func__, ha->hw.mbox[0]);
2220 * Get RCV Statistics
2222 cmd = Q8_GET_STATS_CMD_RCV | Q8_GET_STATS_CMD_TYPE_CNTXT;
2223 // cmd |= Q8_GET_STATS_CMD_CLEAR;
2224 cmd |= (ha->hw.rcv_cntxt_id << 16);
2226 if (ha->qla_watchdog_pause || (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) ||
2228 goto ql_get_stats_exit;
2230 if (qla_get_hw_stats(ha, cmd, sizeof (q80_get_stats_rsp_t)) == 0) {
2231 rstat = (q80_rcv_stats_t *)&stat_rsp->u.rcv;
2232 bcopy(rstat, &ha->hw.rcv, sizeof(q80_rcv_stats_t));
2234 device_printf(ha->pci_dev, "%s: rcv failed [0x%08x]\n",
2235 __func__, ha->hw.mbox[0]);
2238 if (ha->qla_watchdog_pause || (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) ||
2240 goto ql_get_stats_exit;
2242 * Get XMT Statistics
2244 for (i = 0 ; (i < ha->hw.num_tx_rings); i++) {
2245 if (ha->qla_watchdog_pause ||
2246 (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) ||
2248 goto ql_get_stats_exit;
2250 cmd = Q8_GET_STATS_CMD_XMT | Q8_GET_STATS_CMD_TYPE_CNTXT;
2251 // cmd |= Q8_GET_STATS_CMD_CLEAR;
2252 cmd |= (ha->hw.tx_cntxt[i].tx_cntxt_id << 16);
2254 if (qla_get_hw_stats(ha, cmd, sizeof(q80_get_stats_rsp_t))
2256 xstat = (q80_xmt_stats_t *)&stat_rsp->u.xmt;
2257 bcopy(xstat, &ha->hw.xmt[i], sizeof(q80_xmt_stats_t));
2259 device_printf(ha->pci_dev, "%s: xmt failed [0x%08x]\n",
2260 __func__, ha->hw.mbox[0]);
2265 QLA_UNLOCK(ha, __func__);
2272 * Function: Checks if the packet to be transmitted is a candidate for
2273 * Large TCP Segment Offload. If yes, the appropriate fields in the Tx
2274 * Ring Structure are plugged in.
2277 qla_tx_tso(qla_host_t *ha, struct mbuf *mp, q80_tx_cmd_t *tx_cmd, uint8_t *hdr)
2279 struct ether_vlan_header *eh;
2280 struct ip *ip = NULL;
2281 struct ip6_hdr *ip6 = NULL;
2282 struct tcphdr *th = NULL;
2283 uint32_t ehdrlen, hdrlen, ip_hlen, tcp_hlen, tcp_opt_off;
2284 uint16_t etype, opcode, offload = 1;
2290 eh = mtod(mp, struct ether_vlan_header *);
2292 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2293 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2294 etype = ntohs(eh->evl_proto);
2296 ehdrlen = ETHER_HDR_LEN;
2297 etype = ntohs(eh->evl_encap_proto);
2305 tcp_opt_off = ehdrlen + sizeof(struct ip) +
2306 sizeof(struct tcphdr);
2308 if (mp->m_len < tcp_opt_off) {
2309 m_copydata(mp, 0, tcp_opt_off, hdr);
2310 ip = (struct ip *)(hdr + ehdrlen);
2312 ip = (struct ip *)(mp->m_data + ehdrlen);
2315 ip_hlen = ip->ip_hl << 2;
2316 opcode = Q8_TX_CMD_OP_XMT_TCP_LSO;
2319 if ((ip->ip_p != IPPROTO_TCP) ||
2320 (ip_hlen != sizeof (struct ip))){
2321 /* IP Options are not supported */
2325 th = (struct tcphdr *)((caddr_t)ip + ip_hlen);
2329 case ETHERTYPE_IPV6:
2331 tcp_opt_off = ehdrlen + sizeof(struct ip6_hdr) +
2332 sizeof (struct tcphdr);
2334 if (mp->m_len < tcp_opt_off) {
2335 m_copydata(mp, 0, tcp_opt_off, hdr);
2336 ip6 = (struct ip6_hdr *)(hdr + ehdrlen);
2338 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
2341 ip_hlen = sizeof(struct ip6_hdr);
2342 opcode = Q8_TX_CMD_OP_XMT_TCP_LSO_IPV6;
2344 if (ip6->ip6_nxt != IPPROTO_TCP) {
2345 //device_printf(dev, "%s: ipv6\n", __func__);
2348 th = (struct tcphdr *)((caddr_t)ip6 + ip_hlen);
2352 QL_DPRINT8(ha, (dev, "%s: type!=ip\n", __func__));
2360 tcp_hlen = th->th_off << 2;
2361 hdrlen = ehdrlen + ip_hlen + tcp_hlen;
2363 if (mp->m_len < hdrlen) {
2364 if (mp->m_len < tcp_opt_off) {
2365 if (tcp_hlen > sizeof(struct tcphdr)) {
2366 m_copydata(mp, tcp_opt_off,
2367 (tcp_hlen - sizeof(struct tcphdr)),
2371 m_copydata(mp, 0, hdrlen, hdr);
2375 tx_cmd->mss = mp->m_pkthdr.tso_segsz;
2377 tx_cmd->flags_opcode = opcode ;
2378 tx_cmd->tcp_hdr_off = ip_hlen + ehdrlen;
2379 tx_cmd->total_hdr_len = hdrlen;
2381 /* Check for Multicast least significant bit of MSB == 1 */
2382 if (eh->evl_dhost[0] & 0x01) {
2383 tx_cmd->flags_opcode |= Q8_TX_CMD_FLAGS_MULTICAST;
2386 if (mp->m_len < hdrlen) {
2387 printf("%d\n", hdrlen);
2395 * Name: qla_tx_chksum
2396 * Function: Checks if the packet to be transmitted is a candidate for
2397 * TCP/UDP Checksum offload. If yes, the appropriate fields in the Tx
2398 * Ring Structure are plugged in.
2401 qla_tx_chksum(qla_host_t *ha, struct mbuf *mp, uint32_t *op_code,
2402 uint32_t *tcp_hdr_off)
2404 struct ether_vlan_header *eh;
2406 struct ip6_hdr *ip6;
2407 uint32_t ehdrlen, ip_hlen;
2408 uint16_t etype, opcode, offload = 1;
2410 uint8_t buf[sizeof(struct ip6_hdr)];
2416 if ((mp->m_pkthdr.csum_flags &
2417 (CSUM_TCP|CSUM_UDP|CSUM_TCP_IPV6 | CSUM_UDP_IPV6)) == 0)
2420 eh = mtod(mp, struct ether_vlan_header *);
2422 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2423 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2424 etype = ntohs(eh->evl_proto);
2426 ehdrlen = ETHER_HDR_LEN;
2427 etype = ntohs(eh->evl_encap_proto);
2433 ip = (struct ip *)(mp->m_data + ehdrlen);
2435 ip_hlen = sizeof (struct ip);
2437 if (mp->m_len < (ehdrlen + ip_hlen)) {
2438 m_copydata(mp, ehdrlen, sizeof(struct ip), buf);
2439 ip = (struct ip *)buf;
2442 if (ip->ip_p == IPPROTO_TCP)
2443 opcode = Q8_TX_CMD_OP_XMT_TCP_CHKSUM;
2444 else if (ip->ip_p == IPPROTO_UDP)
2445 opcode = Q8_TX_CMD_OP_XMT_UDP_CHKSUM;
2447 //device_printf(dev, "%s: ipv4\n", __func__);
2452 case ETHERTYPE_IPV6:
2453 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
2455 ip_hlen = sizeof(struct ip6_hdr);
2457 if (mp->m_len < (ehdrlen + ip_hlen)) {
2458 m_copydata(mp, ehdrlen, sizeof (struct ip6_hdr),
2460 ip6 = (struct ip6_hdr *)buf;
2463 if (ip6->ip6_nxt == IPPROTO_TCP)
2464 opcode = Q8_TX_CMD_OP_XMT_TCP_CHKSUM_IPV6;
2465 else if (ip6->ip6_nxt == IPPROTO_UDP)
2466 opcode = Q8_TX_CMD_OP_XMT_UDP_CHKSUM_IPV6;
2468 //device_printf(dev, "%s: ipv6\n", __func__);
2481 *tcp_hdr_off = (ip_hlen + ehdrlen);
2486 #define QLA_TX_MIN_FREE 2
2489 * Function: Transmits a packet. It first checks if the packet is a
2490 * candidate for Large TCP Segment Offload and then for UDP/TCP checksum
2491 * offload. If either of these creteria are not met, it is transmitted
2492 * as a regular ethernet frame.
2495 ql_hw_send(qla_host_t *ha, bus_dma_segment_t *segs, int nsegs,
2496 uint32_t tx_idx, struct mbuf *mp, uint32_t txr_idx, uint32_t iscsi_pdu)
2498 struct ether_vlan_header *eh;
2499 qla_hw_t *hw = &ha->hw;
2500 q80_tx_cmd_t *tx_cmd, tso_cmd;
2501 bus_dma_segment_t *c_seg;
2502 uint32_t num_tx_cmds, hdr_len = 0;
2503 uint32_t total_length = 0, bytes, tx_cmd_count = 0, txr_next;
2506 uint8_t *src = NULL, *dst = NULL;
2507 uint8_t frame_hdr[QL_FRAME_HDR_SIZE];
2508 uint32_t op_code = 0;
2509 uint32_t tcp_hdr_off = 0;
2514 * Always make sure there is atleast one empty slot in the tx_ring
2515 * tx_ring is considered full when there only one entry available
2517 num_tx_cmds = (nsegs + (Q8_TX_CMD_MAX_SEGMENTS - 1)) >> 2;
2519 total_length = mp->m_pkthdr.len;
2520 if (total_length > QLA_MAX_TSO_FRAME_SIZE) {
2521 device_printf(dev, "%s: total length exceeds maxlen(%d)\n",
2522 __func__, total_length);
2525 eh = mtod(mp, struct ether_vlan_header *);
2527 if (mp->m_pkthdr.csum_flags & CSUM_TSO) {
2529 bzero((void *)&tso_cmd, sizeof(q80_tx_cmd_t));
2532 ret = qla_tx_tso(ha, mp, &tso_cmd, src);
2535 /* find the additional tx_cmd descriptors required */
2537 if (mp->m_flags & M_VLANTAG)
2538 tso_cmd.total_hdr_len += ETHER_VLAN_ENCAP_LEN;
2540 hdr_len = tso_cmd.total_hdr_len;
2542 bytes = sizeof(q80_tx_cmd_t) - Q8_TX_CMD_TSO_ALIGN;
2543 bytes = QL_MIN(bytes, hdr_len);
2549 bytes = QL_MIN((sizeof(q80_tx_cmd_t)), hdr_len);
2553 hdr_len = tso_cmd.total_hdr_len;
2556 src = (uint8_t *)eh;
2560 (void)qla_tx_chksum(ha, mp, &op_code, &tcp_hdr_off);
2563 if (hw->tx_cntxt[txr_idx].txr_free <= (num_tx_cmds + QLA_TX_MIN_FREE)) {
2564 ql_hw_tx_done_locked(ha, txr_idx);
2565 if (hw->tx_cntxt[txr_idx].txr_free <=
2566 (num_tx_cmds + QLA_TX_MIN_FREE)) {
2567 QL_DPRINT8(ha, (dev, "%s: (hw->txr_free <= "
2568 "(num_tx_cmds + QLA_TX_MIN_FREE))\n",
2574 for (i = 0; i < num_tx_cmds; i++) {
2577 j = (tx_idx+i) & (NUM_TX_DESCRIPTORS - 1);
2579 if (NULL != ha->tx_ring[txr_idx].tx_buf[j].m_head) {
2581 ("%s [%d]: txr_idx = %d tx_idx = %d mbuf = %p\n",\
2582 __func__, __LINE__, txr_idx, j,\
2583 ha->tx_ring[txr_idx].tx_buf[j].m_head));
2588 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[tx_idx];
2590 if (!(mp->m_pkthdr.csum_flags & CSUM_TSO)) {
2592 if (nsegs > ha->hw.max_tx_segs)
2593 ha->hw.max_tx_segs = nsegs;
2595 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t));
2598 tx_cmd->flags_opcode = op_code;
2599 tx_cmd->tcp_hdr_off = tcp_hdr_off;
2602 tx_cmd->flags_opcode = Q8_TX_CMD_OP_XMT_ETHER;
2605 bcopy(&tso_cmd, tx_cmd, sizeof(q80_tx_cmd_t));
2606 ha->tx_tso_frames++;
2609 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2610 tx_cmd->flags_opcode |= Q8_TX_CMD_FLAGS_VLAN_TAGGED;
2613 eh->evl_tag |= ha->hw.user_pri_iscsi << 13;
2615 } else if (mp->m_flags & M_VLANTAG) {
2617 if (hdr_len) { /* TSO */
2618 tx_cmd->flags_opcode |= (Q8_TX_CMD_FLAGS_VLAN_TAGGED |
2619 Q8_TX_CMD_FLAGS_HW_VLAN_ID);
2620 tx_cmd->tcp_hdr_off += ETHER_VLAN_ENCAP_LEN;
2622 tx_cmd->flags_opcode |= Q8_TX_CMD_FLAGS_HW_VLAN_ID;
2624 ha->hw_vlan_tx_frames++;
2625 tx_cmd->vlan_tci = mp->m_pkthdr.ether_vtag;
2628 tx_cmd->vlan_tci |= ha->hw.user_pri_iscsi << 13;
2629 mp->m_pkthdr.ether_vtag = tx_cmd->vlan_tci;
2634 tx_cmd->n_bufs = (uint8_t)nsegs;
2635 tx_cmd->data_len_lo = (uint8_t)(total_length & 0xFF);
2636 tx_cmd->data_len_hi = qla_host_to_le16(((uint16_t)(total_length >> 8)));
2637 tx_cmd->cntxtid = Q8_TX_CMD_PORT_CNXTID(ha->pci_func);
2642 for (i = 0; ((i < Q8_TX_CMD_MAX_SEGMENTS) && nsegs); i++) {
2646 tx_cmd->buf1_addr = c_seg->ds_addr;
2647 tx_cmd->buf1_len = c_seg->ds_len;
2651 tx_cmd->buf2_addr = c_seg->ds_addr;
2652 tx_cmd->buf2_len = c_seg->ds_len;
2656 tx_cmd->buf3_addr = c_seg->ds_addr;
2657 tx_cmd->buf3_len = c_seg->ds_len;
2661 tx_cmd->buf4_addr = c_seg->ds_addr;
2662 tx_cmd->buf4_len = c_seg->ds_len;
2670 txr_next = hw->tx_cntxt[txr_idx].txr_next =
2671 (hw->tx_cntxt[txr_idx].txr_next + 1) &
2672 (NUM_TX_DESCRIPTORS - 1);
2678 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[txr_next];
2679 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t));
2682 if (mp->m_pkthdr.csum_flags & CSUM_TSO) {
2684 /* TSO : Copy the header in the following tx cmd descriptors */
2686 txr_next = hw->tx_cntxt[txr_idx].txr_next;
2688 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[txr_next];
2689 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t));
2691 bytes = sizeof(q80_tx_cmd_t) - Q8_TX_CMD_TSO_ALIGN;
2692 bytes = QL_MIN(bytes, hdr_len);
2694 dst = (uint8_t *)tx_cmd + Q8_TX_CMD_TSO_ALIGN;
2696 if (mp->m_flags & M_VLANTAG) {
2697 /* first copy the src/dst MAC addresses */
2698 bcopy(src, dst, (ETHER_ADDR_LEN * 2));
2699 dst += (ETHER_ADDR_LEN * 2);
2700 src += (ETHER_ADDR_LEN * 2);
2702 *((uint16_t *)dst) = htons(ETHERTYPE_VLAN);
2704 *((uint16_t *)dst) = htons(mp->m_pkthdr.ether_vtag);
2707 /* bytes left in src header */
2708 hdr_len -= ((ETHER_ADDR_LEN * 2) +
2709 ETHER_VLAN_ENCAP_LEN);
2711 /* bytes left in TxCmd Entry */
2712 bytes -= ((ETHER_ADDR_LEN * 2) + ETHER_VLAN_ENCAP_LEN);
2715 bcopy(src, dst, bytes);
2719 bcopy(src, dst, bytes);
2724 txr_next = hw->tx_cntxt[txr_idx].txr_next =
2725 (hw->tx_cntxt[txr_idx].txr_next + 1) &
2726 (NUM_TX_DESCRIPTORS - 1);
2730 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[txr_next];
2731 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t));
2733 bytes = QL_MIN((sizeof(q80_tx_cmd_t)), hdr_len);
2735 bcopy(src, tx_cmd, bytes);
2739 txr_next = hw->tx_cntxt[txr_idx].txr_next =
2740 (hw->tx_cntxt[txr_idx].txr_next + 1) &
2741 (NUM_TX_DESCRIPTORS - 1);
2746 hw->tx_cntxt[txr_idx].txr_free =
2747 hw->tx_cntxt[txr_idx].txr_free - tx_cmd_count;
2749 QL_UPDATE_TX_PRODUCER_INDEX(ha, hw->tx_cntxt[txr_idx].txr_next,\
2751 QL_DPRINT8(ha, (dev, "%s: return\n", __func__));
2758 #define Q8_CONFIG_IND_TBL_SIZE 32 /* < Q8_RSS_IND_TBL_SIZE and power of 2 */
2760 qla_config_rss_ind_table(qla_host_t *ha)
2763 uint8_t rss_ind_tbl[Q8_CONFIG_IND_TBL_SIZE];
2766 for (i = 0; i < Q8_CONFIG_IND_TBL_SIZE; i++) {
2767 rss_ind_tbl[i] = i % ha->hw.num_sds_rings;
2770 for (i = 0; i <= Q8_RSS_IND_TBL_MAX_IDX ;
2771 i = i + Q8_CONFIG_IND_TBL_SIZE) {
2773 if ((i + Q8_CONFIG_IND_TBL_SIZE) > Q8_RSS_IND_TBL_MAX_IDX) {
2774 count = Q8_RSS_IND_TBL_MAX_IDX - i + 1;
2776 count = Q8_CONFIG_IND_TBL_SIZE;
2779 if (qla_set_rss_ind_table(ha, i, count, ha->hw.rcv_cntxt_id,
2788 qla_config_soft_lro(qla_host_t *ha)
2791 qla_hw_t *hw = &ha->hw;
2792 struct lro_ctrl *lro;
2794 for (i = 0; i < hw->num_sds_rings; i++) {
2795 lro = &hw->sds[i].lro;
2797 bzero(lro, sizeof(struct lro_ctrl));
2799 #if (__FreeBSD_version >= 1100101)
2800 if (tcp_lro_init_args(lro, ha->ifp, 0, NUM_RX_DESCRIPTORS)) {
2801 device_printf(ha->pci_dev,
2802 "%s: tcp_lro_init_args [%d] failed\n",
2807 if (tcp_lro_init(lro)) {
2808 device_printf(ha->pci_dev,
2809 "%s: tcp_lro_init [%d] failed\n",
2813 #endif /* #if (__FreeBSD_version >= 1100101) */
2818 QL_DPRINT2(ha, (ha->pci_dev, "%s: LRO initialized\n", __func__));
2823 qla_drain_soft_lro(qla_host_t *ha)
2826 qla_hw_t *hw = &ha->hw;
2827 struct lro_ctrl *lro;
2829 for (i = 0; i < hw->num_sds_rings; i++) {
2830 lro = &hw->sds[i].lro;
2832 #if (__FreeBSD_version >= 1100101)
2833 tcp_lro_flush_all(lro);
2835 struct lro_entry *queued;
2837 while ((!SLIST_EMPTY(&lro->lro_active))) {
2838 queued = SLIST_FIRST(&lro->lro_active);
2839 SLIST_REMOVE_HEAD(&lro->lro_active, next);
2840 tcp_lro_flush(lro, queued);
2842 #endif /* #if (__FreeBSD_version >= 1100101) */
2849 qla_free_soft_lro(qla_host_t *ha)
2852 qla_hw_t *hw = &ha->hw;
2853 struct lro_ctrl *lro;
2855 for (i = 0; i < hw->num_sds_rings; i++) {
2856 lro = &hw->sds[i].lro;
2865 * Name: ql_del_hw_if
2866 * Function: Destroys the hardware specific entities corresponding to an
2867 * Ethernet Interface
2870 ql_del_hw_if(qla_host_t *ha)
2875 (void)qla_stop_nic_func(ha);
2877 qla_del_rcv_cntxt(ha);
2879 if(qla_del_xmt_cntxt(ha))
2880 goto ql_del_hw_if_exit;
2882 if (ha->hw.flags.init_intr_cnxt) {
2883 for (i = 0; i < ha->hw.num_sds_rings; ) {
2885 if ((i + Q8_MAX_INTR_VECTORS) < ha->hw.num_sds_rings)
2886 num_msix = Q8_MAX_INTR_VECTORS;
2888 num_msix = ha->hw.num_sds_rings - i;
2890 if (qla_config_intr_cntxt(ha, i, num_msix, 0))
2896 ha->hw.flags.init_intr_cnxt = 0;
2900 if (ha->hw.enable_soft_lro) {
2901 qla_drain_soft_lro(ha);
2902 qla_free_soft_lro(ha);
2909 qla_confirm_9kb_enable(qla_host_t *ha)
2911 // uint32_t supports_9kb = 0;
2913 ha->hw.mbx_intr_mask_offset = READ_REG32(ha, Q8_MBOX_INT_MASK_MSIX);
2915 /* Use MSI-X vector 0; Enable Firmware Mailbox Interrupt */
2916 WRITE_REG32(ha, Q8_MBOX_INT_ENABLE, BIT_2);
2917 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
2920 qla_get_nic_partition(ha, &supports_9kb, NULL);
2924 ha->hw.enable_9kb = 0;
2930 * Name: ql_init_hw_if
2931 * Function: Creates the hardware specific entities corresponding to an
2932 * Ethernet Interface - Transmit and Receive Contexts. Sets the MAC Address
2933 * corresponding to the interface. Enables LRO if allowed.
2936 ql_init_hw_if(qla_host_t *ha)
2940 uint8_t bcast_mac[6];
2946 for (i = 0; i < ha->hw.num_sds_rings; i++) {
2947 bzero(ha->hw.dma_buf.sds_ring[i].dma_b,
2948 ha->hw.dma_buf.sds_ring[i].size);
2951 for (i = 0; i < ha->hw.num_sds_rings; ) {
2953 if ((i + Q8_MAX_INTR_VECTORS) < ha->hw.num_sds_rings)
2954 num_msix = Q8_MAX_INTR_VECTORS;
2956 num_msix = ha->hw.num_sds_rings - i;
2958 if (qla_config_intr_cntxt(ha, i, num_msix, 1)) {
2964 for (i = 0; i < num_msix; ) {
2965 qla_config_intr_cntxt(ha, i,
2966 Q8_MAX_INTR_VECTORS, 0);
2967 i += Q8_MAX_INTR_VECTORS;
2976 ha->hw.flags.init_intr_cnxt = 1;
2979 * Create Receive Context
2981 if (qla_init_rcv_cntxt(ha)) {
2985 for (i = 0; i < ha->hw.num_rds_rings; i++) {
2986 rdesc = &ha->hw.rds[i];
2987 rdesc->rx_next = NUM_RX_DESCRIPTORS - 2;
2989 /* Update the RDS Producer Indices */
2990 QL_UPDATE_RDS_PRODUCER_INDEX(ha, rdesc->prod_std,\
2995 * Create Transmit Context
2997 if (qla_init_xmt_cntxt(ha)) {
2998 qla_del_rcv_cntxt(ha);
3001 ha->hw.max_tx_segs = 0;
3003 if (qla_config_mac_addr(ha, ha->hw.mac_addr, 1, 1))
3006 ha->hw.flags.unicast_mac = 1;
3008 bcast_mac[0] = 0xFF; bcast_mac[1] = 0xFF; bcast_mac[2] = 0xFF;
3009 bcast_mac[3] = 0xFF; bcast_mac[4] = 0xFF; bcast_mac[5] = 0xFF;
3011 if (qla_config_mac_addr(ha, bcast_mac, 1, 1))
3014 ha->hw.flags.bcast_mac = 1;
3017 * program any cached multicast addresses
3019 if (qla_hw_add_all_mcast(ha))
3022 if (ql_set_max_mtu(ha, ha->max_frame_size, ha->hw.rcv_cntxt_id))
3025 if (qla_config_rss(ha, ha->hw.rcv_cntxt_id))
3028 if (qla_config_rss_ind_table(ha))
3031 if (qla_config_intr_coalesce(ha, ha->hw.rcv_cntxt_id, 0, 1))
3034 if (qla_link_event_req(ha, ha->hw.rcv_cntxt_id))
3037 if (ha->ifp->if_capenable & IFCAP_LRO) {
3038 if (ha->hw.enable_hw_lro) {
3039 ha->hw.enable_soft_lro = 0;
3041 if (qla_config_fw_lro(ha, ha->hw.rcv_cntxt_id))
3044 ha->hw.enable_soft_lro = 1;
3046 if (qla_config_soft_lro(ha))
3051 if (qla_init_nic_func(ha))
3054 if (qla_query_fw_dcbx_caps(ha))
3057 for (i = 0; i < ha->hw.num_sds_rings; i++)
3058 QL_ENABLE_INTERRUPTS(ha, i);
3064 qla_map_sds_to_rds(qla_host_t *ha, uint32_t start_idx, uint32_t num_idx)
3066 device_t dev = ha->pci_dev;
3067 q80_rq_map_sds_to_rds_t *map_rings;
3068 q80_rsp_map_sds_to_rds_t *map_rings_rsp;
3070 qla_hw_t *hw = &ha->hw;
3072 map_rings = (q80_rq_map_sds_to_rds_t *)ha->hw.mbox;
3073 bzero(map_rings, sizeof(q80_rq_map_sds_to_rds_t));
3075 map_rings->opcode = Q8_MBX_MAP_SDS_TO_RDS;
3076 map_rings->count_version = (sizeof (q80_rq_map_sds_to_rds_t) >> 2);
3077 map_rings->count_version |= Q8_MBX_CMD_VERSION;
3079 map_rings->cntxt_id = hw->rcv_cntxt_id;
3080 map_rings->num_rings = num_idx;
3082 for (i = 0; i < num_idx; i++) {
3083 map_rings->sds_rds[i].sds_ring = i + start_idx;
3084 map_rings->sds_rds[i].rds_ring = i + start_idx;
3087 if (qla_mbx_cmd(ha, (uint32_t *)map_rings,
3088 (sizeof (q80_rq_map_sds_to_rds_t) >> 2),
3089 ha->hw.mbox, (sizeof(q80_rsp_add_rcv_rings_t) >> 2), 0)) {
3090 device_printf(dev, "%s: failed0\n", __func__);
3094 map_rings_rsp = (q80_rsp_map_sds_to_rds_t *)ha->hw.mbox;
3096 err = Q8_MBX_RSP_STATUS(map_rings_rsp->regcnt_status);
3099 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
3107 * Name: qla_init_rcv_cntxt
3108 * Function: Creates the Receive Context.
3111 qla_init_rcv_cntxt(qla_host_t *ha)
3113 q80_rq_rcv_cntxt_t *rcntxt;
3114 q80_rsp_rcv_cntxt_t *rcntxt_rsp;
3115 q80_stat_desc_t *sdesc;
3117 qla_hw_t *hw = &ha->hw;
3120 uint32_t rcntxt_sds_rings;
3121 uint32_t rcntxt_rds_rings;
3127 * Create Receive Context
3130 for (i = 0; i < hw->num_sds_rings; i++) {
3131 sdesc = (q80_stat_desc_t *)&hw->sds[i].sds_ring_base[0];
3133 for (j = 0; j < NUM_STATUS_DESCRIPTORS; j++) {
3134 sdesc->data[0] = 1ULL;
3135 sdesc->data[1] = 1ULL;
3139 rcntxt_sds_rings = hw->num_sds_rings;
3140 if (hw->num_sds_rings > MAX_RCNTXT_SDS_RINGS)
3141 rcntxt_sds_rings = MAX_RCNTXT_SDS_RINGS;
3143 rcntxt_rds_rings = hw->num_rds_rings;
3145 if (hw->num_rds_rings > MAX_RDS_RING_SETS)
3146 rcntxt_rds_rings = MAX_RDS_RING_SETS;
3148 rcntxt = (q80_rq_rcv_cntxt_t *)ha->hw.mbox;
3149 bzero(rcntxt, (sizeof (q80_rq_rcv_cntxt_t)));
3151 rcntxt->opcode = Q8_MBX_CREATE_RX_CNTXT;
3152 rcntxt->count_version = (sizeof (q80_rq_rcv_cntxt_t) >> 2);
3153 rcntxt->count_version |= Q8_MBX_CMD_VERSION;
3155 rcntxt->cap0 = Q8_RCV_CNTXT_CAP0_BASEFW |
3156 Q8_RCV_CNTXT_CAP0_LRO |
3157 Q8_RCV_CNTXT_CAP0_HW_LRO |
3158 Q8_RCV_CNTXT_CAP0_RSS |
3159 Q8_RCV_CNTXT_CAP0_SGL_LRO;
3161 if (ha->hw.enable_9kb)
3162 rcntxt->cap0 |= Q8_RCV_CNTXT_CAP0_SINGLE_JUMBO;
3164 rcntxt->cap0 |= Q8_RCV_CNTXT_CAP0_SGL_JUMBO;
3166 if (ha->hw.num_rds_rings > 1) {
3167 rcntxt->nrds_sets_rings = rcntxt_rds_rings | (1 << 5);
3168 rcntxt->cap0 |= Q8_RCV_CNTXT_CAP0_MULTI_RDS;
3170 rcntxt->nrds_sets_rings = 0x1 | (1 << 5);
3172 rcntxt->nsds_rings = rcntxt_sds_rings;
3174 rcntxt->rds_producer_mode = Q8_RCV_CNTXT_RDS_PROD_MODE_UNIQUE;
3176 rcntxt->rcv_vpid = 0;
3178 for (i = 0; i < rcntxt_sds_rings; i++) {
3179 rcntxt->sds[i].paddr =
3180 qla_host_to_le64(hw->dma_buf.sds_ring[i].dma_addr);
3181 rcntxt->sds[i].size =
3182 qla_host_to_le32(NUM_STATUS_DESCRIPTORS);
3183 rcntxt->sds[i].intr_id = qla_host_to_le16(hw->intr_id[i]);
3184 rcntxt->sds[i].intr_src_bit = qla_host_to_le16(0);
3187 for (i = 0; i < rcntxt_rds_rings; i++) {
3188 rcntxt->rds[i].paddr_std =
3189 qla_host_to_le64(hw->dma_buf.rds_ring[i].dma_addr);
3191 if (ha->hw.enable_9kb)
3192 rcntxt->rds[i].std_bsize =
3193 qla_host_to_le64(MJUM9BYTES);
3195 rcntxt->rds[i].std_bsize = qla_host_to_le64(MCLBYTES);
3197 rcntxt->rds[i].std_nentries =
3198 qla_host_to_le32(NUM_RX_DESCRIPTORS);
3201 if (qla_mbx_cmd(ha, (uint32_t *)rcntxt,
3202 (sizeof (q80_rq_rcv_cntxt_t) >> 2),
3203 ha->hw.mbox, (sizeof(q80_rsp_rcv_cntxt_t) >> 2), 0)) {
3204 device_printf(dev, "%s: failed0\n", __func__);
3208 rcntxt_rsp = (q80_rsp_rcv_cntxt_t *)ha->hw.mbox;
3210 err = Q8_MBX_RSP_STATUS(rcntxt_rsp->regcnt_status);
3213 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
3217 for (i = 0; i < rcntxt_sds_rings; i++) {
3218 hw->sds[i].sds_consumer = rcntxt_rsp->sds_cons[i];
3221 for (i = 0; i < rcntxt_rds_rings; i++) {
3222 hw->rds[i].prod_std = rcntxt_rsp->rds[i].prod_std;
3225 hw->rcv_cntxt_id = rcntxt_rsp->cntxt_id;
3227 ha->hw.flags.init_rx_cnxt = 1;
3229 if (hw->num_sds_rings > MAX_RCNTXT_SDS_RINGS) {
3231 for (i = MAX_RCNTXT_SDS_RINGS; i < hw->num_sds_rings;) {
3233 if ((i + MAX_RCNTXT_SDS_RINGS) < hw->num_sds_rings)
3234 max_idx = MAX_RCNTXT_SDS_RINGS;
3236 max_idx = hw->num_sds_rings - i;
3238 err = qla_add_rcv_rings(ha, i, max_idx);
3246 if (hw->num_rds_rings > 1) {
3248 for (i = 0; i < hw->num_rds_rings; ) {
3250 if ((i + MAX_SDS_TO_RDS_MAP) < hw->num_rds_rings)
3251 max_idx = MAX_SDS_TO_RDS_MAP;
3253 max_idx = hw->num_rds_rings - i;
3255 err = qla_map_sds_to_rds(ha, i, max_idx);
3267 qla_add_rcv_rings(qla_host_t *ha, uint32_t sds_idx, uint32_t nsds)
3269 device_t dev = ha->pci_dev;
3270 q80_rq_add_rcv_rings_t *add_rcv;
3271 q80_rsp_add_rcv_rings_t *add_rcv_rsp;
3273 qla_hw_t *hw = &ha->hw;
3275 add_rcv = (q80_rq_add_rcv_rings_t *)ha->hw.mbox;
3276 bzero(add_rcv, sizeof (q80_rq_add_rcv_rings_t));
3278 add_rcv->opcode = Q8_MBX_ADD_RX_RINGS;
3279 add_rcv->count_version = (sizeof (q80_rq_add_rcv_rings_t) >> 2);
3280 add_rcv->count_version |= Q8_MBX_CMD_VERSION;
3282 add_rcv->nrds_sets_rings = nsds | (1 << 5);
3283 add_rcv->nsds_rings = nsds;
3284 add_rcv->cntxt_id = hw->rcv_cntxt_id;
3286 for (i = 0; i < nsds; i++) {
3290 add_rcv->sds[i].paddr =
3291 qla_host_to_le64(hw->dma_buf.sds_ring[j].dma_addr);
3293 add_rcv->sds[i].size =
3294 qla_host_to_le32(NUM_STATUS_DESCRIPTORS);
3296 add_rcv->sds[i].intr_id = qla_host_to_le16(hw->intr_id[j]);
3297 add_rcv->sds[i].intr_src_bit = qla_host_to_le16(0);
3301 for (i = 0; (i < nsds); i++) {
3304 add_rcv->rds[i].paddr_std =
3305 qla_host_to_le64(hw->dma_buf.rds_ring[j].dma_addr);
3307 if (ha->hw.enable_9kb)
3308 add_rcv->rds[i].std_bsize =
3309 qla_host_to_le64(MJUM9BYTES);
3311 add_rcv->rds[i].std_bsize = qla_host_to_le64(MCLBYTES);
3313 add_rcv->rds[i].std_nentries =
3314 qla_host_to_le32(NUM_RX_DESCRIPTORS);
3318 if (qla_mbx_cmd(ha, (uint32_t *)add_rcv,
3319 (sizeof (q80_rq_add_rcv_rings_t) >> 2),
3320 ha->hw.mbox, (sizeof(q80_rsp_add_rcv_rings_t) >> 2), 0)) {
3321 device_printf(dev, "%s: failed0\n", __func__);
3325 add_rcv_rsp = (q80_rsp_add_rcv_rings_t *)ha->hw.mbox;
3327 err = Q8_MBX_RSP_STATUS(add_rcv_rsp->regcnt_status);
3330 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
3334 for (i = 0; i < nsds; i++) {
3335 hw->sds[(i + sds_idx)].sds_consumer = add_rcv_rsp->sds_cons[i];
3338 for (i = 0; i < nsds; i++) {
3339 hw->rds[(i + sds_idx)].prod_std = add_rcv_rsp->rds[i].prod_std;
3346 * Name: qla_del_rcv_cntxt
3347 * Function: Destroys the Receive Context.
3350 qla_del_rcv_cntxt(qla_host_t *ha)
3352 device_t dev = ha->pci_dev;
3353 q80_rcv_cntxt_destroy_t *rcntxt;
3354 q80_rcv_cntxt_destroy_rsp_t *rcntxt_rsp;
3356 uint8_t bcast_mac[6];
3358 if (!ha->hw.flags.init_rx_cnxt)
3361 if (qla_hw_del_all_mcast(ha))
3364 if (ha->hw.flags.bcast_mac) {
3366 bcast_mac[0] = 0xFF; bcast_mac[1] = 0xFF; bcast_mac[2] = 0xFF;
3367 bcast_mac[3] = 0xFF; bcast_mac[4] = 0xFF; bcast_mac[5] = 0xFF;
3369 if (qla_config_mac_addr(ha, bcast_mac, 0, 1))
3371 ha->hw.flags.bcast_mac = 0;
3375 if (ha->hw.flags.unicast_mac) {
3376 if (qla_config_mac_addr(ha, ha->hw.mac_addr, 0, 1))
3378 ha->hw.flags.unicast_mac = 0;
3381 rcntxt = (q80_rcv_cntxt_destroy_t *)ha->hw.mbox;
3382 bzero(rcntxt, (sizeof (q80_rcv_cntxt_destroy_t)));
3384 rcntxt->opcode = Q8_MBX_DESTROY_RX_CNTXT;
3385 rcntxt->count_version = (sizeof (q80_rcv_cntxt_destroy_t) >> 2);
3386 rcntxt->count_version |= Q8_MBX_CMD_VERSION;
3388 rcntxt->cntxt_id = ha->hw.rcv_cntxt_id;
3390 if (qla_mbx_cmd(ha, (uint32_t *)rcntxt,
3391 (sizeof (q80_rcv_cntxt_destroy_t) >> 2),
3392 ha->hw.mbox, (sizeof(q80_rcv_cntxt_destroy_rsp_t) >> 2), 0)) {
3393 device_printf(dev, "%s: failed0\n", __func__);
3396 rcntxt_rsp = (q80_rcv_cntxt_destroy_rsp_t *)ha->hw.mbox;
3398 err = Q8_MBX_RSP_STATUS(rcntxt_rsp->regcnt_status);
3401 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
3404 ha->hw.flags.init_rx_cnxt = 0;
3409 * Name: qla_init_xmt_cntxt
3410 * Function: Creates the Transmit Context.
3413 qla_init_xmt_cntxt_i(qla_host_t *ha, uint32_t txr_idx)
3416 qla_hw_t *hw = &ha->hw;
3417 q80_rq_tx_cntxt_t *tcntxt;
3418 q80_rsp_tx_cntxt_t *tcntxt_rsp;
3420 qla_hw_tx_cntxt_t *hw_tx_cntxt;
3423 hw_tx_cntxt = &hw->tx_cntxt[txr_idx];
3428 * Create Transmit Context
3430 tcntxt = (q80_rq_tx_cntxt_t *)ha->hw.mbox;
3431 bzero(tcntxt, (sizeof (q80_rq_tx_cntxt_t)));
3433 tcntxt->opcode = Q8_MBX_CREATE_TX_CNTXT;
3434 tcntxt->count_version = (sizeof (q80_rq_tx_cntxt_t) >> 2);
3435 tcntxt->count_version |= Q8_MBX_CMD_VERSION;
3439 #ifdef QL_ENABLE_ISCSI_TLV
3441 tcntxt->cap0 = Q8_TX_CNTXT_CAP0_BASEFW | Q8_TX_CNTXT_CAP0_LSO |
3442 Q8_TX_CNTXT_CAP0_TC;
3444 if (txr_idx >= (ha->hw.num_tx_rings >> 1)) {
3445 tcntxt->traffic_class = 1;
3448 intr_idx = txr_idx % (ha->hw.num_tx_rings >> 1);
3451 tcntxt->cap0 = Q8_TX_CNTXT_CAP0_BASEFW | Q8_TX_CNTXT_CAP0_LSO;
3453 #endif /* #ifdef QL_ENABLE_ISCSI_TLV */
3455 tcntxt->ntx_rings = 1;
3457 tcntxt->tx_ring[0].paddr =
3458 qla_host_to_le64(hw_tx_cntxt->tx_ring_paddr);
3459 tcntxt->tx_ring[0].tx_consumer =
3460 qla_host_to_le64(hw_tx_cntxt->tx_cons_paddr);
3461 tcntxt->tx_ring[0].nentries = qla_host_to_le16(NUM_TX_DESCRIPTORS);
3463 tcntxt->tx_ring[0].intr_id = qla_host_to_le16(hw->intr_id[intr_idx]);
3464 tcntxt->tx_ring[0].intr_src_bit = qla_host_to_le16(0);
3466 hw_tx_cntxt->txr_free = NUM_TX_DESCRIPTORS;
3467 hw_tx_cntxt->txr_next = hw_tx_cntxt->txr_comp = 0;
3468 *hw_tx_cntxt->tx_cons = 0;
3470 if (qla_mbx_cmd(ha, (uint32_t *)tcntxt,
3471 (sizeof (q80_rq_tx_cntxt_t) >> 2),
3473 (sizeof(q80_rsp_tx_cntxt_t) >> 2), 0)) {
3474 device_printf(dev, "%s: failed0\n", __func__);
3477 tcntxt_rsp = (q80_rsp_tx_cntxt_t *)ha->hw.mbox;
3479 err = Q8_MBX_RSP_STATUS(tcntxt_rsp->regcnt_status);
3482 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
3486 hw_tx_cntxt->tx_prod_reg = tcntxt_rsp->tx_ring[0].prod_index;
3487 hw_tx_cntxt->tx_cntxt_id = tcntxt_rsp->tx_ring[0].cntxt_id;
3489 if (qla_config_intr_coalesce(ha, hw_tx_cntxt->tx_cntxt_id, 0, 0))
3497 * Name: qla_del_xmt_cntxt
3498 * Function: Destroys the Transmit Context.
3501 qla_del_xmt_cntxt_i(qla_host_t *ha, uint32_t txr_idx)
3503 device_t dev = ha->pci_dev;
3504 q80_tx_cntxt_destroy_t *tcntxt;
3505 q80_tx_cntxt_destroy_rsp_t *tcntxt_rsp;
3508 tcntxt = (q80_tx_cntxt_destroy_t *)ha->hw.mbox;
3509 bzero(tcntxt, (sizeof (q80_tx_cntxt_destroy_t)));
3511 tcntxt->opcode = Q8_MBX_DESTROY_TX_CNTXT;
3512 tcntxt->count_version = (sizeof (q80_tx_cntxt_destroy_t) >> 2);
3513 tcntxt->count_version |= Q8_MBX_CMD_VERSION;
3515 tcntxt->cntxt_id = ha->hw.tx_cntxt[txr_idx].tx_cntxt_id;
3517 if (qla_mbx_cmd(ha, (uint32_t *)tcntxt,
3518 (sizeof (q80_tx_cntxt_destroy_t) >> 2),
3519 ha->hw.mbox, (sizeof (q80_tx_cntxt_destroy_rsp_t) >> 2), 0)) {
3520 device_printf(dev, "%s: failed0\n", __func__);
3523 tcntxt_rsp = (q80_tx_cntxt_destroy_rsp_t *)ha->hw.mbox;
3525 err = Q8_MBX_RSP_STATUS(tcntxt_rsp->regcnt_status);
3528 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
3535 qla_del_xmt_cntxt(qla_host_t *ha)
3540 if (!ha->hw.flags.init_tx_cnxt)
3543 for (i = 0; i < ha->hw.num_tx_rings; i++) {
3544 if ((ret = qla_del_xmt_cntxt_i(ha, i)) != 0)
3547 ha->hw.flags.init_tx_cnxt = 0;
3553 qla_init_xmt_cntxt(qla_host_t *ha)
3557 for (i = 0; i < ha->hw.num_tx_rings; i++) {
3558 if (qla_init_xmt_cntxt_i(ha, i) != 0) {
3559 for (j = 0; j < i; j++) {
3560 if (qla_del_xmt_cntxt_i(ha, j))
3566 ha->hw.flags.init_tx_cnxt = 1;
3571 qla_hw_all_mcast(qla_host_t *ha, uint32_t add_mcast)
3577 nmcast = ha->hw.nmcast;
3579 QL_DPRINT2(ha, (ha->pci_dev,
3580 "%s:[0x%x] enter nmcast = %d \n", __func__, add_mcast, nmcast));
3582 mcast = ha->hw.mac_addr_arr;
3583 memset(mcast, 0, (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN));
3585 for (i = 0 ; ((i < Q8_MAX_NUM_MULTICAST_ADDRS) && nmcast); i++) {
3586 if ((ha->hw.mcast[i].addr[0] != 0) ||
3587 (ha->hw.mcast[i].addr[1] != 0) ||
3588 (ha->hw.mcast[i].addr[2] != 0) ||
3589 (ha->hw.mcast[i].addr[3] != 0) ||
3590 (ha->hw.mcast[i].addr[4] != 0) ||
3591 (ha->hw.mcast[i].addr[5] != 0)) {
3593 bcopy(ha->hw.mcast[i].addr, mcast, ETHER_ADDR_LEN);
3594 mcast = mcast + ETHER_ADDR_LEN;
3597 device_printf(ha->pci_dev,
3598 "%s: %x:%x:%x:%x:%x:%x \n",
3599 __func__, ha->hw.mcast[i].addr[0],
3600 ha->hw.mcast[i].addr[1], ha->hw.mcast[i].addr[2],
3601 ha->hw.mcast[i].addr[3], ha->hw.mcast[i].addr[4],
3602 ha->hw.mcast[i].addr[5]);
3604 if (count == Q8_MAX_MAC_ADDRS) {
3605 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr,
3606 add_mcast, count)) {
3607 device_printf(ha->pci_dev,
3608 "%s: failed\n", __func__);
3613 mcast = ha->hw.mac_addr_arr;
3615 (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN));
3623 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr, add_mcast,
3625 device_printf(ha->pci_dev, "%s: failed\n", __func__);
3629 QL_DPRINT2(ha, (ha->pci_dev,
3630 "%s:[0x%x] exit nmcast = %d \n", __func__, add_mcast, nmcast));
3636 qla_hw_add_all_mcast(qla_host_t *ha)
3640 ret = qla_hw_all_mcast(ha, 1);
3646 qla_hw_del_all_mcast(qla_host_t *ha)
3650 ret = qla_hw_all_mcast(ha, 0);
3652 bzero(ha->hw.mcast, (sizeof (qla_mcast_t) * Q8_MAX_NUM_MULTICAST_ADDRS));
3659 qla_hw_mac_addr_present(qla_host_t *ha, uint8_t *mta)
3663 for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) {
3664 if (QL_MAC_CMP(ha->hw.mcast[i].addr, mta) == 0)
3665 return (0); /* its been already added */
3671 qla_hw_add_mcast(qla_host_t *ha, uint8_t *mta, uint32_t nmcast)
3675 for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) {
3677 if ((ha->hw.mcast[i].addr[0] == 0) &&
3678 (ha->hw.mcast[i].addr[1] == 0) &&
3679 (ha->hw.mcast[i].addr[2] == 0) &&
3680 (ha->hw.mcast[i].addr[3] == 0) &&
3681 (ha->hw.mcast[i].addr[4] == 0) &&
3682 (ha->hw.mcast[i].addr[5] == 0)) {
3684 bcopy(mta, ha->hw.mcast[i].addr, Q8_MAC_ADDR_LEN);
3687 mta = mta + ETHER_ADDR_LEN;
3699 qla_hw_del_mcast(qla_host_t *ha, uint8_t *mta, uint32_t nmcast)
3703 for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) {
3704 if (QL_MAC_CMP(ha->hw.mcast[i].addr, mta) == 0) {
3706 ha->hw.mcast[i].addr[0] = 0;
3707 ha->hw.mcast[i].addr[1] = 0;
3708 ha->hw.mcast[i].addr[2] = 0;
3709 ha->hw.mcast[i].addr[3] = 0;
3710 ha->hw.mcast[i].addr[4] = 0;
3711 ha->hw.mcast[i].addr[5] = 0;
3715 mta = mta + ETHER_ADDR_LEN;
3726 * Name: ql_hw_set_multi
3727 * Function: Sets the Multicast Addresses provided by the host O.S into the
3728 * hardware (for the given interface)
3731 ql_hw_set_multi(qla_host_t *ha, uint8_t *mcast_addr, uint32_t mcnt,
3734 uint8_t *mta = mcast_addr;
3740 mcast = ha->hw.mac_addr_arr;
3741 memset(mcast, 0, (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN));
3743 for (i = 0; i < mcnt; i++) {
3744 if (mta[0] || mta[1] || mta[2] || mta[3] || mta[4] || mta[5]) {
3746 if (qla_hw_mac_addr_present(ha, mta) != 0) {
3747 bcopy(mta, mcast, ETHER_ADDR_LEN);
3748 mcast = mcast + ETHER_ADDR_LEN;
3752 if (qla_hw_mac_addr_present(ha, mta) == 0) {
3753 bcopy(mta, mcast, ETHER_ADDR_LEN);
3754 mcast = mcast + ETHER_ADDR_LEN;
3759 if (count == Q8_MAX_MAC_ADDRS) {
3760 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr,
3762 device_printf(ha->pci_dev, "%s: failed\n",
3768 qla_hw_add_mcast(ha, ha->hw.mac_addr_arr,
3771 qla_hw_del_mcast(ha, ha->hw.mac_addr_arr,
3776 mcast = ha->hw.mac_addr_arr;
3777 memset(mcast, 0, (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN));
3780 mta += Q8_MAC_ADDR_LEN;
3784 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr, add_mac,
3786 device_printf(ha->pci_dev, "%s: failed\n", __func__);
3790 qla_hw_add_mcast(ha, ha->hw.mac_addr_arr, count);
3792 qla_hw_del_mcast(ha, ha->hw.mac_addr_arr, count);
3800 * Name: ql_hw_tx_done_locked
3801 * Function: Handle Transmit Completions
3804 ql_hw_tx_done_locked(qla_host_t *ha, uint32_t txr_idx)
3807 qla_hw_t *hw = &ha->hw;
3808 uint32_t comp_idx, comp_count = 0;
3809 qla_hw_tx_cntxt_t *hw_tx_cntxt;
3811 hw_tx_cntxt = &hw->tx_cntxt[txr_idx];
3813 /* retrieve index of last entry in tx ring completed */
3814 comp_idx = qla_le32_to_host(*(hw_tx_cntxt->tx_cons));
3816 while (comp_idx != hw_tx_cntxt->txr_comp) {
3818 txb = &ha->tx_ring[txr_idx].tx_buf[hw_tx_cntxt->txr_comp];
3820 hw_tx_cntxt->txr_comp++;
3821 if (hw_tx_cntxt->txr_comp == NUM_TX_DESCRIPTORS)
3822 hw_tx_cntxt->txr_comp = 0;
3827 ha->ifp->if_opackets++;
3829 bus_dmamap_sync(ha->tx_tag, txb->map,
3830 BUS_DMASYNC_POSTWRITE);
3831 bus_dmamap_unload(ha->tx_tag, txb->map);
3832 m_freem(txb->m_head);
3838 hw_tx_cntxt->txr_free += comp_count;
3840 if (hw_tx_cntxt->txr_free > NUM_TX_DESCRIPTORS)
3841 device_printf(ha->pci_dev, "%s [%d]: txr_idx = %d txr_free = %d"
3842 "txr_next = %d txr_comp = %d\n", __func__, __LINE__,
3843 txr_idx, hw_tx_cntxt->txr_free,
3844 hw_tx_cntxt->txr_next, hw_tx_cntxt->txr_comp);
3846 QL_ASSERT(ha, (hw_tx_cntxt->txr_free <= NUM_TX_DESCRIPTORS), \
3847 ("%s [%d]: txr_idx = %d txr_free = %d txr_next = %d txr_comp = %d\n",\
3848 __func__, __LINE__, txr_idx, hw_tx_cntxt->txr_free, \
3849 hw_tx_cntxt->txr_next, hw_tx_cntxt->txr_comp));
3855 ql_update_link_state(qla_host_t *ha)
3857 uint32_t link_state = 0;
3858 uint32_t prev_link_state;
3860 prev_link_state = ha->hw.link_up;
3862 if (ha->ifp->if_drv_flags & IFF_DRV_RUNNING) {
3863 link_state = READ_REG32(ha, Q8_LINK_STATE);
3865 if (ha->pci_func == 0) {
3866 link_state = (((link_state & 0xF) == 1)? 1 : 0);
3868 link_state = ((((link_state >> 4)& 0xF) == 1)? 1 : 0);
3872 atomic_store_rel_8(&ha->hw.link_up, (uint8_t)link_state);
3874 if (prev_link_state != ha->hw.link_up) {
3875 if (ha->hw.link_up) {
3876 if_link_state_change(ha->ifp, LINK_STATE_UP);
3878 if_link_state_change(ha->ifp, LINK_STATE_DOWN);
3885 ql_hw_check_health(qla_host_t *ha)
3889 ha->hw.health_count++;
3891 if (ha->hw.health_count < 500)
3894 ha->hw.health_count = 0;
3896 val = READ_REG32(ha, Q8_ASIC_TEMPERATURE);
3898 if (((val & 0xFFFF) == 2) || ((val & 0xFFFF) == 3) ||
3899 (QL_ERR_INJECT(ha, INJCT_TEMPERATURE_FAILURE))) {
3900 device_printf(ha->pci_dev, "%s: Temperature Alert"
3901 " at ts_usecs %ld ts_reg = 0x%08x\n",
3902 __func__, qla_get_usec_timestamp(), val);
3904 if (ha->hw.sp_log_stop_events & Q8_SP_LOG_STOP_TEMP_FAILURE)
3905 ha->hw.sp_log_stop = -1;
3907 QL_INITIATE_RECOVERY(ha);
3911 val = READ_REG32(ha, Q8_FIRMWARE_HEARTBEAT);
3913 if ((val != ha->hw.hbeat_value) &&
3914 (!(QL_ERR_INJECT(ha, INJCT_HEARTBEAT_FAILURE)))) {
3915 ha->hw.hbeat_value = val;
3916 ha->hw.hbeat_failure = 0;
3920 ha->hw.hbeat_failure++;
3923 if ((ha->dbg_level & 0x8000) && (ha->hw.hbeat_failure == 1))
3924 device_printf(ha->pci_dev, "%s: Heartbeat Failue 1[0x%08x]\n",
3926 if (ha->hw.hbeat_failure < 2) /* we ignore the first failure */
3929 uint32_t peg_halt_status1;
3930 uint32_t peg_halt_status2;
3932 peg_halt_status1 = READ_REG32(ha, Q8_PEG_HALT_STATUS1);
3933 peg_halt_status2 = READ_REG32(ha, Q8_PEG_HALT_STATUS2);
3935 device_printf(ha->pci_dev,
3936 "%s: Heartbeat Failue at ts_usecs = %ld "
3937 "fw_heart_beat = 0x%08x "
3938 "peg_halt_status1 = 0x%08x "
3939 "peg_halt_status2 = 0x%08x\n",
3940 __func__, qla_get_usec_timestamp(), val,
3941 peg_halt_status1, peg_halt_status2);
3943 if (ha->hw.sp_log_stop_events & Q8_SP_LOG_STOP_HBEAT_FAILURE)
3944 ha->hw.sp_log_stop = -1;
3946 QL_INITIATE_RECOVERY(ha);
3952 qla_init_nic_func(qla_host_t *ha)
3955 q80_init_nic_func_t *init_nic;
3956 q80_init_nic_func_rsp_t *init_nic_rsp;
3961 init_nic = (q80_init_nic_func_t *)ha->hw.mbox;
3962 bzero(init_nic, sizeof(q80_init_nic_func_t));
3964 init_nic->opcode = Q8_MBX_INIT_NIC_FUNC;
3965 init_nic->count_version = (sizeof (q80_init_nic_func_t) >> 2);
3966 init_nic->count_version |= Q8_MBX_CMD_VERSION;
3968 init_nic->options = Q8_INIT_NIC_REG_DCBX_CHNG_AEN;
3969 init_nic->options |= Q8_INIT_NIC_REG_SFP_CHNG_AEN;
3970 init_nic->options |= Q8_INIT_NIC_REG_IDC_AEN;
3972 //qla_dump_buf8(ha, __func__, init_nic, sizeof (q80_init_nic_func_t));
3973 if (qla_mbx_cmd(ha, (uint32_t *)init_nic,
3974 (sizeof (q80_init_nic_func_t) >> 2),
3975 ha->hw.mbox, (sizeof (q80_init_nic_func_rsp_t) >> 2), 0)) {
3976 device_printf(dev, "%s: failed\n", __func__);
3980 init_nic_rsp = (q80_init_nic_func_rsp_t *)ha->hw.mbox;
3981 // qla_dump_buf8(ha, __func__, init_nic_rsp, sizeof (q80_init_nic_func_rsp_t));
3983 err = Q8_MBX_RSP_STATUS(init_nic_rsp->regcnt_status);
3986 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
3988 device_printf(dev, "%s: successful\n", __func__);
3995 qla_stop_nic_func(qla_host_t *ha)
3998 q80_stop_nic_func_t *stop_nic;
3999 q80_stop_nic_func_rsp_t *stop_nic_rsp;
4004 stop_nic = (q80_stop_nic_func_t *)ha->hw.mbox;
4005 bzero(stop_nic, sizeof(q80_stop_nic_func_t));
4007 stop_nic->opcode = Q8_MBX_STOP_NIC_FUNC;
4008 stop_nic->count_version = (sizeof (q80_stop_nic_func_t) >> 2);
4009 stop_nic->count_version |= Q8_MBX_CMD_VERSION;
4011 stop_nic->options = Q8_STOP_NIC_DEREG_DCBX_CHNG_AEN;
4012 stop_nic->options |= Q8_STOP_NIC_DEREG_SFP_CHNG_AEN;
4014 //qla_dump_buf8(ha, __func__, stop_nic, sizeof (q80_stop_nic_func_t));
4015 if (qla_mbx_cmd(ha, (uint32_t *)stop_nic,
4016 (sizeof (q80_stop_nic_func_t) >> 2),
4017 ha->hw.mbox, (sizeof (q80_stop_nic_func_rsp_t) >> 2), 0)) {
4018 device_printf(dev, "%s: failed\n", __func__);
4022 stop_nic_rsp = (q80_stop_nic_func_rsp_t *)ha->hw.mbox;
4023 //qla_dump_buf8(ha, __func__, stop_nic_rsp, sizeof (q80_stop_nic_func_rsp_ t));
4025 err = Q8_MBX_RSP_STATUS(stop_nic_rsp->regcnt_status);
4028 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
4035 qla_query_fw_dcbx_caps(qla_host_t *ha)
4038 q80_query_fw_dcbx_caps_t *fw_dcbx;
4039 q80_query_fw_dcbx_caps_rsp_t *fw_dcbx_rsp;
4044 fw_dcbx = (q80_query_fw_dcbx_caps_t *)ha->hw.mbox;
4045 bzero(fw_dcbx, sizeof(q80_query_fw_dcbx_caps_t));
4047 fw_dcbx->opcode = Q8_MBX_GET_FW_DCBX_CAPS;
4048 fw_dcbx->count_version = (sizeof (q80_query_fw_dcbx_caps_t) >> 2);
4049 fw_dcbx->count_version |= Q8_MBX_CMD_VERSION;
4051 ql_dump_buf8(ha, __func__, fw_dcbx, sizeof (q80_query_fw_dcbx_caps_t));
4052 if (qla_mbx_cmd(ha, (uint32_t *)fw_dcbx,
4053 (sizeof (q80_query_fw_dcbx_caps_t) >> 2),
4054 ha->hw.mbox, (sizeof (q80_query_fw_dcbx_caps_rsp_t) >> 2), 0)) {
4055 device_printf(dev, "%s: failed\n", __func__);
4059 fw_dcbx_rsp = (q80_query_fw_dcbx_caps_rsp_t *)ha->hw.mbox;
4060 ql_dump_buf8(ha, __func__, fw_dcbx_rsp,
4061 sizeof (q80_query_fw_dcbx_caps_rsp_t));
4063 err = Q8_MBX_RSP_STATUS(fw_dcbx_rsp->regcnt_status);
4066 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
4073 qla_idc_ack(qla_host_t *ha, uint32_t aen_mb1, uint32_t aen_mb2,
4074 uint32_t aen_mb3, uint32_t aen_mb4)
4077 q80_idc_ack_t *idc_ack;
4078 q80_idc_ack_rsp_t *idc_ack_rsp;
4084 idc_ack = (q80_idc_ack_t *)ha->hw.mbox;
4085 bzero(idc_ack, sizeof(q80_idc_ack_t));
4087 idc_ack->opcode = Q8_MBX_IDC_ACK;
4088 idc_ack->count_version = (sizeof (q80_idc_ack_t) >> 2);
4089 idc_ack->count_version |= Q8_MBX_CMD_VERSION;
4091 idc_ack->aen_mb1 = aen_mb1;
4092 idc_ack->aen_mb2 = aen_mb2;
4093 idc_ack->aen_mb3 = aen_mb3;
4094 idc_ack->aen_mb4 = aen_mb4;
4096 ha->hw.imd_compl= 0;
4098 if (qla_mbx_cmd(ha, (uint32_t *)idc_ack,
4099 (sizeof (q80_idc_ack_t) >> 2),
4100 ha->hw.mbox, (sizeof (q80_idc_ack_rsp_t) >> 2), 0)) {
4101 device_printf(dev, "%s: failed\n", __func__);
4105 idc_ack_rsp = (q80_idc_ack_rsp_t *)ha->hw.mbox;
4107 err = Q8_MBX_RSP_STATUS(idc_ack_rsp->regcnt_status);
4110 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
4114 while (count && !ha->hw.imd_compl) {
4115 qla_mdelay(__func__, 100);
4122 device_printf(dev, "%s: count %d\n", __func__, count);
4128 qla_set_port_config(qla_host_t *ha, uint32_t cfg_bits)
4131 q80_set_port_cfg_t *pcfg;
4132 q80_set_port_cfg_rsp_t *pfg_rsp;
4138 pcfg = (q80_set_port_cfg_t *)ha->hw.mbox;
4139 bzero(pcfg, sizeof(q80_set_port_cfg_t));
4141 pcfg->opcode = Q8_MBX_SET_PORT_CONFIG;
4142 pcfg->count_version = (sizeof (q80_set_port_cfg_t) >> 2);
4143 pcfg->count_version |= Q8_MBX_CMD_VERSION;
4145 pcfg->cfg_bits = cfg_bits;
4147 device_printf(dev, "%s: cfg_bits"
4148 " [STD_PAUSE_DIR, PAUSE_TYPE, DCBX]"
4149 " [0x%x, 0x%x, 0x%x]\n", __func__,
4150 ((cfg_bits & Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK)>>20),
4151 ((cfg_bits & Q8_PORT_CFG_BITS_PAUSE_CFG_MASK) >> 5),
4152 ((cfg_bits & Q8_PORT_CFG_BITS_DCBX_ENABLE) ? 1: 0));
4154 ha->hw.imd_compl= 0;
4156 if (qla_mbx_cmd(ha, (uint32_t *)pcfg,
4157 (sizeof (q80_set_port_cfg_t) >> 2),
4158 ha->hw.mbox, (sizeof (q80_set_port_cfg_rsp_t) >> 2), 0)) {
4159 device_printf(dev, "%s: failed\n", __func__);
4163 pfg_rsp = (q80_set_port_cfg_rsp_t *)ha->hw.mbox;
4165 err = Q8_MBX_RSP_STATUS(pfg_rsp->regcnt_status);
4167 if (err == Q8_MBX_RSP_IDC_INTRMD_RSP) {
4168 while (count && !ha->hw.imd_compl) {
4169 qla_mdelay(__func__, 100);
4173 device_printf(dev, "%s: count %d\n", __func__, count);
4180 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
4189 qla_get_minidump_tmplt_size(qla_host_t *ha, uint32_t *size)
4192 device_t dev = ha->pci_dev;
4193 q80_config_md_templ_size_t *md_size;
4194 q80_config_md_templ_size_rsp_t *md_size_rsp;
4196 #ifndef QL_LDFLASH_FW
4198 ql_minidump_template_hdr_t *hdr;
4200 hdr = (ql_minidump_template_hdr_t *)ql83xx_minidump;
4201 *size = hdr->size_of_template;
4204 #endif /* #ifdef QL_LDFLASH_FW */
4206 md_size = (q80_config_md_templ_size_t *) ha->hw.mbox;
4207 bzero(md_size, sizeof(q80_config_md_templ_size_t));
4209 md_size->opcode = Q8_MBX_GET_MINIDUMP_TMPLT_SIZE;
4210 md_size->count_version = (sizeof (q80_config_md_templ_size_t) >> 2);
4211 md_size->count_version |= Q8_MBX_CMD_VERSION;
4213 if (qla_mbx_cmd(ha, (uint32_t *) md_size,
4214 (sizeof(q80_config_md_templ_size_t) >> 2), ha->hw.mbox,
4215 (sizeof(q80_config_md_templ_size_rsp_t) >> 2), 0)) {
4217 device_printf(dev, "%s: failed\n", __func__);
4222 md_size_rsp = (q80_config_md_templ_size_rsp_t *) ha->hw.mbox;
4224 err = Q8_MBX_RSP_STATUS(md_size_rsp->regcnt_status);
4227 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
4231 *size = md_size_rsp->templ_size;
4237 qla_get_port_config(qla_host_t *ha, uint32_t *cfg_bits)
4240 q80_get_port_cfg_t *pcfg;
4241 q80_get_port_cfg_rsp_t *pcfg_rsp;
4246 pcfg = (q80_get_port_cfg_t *)ha->hw.mbox;
4247 bzero(pcfg, sizeof(q80_get_port_cfg_t));
4249 pcfg->opcode = Q8_MBX_GET_PORT_CONFIG;
4250 pcfg->count_version = (sizeof (q80_get_port_cfg_t) >> 2);
4251 pcfg->count_version |= Q8_MBX_CMD_VERSION;
4253 if (qla_mbx_cmd(ha, (uint32_t *)pcfg,
4254 (sizeof (q80_get_port_cfg_t) >> 2),
4255 ha->hw.mbox, (sizeof (q80_get_port_cfg_rsp_t) >> 2), 0)) {
4256 device_printf(dev, "%s: failed\n", __func__);
4260 pcfg_rsp = (q80_get_port_cfg_rsp_t *)ha->hw.mbox;
4262 err = Q8_MBX_RSP_STATUS(pcfg_rsp->regcnt_status);
4265 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
4269 device_printf(dev, "%s: [cfg_bits, port type]"
4270 " [0x%08x, 0x%02x] [STD_PAUSE_DIR, PAUSE_TYPE, DCBX]"
4271 " [0x%x, 0x%x, 0x%x]\n", __func__,
4272 pcfg_rsp->cfg_bits, pcfg_rsp->phys_port_type,
4273 ((pcfg_rsp->cfg_bits & Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK)>>20),
4274 ((pcfg_rsp->cfg_bits & Q8_PORT_CFG_BITS_PAUSE_CFG_MASK) >> 5),
4275 ((pcfg_rsp->cfg_bits & Q8_PORT_CFG_BITS_DCBX_ENABLE) ? 1: 0)
4278 *cfg_bits = pcfg_rsp->cfg_bits;
4284 ql_iscsi_pdu(qla_host_t *ha, struct mbuf *mp)
4286 struct ether_vlan_header *eh;
4288 struct ip *ip = NULL;
4289 struct ip6_hdr *ip6 = NULL;
4290 struct tcphdr *th = NULL;
4293 uint8_t buf[sizeof(struct ip6_hdr)];
4295 eh = mtod(mp, struct ether_vlan_header *);
4297 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
4298 hdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
4299 etype = ntohs(eh->evl_proto);
4301 hdrlen = ETHER_HDR_LEN;
4302 etype = ntohs(eh->evl_encap_proto);
4305 if (etype == ETHERTYPE_IP) {
4307 offset = (hdrlen + sizeof (struct ip));
4309 if (mp->m_len >= offset) {
4310 ip = (struct ip *)(mp->m_data + hdrlen);
4312 m_copydata(mp, hdrlen, sizeof (struct ip), buf);
4313 ip = (struct ip *)buf;
4316 if (ip->ip_p == IPPROTO_TCP) {
4318 hdrlen += ip->ip_hl << 2;
4319 offset = hdrlen + 4;
4321 if (mp->m_len >= offset) {
4322 th = (struct tcphdr *)(mp->m_data + hdrlen);;
4324 m_copydata(mp, hdrlen, 4, buf);
4325 th = (struct tcphdr *)buf;
4329 } else if (etype == ETHERTYPE_IPV6) {
4331 offset = (hdrlen + sizeof (struct ip6_hdr));
4333 if (mp->m_len >= offset) {
4334 ip6 = (struct ip6_hdr *)(mp->m_data + hdrlen);
4336 m_copydata(mp, hdrlen, sizeof (struct ip6_hdr), buf);
4337 ip6 = (struct ip6_hdr *)buf;
4340 if (ip6->ip6_nxt == IPPROTO_TCP) {
4342 hdrlen += sizeof(struct ip6_hdr);
4343 offset = hdrlen + 4;
4345 if (mp->m_len >= offset) {
4346 th = (struct tcphdr *)(mp->m_data + hdrlen);;
4348 m_copydata(mp, hdrlen, 4, buf);
4349 th = (struct tcphdr *)buf;
4355 if ((th->th_sport == htons(3260)) ||
4356 (th->th_dport == htons(3260)))
4363 qla_hw_async_event(qla_host_t *ha)
4365 switch (ha->hw.aen_mb0) {
4367 (void)qla_idc_ack(ha, ha->hw.aen_mb1, ha->hw.aen_mb2,
4368 ha->hw.aen_mb3, ha->hw.aen_mb4);
4379 #ifdef QL_LDFLASH_FW
4381 ql_get_minidump_template(qla_host_t *ha)
4384 device_t dev = ha->pci_dev;
4385 q80_config_md_templ_cmd_t *md_templ;
4386 q80_config_md_templ_cmd_rsp_t *md_templ_rsp;
4388 md_templ = (q80_config_md_templ_cmd_t *) ha->hw.mbox;
4389 bzero(md_templ, (sizeof (q80_config_md_templ_cmd_t)));
4391 md_templ->opcode = Q8_MBX_GET_MINIDUMP_TMPLT;
4392 md_templ->count_version = ( sizeof(q80_config_md_templ_cmd_t) >> 2);
4393 md_templ->count_version |= Q8_MBX_CMD_VERSION;
4395 md_templ->buf_addr = ha->hw.dma_buf.minidump.dma_addr;
4396 md_templ->buff_size = ha->hw.dma_buf.minidump.size;
4398 if (qla_mbx_cmd(ha, (uint32_t *) md_templ,
4399 (sizeof(q80_config_md_templ_cmd_t) >> 2),
4401 (sizeof(q80_config_md_templ_cmd_rsp_t) >> 2), 0)) {
4403 device_printf(dev, "%s: failed\n", __func__);
4408 md_templ_rsp = (q80_config_md_templ_cmd_rsp_t *) ha->hw.mbox;
4410 err = Q8_MBX_RSP_STATUS(md_templ_rsp->regcnt_status);
4413 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
4420 #endif /* #ifdef QL_LDFLASH_FW */
4423 * Minidump related functionality
4426 static int ql_parse_template(qla_host_t *ha);
4428 static uint32_t ql_rdcrb(qla_host_t *ha,
4429 ql_minidump_entry_rdcrb_t *crb_entry,
4430 uint32_t * data_buff);
4432 static uint32_t ql_pollrd(qla_host_t *ha,
4433 ql_minidump_entry_pollrd_t *entry,
4434 uint32_t * data_buff);
4436 static uint32_t ql_pollrd_modify_write(qla_host_t *ha,
4437 ql_minidump_entry_rd_modify_wr_with_poll_t *entry,
4438 uint32_t *data_buff);
4440 static uint32_t ql_L2Cache(qla_host_t *ha,
4441 ql_minidump_entry_cache_t *cacheEntry,
4442 uint32_t * data_buff);
4444 static uint32_t ql_L1Cache(qla_host_t *ha,
4445 ql_minidump_entry_cache_t *cacheEntry,
4446 uint32_t *data_buff);
4448 static uint32_t ql_rdocm(qla_host_t *ha,
4449 ql_minidump_entry_rdocm_t *ocmEntry,
4450 uint32_t *data_buff);
4452 static uint32_t ql_rdmem(qla_host_t *ha,
4453 ql_minidump_entry_rdmem_t *mem_entry,
4454 uint32_t *data_buff);
4456 static uint32_t ql_rdrom(qla_host_t *ha,
4457 ql_minidump_entry_rdrom_t *romEntry,
4458 uint32_t *data_buff);
4460 static uint32_t ql_rdmux(qla_host_t *ha,
4461 ql_minidump_entry_mux_t *muxEntry,
4462 uint32_t *data_buff);
4464 static uint32_t ql_rdmux2(qla_host_t *ha,
4465 ql_minidump_entry_mux2_t *muxEntry,
4466 uint32_t *data_buff);
4468 static uint32_t ql_rdqueue(qla_host_t *ha,
4469 ql_minidump_entry_queue_t *queueEntry,
4470 uint32_t *data_buff);
4472 static uint32_t ql_cntrl(qla_host_t *ha,
4473 ql_minidump_template_hdr_t *template_hdr,
4474 ql_minidump_entry_cntrl_t *crbEntry);
4478 ql_minidump_size(qla_host_t *ha)
4482 ql_minidump_template_hdr_t *hdr;
4484 hdr = (ql_minidump_template_hdr_t *)ha->hw.dma_buf.minidump.dma_b;
4488 for (k = 1; k < QL_DBG_CAP_SIZE_ARRAY_LEN; k++) {
4489 if (i & ha->hw.mdump_capture_mask)
4490 size += hdr->capture_size_array[k];
4497 ql_free_minidump_buffer(qla_host_t *ha)
4499 if (ha->hw.mdump_buffer != NULL) {
4500 free(ha->hw.mdump_buffer, M_QLA83XXBUF);
4501 ha->hw.mdump_buffer = NULL;
4502 ha->hw.mdump_buffer_size = 0;
4508 ql_alloc_minidump_buffer(qla_host_t *ha)
4510 ha->hw.mdump_buffer_size = ql_minidump_size(ha);
4512 if (!ha->hw.mdump_buffer_size)
4515 ha->hw.mdump_buffer = malloc(ha->hw.mdump_buffer_size, M_QLA83XXBUF,
4518 if (ha->hw.mdump_buffer == NULL)
4525 ql_free_minidump_template_buffer(qla_host_t *ha)
4527 if (ha->hw.mdump_template != NULL) {
4528 free(ha->hw.mdump_template, M_QLA83XXBUF);
4529 ha->hw.mdump_template = NULL;
4530 ha->hw.mdump_template_size = 0;
4536 ql_alloc_minidump_template_buffer(qla_host_t *ha)
4538 ha->hw.mdump_template_size = ha->hw.dma_buf.minidump.size;
4540 ha->hw.mdump_template = malloc(ha->hw.mdump_template_size,
4541 M_QLA83XXBUF, M_NOWAIT);
4543 if (ha->hw.mdump_template == NULL)
4550 ql_alloc_minidump_buffers(qla_host_t *ha)
4554 ret = ql_alloc_minidump_template_buffer(ha);
4559 ret = ql_alloc_minidump_buffer(ha);
4562 ql_free_minidump_template_buffer(ha);
4569 ql_validate_minidump_checksum(qla_host_t *ha)
4573 uint32_t *template_buff;
4575 count = ha->hw.dma_buf.minidump.size / sizeof (uint32_t);
4576 template_buff = ha->hw.dma_buf.minidump.dma_b;
4578 while (count-- > 0) {
4579 sum += *template_buff++;
4583 sum = (sum & 0xFFFFFFFF) + (sum >> 32);
4590 ql_minidump_init(qla_host_t *ha)
4593 uint32_t template_size = 0;
4594 device_t dev = ha->pci_dev;
4597 * Get Minidump Template Size
4599 ret = qla_get_minidump_tmplt_size(ha, &template_size);
4601 if (ret || (template_size == 0)) {
4602 device_printf(dev, "%s: failed [%d, %d]\n", __func__, ret,
4608 * Allocate Memory for Minidump Template
4611 ha->hw.dma_buf.minidump.alignment = 8;
4612 ha->hw.dma_buf.minidump.size = template_size;
4614 #ifdef QL_LDFLASH_FW
4615 if (ql_alloc_dmabuf(ha, &ha->hw.dma_buf.minidump)) {
4617 device_printf(dev, "%s: minidump dma alloc failed\n", __func__);
4621 ha->hw.dma_buf.flags.minidump = 1;
4624 * Retrieve Minidump Template
4626 ret = ql_get_minidump_template(ha);
4628 ha->hw.dma_buf.minidump.dma_b = ql83xx_minidump;
4630 #endif /* #ifdef QL_LDFLASH_FW */
4634 ret = ql_validate_minidump_checksum(ha);
4638 ret = ql_alloc_minidump_buffers(ha);
4641 ha->hw.mdump_init = 1;
4644 "%s: ql_alloc_minidump_buffers"
4645 " failed\n", __func__);
4647 device_printf(dev, "%s: ql_validate_minidump_checksum"
4648 " failed\n", __func__);
4651 device_printf(dev, "%s: ql_get_minidump_template failed\n",
4656 ql_minidump_free(ha);
4662 ql_minidump_free(qla_host_t *ha)
4664 ha->hw.mdump_init = 0;
4665 if (ha->hw.dma_buf.flags.minidump) {
4666 ha->hw.dma_buf.flags.minidump = 0;
4667 ql_free_dmabuf(ha, &ha->hw.dma_buf.minidump);
4670 ql_free_minidump_template_buffer(ha);
4671 ql_free_minidump_buffer(ha);
4677 ql_minidump(qla_host_t *ha)
4679 if (!ha->hw.mdump_init)
4682 if (ha->hw.mdump_done)
4684 ha->hw.mdump_usec_ts = qla_get_usec_timestamp();
4685 ha->hw.mdump_start_seq_index = ql_stop_sequence(ha);
4687 bzero(ha->hw.mdump_buffer, ha->hw.mdump_buffer_size);
4688 bzero(ha->hw.mdump_template, ha->hw.mdump_template_size);
4690 bcopy(ha->hw.dma_buf.minidump.dma_b, ha->hw.mdump_template,
4691 ha->hw.mdump_template_size);
4693 ql_parse_template(ha);
4695 ql_start_sequence(ha, ha->hw.mdump_start_seq_index);
4697 ha->hw.mdump_done = 1;
4707 ql_entry_err_chk(ql_minidump_entry_t *entry, uint32_t esize)
4709 if (esize != entry->hdr.entry_capture_size) {
4710 entry->hdr.entry_capture_size = esize;
4711 entry->hdr.driver_flags |= QL_DBG_SIZE_ERR_FLAG;
4718 ql_parse_template(qla_host_t *ha)
4720 uint32_t num_of_entries, buff_level, e_cnt, esize;
4721 uint32_t end_cnt, rv = 0;
4722 char *dump_buff, *dbuff;
4723 int sane_start = 0, sane_end = 0;
4724 ql_minidump_template_hdr_t *template_hdr;
4725 ql_minidump_entry_t *entry;
4726 uint32_t capture_mask;
4729 /* Setup parameters */
4730 template_hdr = (ql_minidump_template_hdr_t *)ha->hw.mdump_template;
4732 if (template_hdr->entry_type == TLHDR)
4735 dump_buff = (char *) ha->hw.mdump_buffer;
4737 num_of_entries = template_hdr->num_of_entries;
4739 entry = (ql_minidump_entry_t *) ((char *)template_hdr
4740 + template_hdr->first_entry_offset );
4742 template_hdr->saved_state_array[QL_OCM0_ADDR_INDX] =
4743 template_hdr->ocm_window_array[ha->pci_func];
4744 template_hdr->saved_state_array[QL_PCIE_FUNC_INDX] = ha->pci_func;
4746 capture_mask = ha->hw.mdump_capture_mask;
4747 dump_size = ha->hw.mdump_buffer_size;
4749 template_hdr->driver_capture_mask = capture_mask;
4751 QL_DPRINT80(ha, (ha->pci_dev,
4752 "%s: sane_start = %d num_of_entries = %d "
4753 "capture_mask = 0x%x dump_size = %d \n",
4754 __func__, sane_start, num_of_entries, capture_mask, dump_size));
4756 for (buff_level = 0, e_cnt = 0; e_cnt < num_of_entries; e_cnt++) {
4759 * If the capture_mask of the entry does not match capture mask
4760 * skip the entry after marking the driver_flags indicator.
4763 if (!(entry->hdr.entry_capture_mask & capture_mask)) {
4765 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG;
4766 entry = (ql_minidump_entry_t *) ((char *) entry
4767 + entry->hdr.entry_size);
4772 * This is ONLY needed in implementations where
4773 * the capture buffer allocated is too small to capture
4774 * all of the required entries for a given capture mask.
4775 * We need to empty the buffer contents to a file
4776 * if possible, before processing the next entry
4777 * If the buff_full_flag is set, no further capture will happen
4778 * and all remaining non-control entries will be skipped.
4780 if (entry->hdr.entry_capture_size != 0) {
4781 if ((buff_level + entry->hdr.entry_capture_size) >
4783 /* Try to recover by emptying buffer to file */
4784 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG;
4785 entry = (ql_minidump_entry_t *) ((char *) entry
4786 + entry->hdr.entry_size);
4792 * Decode the entry type and process it accordingly
4795 switch (entry->hdr.entry_type) {
4800 if (sane_end == 0) {
4807 dbuff = dump_buff + buff_level;
4808 esize = ql_rdcrb(ha, (void *)entry, (void *)dbuff);
4809 ql_entry_err_chk(entry, esize);
4810 buff_level += esize;
4814 dbuff = dump_buff + buff_level;
4815 esize = ql_pollrd(ha, (void *)entry, (void *)dbuff);
4816 ql_entry_err_chk(entry, esize);
4817 buff_level += esize;
4821 dbuff = dump_buff + buff_level;
4822 esize = ql_pollrd_modify_write(ha, (void *)entry,
4824 ql_entry_err_chk(entry, esize);
4825 buff_level += esize;
4832 dbuff = dump_buff + buff_level;
4833 esize = ql_L2Cache(ha, (void *)entry, (void *)dbuff);
4835 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG;
4837 ql_entry_err_chk(entry, esize);
4838 buff_level += esize;
4844 dbuff = dump_buff + buff_level;
4845 esize = ql_L1Cache(ha, (void *)entry, (void *)dbuff);
4846 ql_entry_err_chk(entry, esize);
4847 buff_level += esize;
4851 dbuff = dump_buff + buff_level;
4852 esize = ql_rdocm(ha, (void *)entry, (void *)dbuff);
4853 ql_entry_err_chk(entry, esize);
4854 buff_level += esize;
4858 dbuff = dump_buff + buff_level;
4859 esize = ql_rdmem(ha, (void *)entry, (void *)dbuff);
4860 ql_entry_err_chk(entry, esize);
4861 buff_level += esize;
4866 dbuff = dump_buff + buff_level;
4867 esize = ql_rdrom(ha, (void *)entry, (void *)dbuff);
4868 ql_entry_err_chk(entry, esize);
4869 buff_level += esize;
4873 dbuff = dump_buff + buff_level;
4874 esize = ql_rdmux(ha, (void *)entry, (void *)dbuff);
4875 ql_entry_err_chk(entry, esize);
4876 buff_level += esize;
4880 dbuff = dump_buff + buff_level;
4881 esize = ql_rdmux2(ha, (void *)entry, (void *)dbuff);
4882 ql_entry_err_chk(entry, esize);
4883 buff_level += esize;
4887 dbuff = dump_buff + buff_level;
4888 esize = ql_rdqueue(ha, (void *)entry, (void *)dbuff);
4889 ql_entry_err_chk(entry, esize);
4890 buff_level += esize;
4894 if ((rv = ql_cntrl(ha, template_hdr, (void *)entry))) {
4895 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG;
4899 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG;
4902 /* next entry in the template */
4903 entry = (ql_minidump_entry_t *) ((char *) entry
4904 + entry->hdr.entry_size);
4907 if (!sane_start || (sane_end > 1)) {
4908 device_printf(ha->pci_dev,
4909 "\n%s: Template configuration error. Check Template\n",
4913 QL_DPRINT80(ha, (ha->pci_dev, "%s: Minidump num of entries = %d\n",
4914 __func__, template_hdr->num_of_entries));
4920 * Read CRB operation.
4923 ql_rdcrb(qla_host_t *ha, ql_minidump_entry_rdcrb_t * crb_entry,
4924 uint32_t * data_buff)
4928 uint32_t op_count, addr, stride, value = 0;
4930 addr = crb_entry->addr;
4931 op_count = crb_entry->op_count;
4932 stride = crb_entry->addr_stride;
4934 for (loop_cnt = 0; loop_cnt < op_count; loop_cnt++) {
4936 ret = ql_rdwr_indreg32(ha, addr, &value, 1);
4941 *data_buff++ = addr;
4942 *data_buff++ = value;
4943 addr = addr + stride;
4947 * for testing purpose we return amount of data written
4949 return (op_count * (2 * sizeof(uint32_t)));
4957 ql_L2Cache(qla_host_t *ha, ql_minidump_entry_cache_t *cacheEntry,
4958 uint32_t * data_buff)
4964 uint32_t read_value;
4965 uint32_t addr, read_addr, cntrl_addr, tag_reg_addr, cntl_value_w;
4966 uint32_t tag_value, read_cnt;
4967 volatile uint8_t cntl_value_r;
4971 loop_cnt = cacheEntry->op_count;
4973 read_addr = cacheEntry->read_addr;
4974 cntrl_addr = cacheEntry->control_addr;
4975 cntl_value_w = (uint32_t) cacheEntry->write_value;
4977 tag_reg_addr = cacheEntry->tag_reg_addr;
4979 tag_value = cacheEntry->init_tag_value;
4980 read_cnt = cacheEntry->read_addr_cnt;
4982 for (i = 0; i < loop_cnt; i++) {
4984 ret = ql_rdwr_indreg32(ha, tag_reg_addr, &tag_value, 0);
4988 if (cacheEntry->write_value != 0) {
4990 ret = ql_rdwr_indreg32(ha, cntrl_addr,
4996 if (cacheEntry->poll_mask != 0) {
4998 timeout = cacheEntry->poll_wait;
5000 ret = ql_rdwr_indreg32(ha, cntrl_addr, &data, 1);
5004 cntl_value_r = (uint8_t)data;
5006 while ((cntl_value_r & cacheEntry->poll_mask) != 0) {
5009 qla_mdelay(__func__, 1);
5014 ret = ql_rdwr_indreg32(ha, cntrl_addr,
5019 cntl_value_r = (uint8_t)data;
5022 /* Report timeout error.
5023 * core dump capture failed
5024 * Skip remaining entries.
5025 * Write buffer out to file
5026 * Use driver specific fields in template header
5027 * to report this error.
5034 for (k = 0; k < read_cnt; k++) {
5036 ret = ql_rdwr_indreg32(ha, addr, &read_value, 1);
5040 *data_buff++ = read_value;
5041 addr += cacheEntry->read_addr_stride;
5044 tag_value += cacheEntry->tag_value_stride;
5047 return (read_cnt * loop_cnt * sizeof(uint32_t));
5055 ql_L1Cache(qla_host_t *ha,
5056 ql_minidump_entry_cache_t *cacheEntry,
5057 uint32_t *data_buff)
5063 uint32_t read_value;
5064 uint32_t addr, read_addr, cntrl_addr, tag_reg_addr;
5065 uint32_t tag_value, read_cnt;
5066 uint32_t cntl_value_w;
5068 loop_cnt = cacheEntry->op_count;
5070 read_addr = cacheEntry->read_addr;
5071 cntrl_addr = cacheEntry->control_addr;
5072 cntl_value_w = (uint32_t) cacheEntry->write_value;
5074 tag_reg_addr = cacheEntry->tag_reg_addr;
5076 tag_value = cacheEntry->init_tag_value;
5077 read_cnt = cacheEntry->read_addr_cnt;
5079 for (i = 0; i < loop_cnt; i++) {
5081 ret = ql_rdwr_indreg32(ha, tag_reg_addr, &tag_value, 0);
5085 ret = ql_rdwr_indreg32(ha, cntrl_addr, &cntl_value_w, 0);
5090 for (k = 0; k < read_cnt; k++) {
5092 ret = ql_rdwr_indreg32(ha, addr, &read_value, 1);
5096 *data_buff++ = read_value;
5097 addr += cacheEntry->read_addr_stride;
5100 tag_value += cacheEntry->tag_value_stride;
5103 return (read_cnt * loop_cnt * sizeof(uint32_t));
5107 * Reading OCM memory
5111 ql_rdocm(qla_host_t *ha,
5112 ql_minidump_entry_rdocm_t *ocmEntry,
5113 uint32_t *data_buff)
5116 volatile uint32_t addr;
5117 volatile uint32_t value;
5119 addr = ocmEntry->read_addr;
5120 loop_cnt = ocmEntry->op_count;
5122 for (i = 0; i < loop_cnt; i++) {
5123 value = READ_REG32(ha, addr);
5124 *data_buff++ = value;
5125 addr += ocmEntry->read_addr_stride;
5127 return (loop_cnt * sizeof(value));
5135 ql_rdmem(qla_host_t *ha,
5136 ql_minidump_entry_rdmem_t *mem_entry,
5137 uint32_t *data_buff)
5141 volatile uint32_t addr;
5142 q80_offchip_mem_val_t val;
5144 addr = mem_entry->read_addr;
5146 /* size in bytes / 16 */
5147 loop_cnt = mem_entry->read_data_size / (sizeof(uint32_t) * 4);
5149 for (i = 0; i < loop_cnt; i++) {
5151 ret = ql_rdwr_offchip_mem(ha, (addr & 0x0ffffffff), &val, 1);
5155 *data_buff++ = val.data_lo;
5156 *data_buff++ = val.data_hi;
5157 *data_buff++ = val.data_ulo;
5158 *data_buff++ = val.data_uhi;
5160 addr += (sizeof(uint32_t) * 4);
5163 return (loop_cnt * (sizeof(uint32_t) * 4));
5171 ql_rdrom(qla_host_t *ha,
5172 ql_minidump_entry_rdrom_t *romEntry,
5173 uint32_t *data_buff)
5180 addr = romEntry->read_addr;
5181 loop_cnt = romEntry->read_data_size; /* This is size in bytes */
5182 loop_cnt /= sizeof(value);
5184 for (i = 0; i < loop_cnt; i++) {
5186 ret = ql_rd_flash32(ha, addr, &value);
5190 *data_buff++ = value;
5191 addr += sizeof(value);
5194 return (loop_cnt * sizeof(value));
5202 ql_rdmux(qla_host_t *ha,
5203 ql_minidump_entry_mux_t *muxEntry,
5204 uint32_t *data_buff)
5208 uint32_t read_value, sel_value;
5209 uint32_t read_addr, select_addr;
5211 select_addr = muxEntry->select_addr;
5212 sel_value = muxEntry->select_value;
5213 read_addr = muxEntry->read_addr;
5215 for (loop_cnt = 0; loop_cnt < muxEntry->op_count; loop_cnt++) {
5217 ret = ql_rdwr_indreg32(ha, select_addr, &sel_value, 0);
5221 ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1);
5225 *data_buff++ = sel_value;
5226 *data_buff++ = read_value;
5228 sel_value += muxEntry->select_value_stride;
5231 return (loop_cnt * (2 * sizeof(uint32_t)));
5235 ql_rdmux2(qla_host_t *ha,
5236 ql_minidump_entry_mux2_t *muxEntry,
5237 uint32_t *data_buff)
5242 uint32_t select_addr_1, select_addr_2;
5243 uint32_t select_value_1, select_value_2;
5244 uint32_t select_value_count, select_value_mask;
5245 uint32_t read_addr, read_value;
5247 select_addr_1 = muxEntry->select_addr_1;
5248 select_addr_2 = muxEntry->select_addr_2;
5249 select_value_1 = muxEntry->select_value_1;
5250 select_value_2 = muxEntry->select_value_2;
5251 select_value_count = muxEntry->select_value_count;
5252 select_value_mask = muxEntry->select_value_mask;
5254 read_addr = muxEntry->read_addr;
5256 for (loop_cnt = 0; loop_cnt < muxEntry->select_value_count;
5259 uint32_t temp_sel_val;
5261 ret = ql_rdwr_indreg32(ha, select_addr_1, &select_value_1, 0);
5265 temp_sel_val = select_value_1 & select_value_mask;
5267 ret = ql_rdwr_indreg32(ha, select_addr_2, &temp_sel_val, 0);
5271 ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1);
5275 *data_buff++ = temp_sel_val;
5276 *data_buff++ = read_value;
5278 ret = ql_rdwr_indreg32(ha, select_addr_1, &select_value_2, 0);
5282 temp_sel_val = select_value_2 & select_value_mask;
5284 ret = ql_rdwr_indreg32(ha, select_addr_2, &temp_sel_val, 0);
5288 ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1);
5292 *data_buff++ = temp_sel_val;
5293 *data_buff++ = read_value;
5295 select_value_1 += muxEntry->select_value_stride;
5296 select_value_2 += muxEntry->select_value_stride;
5299 return (loop_cnt * (4 * sizeof(uint32_t)));
5303 * Handling Queue State Reads.
5307 ql_rdqueue(qla_host_t *ha,
5308 ql_minidump_entry_queue_t *queueEntry,
5309 uint32_t *data_buff)
5313 uint32_t read_value;
5314 uint32_t read_addr, read_stride, select_addr;
5315 uint32_t queue_id, read_cnt;
5317 read_cnt = queueEntry->read_addr_cnt;
5318 read_stride = queueEntry->read_addr_stride;
5319 select_addr = queueEntry->select_addr;
5321 for (loop_cnt = 0, queue_id = 0; loop_cnt < queueEntry->op_count;
5324 ret = ql_rdwr_indreg32(ha, select_addr, &queue_id, 0);
5328 read_addr = queueEntry->read_addr;
5330 for (k = 0; k < read_cnt; k++) {
5332 ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1);
5336 *data_buff++ = read_value;
5337 read_addr += read_stride;
5340 queue_id += queueEntry->queue_id_stride;
5343 return (loop_cnt * (read_cnt * sizeof(uint32_t)));
5347 * Handling control entries.
5351 ql_cntrl(qla_host_t *ha,
5352 ql_minidump_template_hdr_t *template_hdr,
5353 ql_minidump_entry_cntrl_t *crbEntry)
5357 uint32_t opcode, read_value, addr, entry_addr;
5360 entry_addr = crbEntry->addr;
5362 for (count = 0; count < crbEntry->op_count; count++) {
5363 opcode = crbEntry->opcode;
5365 if (opcode & QL_DBG_OPCODE_WR) {
5367 ret = ql_rdwr_indreg32(ha, entry_addr,
5368 &crbEntry->value_1, 0);
5372 opcode &= ~QL_DBG_OPCODE_WR;
5375 if (opcode & QL_DBG_OPCODE_RW) {
5377 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 1);
5381 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 0);
5385 opcode &= ~QL_DBG_OPCODE_RW;
5388 if (opcode & QL_DBG_OPCODE_AND) {
5390 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 1);
5394 read_value &= crbEntry->value_2;
5395 opcode &= ~QL_DBG_OPCODE_AND;
5397 if (opcode & QL_DBG_OPCODE_OR) {
5398 read_value |= crbEntry->value_3;
5399 opcode &= ~QL_DBG_OPCODE_OR;
5402 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 0);
5407 if (opcode & QL_DBG_OPCODE_OR) {
5409 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 1);
5413 read_value |= crbEntry->value_3;
5415 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 0);
5419 opcode &= ~QL_DBG_OPCODE_OR;
5422 if (opcode & QL_DBG_OPCODE_POLL) {
5424 opcode &= ~QL_DBG_OPCODE_POLL;
5425 timeout = crbEntry->poll_timeout;
5428 ret = ql_rdwr_indreg32(ha, addr, &read_value, 1);
5432 while ((read_value & crbEntry->value_2)
5433 != crbEntry->value_1) {
5436 qla_mdelay(__func__, 1);
5441 ret = ql_rdwr_indreg32(ha, addr,
5449 * Report timeout error.
5450 * core dump capture failed
5451 * Skip remaining entries.
5452 * Write buffer out to file
5453 * Use driver specific fields in template header
5454 * to report this error.
5460 if (opcode & QL_DBG_OPCODE_RDSTATE) {
5462 * decide which address to use.
5464 if (crbEntry->state_index_a) {
5465 addr = template_hdr->saved_state_array[
5466 crbEntry-> state_index_a];
5471 ret = ql_rdwr_indreg32(ha, addr, &read_value, 1);
5475 template_hdr->saved_state_array[crbEntry->state_index_v]
5477 opcode &= ~QL_DBG_OPCODE_RDSTATE;
5480 if (opcode & QL_DBG_OPCODE_WRSTATE) {
5482 * decide which value to use.
5484 if (crbEntry->state_index_v) {
5485 read_value = template_hdr->saved_state_array[
5486 crbEntry->state_index_v];
5488 read_value = crbEntry->value_1;
5491 * decide which address to use.
5493 if (crbEntry->state_index_a) {
5494 addr = template_hdr->saved_state_array[
5495 crbEntry-> state_index_a];
5500 ret = ql_rdwr_indreg32(ha, addr, &read_value, 0);
5504 opcode &= ~QL_DBG_OPCODE_WRSTATE;
5507 if (opcode & QL_DBG_OPCODE_MDSTATE) {
5508 /* Read value from saved state using index */
5509 read_value = template_hdr->saved_state_array[
5510 crbEntry->state_index_v];
5512 read_value <<= crbEntry->shl; /*Shift left operation */
5513 read_value >>= crbEntry->shr; /*Shift right operation */
5515 if (crbEntry->value_2) {
5516 /* check if AND mask is provided */
5517 read_value &= crbEntry->value_2;
5520 read_value |= crbEntry->value_3; /* OR operation */
5521 read_value += crbEntry->value_1; /* increment op */
5523 /* Write value back to state area. */
5525 template_hdr->saved_state_array[crbEntry->state_index_v]
5527 opcode &= ~QL_DBG_OPCODE_MDSTATE;
5530 entry_addr += crbEntry->addr_stride;
5537 * Handling rd poll entry.
5541 ql_pollrd(qla_host_t *ha, ql_minidump_entry_pollrd_t *entry,
5542 uint32_t *data_buff)
5546 uint32_t op_count, select_addr, select_value_stride, select_value;
5547 uint32_t read_addr, poll, mask, data_size, data;
5548 uint32_t wait_count = 0;
5550 select_addr = entry->select_addr;
5551 read_addr = entry->read_addr;
5552 select_value = entry->select_value;
5553 select_value_stride = entry->select_value_stride;
5554 op_count = entry->op_count;
5557 data_size = entry->data_size;
5559 for (loop_cnt = 0; loop_cnt < op_count; loop_cnt++) {
5561 ret = ql_rdwr_indreg32(ha, select_addr, &select_value, 0);
5567 while (wait_count < poll) {
5571 ret = ql_rdwr_indreg32(ha, select_addr, &temp, 1);
5575 if ( (temp & mask) != 0 ) {
5581 if (wait_count == poll) {
5582 device_printf(ha->pci_dev,
5583 "%s: Error in processing entry\n", __func__);
5584 device_printf(ha->pci_dev,
5585 "%s: wait_count <0x%x> poll <0x%x>\n",
5586 __func__, wait_count, poll);
5590 ret = ql_rdwr_indreg32(ha, read_addr, &data, 1);
5594 *data_buff++ = select_value;
5595 *data_buff++ = data;
5596 select_value = select_value + select_value_stride;
5600 * for testing purpose we return amount of data written
5602 return (loop_cnt * (2 * sizeof(uint32_t)));
5607 * Handling rd modify write poll entry.
5611 ql_pollrd_modify_write(qla_host_t *ha,
5612 ql_minidump_entry_rd_modify_wr_with_poll_t *entry,
5613 uint32_t *data_buff)
5616 uint32_t addr_1, addr_2, value_1, value_2, data;
5617 uint32_t poll, mask, data_size, modify_mask;
5618 uint32_t wait_count = 0;
5620 addr_1 = entry->addr_1;
5621 addr_2 = entry->addr_2;
5622 value_1 = entry->value_1;
5623 value_2 = entry->value_2;
5627 modify_mask = entry->modify_mask;
5628 data_size = entry->data_size;
5631 ret = ql_rdwr_indreg32(ha, addr_1, &value_1, 0);
5636 while (wait_count < poll) {
5640 ret = ql_rdwr_indreg32(ha, addr_1, &temp, 1);
5644 if ( (temp & mask) != 0 ) {
5650 if (wait_count == poll) {
5651 device_printf(ha->pci_dev, "%s Error in processing entry\n",
5655 ret = ql_rdwr_indreg32(ha, addr_2, &data, 1);
5659 data = (data & modify_mask);
5661 ret = ql_rdwr_indreg32(ha, addr_2, &data, 0);
5665 ret = ql_rdwr_indreg32(ha, addr_1, &value_2, 0);
5671 while (wait_count < poll) {
5675 ret = ql_rdwr_indreg32(ha, addr_1, &temp, 1);
5679 if ( (temp & mask) != 0 ) {
5684 *data_buff++ = addr_2;
5685 *data_buff++ = data;
5689 * for testing purpose we return amount of data written
5691 return (2 * sizeof(uint32_t));