2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013-2016 Qlogic Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
32 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
33 * Content: Contains Hardware dependent functions
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
42 #include "ql_inline.h"
46 #include "ql_minidump.h"
52 static void qla_del_rcv_cntxt(qla_host_t *ha);
53 static int qla_init_rcv_cntxt(qla_host_t *ha);
54 static void qla_del_xmt_cntxt(qla_host_t *ha);
55 static int qla_init_xmt_cntxt(qla_host_t *ha);
56 static int qla_mbx_cmd(qla_host_t *ha, uint32_t *h_mbox, uint32_t n_hmbox,
57 uint32_t *fw_mbox, uint32_t n_fwmbox, uint32_t no_pause);
58 static int qla_config_intr_cntxt(qla_host_t *ha, uint32_t start_idx,
59 uint32_t num_intrs, uint32_t create);
60 static int qla_config_rss(qla_host_t *ha, uint16_t cntxt_id);
61 static int qla_config_intr_coalesce(qla_host_t *ha, uint16_t cntxt_id,
62 int tenable, int rcv);
63 static int qla_set_mac_rcv_mode(qla_host_t *ha, uint32_t mode);
64 static int qla_link_event_req(qla_host_t *ha, uint16_t cntxt_id);
66 static int qla_tx_tso(qla_host_t *ha, struct mbuf *mp, q80_tx_cmd_t *tx_cmd,
68 static int qla_hw_add_all_mcast(qla_host_t *ha);
69 static int qla_add_rcv_rings(qla_host_t *ha, uint32_t sds_idx, uint32_t nsds);
71 static int qla_init_nic_func(qla_host_t *ha);
72 static int qla_stop_nic_func(qla_host_t *ha);
73 static int qla_query_fw_dcbx_caps(qla_host_t *ha);
74 static int qla_set_port_config(qla_host_t *ha, uint32_t cfg_bits);
75 static int qla_get_port_config(qla_host_t *ha, uint32_t *cfg_bits);
76 static int qla_set_cam_search_mode(qla_host_t *ha, uint32_t search_mode);
77 static int qla_get_cam_search_mode(qla_host_t *ha);
79 static void ql_minidump_free(qla_host_t *ha);
84 qla_stop_pegs(qla_host_t *ha)
88 ql_rdwr_indreg32(ha, Q8_CRB_PEG_0, &val, 0);
89 ql_rdwr_indreg32(ha, Q8_CRB_PEG_1, &val, 0);
90 ql_rdwr_indreg32(ha, Q8_CRB_PEG_2, &val, 0);
91 ql_rdwr_indreg32(ha, Q8_CRB_PEG_3, &val, 0);
92 ql_rdwr_indreg32(ha, Q8_CRB_PEG_4, &val, 0);
93 device_printf(ha->pci_dev, "%s PEGS HALTED!!!!!\n", __func__);
97 qla_sysctl_stop_pegs(SYSCTL_HANDLER_ARGS)
102 err = sysctl_handle_int(oidp, &ret, 0, req);
105 if (err || !req->newptr)
109 ha = (qla_host_t *)arg1;
110 if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) {
112 QLA_UNLOCK(ha, __func__);
118 #endif /* #ifdef QL_DBG */
121 qla_validate_set_port_cfg_bit(uint32_t bits)
123 if ((bits & 0xF) > 1)
126 if (((bits >> 4) & 0xF) > 2)
129 if (((bits >> 8) & 0xF) > 2)
136 qla_sysctl_port_cfg(SYSCTL_HANDLER_ARGS)
142 err = sysctl_handle_int(oidp, &ret, 0, req);
144 if (err || !req->newptr)
147 ha = (qla_host_t *)arg1;
149 if ((qla_validate_set_port_cfg_bit((uint32_t)ret) == 0)) {
151 err = qla_get_port_config(ha, &cfg_bits);
154 goto qla_sysctl_set_port_cfg_exit;
157 cfg_bits |= Q8_PORT_CFG_BITS_DCBX_ENABLE;
159 cfg_bits &= ~Q8_PORT_CFG_BITS_DCBX_ENABLE;
163 cfg_bits &= ~Q8_PORT_CFG_BITS_PAUSE_CFG_MASK;
165 if ((ret & 0xF) == 0) {
166 cfg_bits |= Q8_PORT_CFG_BITS_PAUSE_DISABLED;
167 } else if ((ret & 0xF) == 1){
168 cfg_bits |= Q8_PORT_CFG_BITS_PAUSE_STD;
170 cfg_bits |= Q8_PORT_CFG_BITS_PAUSE_PPM;
174 cfg_bits &= ~Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK;
177 cfg_bits |= Q8_PORT_CFG_BITS_STDPAUSE_XMT_RCV;
178 } else if (ret == 1){
179 cfg_bits |= Q8_PORT_CFG_BITS_STDPAUSE_XMT;
181 cfg_bits |= Q8_PORT_CFG_BITS_STDPAUSE_RCV;
184 if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) {
185 err = qla_set_port_config(ha, cfg_bits);
186 QLA_UNLOCK(ha, __func__);
188 device_printf(ha->pci_dev, "%s: failed\n", __func__);
191 if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) {
192 err = qla_get_port_config(ha, &cfg_bits);
193 QLA_UNLOCK(ha, __func__);
195 device_printf(ha->pci_dev, "%s: failed\n", __func__);
199 qla_sysctl_set_port_cfg_exit:
204 qla_sysctl_set_cam_search_mode(SYSCTL_HANDLER_ARGS)
209 err = sysctl_handle_int(oidp, &ret, 0, req);
211 if (err || !req->newptr)
214 ha = (qla_host_t *)arg1;
216 if ((ret == Q8_HW_CONFIG_CAM_SEARCH_MODE_INTERNAL) ||
217 (ret == Q8_HW_CONFIG_CAM_SEARCH_MODE_AUTO)) {
219 if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) {
220 err = qla_set_cam_search_mode(ha, (uint32_t)ret);
221 QLA_UNLOCK(ha, __func__);
223 device_printf(ha->pci_dev, "%s: failed\n", __func__);
227 device_printf(ha->pci_dev, "%s: ret = %d\n", __func__, ret);
234 qla_sysctl_get_cam_search_mode(SYSCTL_HANDLER_ARGS)
239 err = sysctl_handle_int(oidp, &ret, 0, req);
241 if (err || !req->newptr)
244 ha = (qla_host_t *)arg1;
245 if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) {
246 err = qla_get_cam_search_mode(ha);
247 QLA_UNLOCK(ha, __func__);
249 device_printf(ha->pci_dev, "%s: failed\n", __func__);
256 qlnx_add_hw_mac_stats_sysctls(qla_host_t *ha)
258 struct sysctl_ctx_list *ctx;
259 struct sysctl_oid_list *children;
260 struct sysctl_oid *ctx_oid;
262 ctx = device_get_sysctl_ctx(ha->pci_dev);
263 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev));
265 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_hw_mac",
266 CTLFLAG_RD, NULL, "stats_hw_mac");
267 children = SYSCTL_CHILDREN(ctx_oid);
269 SYSCTL_ADD_QUAD(ctx, children,
270 OID_AUTO, "xmt_frames",
271 CTLFLAG_RD, &ha->hw.mac.xmt_frames,
274 SYSCTL_ADD_QUAD(ctx, children,
275 OID_AUTO, "xmt_bytes",
276 CTLFLAG_RD, &ha->hw.mac.xmt_bytes,
279 SYSCTL_ADD_QUAD(ctx, children,
280 OID_AUTO, "xmt_mcast_pkts",
281 CTLFLAG_RD, &ha->hw.mac.xmt_mcast_pkts,
284 SYSCTL_ADD_QUAD(ctx, children,
285 OID_AUTO, "xmt_bcast_pkts",
286 CTLFLAG_RD, &ha->hw.mac.xmt_bcast_pkts,
289 SYSCTL_ADD_QUAD(ctx, children,
290 OID_AUTO, "xmt_pause_frames",
291 CTLFLAG_RD, &ha->hw.mac.xmt_pause_frames,
294 SYSCTL_ADD_QUAD(ctx, children,
295 OID_AUTO, "xmt_cntrl_pkts",
296 CTLFLAG_RD, &ha->hw.mac.xmt_cntrl_pkts,
299 SYSCTL_ADD_QUAD(ctx, children,
300 OID_AUTO, "xmt_pkt_lt_64bytes",
301 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_64bytes,
302 "xmt_pkt_lt_64bytes");
304 SYSCTL_ADD_QUAD(ctx, children,
305 OID_AUTO, "xmt_pkt_lt_127bytes",
306 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_127bytes,
307 "xmt_pkt_lt_127bytes");
309 SYSCTL_ADD_QUAD(ctx, children,
310 OID_AUTO, "xmt_pkt_lt_255bytes",
311 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_255bytes,
312 "xmt_pkt_lt_255bytes");
314 SYSCTL_ADD_QUAD(ctx, children,
315 OID_AUTO, "xmt_pkt_lt_511bytes",
316 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_511bytes,
317 "xmt_pkt_lt_511bytes");
319 SYSCTL_ADD_QUAD(ctx, children,
320 OID_AUTO, "xmt_pkt_lt_1023bytes",
321 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_1023bytes,
322 "xmt_pkt_lt_1023bytes");
324 SYSCTL_ADD_QUAD(ctx, children,
325 OID_AUTO, "xmt_pkt_lt_1518bytes",
326 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_1518bytes,
327 "xmt_pkt_lt_1518bytes");
329 SYSCTL_ADD_QUAD(ctx, children,
330 OID_AUTO, "xmt_pkt_gt_1518bytes",
331 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_gt_1518bytes,
332 "xmt_pkt_gt_1518bytes");
334 SYSCTL_ADD_QUAD(ctx, children,
335 OID_AUTO, "rcv_frames",
336 CTLFLAG_RD, &ha->hw.mac.rcv_frames,
339 SYSCTL_ADD_QUAD(ctx, children,
340 OID_AUTO, "rcv_bytes",
341 CTLFLAG_RD, &ha->hw.mac.rcv_bytes,
344 SYSCTL_ADD_QUAD(ctx, children,
345 OID_AUTO, "rcv_mcast_pkts",
346 CTLFLAG_RD, &ha->hw.mac.rcv_mcast_pkts,
349 SYSCTL_ADD_QUAD(ctx, children,
350 OID_AUTO, "rcv_bcast_pkts",
351 CTLFLAG_RD, &ha->hw.mac.rcv_bcast_pkts,
354 SYSCTL_ADD_QUAD(ctx, children,
355 OID_AUTO, "rcv_pause_frames",
356 CTLFLAG_RD, &ha->hw.mac.rcv_pause_frames,
359 SYSCTL_ADD_QUAD(ctx, children,
360 OID_AUTO, "rcv_cntrl_pkts",
361 CTLFLAG_RD, &ha->hw.mac.rcv_cntrl_pkts,
364 SYSCTL_ADD_QUAD(ctx, children,
365 OID_AUTO, "rcv_pkt_lt_64bytes",
366 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_64bytes,
367 "rcv_pkt_lt_64bytes");
369 SYSCTL_ADD_QUAD(ctx, children,
370 OID_AUTO, "rcv_pkt_lt_127bytes",
371 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_127bytes,
372 "rcv_pkt_lt_127bytes");
374 SYSCTL_ADD_QUAD(ctx, children,
375 OID_AUTO, "rcv_pkt_lt_255bytes",
376 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_255bytes,
377 "rcv_pkt_lt_255bytes");
379 SYSCTL_ADD_QUAD(ctx, children,
380 OID_AUTO, "rcv_pkt_lt_511bytes",
381 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_511bytes,
382 "rcv_pkt_lt_511bytes");
384 SYSCTL_ADD_QUAD(ctx, children,
385 OID_AUTO, "rcv_pkt_lt_1023bytes",
386 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_1023bytes,
387 "rcv_pkt_lt_1023bytes");
389 SYSCTL_ADD_QUAD(ctx, children,
390 OID_AUTO, "rcv_pkt_lt_1518bytes",
391 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_1518bytes,
392 "rcv_pkt_lt_1518bytes");
394 SYSCTL_ADD_QUAD(ctx, children,
395 OID_AUTO, "rcv_pkt_gt_1518bytes",
396 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_gt_1518bytes,
397 "rcv_pkt_gt_1518bytes");
399 SYSCTL_ADD_QUAD(ctx, children,
400 OID_AUTO, "rcv_len_error",
401 CTLFLAG_RD, &ha->hw.mac.rcv_len_error,
404 SYSCTL_ADD_QUAD(ctx, children,
405 OID_AUTO, "rcv_len_small",
406 CTLFLAG_RD, &ha->hw.mac.rcv_len_small,
409 SYSCTL_ADD_QUAD(ctx, children,
410 OID_AUTO, "rcv_len_large",
411 CTLFLAG_RD, &ha->hw.mac.rcv_len_large,
414 SYSCTL_ADD_QUAD(ctx, children,
415 OID_AUTO, "rcv_jabber",
416 CTLFLAG_RD, &ha->hw.mac.rcv_jabber,
419 SYSCTL_ADD_QUAD(ctx, children,
420 OID_AUTO, "rcv_dropped",
421 CTLFLAG_RD, &ha->hw.mac.rcv_dropped,
424 SYSCTL_ADD_QUAD(ctx, children,
425 OID_AUTO, "fcs_error",
426 CTLFLAG_RD, &ha->hw.mac.fcs_error,
429 SYSCTL_ADD_QUAD(ctx, children,
430 OID_AUTO, "align_error",
431 CTLFLAG_RD, &ha->hw.mac.align_error,
434 SYSCTL_ADD_QUAD(ctx, children,
435 OID_AUTO, "eswitched_frames",
436 CTLFLAG_RD, &ha->hw.mac.eswitched_frames,
439 SYSCTL_ADD_QUAD(ctx, children,
440 OID_AUTO, "eswitched_bytes",
441 CTLFLAG_RD, &ha->hw.mac.eswitched_bytes,
444 SYSCTL_ADD_QUAD(ctx, children,
445 OID_AUTO, "eswitched_mcast_frames",
446 CTLFLAG_RD, &ha->hw.mac.eswitched_mcast_frames,
447 "eswitched_mcast_frames");
449 SYSCTL_ADD_QUAD(ctx, children,
450 OID_AUTO, "eswitched_bcast_frames",
451 CTLFLAG_RD, &ha->hw.mac.eswitched_bcast_frames,
452 "eswitched_bcast_frames");
454 SYSCTL_ADD_QUAD(ctx, children,
455 OID_AUTO, "eswitched_ucast_frames",
456 CTLFLAG_RD, &ha->hw.mac.eswitched_ucast_frames,
457 "eswitched_ucast_frames");
459 SYSCTL_ADD_QUAD(ctx, children,
460 OID_AUTO, "eswitched_err_free_frames",
461 CTLFLAG_RD, &ha->hw.mac.eswitched_err_free_frames,
462 "eswitched_err_free_frames");
464 SYSCTL_ADD_QUAD(ctx, children,
465 OID_AUTO, "eswitched_err_free_bytes",
466 CTLFLAG_RD, &ha->hw.mac.eswitched_err_free_bytes,
467 "eswitched_err_free_bytes");
473 qlnx_add_hw_rcv_stats_sysctls(qla_host_t *ha)
475 struct sysctl_ctx_list *ctx;
476 struct sysctl_oid_list *children;
477 struct sysctl_oid *ctx_oid;
479 ctx = device_get_sysctl_ctx(ha->pci_dev);
480 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev));
482 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_hw_rcv",
483 CTLFLAG_RD, NULL, "stats_hw_rcv");
484 children = SYSCTL_CHILDREN(ctx_oid);
486 SYSCTL_ADD_QUAD(ctx, children,
487 OID_AUTO, "total_bytes",
488 CTLFLAG_RD, &ha->hw.rcv.total_bytes,
491 SYSCTL_ADD_QUAD(ctx, children,
492 OID_AUTO, "total_pkts",
493 CTLFLAG_RD, &ha->hw.rcv.total_pkts,
496 SYSCTL_ADD_QUAD(ctx, children,
497 OID_AUTO, "lro_pkt_count",
498 CTLFLAG_RD, &ha->hw.rcv.lro_pkt_count,
501 SYSCTL_ADD_QUAD(ctx, children,
502 OID_AUTO, "sw_pkt_count",
503 CTLFLAG_RD, &ha->hw.rcv.sw_pkt_count,
506 SYSCTL_ADD_QUAD(ctx, children,
507 OID_AUTO, "ip_chksum_err",
508 CTLFLAG_RD, &ha->hw.rcv.ip_chksum_err,
511 SYSCTL_ADD_QUAD(ctx, children,
512 OID_AUTO, "pkts_wo_acntxts",
513 CTLFLAG_RD, &ha->hw.rcv.pkts_wo_acntxts,
516 SYSCTL_ADD_QUAD(ctx, children,
517 OID_AUTO, "pkts_dropped_no_sds_card",
518 CTLFLAG_RD, &ha->hw.rcv.pkts_dropped_no_sds_card,
519 "pkts_dropped_no_sds_card");
521 SYSCTL_ADD_QUAD(ctx, children,
522 OID_AUTO, "pkts_dropped_no_sds_host",
523 CTLFLAG_RD, &ha->hw.rcv.pkts_dropped_no_sds_host,
524 "pkts_dropped_no_sds_host");
526 SYSCTL_ADD_QUAD(ctx, children,
527 OID_AUTO, "oversized_pkts",
528 CTLFLAG_RD, &ha->hw.rcv.oversized_pkts,
531 SYSCTL_ADD_QUAD(ctx, children,
532 OID_AUTO, "pkts_dropped_no_rds",
533 CTLFLAG_RD, &ha->hw.rcv.pkts_dropped_no_rds,
534 "pkts_dropped_no_rds");
536 SYSCTL_ADD_QUAD(ctx, children,
537 OID_AUTO, "unxpctd_mcast_pkts",
538 CTLFLAG_RD, &ha->hw.rcv.unxpctd_mcast_pkts,
539 "unxpctd_mcast_pkts");
541 SYSCTL_ADD_QUAD(ctx, children,
542 OID_AUTO, "re1_fbq_error",
543 CTLFLAG_RD, &ha->hw.rcv.re1_fbq_error,
546 SYSCTL_ADD_QUAD(ctx, children,
547 OID_AUTO, "invalid_mac_addr",
548 CTLFLAG_RD, &ha->hw.rcv.invalid_mac_addr,
551 SYSCTL_ADD_QUAD(ctx, children,
552 OID_AUTO, "rds_prime_trys",
553 CTLFLAG_RD, &ha->hw.rcv.rds_prime_trys,
556 SYSCTL_ADD_QUAD(ctx, children,
557 OID_AUTO, "rds_prime_success",
558 CTLFLAG_RD, &ha->hw.rcv.rds_prime_success,
559 "rds_prime_success");
561 SYSCTL_ADD_QUAD(ctx, children,
562 OID_AUTO, "lro_flows_added",
563 CTLFLAG_RD, &ha->hw.rcv.lro_flows_added,
566 SYSCTL_ADD_QUAD(ctx, children,
567 OID_AUTO, "lro_flows_deleted",
568 CTLFLAG_RD, &ha->hw.rcv.lro_flows_deleted,
569 "lro_flows_deleted");
571 SYSCTL_ADD_QUAD(ctx, children,
572 OID_AUTO, "lro_flows_active",
573 CTLFLAG_RD, &ha->hw.rcv.lro_flows_active,
576 SYSCTL_ADD_QUAD(ctx, children,
577 OID_AUTO, "pkts_droped_unknown",
578 CTLFLAG_RD, &ha->hw.rcv.pkts_droped_unknown,
579 "pkts_droped_unknown");
581 SYSCTL_ADD_QUAD(ctx, children,
582 OID_AUTO, "pkts_cnt_oversized",
583 CTLFLAG_RD, &ha->hw.rcv.pkts_cnt_oversized,
584 "pkts_cnt_oversized");
590 qlnx_add_hw_xmt_stats_sysctls(qla_host_t *ha)
592 struct sysctl_ctx_list *ctx;
593 struct sysctl_oid_list *children;
594 struct sysctl_oid_list *node_children;
595 struct sysctl_oid *ctx_oid;
597 uint8_t name_str[16];
599 ctx = device_get_sysctl_ctx(ha->pci_dev);
600 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev));
602 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_hw_xmt",
603 CTLFLAG_RD, NULL, "stats_hw_xmt");
604 children = SYSCTL_CHILDREN(ctx_oid);
606 for (i = 0; i < ha->hw.num_tx_rings; i++) {
608 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str)));
609 snprintf(name_str, sizeof(name_str), "%d", i);
611 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name_str,
612 CTLFLAG_RD, NULL, name_str);
613 node_children = SYSCTL_CHILDREN(ctx_oid);
617 SYSCTL_ADD_QUAD(ctx, node_children,
618 OID_AUTO, "total_bytes",
619 CTLFLAG_RD, &ha->hw.xmt[i].total_bytes,
622 SYSCTL_ADD_QUAD(ctx, node_children,
623 OID_AUTO, "total_pkts",
624 CTLFLAG_RD, &ha->hw.xmt[i].total_pkts,
627 SYSCTL_ADD_QUAD(ctx, node_children,
629 CTLFLAG_RD, &ha->hw.xmt[i].errors,
632 SYSCTL_ADD_QUAD(ctx, node_children,
633 OID_AUTO, "pkts_dropped",
634 CTLFLAG_RD, &ha->hw.xmt[i].pkts_dropped,
637 SYSCTL_ADD_QUAD(ctx, node_children,
638 OID_AUTO, "switch_pkts",
639 CTLFLAG_RD, &ha->hw.xmt[i].switch_pkts,
642 SYSCTL_ADD_QUAD(ctx, node_children,
643 OID_AUTO, "num_buffers",
644 CTLFLAG_RD, &ha->hw.xmt[i].num_buffers,
652 qlnx_add_hw_stats_sysctls(qla_host_t *ha)
654 qlnx_add_hw_mac_stats_sysctls(ha);
655 qlnx_add_hw_rcv_stats_sysctls(ha);
656 qlnx_add_hw_xmt_stats_sysctls(ha);
662 qlnx_add_drvr_sds_stats(qla_host_t *ha)
664 struct sysctl_ctx_list *ctx;
665 struct sysctl_oid_list *children;
666 struct sysctl_oid_list *node_children;
667 struct sysctl_oid *ctx_oid;
669 uint8_t name_str[16];
671 ctx = device_get_sysctl_ctx(ha->pci_dev);
672 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev));
674 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_drvr_sds",
675 CTLFLAG_RD, NULL, "stats_drvr_sds");
676 children = SYSCTL_CHILDREN(ctx_oid);
678 for (i = 0; i < ha->hw.num_sds_rings; i++) {
680 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str)));
681 snprintf(name_str, sizeof(name_str), "%d", i);
683 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name_str,
684 CTLFLAG_RD, NULL, name_str);
685 node_children = SYSCTL_CHILDREN(ctx_oid);
687 SYSCTL_ADD_QUAD(ctx, node_children,
688 OID_AUTO, "intr_count",
689 CTLFLAG_RD, &ha->hw.sds[i].intr_count,
692 SYSCTL_ADD_UINT(ctx, node_children,
694 CTLFLAG_RD, &ha->hw.sds[i].rx_free,
695 ha->hw.sds[i].rx_free, "rx_free");
701 qlnx_add_drvr_rds_stats(qla_host_t *ha)
703 struct sysctl_ctx_list *ctx;
704 struct sysctl_oid_list *children;
705 struct sysctl_oid_list *node_children;
706 struct sysctl_oid *ctx_oid;
708 uint8_t name_str[16];
710 ctx = device_get_sysctl_ctx(ha->pci_dev);
711 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev));
713 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_drvr_rds",
714 CTLFLAG_RD, NULL, "stats_drvr_rds");
715 children = SYSCTL_CHILDREN(ctx_oid);
717 for (i = 0; i < ha->hw.num_rds_rings; i++) {
719 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str)));
720 snprintf(name_str, sizeof(name_str), "%d", i);
722 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name_str,
723 CTLFLAG_RD, NULL, name_str);
724 node_children = SYSCTL_CHILDREN(ctx_oid);
726 SYSCTL_ADD_QUAD(ctx, node_children,
728 CTLFLAG_RD, &ha->hw.rds[i].count,
731 SYSCTL_ADD_QUAD(ctx, node_children,
732 OID_AUTO, "lro_pkt_count",
733 CTLFLAG_RD, &ha->hw.rds[i].lro_pkt_count,
736 SYSCTL_ADD_QUAD(ctx, node_children,
737 OID_AUTO, "lro_bytes",
738 CTLFLAG_RD, &ha->hw.rds[i].lro_bytes,
746 qlnx_add_drvr_tx_stats(qla_host_t *ha)
748 struct sysctl_ctx_list *ctx;
749 struct sysctl_oid_list *children;
750 struct sysctl_oid_list *node_children;
751 struct sysctl_oid *ctx_oid;
753 uint8_t name_str[16];
755 ctx = device_get_sysctl_ctx(ha->pci_dev);
756 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev));
758 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_drvr_xmt",
759 CTLFLAG_RD, NULL, "stats_drvr_xmt");
760 children = SYSCTL_CHILDREN(ctx_oid);
762 for (i = 0; i < ha->hw.num_tx_rings; i++) {
764 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str)));
765 snprintf(name_str, sizeof(name_str), "%d", i);
767 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name_str,
768 CTLFLAG_RD, NULL, name_str);
769 node_children = SYSCTL_CHILDREN(ctx_oid);
771 SYSCTL_ADD_QUAD(ctx, node_children,
773 CTLFLAG_RD, &ha->tx_ring[i].count,
776 #ifdef QL_ENABLE_ISCSI_TLV
777 SYSCTL_ADD_QUAD(ctx, node_children,
778 OID_AUTO, "iscsi_pkt_count",
779 CTLFLAG_RD, &ha->tx_ring[i].iscsi_pkt_count,
781 #endif /* #ifdef QL_ENABLE_ISCSI_TLV */
788 qlnx_add_drvr_stats_sysctls(qla_host_t *ha)
790 qlnx_add_drvr_sds_stats(ha);
791 qlnx_add_drvr_rds_stats(ha);
792 qlnx_add_drvr_tx_stats(ha);
797 * Name: ql_hw_add_sysctls
798 * Function: Add P3Plus specific sysctls
801 ql_hw_add_sysctls(qla_host_t *ha)
807 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
808 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
809 OID_AUTO, "num_rds_rings", CTLFLAG_RD, &ha->hw.num_rds_rings,
810 ha->hw.num_rds_rings, "Number of Rcv Descriptor Rings");
812 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
813 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
814 OID_AUTO, "num_sds_rings", CTLFLAG_RD, &ha->hw.num_sds_rings,
815 ha->hw.num_sds_rings, "Number of Status Descriptor Rings");
817 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
818 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
819 OID_AUTO, "num_tx_rings", CTLFLAG_RD, &ha->hw.num_tx_rings,
820 ha->hw.num_tx_rings, "Number of Transmit Rings");
822 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
823 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
824 OID_AUTO, "tx_ring_index", CTLFLAG_RW, &ha->txr_idx,
825 ha->txr_idx, "Tx Ring Used");
827 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
828 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
829 OID_AUTO, "max_tx_segs", CTLFLAG_RD, &ha->hw.max_tx_segs,
830 ha->hw.max_tx_segs, "Max # of Segments in a non-TSO pkt");
832 ha->hw.sds_cidx_thres = 32;
833 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
834 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
835 OID_AUTO, "sds_cidx_thres", CTLFLAG_RW, &ha->hw.sds_cidx_thres,
836 ha->hw.sds_cidx_thres,
837 "Number of SDS entries to process before updating"
838 " SDS Ring Consumer Index");
840 ha->hw.rds_pidx_thres = 32;
841 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
842 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
843 OID_AUTO, "rds_pidx_thres", CTLFLAG_RW, &ha->hw.rds_pidx_thres,
844 ha->hw.rds_pidx_thres,
845 "Number of Rcv Rings Entries to post before updating"
846 " RDS Ring Producer Index");
848 ha->hw.rcv_intr_coalesce = (3 << 16) | 256;
849 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
850 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
851 OID_AUTO, "rcv_intr_coalesce", CTLFLAG_RW,
852 &ha->hw.rcv_intr_coalesce,
853 ha->hw.rcv_intr_coalesce,
854 "Rcv Intr Coalescing Parameters\n"
855 "\tbits 15:0 max packets\n"
856 "\tbits 31:16 max micro-seconds to wait\n"
858 "\tifconfig <if> down && ifconfig <if> up\n"
859 "\tto take effect \n");
861 ha->hw.xmt_intr_coalesce = (64 << 16) | 64;
862 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
863 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
864 OID_AUTO, "xmt_intr_coalesce", CTLFLAG_RW,
865 &ha->hw.xmt_intr_coalesce,
866 ha->hw.xmt_intr_coalesce,
867 "Xmt Intr Coalescing Parameters\n"
868 "\tbits 15:0 max packets\n"
869 "\tbits 31:16 max micro-seconds to wait\n"
871 "\tifconfig <if> down && ifconfig <if> up\n"
872 "\tto take effect \n");
874 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
875 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
876 OID_AUTO, "port_cfg", CTLTYPE_INT | CTLFLAG_RW,
878 qla_sysctl_port_cfg, "I",
879 "Set Port Configuration if values below "
880 "otherwise Get Port Configuration\n"
881 "\tBits 0-3 ; 1 = DCBX Enable; 0 = DCBX Disable\n"
882 "\tBits 4-7 : 0 = no pause; 1 = std ; 2 = ppm \n"
883 "\tBits 8-11: std pause cfg; 0 = xmt and rcv;"
884 " 1 = xmt only; 2 = rcv only;\n"
887 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
888 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
889 OID_AUTO, "set_cam_search_mode", CTLTYPE_INT | CTLFLAG_RW,
891 qla_sysctl_set_cam_search_mode, "I",
892 "Set CAM Search Mode"
893 "\t 1 = search mode internal\n"
894 "\t 2 = search mode auto\n");
896 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
897 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
898 OID_AUTO, "get_cam_search_mode", CTLTYPE_INT | CTLFLAG_RW,
900 qla_sysctl_get_cam_search_mode, "I",
901 "Get CAM Search Mode"
902 "\t 1 = search mode internal\n"
903 "\t 2 = search mode auto\n");
905 ha->hw.enable_9kb = 1;
907 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
908 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
909 OID_AUTO, "enable_9kb", CTLFLAG_RW, &ha->hw.enable_9kb,
910 ha->hw.enable_9kb, "Enable 9Kbyte Buffers when MTU = 9000");
912 ha->hw.enable_hw_lro = 1;
914 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
915 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
916 OID_AUTO, "enable_hw_lro", CTLFLAG_RW, &ha->hw.enable_hw_lro,
917 ha->hw.enable_hw_lro, "Enable Hardware LRO; Default is true \n"
918 "\t 1 : Hardware LRO if LRO is enabled\n"
919 "\t 0 : Software LRO if LRO is enabled\n"
920 "\t Any change requires ifconfig down/up to take effect\n"
921 "\t Note that LRO may be turned off/on via ifconfig\n");
923 ha->hw.mdump_active = 0;
924 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
925 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
926 OID_AUTO, "minidump_active", CTLFLAG_RW, &ha->hw.mdump_active,
928 "Minidump retrieval is Active");
930 ha->hw.mdump_done = 0;
931 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
932 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
933 OID_AUTO, "mdump_done", CTLFLAG_RW,
934 &ha->hw.mdump_done, ha->hw.mdump_done,
935 "Minidump has been done and available for retrieval");
937 ha->hw.mdump_capture_mask = 0xF;
938 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
939 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
940 OID_AUTO, "minidump_capture_mask", CTLFLAG_RW,
941 &ha->hw.mdump_capture_mask, ha->hw.mdump_capture_mask,
942 "Minidump capture mask");
946 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
947 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
948 OID_AUTO, "err_inject",
949 CTLFLAG_RW, &ha->err_inject, ha->err_inject,
950 "Error to be injected\n"
951 "\t\t\t 0: No Errors\n"
952 "\t\t\t 1: rcv: rxb struct invalid\n"
953 "\t\t\t 2: rcv: mp == NULL\n"
954 "\t\t\t 3: lro: rxb struct invalid\n"
955 "\t\t\t 4: lro: mp == NULL\n"
956 "\t\t\t 5: rcv: num handles invalid\n"
957 "\t\t\t 6: reg: indirect reg rd_wr failure\n"
958 "\t\t\t 7: ocm: offchip memory rd_wr failure\n"
959 "\t\t\t 8: mbx: mailbox command failure\n"
960 "\t\t\t 9: heartbeat failure\n"
961 "\t\t\t A: temperature failure\n"
962 "\t\t\t 11: m_getcl or m_getjcl failure\n" );
964 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
965 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
966 OID_AUTO, "peg_stop", CTLTYPE_INT | CTLFLAG_RW,
968 qla_sysctl_stop_pegs, "I", "Peg Stop");
970 #endif /* #ifdef QL_DBG */
972 ha->hw.user_pri_nic = 0;
973 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
974 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
975 OID_AUTO, "user_pri_nic", CTLFLAG_RW, &ha->hw.user_pri_nic,
977 "VLAN Tag User Priority for Normal Ethernet Packets");
979 ha->hw.user_pri_iscsi = 4;
980 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
981 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
982 OID_AUTO, "user_pri_iscsi", CTLFLAG_RW, &ha->hw.user_pri_iscsi,
983 ha->hw.user_pri_iscsi,
984 "VLAN Tag User Priority for iSCSI Packets");
986 qlnx_add_hw_stats_sysctls(ha);
987 qlnx_add_drvr_stats_sysctls(ha);
993 ql_hw_link_status(qla_host_t *ha)
995 device_printf(ha->pci_dev, "cable_oui\t\t 0x%08x\n", ha->hw.cable_oui);
997 if (ha->hw.link_up) {
998 device_printf(ha->pci_dev, "link Up\n");
1000 device_printf(ha->pci_dev, "link Down\n");
1003 if (ha->hw.flags.fduplex) {
1004 device_printf(ha->pci_dev, "Full Duplex\n");
1006 device_printf(ha->pci_dev, "Half Duplex\n");
1009 if (ha->hw.flags.autoneg) {
1010 device_printf(ha->pci_dev, "Auto Negotiation Enabled\n");
1012 device_printf(ha->pci_dev, "Auto Negotiation Disabled\n");
1015 switch (ha->hw.link_speed) {
1017 device_printf(ha->pci_dev, "link speed\t\t 10Gps\n");
1021 device_printf(ha->pci_dev, "link speed\t\t 1Gps\n");
1025 device_printf(ha->pci_dev, "link speed\t\t 100Mbps\n");
1029 device_printf(ha->pci_dev, "link speed\t\t Unknown\n");
1033 switch (ha->hw.module_type) {
1036 device_printf(ha->pci_dev, "Module Type 10GBase-LRM\n");
1040 device_printf(ha->pci_dev, "Module Type 10GBase-LR\n");
1044 device_printf(ha->pci_dev, "Module Type 10GBase-SR\n");
1048 device_printf(ha->pci_dev,
1049 "Module Type 10GE Passive Copper(Compliant)[%d m]\n",
1050 ha->hw.cable_length);
1054 device_printf(ha->pci_dev, "Module Type 10GE Active"
1055 " Limiting Copper(Compliant)[%d m]\n",
1056 ha->hw.cable_length);
1060 device_printf(ha->pci_dev,
1061 "Module Type 10GE Passive Copper"
1062 " (Legacy, Best Effort)[%d m]\n",
1063 ha->hw.cable_length);
1067 device_printf(ha->pci_dev, "Module Type 1000Base-SX\n");
1071 device_printf(ha->pci_dev, "Module Type 1000Base-LX\n");
1075 device_printf(ha->pci_dev, "Module Type 1000Base-CX\n");
1079 device_printf(ha->pci_dev, "Module Type 1000Base-T\n");
1083 device_printf(ha->pci_dev, "Module Type 1GE Passive Copper"
1084 "(Legacy, Best Effort)\n");
1088 device_printf(ha->pci_dev, "Unknown Module Type 0x%x\n",
1089 ha->hw.module_type);
1093 if (ha->hw.link_faults == 1)
1094 device_printf(ha->pci_dev, "SFP Power Fault\n");
1099 * Function: Frees the DMA'able memory allocated in ql_alloc_dma()
1102 ql_free_dma(qla_host_t *ha)
1106 if (ha->hw.dma_buf.flags.sds_ring) {
1107 for (i = 0; i < ha->hw.num_sds_rings; i++) {
1108 ql_free_dmabuf(ha, &ha->hw.dma_buf.sds_ring[i]);
1110 ha->hw.dma_buf.flags.sds_ring = 0;
1113 if (ha->hw.dma_buf.flags.rds_ring) {
1114 for (i = 0; i < ha->hw.num_rds_rings; i++) {
1115 ql_free_dmabuf(ha, &ha->hw.dma_buf.rds_ring[i]);
1117 ha->hw.dma_buf.flags.rds_ring = 0;
1120 if (ha->hw.dma_buf.flags.tx_ring) {
1121 ql_free_dmabuf(ha, &ha->hw.dma_buf.tx_ring);
1122 ha->hw.dma_buf.flags.tx_ring = 0;
1124 ql_minidump_free(ha);
1128 * Name: ql_alloc_dma
1129 * Function: Allocates DMA'able memory for Tx/Rx Rings, Tx/Rx Contexts.
1132 ql_alloc_dma(qla_host_t *ha)
1135 uint32_t i, j, size, tx_ring_size;
1137 qla_hw_tx_cntxt_t *tx_cntxt;
1143 QL_DPRINT2(ha, (dev, "%s: enter\n", __func__));
1147 * Allocate Transmit Ring
1149 tx_ring_size = (sizeof(q80_tx_cmd_t) * NUM_TX_DESCRIPTORS);
1150 size = (tx_ring_size * ha->hw.num_tx_rings);
1152 hw->dma_buf.tx_ring.alignment = 8;
1153 hw->dma_buf.tx_ring.size = size + PAGE_SIZE;
1155 if (ql_alloc_dmabuf(ha, &hw->dma_buf.tx_ring)) {
1156 device_printf(dev, "%s: tx ring alloc failed\n", __func__);
1157 goto ql_alloc_dma_exit;
1160 vaddr = (uint8_t *)hw->dma_buf.tx_ring.dma_b;
1161 paddr = hw->dma_buf.tx_ring.dma_addr;
1163 for (i = 0; i < ha->hw.num_tx_rings; i++) {
1164 tx_cntxt = (qla_hw_tx_cntxt_t *)&hw->tx_cntxt[i];
1166 tx_cntxt->tx_ring_base = (q80_tx_cmd_t *)vaddr;
1167 tx_cntxt->tx_ring_paddr = paddr;
1169 vaddr += tx_ring_size;
1170 paddr += tx_ring_size;
1173 for (i = 0; i < ha->hw.num_tx_rings; i++) {
1174 tx_cntxt = (qla_hw_tx_cntxt_t *)&hw->tx_cntxt[i];
1176 tx_cntxt->tx_cons = (uint32_t *)vaddr;
1177 tx_cntxt->tx_cons_paddr = paddr;
1179 vaddr += sizeof (uint32_t);
1180 paddr += sizeof (uint32_t);
1183 ha->hw.dma_buf.flags.tx_ring = 1;
1185 QL_DPRINT2(ha, (dev, "%s: tx_ring phys %p virt %p\n",
1186 __func__, (void *)(hw->dma_buf.tx_ring.dma_addr),
1187 hw->dma_buf.tx_ring.dma_b));
1189 * Allocate Receive Descriptor Rings
1192 for (i = 0; i < hw->num_rds_rings; i++) {
1194 hw->dma_buf.rds_ring[i].alignment = 8;
1195 hw->dma_buf.rds_ring[i].size =
1196 (sizeof(q80_recv_desc_t)) * NUM_RX_DESCRIPTORS;
1198 if (ql_alloc_dmabuf(ha, &hw->dma_buf.rds_ring[i])) {
1199 device_printf(dev, "%s: rds ring[%d] alloc failed\n",
1202 for (j = 0; j < i; j++)
1203 ql_free_dmabuf(ha, &hw->dma_buf.rds_ring[j]);
1205 goto ql_alloc_dma_exit;
1207 QL_DPRINT4(ha, (dev, "%s: rx_ring[%d] phys %p virt %p\n",
1208 __func__, i, (void *)(hw->dma_buf.rds_ring[i].dma_addr),
1209 hw->dma_buf.rds_ring[i].dma_b));
1212 hw->dma_buf.flags.rds_ring = 1;
1215 * Allocate Status Descriptor Rings
1218 for (i = 0; i < hw->num_sds_rings; i++) {
1219 hw->dma_buf.sds_ring[i].alignment = 8;
1220 hw->dma_buf.sds_ring[i].size =
1221 (sizeof(q80_stat_desc_t)) * NUM_STATUS_DESCRIPTORS;
1223 if (ql_alloc_dmabuf(ha, &hw->dma_buf.sds_ring[i])) {
1224 device_printf(dev, "%s: sds ring alloc failed\n",
1227 for (j = 0; j < i; j++)
1228 ql_free_dmabuf(ha, &hw->dma_buf.sds_ring[j]);
1230 goto ql_alloc_dma_exit;
1232 QL_DPRINT4(ha, (dev, "%s: sds_ring[%d] phys %p virt %p\n",
1234 (void *)(hw->dma_buf.sds_ring[i].dma_addr),
1235 hw->dma_buf.sds_ring[i].dma_b));
1237 for (i = 0; i < hw->num_sds_rings; i++) {
1238 hw->sds[i].sds_ring_base =
1239 (q80_stat_desc_t *)hw->dma_buf.sds_ring[i].dma_b;
1242 hw->dma_buf.flags.sds_ring = 1;
1251 #define Q8_MBX_MSEC_DELAY 5000
1254 qla_mbx_cmd(qla_host_t *ha, uint32_t *h_mbox, uint32_t n_hmbox,
1255 uint32_t *fw_mbox, uint32_t n_fwmbox, uint32_t no_pause)
1261 if (QL_ERR_INJECT(ha, INJCT_MBX_CMD_FAILURE)) {
1263 ha->qla_initiate_recovery = 1;
1264 goto exit_qla_mbx_cmd;
1270 i = Q8_MBX_MSEC_DELAY;
1273 data = READ_REG32(ha, Q8_HOST_MBOX_CNTRL);
1279 qla_mdelay(__func__, 1);
1285 device_printf(ha->pci_dev, "%s: host_mbx_cntrl 0x%08x\n",
1288 ha->qla_initiate_recovery = 1;
1289 goto exit_qla_mbx_cmd;
1292 for (i = 0; i < n_hmbox; i++) {
1293 WRITE_REG32(ha, (Q8_HOST_MBOX0 + (i << 2)), *h_mbox);
1297 WRITE_REG32(ha, Q8_HOST_MBOX_CNTRL, 0x1);
1300 i = Q8_MBX_MSEC_DELAY;
1302 data = READ_REG32(ha, Q8_FW_MBOX_CNTRL);
1304 if ((data & 0x3) == 1) {
1305 data = READ_REG32(ha, Q8_FW_MBOX0);
1306 if ((data & 0xF000) != 0x8000)
1312 qla_mdelay(__func__, 1);
1317 device_printf(ha->pci_dev, "%s: fw_mbx_cntrl 0x%08x\n",
1320 ha->qla_initiate_recovery = 1;
1321 goto exit_qla_mbx_cmd;
1324 for (i = 0; i < n_fwmbox; i++) {
1325 *fw_mbox++ = READ_REG32(ha, (Q8_FW_MBOX0 + (i << 2)));
1328 WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0);
1329 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
1336 qla_get_nic_partition(qla_host_t *ha, uint32_t *supports_9kb,
1339 uint32_t *mbox, err;
1340 device_t dev = ha->pci_dev;
1342 bzero(ha->hw.mbox, (sizeof (uint32_t) * Q8_NUM_MBOX));
1346 mbox[0] = Q8_MBX_GET_NIC_PARTITION | (0x2 << 16) | (0x2 << 29);
1348 if (qla_mbx_cmd(ha, mbox, 2, mbox, 19, 0)) {
1349 device_printf(dev, "%s: failed0\n", __func__);
1352 err = mbox[0] >> 25;
1354 if (supports_9kb != NULL) {
1355 if (mbox[16] & 0x80) /* bit 7 of mbox 16 */
1361 if (num_rcvq != NULL)
1362 *num_rcvq = ((mbox[6] >> 16) & 0xFFFF);
1364 if ((err != 1) && (err != 0)) {
1365 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
1372 qla_config_intr_cntxt(qla_host_t *ha, uint32_t start_idx, uint32_t num_intrs,
1376 device_t dev = ha->pci_dev;
1377 q80_config_intr_t *c_intr;
1378 q80_config_intr_rsp_t *c_intr_rsp;
1380 c_intr = (q80_config_intr_t *)ha->hw.mbox;
1381 bzero(c_intr, (sizeof (q80_config_intr_t)));
1383 c_intr->opcode = Q8_MBX_CONFIG_INTR;
1385 c_intr->count_version = (sizeof (q80_config_intr_t) >> 2);
1386 c_intr->count_version |= Q8_MBX_CMD_VERSION;
1388 c_intr->nentries = num_intrs;
1390 for (i = 0; i < num_intrs; i++) {
1392 c_intr->intr[i].cmd_type = Q8_MBX_CONFIG_INTR_CREATE;
1393 c_intr->intr[i].msix_index = start_idx + 1 + i;
1395 c_intr->intr[i].cmd_type = Q8_MBX_CONFIG_INTR_DELETE;
1396 c_intr->intr[i].msix_index =
1397 ha->hw.intr_id[(start_idx + i)];
1400 c_intr->intr[i].cmd_type |= Q8_MBX_CONFIG_INTR_TYPE_MSI_X;
1403 if (qla_mbx_cmd(ha, (uint32_t *)c_intr,
1404 (sizeof (q80_config_intr_t) >> 2),
1405 ha->hw.mbox, (sizeof (q80_config_intr_rsp_t) >> 2), 0)) {
1406 device_printf(dev, "%s: failed0\n", __func__);
1410 c_intr_rsp = (q80_config_intr_rsp_t *)ha->hw.mbox;
1412 err = Q8_MBX_RSP_STATUS(c_intr_rsp->regcnt_status);
1415 device_printf(dev, "%s: failed1 [0x%08x, %d]\n", __func__, err,
1416 c_intr_rsp->nentries);
1418 for (i = 0; i < c_intr_rsp->nentries; i++) {
1419 device_printf(dev, "%s: [%d]:[0x%x 0x%x 0x%x]\n",
1421 c_intr_rsp->intr[i].status,
1422 c_intr_rsp->intr[i].intr_id,
1423 c_intr_rsp->intr[i].intr_src);
1429 for (i = 0; ((i < num_intrs) && create); i++) {
1430 if (!c_intr_rsp->intr[i].status) {
1431 ha->hw.intr_id[(start_idx + i)] =
1432 c_intr_rsp->intr[i].intr_id;
1433 ha->hw.intr_src[(start_idx + i)] =
1434 c_intr_rsp->intr[i].intr_src;
1442 * Name: qla_config_rss
1443 * Function: Configure RSS for the context/interface.
1445 static const uint64_t rss_key[] = { 0xbeac01fa6a42b73bULL,
1446 0x8030f20c77cb2da3ULL,
1447 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
1448 0x255b0ec26d5a56daULL };
1451 qla_config_rss(qla_host_t *ha, uint16_t cntxt_id)
1453 q80_config_rss_t *c_rss;
1454 q80_config_rss_rsp_t *c_rss_rsp;
1456 device_t dev = ha->pci_dev;
1458 c_rss = (q80_config_rss_t *)ha->hw.mbox;
1459 bzero(c_rss, (sizeof (q80_config_rss_t)));
1461 c_rss->opcode = Q8_MBX_CONFIG_RSS;
1463 c_rss->count_version = (sizeof (q80_config_rss_t) >> 2);
1464 c_rss->count_version |= Q8_MBX_CMD_VERSION;
1466 c_rss->hash_type = (Q8_MBX_RSS_HASH_TYPE_IPV4_TCP_IP |
1467 Q8_MBX_RSS_HASH_TYPE_IPV6_TCP_IP);
1468 //c_rss->hash_type = (Q8_MBX_RSS_HASH_TYPE_IPV4_TCP |
1469 // Q8_MBX_RSS_HASH_TYPE_IPV6_TCP);
1471 c_rss->flags = Q8_MBX_RSS_FLAGS_ENABLE_RSS;
1472 c_rss->flags |= Q8_MBX_RSS_FLAGS_USE_IND_TABLE;
1474 c_rss->indtbl_mask = Q8_MBX_RSS_INDTBL_MASK;
1476 c_rss->indtbl_mask |= Q8_MBX_RSS_FLAGS_MULTI_RSS_VALID;
1477 c_rss->flags |= Q8_MBX_RSS_FLAGS_TYPE_CRSS;
1479 c_rss->cntxt_id = cntxt_id;
1481 for (i = 0; i < 5; i++) {
1482 c_rss->rss_key[i] = rss_key[i];
1485 if (qla_mbx_cmd(ha, (uint32_t *)c_rss,
1486 (sizeof (q80_config_rss_t) >> 2),
1487 ha->hw.mbox, (sizeof(q80_config_rss_rsp_t) >> 2), 0)) {
1488 device_printf(dev, "%s: failed0\n", __func__);
1491 c_rss_rsp = (q80_config_rss_rsp_t *)ha->hw.mbox;
1493 err = Q8_MBX_RSP_STATUS(c_rss_rsp->regcnt_status);
1496 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
1503 qla_set_rss_ind_table(qla_host_t *ha, uint32_t start_idx, uint32_t count,
1504 uint16_t cntxt_id, uint8_t *ind_table)
1506 q80_config_rss_ind_table_t *c_rss_ind;
1507 q80_config_rss_ind_table_rsp_t *c_rss_ind_rsp;
1509 device_t dev = ha->pci_dev;
1511 if ((count > Q8_RSS_IND_TBL_SIZE) ||
1512 ((start_idx + count - 1) > Q8_RSS_IND_TBL_MAX_IDX)) {
1513 device_printf(dev, "%s: illegal count [%d, %d]\n", __func__,
1518 c_rss_ind = (q80_config_rss_ind_table_t *)ha->hw.mbox;
1519 bzero(c_rss_ind, sizeof (q80_config_rss_ind_table_t));
1521 c_rss_ind->opcode = Q8_MBX_CONFIG_RSS_TABLE;
1522 c_rss_ind->count_version = (sizeof (q80_config_rss_ind_table_t) >> 2);
1523 c_rss_ind->count_version |= Q8_MBX_CMD_VERSION;
1525 c_rss_ind->start_idx = start_idx;
1526 c_rss_ind->end_idx = start_idx + count - 1;
1527 c_rss_ind->cntxt_id = cntxt_id;
1528 bcopy(ind_table, c_rss_ind->ind_table, count);
1530 if (qla_mbx_cmd(ha, (uint32_t *)c_rss_ind,
1531 (sizeof (q80_config_rss_ind_table_t) >> 2), ha->hw.mbox,
1532 (sizeof(q80_config_rss_ind_table_rsp_t) >> 2), 0)) {
1533 device_printf(dev, "%s: failed0\n", __func__);
1537 c_rss_ind_rsp = (q80_config_rss_ind_table_rsp_t *)ha->hw.mbox;
1538 err = Q8_MBX_RSP_STATUS(c_rss_ind_rsp->regcnt_status);
1541 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
1548 * Name: qla_config_intr_coalesce
1549 * Function: Configure Interrupt Coalescing.
1552 qla_config_intr_coalesce(qla_host_t *ha, uint16_t cntxt_id, int tenable,
1555 q80_config_intr_coalesc_t *intrc;
1556 q80_config_intr_coalesc_rsp_t *intrc_rsp;
1558 device_t dev = ha->pci_dev;
1560 intrc = (q80_config_intr_coalesc_t *)ha->hw.mbox;
1561 bzero(intrc, (sizeof (q80_config_intr_coalesc_t)));
1563 intrc->opcode = Q8_MBX_CONFIG_INTR_COALESCE;
1564 intrc->count_version = (sizeof (q80_config_intr_coalesc_t) >> 2);
1565 intrc->count_version |= Q8_MBX_CMD_VERSION;
1568 intrc->flags = Q8_MBX_INTRC_FLAGS_RCV;
1569 intrc->max_pkts = ha->hw.rcv_intr_coalesce & 0xFFFF;
1570 intrc->max_mswait = (ha->hw.rcv_intr_coalesce >> 16) & 0xFFFF;
1572 intrc->flags = Q8_MBX_INTRC_FLAGS_XMT;
1573 intrc->max_pkts = ha->hw.xmt_intr_coalesce & 0xFFFF;
1574 intrc->max_mswait = (ha->hw.xmt_intr_coalesce >> 16) & 0xFFFF;
1577 intrc->cntxt_id = cntxt_id;
1580 intrc->flags |= Q8_MBX_INTRC_FLAGS_PERIODIC;
1581 intrc->timer_type = Q8_MBX_INTRC_TIMER_PERIODIC;
1583 for (i = 0; i < ha->hw.num_sds_rings; i++) {
1584 intrc->sds_ring_mask |= (1 << i);
1586 intrc->ms_timeout = 1000;
1589 if (qla_mbx_cmd(ha, (uint32_t *)intrc,
1590 (sizeof (q80_config_intr_coalesc_t) >> 2),
1591 ha->hw.mbox, (sizeof(q80_config_intr_coalesc_rsp_t) >> 2), 0)) {
1592 device_printf(dev, "%s: failed0\n", __func__);
1595 intrc_rsp = (q80_config_intr_coalesc_rsp_t *)ha->hw.mbox;
1597 err = Q8_MBX_RSP_STATUS(intrc_rsp->regcnt_status);
1600 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
1609 * Name: qla_config_mac_addr
1610 * Function: binds a MAC address to the context/interface.
1611 * Can be unicast, multicast or broadcast.
1614 qla_config_mac_addr(qla_host_t *ha, uint8_t *mac_addr, uint32_t add_mac,
1617 q80_config_mac_addr_t *cmac;
1618 q80_config_mac_addr_rsp_t *cmac_rsp;
1620 device_t dev = ha->pci_dev;
1622 uint8_t *mac_cpy = mac_addr;
1624 if (num_mac > Q8_MAX_MAC_ADDRS) {
1625 device_printf(dev, "%s: %s num_mac [0x%x] > Q8_MAX_MAC_ADDRS\n",
1626 __func__, (add_mac ? "Add" : "Del"), num_mac);
1630 cmac = (q80_config_mac_addr_t *)ha->hw.mbox;
1631 bzero(cmac, (sizeof (q80_config_mac_addr_t)));
1633 cmac->opcode = Q8_MBX_CONFIG_MAC_ADDR;
1634 cmac->count_version = sizeof (q80_config_mac_addr_t) >> 2;
1635 cmac->count_version |= Q8_MBX_CMD_VERSION;
1638 cmac->cmd = Q8_MBX_CMAC_CMD_ADD_MAC_ADDR;
1640 cmac->cmd = Q8_MBX_CMAC_CMD_DEL_MAC_ADDR;
1642 cmac->cmd |= Q8_MBX_CMAC_CMD_CAM_INGRESS;
1644 cmac->nmac_entries = num_mac;
1645 cmac->cntxt_id = ha->hw.rcv_cntxt_id;
1647 for (i = 0; i < num_mac; i++) {
1648 bcopy(mac_addr, cmac->mac_addr[i].addr, Q8_ETHER_ADDR_LEN);
1649 mac_addr = mac_addr + ETHER_ADDR_LEN;
1652 if (qla_mbx_cmd(ha, (uint32_t *)cmac,
1653 (sizeof (q80_config_mac_addr_t) >> 2),
1654 ha->hw.mbox, (sizeof(q80_config_mac_addr_rsp_t) >> 2), 1)) {
1655 device_printf(dev, "%s: %s failed0\n", __func__,
1656 (add_mac ? "Add" : "Del"));
1659 cmac_rsp = (q80_config_mac_addr_rsp_t *)ha->hw.mbox;
1661 err = Q8_MBX_RSP_STATUS(cmac_rsp->regcnt_status);
1664 device_printf(dev, "%s: %s failed1 [0x%08x]\n", __func__,
1665 (add_mac ? "Add" : "Del"), err);
1666 for (i = 0; i < num_mac; i++) {
1667 device_printf(dev, "%s: %02x:%02x:%02x:%02x:%02x:%02x\n",
1668 __func__, mac_cpy[0], mac_cpy[1], mac_cpy[2],
1669 mac_cpy[3], mac_cpy[4], mac_cpy[5]);
1670 mac_cpy += ETHER_ADDR_LEN;
1680 * Name: qla_set_mac_rcv_mode
1681 * Function: Enable/Disable AllMulticast and Promiscous Modes.
1684 qla_set_mac_rcv_mode(qla_host_t *ha, uint32_t mode)
1686 q80_config_mac_rcv_mode_t *rcv_mode;
1688 q80_config_mac_rcv_mode_rsp_t *rcv_mode_rsp;
1689 device_t dev = ha->pci_dev;
1691 rcv_mode = (q80_config_mac_rcv_mode_t *)ha->hw.mbox;
1692 bzero(rcv_mode, (sizeof (q80_config_mac_rcv_mode_t)));
1694 rcv_mode->opcode = Q8_MBX_CONFIG_MAC_RX_MODE;
1695 rcv_mode->count_version = sizeof (q80_config_mac_rcv_mode_t) >> 2;
1696 rcv_mode->count_version |= Q8_MBX_CMD_VERSION;
1698 rcv_mode->mode = mode;
1700 rcv_mode->cntxt_id = ha->hw.rcv_cntxt_id;
1702 if (qla_mbx_cmd(ha, (uint32_t *)rcv_mode,
1703 (sizeof (q80_config_mac_rcv_mode_t) >> 2),
1704 ha->hw.mbox, (sizeof(q80_config_mac_rcv_mode_rsp_t) >> 2), 1)) {
1705 device_printf(dev, "%s: failed0\n", __func__);
1708 rcv_mode_rsp = (q80_config_mac_rcv_mode_rsp_t *)ha->hw.mbox;
1710 err = Q8_MBX_RSP_STATUS(rcv_mode_rsp->regcnt_status);
1713 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
1721 ql_set_promisc(qla_host_t *ha)
1725 ha->hw.mac_rcv_mode |= Q8_MBX_MAC_RCV_PROMISC_ENABLE;
1726 ret = qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode);
1731 qla_reset_promisc(qla_host_t *ha)
1733 ha->hw.mac_rcv_mode &= ~Q8_MBX_MAC_RCV_PROMISC_ENABLE;
1734 (void)qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode);
1738 ql_set_allmulti(qla_host_t *ha)
1742 ha->hw.mac_rcv_mode |= Q8_MBX_MAC_ALL_MULTI_ENABLE;
1743 ret = qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode);
1748 qla_reset_allmulti(qla_host_t *ha)
1750 ha->hw.mac_rcv_mode &= ~Q8_MBX_MAC_ALL_MULTI_ENABLE;
1751 (void)qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode);
1755 * Name: ql_set_max_mtu
1757 * Sets the maximum transfer unit size for the specified rcv context.
1760 ql_set_max_mtu(qla_host_t *ha, uint32_t mtu, uint16_t cntxt_id)
1763 q80_set_max_mtu_t *max_mtu;
1764 q80_set_max_mtu_rsp_t *max_mtu_rsp;
1769 max_mtu = (q80_set_max_mtu_t *)ha->hw.mbox;
1770 bzero(max_mtu, (sizeof (q80_set_max_mtu_t)));
1772 max_mtu->opcode = Q8_MBX_SET_MAX_MTU;
1773 max_mtu->count_version = (sizeof (q80_set_max_mtu_t) >> 2);
1774 max_mtu->count_version |= Q8_MBX_CMD_VERSION;
1776 max_mtu->cntxt_id = cntxt_id;
1779 if (qla_mbx_cmd(ha, (uint32_t *)max_mtu,
1780 (sizeof (q80_set_max_mtu_t) >> 2),
1781 ha->hw.mbox, (sizeof (q80_set_max_mtu_rsp_t) >> 2), 1)) {
1782 device_printf(dev, "%s: failed\n", __func__);
1786 max_mtu_rsp = (q80_set_max_mtu_rsp_t *)ha->hw.mbox;
1788 err = Q8_MBX_RSP_STATUS(max_mtu_rsp->regcnt_status);
1791 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
1798 qla_link_event_req(qla_host_t *ha, uint16_t cntxt_id)
1801 q80_link_event_t *lnk;
1802 q80_link_event_rsp_t *lnk_rsp;
1807 lnk = (q80_link_event_t *)ha->hw.mbox;
1808 bzero(lnk, (sizeof (q80_link_event_t)));
1810 lnk->opcode = Q8_MBX_LINK_EVENT_REQ;
1811 lnk->count_version = (sizeof (q80_link_event_t) >> 2);
1812 lnk->count_version |= Q8_MBX_CMD_VERSION;
1814 lnk->cntxt_id = cntxt_id;
1815 lnk->cmd = Q8_LINK_EVENT_CMD_ENABLE_ASYNC;
1817 if (qla_mbx_cmd(ha, (uint32_t *)lnk, (sizeof (q80_link_event_t) >> 2),
1818 ha->hw.mbox, (sizeof (q80_link_event_rsp_t) >> 2), 0)) {
1819 device_printf(dev, "%s: failed\n", __func__);
1823 lnk_rsp = (q80_link_event_rsp_t *)ha->hw.mbox;
1825 err = Q8_MBX_RSP_STATUS(lnk_rsp->regcnt_status);
1828 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
1835 qla_config_fw_lro(qla_host_t *ha, uint16_t cntxt_id)
1838 q80_config_fw_lro_t *fw_lro;
1839 q80_config_fw_lro_rsp_t *fw_lro_rsp;
1844 fw_lro = (q80_config_fw_lro_t *)ha->hw.mbox;
1845 bzero(fw_lro, sizeof(q80_config_fw_lro_t));
1847 fw_lro->opcode = Q8_MBX_CONFIG_FW_LRO;
1848 fw_lro->count_version = (sizeof (q80_config_fw_lro_t) >> 2);
1849 fw_lro->count_version |= Q8_MBX_CMD_VERSION;
1851 fw_lro->flags |= Q8_MBX_FW_LRO_IPV4 | Q8_MBX_FW_LRO_IPV4_WO_DST_IP_CHK;
1852 fw_lro->flags |= Q8_MBX_FW_LRO_IPV6 | Q8_MBX_FW_LRO_IPV6_WO_DST_IP_CHK;
1854 fw_lro->cntxt_id = cntxt_id;
1856 if (qla_mbx_cmd(ha, (uint32_t *)fw_lro,
1857 (sizeof (q80_config_fw_lro_t) >> 2),
1858 ha->hw.mbox, (sizeof (q80_config_fw_lro_rsp_t) >> 2), 0)) {
1859 device_printf(dev, "%s: failed\n", __func__);
1863 fw_lro_rsp = (q80_config_fw_lro_rsp_t *)ha->hw.mbox;
1865 err = Q8_MBX_RSP_STATUS(fw_lro_rsp->regcnt_status);
1868 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
1875 qla_set_cam_search_mode(qla_host_t *ha, uint32_t search_mode)
1878 q80_hw_config_t *hw_config;
1879 q80_hw_config_rsp_t *hw_config_rsp;
1884 hw_config = (q80_hw_config_t *)ha->hw.mbox;
1885 bzero(hw_config, sizeof (q80_hw_config_t));
1887 hw_config->opcode = Q8_MBX_HW_CONFIG;
1888 hw_config->count_version = Q8_HW_CONFIG_SET_CAM_SEARCH_MODE_COUNT;
1889 hw_config->count_version |= Q8_MBX_CMD_VERSION;
1891 hw_config->cmd = Q8_HW_CONFIG_SET_CAM_SEARCH_MODE;
1893 hw_config->u.set_cam_search_mode.mode = search_mode;
1895 if (qla_mbx_cmd(ha, (uint32_t *)hw_config,
1896 (sizeof (q80_hw_config_t) >> 2),
1897 ha->hw.mbox, (sizeof (q80_hw_config_rsp_t) >> 2), 0)) {
1898 device_printf(dev, "%s: failed\n", __func__);
1901 hw_config_rsp = (q80_hw_config_rsp_t *)ha->hw.mbox;
1903 err = Q8_MBX_RSP_STATUS(hw_config_rsp->regcnt_status);
1906 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
1913 qla_get_cam_search_mode(qla_host_t *ha)
1916 q80_hw_config_t *hw_config;
1917 q80_hw_config_rsp_t *hw_config_rsp;
1922 hw_config = (q80_hw_config_t *)ha->hw.mbox;
1923 bzero(hw_config, sizeof (q80_hw_config_t));
1925 hw_config->opcode = Q8_MBX_HW_CONFIG;
1926 hw_config->count_version = Q8_HW_CONFIG_GET_CAM_SEARCH_MODE_COUNT;
1927 hw_config->count_version |= Q8_MBX_CMD_VERSION;
1929 hw_config->cmd = Q8_HW_CONFIG_GET_CAM_SEARCH_MODE;
1931 if (qla_mbx_cmd(ha, (uint32_t *)hw_config,
1932 (sizeof (q80_hw_config_t) >> 2),
1933 ha->hw.mbox, (sizeof (q80_hw_config_rsp_t) >> 2), 0)) {
1934 device_printf(dev, "%s: failed\n", __func__);
1937 hw_config_rsp = (q80_hw_config_rsp_t *)ha->hw.mbox;
1939 err = Q8_MBX_RSP_STATUS(hw_config_rsp->regcnt_status);
1942 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
1944 device_printf(dev, "%s: cam search mode [0x%08x]\n", __func__,
1945 hw_config_rsp->u.get_cam_search_mode.mode);
1952 qla_get_hw_stats(qla_host_t *ha, uint32_t cmd, uint32_t rsp_size)
1955 q80_get_stats_t *stat;
1956 q80_get_stats_rsp_t *stat_rsp;
1961 stat = (q80_get_stats_t *)ha->hw.mbox;
1962 bzero(stat, (sizeof (q80_get_stats_t)));
1964 stat->opcode = Q8_MBX_GET_STATS;
1965 stat->count_version = 2;
1966 stat->count_version |= Q8_MBX_CMD_VERSION;
1970 if (qla_mbx_cmd(ha, (uint32_t *)stat, 2,
1971 ha->hw.mbox, (rsp_size >> 2), 0)) {
1972 device_printf(dev, "%s: failed\n", __func__);
1976 stat_rsp = (q80_get_stats_rsp_t *)ha->hw.mbox;
1978 err = Q8_MBX_RSP_STATUS(stat_rsp->regcnt_status);
1988 ql_get_stats(qla_host_t *ha)
1990 q80_get_stats_rsp_t *stat_rsp;
1991 q80_mac_stats_t *mstat;
1992 q80_xmt_stats_t *xstat;
1993 q80_rcv_stats_t *rstat;
1996 struct ifnet *ifp = ha->ifp;
2001 if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) != 0) {
2002 device_printf(ha->pci_dev, "%s: failed\n", __func__);
2006 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2007 QLA_UNLOCK(ha, __func__);
2011 stat_rsp = (q80_get_stats_rsp_t *)ha->hw.mbox;
2013 * Get MAC Statistics
2015 cmd = Q8_GET_STATS_CMD_TYPE_MAC;
2016 // cmd |= Q8_GET_STATS_CMD_CLEAR;
2018 cmd |= ((ha->pci_func & 0x1) << 16);
2020 if (ha->qla_watchdog_pause)
2021 goto ql_get_stats_exit;
2023 if (qla_get_hw_stats(ha, cmd, sizeof (q80_get_stats_rsp_t)) == 0) {
2024 mstat = (q80_mac_stats_t *)&stat_rsp->u.mac;
2025 bcopy(mstat, &ha->hw.mac, sizeof(q80_mac_stats_t));
2027 device_printf(ha->pci_dev, "%s: mac failed [0x%08x]\n",
2028 __func__, ha->hw.mbox[0]);
2031 * Get RCV Statistics
2033 cmd = Q8_GET_STATS_CMD_RCV | Q8_GET_STATS_CMD_TYPE_CNTXT;
2034 // cmd |= Q8_GET_STATS_CMD_CLEAR;
2035 cmd |= (ha->hw.rcv_cntxt_id << 16);
2037 if (ha->qla_watchdog_pause)
2038 goto ql_get_stats_exit;
2040 if (qla_get_hw_stats(ha, cmd, sizeof (q80_get_stats_rsp_t)) == 0) {
2041 rstat = (q80_rcv_stats_t *)&stat_rsp->u.rcv;
2042 bcopy(rstat, &ha->hw.rcv, sizeof(q80_rcv_stats_t));
2044 device_printf(ha->pci_dev, "%s: rcv failed [0x%08x]\n",
2045 __func__, ha->hw.mbox[0]);
2048 if (ha->qla_watchdog_pause)
2049 goto ql_get_stats_exit;
2051 * Get XMT Statistics
2053 for (i = 0 ; ((i < ha->hw.num_tx_rings) && (!ha->qla_watchdog_pause));
2055 cmd = Q8_GET_STATS_CMD_XMT | Q8_GET_STATS_CMD_TYPE_CNTXT;
2056 // cmd |= Q8_GET_STATS_CMD_CLEAR;
2057 cmd |= (ha->hw.tx_cntxt[i].tx_cntxt_id << 16);
2059 if (qla_get_hw_stats(ha, cmd, sizeof(q80_get_stats_rsp_t))
2061 xstat = (q80_xmt_stats_t *)&stat_rsp->u.xmt;
2062 bcopy(xstat, &ha->hw.xmt[i], sizeof(q80_xmt_stats_t));
2064 device_printf(ha->pci_dev, "%s: xmt failed [0x%08x]\n",
2065 __func__, ha->hw.mbox[0]);
2070 QLA_UNLOCK(ha, __func__);
2077 * Function: Checks if the packet to be transmitted is a candidate for
2078 * Large TCP Segment Offload. If yes, the appropriate fields in the Tx
2079 * Ring Structure are plugged in.
2082 qla_tx_tso(qla_host_t *ha, struct mbuf *mp, q80_tx_cmd_t *tx_cmd, uint8_t *hdr)
2084 struct ether_vlan_header *eh;
2085 struct ip *ip = NULL;
2086 struct ip6_hdr *ip6 = NULL;
2087 struct tcphdr *th = NULL;
2088 uint32_t ehdrlen, hdrlen, ip_hlen, tcp_hlen, tcp_opt_off;
2089 uint16_t etype, opcode, offload = 1;
2095 eh = mtod(mp, struct ether_vlan_header *);
2097 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2098 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2099 etype = ntohs(eh->evl_proto);
2101 ehdrlen = ETHER_HDR_LEN;
2102 etype = ntohs(eh->evl_encap_proto);
2110 tcp_opt_off = ehdrlen + sizeof(struct ip) +
2111 sizeof(struct tcphdr);
2113 if (mp->m_len < tcp_opt_off) {
2114 m_copydata(mp, 0, tcp_opt_off, hdr);
2115 ip = (struct ip *)(hdr + ehdrlen);
2117 ip = (struct ip *)(mp->m_data + ehdrlen);
2120 ip_hlen = ip->ip_hl << 2;
2121 opcode = Q8_TX_CMD_OP_XMT_TCP_LSO;
2124 if ((ip->ip_p != IPPROTO_TCP) ||
2125 (ip_hlen != sizeof (struct ip))){
2126 /* IP Options are not supported */
2130 th = (struct tcphdr *)((caddr_t)ip + ip_hlen);
2134 case ETHERTYPE_IPV6:
2136 tcp_opt_off = ehdrlen + sizeof(struct ip6_hdr) +
2137 sizeof (struct tcphdr);
2139 if (mp->m_len < tcp_opt_off) {
2140 m_copydata(mp, 0, tcp_opt_off, hdr);
2141 ip6 = (struct ip6_hdr *)(hdr + ehdrlen);
2143 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
2146 ip_hlen = sizeof(struct ip6_hdr);
2147 opcode = Q8_TX_CMD_OP_XMT_TCP_LSO_IPV6;
2149 if (ip6->ip6_nxt != IPPROTO_TCP) {
2150 //device_printf(dev, "%s: ipv6\n", __func__);
2153 th = (struct tcphdr *)((caddr_t)ip6 + ip_hlen);
2157 QL_DPRINT8(ha, (dev, "%s: type!=ip\n", __func__));
2165 tcp_hlen = th->th_off << 2;
2166 hdrlen = ehdrlen + ip_hlen + tcp_hlen;
2168 if (mp->m_len < hdrlen) {
2169 if (mp->m_len < tcp_opt_off) {
2170 if (tcp_hlen > sizeof(struct tcphdr)) {
2171 m_copydata(mp, tcp_opt_off,
2172 (tcp_hlen - sizeof(struct tcphdr)),
2176 m_copydata(mp, 0, hdrlen, hdr);
2180 tx_cmd->mss = mp->m_pkthdr.tso_segsz;
2182 tx_cmd->flags_opcode = opcode ;
2183 tx_cmd->tcp_hdr_off = ip_hlen + ehdrlen;
2184 tx_cmd->total_hdr_len = hdrlen;
2186 /* Check for Multicast least significant bit of MSB == 1 */
2187 if (eh->evl_dhost[0] & 0x01) {
2188 tx_cmd->flags_opcode |= Q8_TX_CMD_FLAGS_MULTICAST;
2191 if (mp->m_len < hdrlen) {
2192 printf("%d\n", hdrlen);
2200 * Name: qla_tx_chksum
2201 * Function: Checks if the packet to be transmitted is a candidate for
2202 * TCP/UDP Checksum offload. If yes, the appropriate fields in the Tx
2203 * Ring Structure are plugged in.
2206 qla_tx_chksum(qla_host_t *ha, struct mbuf *mp, uint32_t *op_code,
2207 uint32_t *tcp_hdr_off)
2209 struct ether_vlan_header *eh;
2211 struct ip6_hdr *ip6;
2212 uint32_t ehdrlen, ip_hlen;
2213 uint16_t etype, opcode, offload = 1;
2215 uint8_t buf[sizeof(struct ip6_hdr)];
2221 if ((mp->m_pkthdr.csum_flags &
2222 (CSUM_TCP|CSUM_UDP|CSUM_TCP_IPV6 | CSUM_UDP_IPV6)) == 0)
2225 eh = mtod(mp, struct ether_vlan_header *);
2227 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2228 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
2229 etype = ntohs(eh->evl_proto);
2231 ehdrlen = ETHER_HDR_LEN;
2232 etype = ntohs(eh->evl_encap_proto);
2238 ip = (struct ip *)(mp->m_data + ehdrlen);
2240 ip_hlen = sizeof (struct ip);
2242 if (mp->m_len < (ehdrlen + ip_hlen)) {
2243 m_copydata(mp, ehdrlen, sizeof(struct ip), buf);
2244 ip = (struct ip *)buf;
2247 if (ip->ip_p == IPPROTO_TCP)
2248 opcode = Q8_TX_CMD_OP_XMT_TCP_CHKSUM;
2249 else if (ip->ip_p == IPPROTO_UDP)
2250 opcode = Q8_TX_CMD_OP_XMT_UDP_CHKSUM;
2252 //device_printf(dev, "%s: ipv4\n", __func__);
2257 case ETHERTYPE_IPV6:
2258 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
2260 ip_hlen = sizeof(struct ip6_hdr);
2262 if (mp->m_len < (ehdrlen + ip_hlen)) {
2263 m_copydata(mp, ehdrlen, sizeof (struct ip6_hdr),
2265 ip6 = (struct ip6_hdr *)buf;
2268 if (ip6->ip6_nxt == IPPROTO_TCP)
2269 opcode = Q8_TX_CMD_OP_XMT_TCP_CHKSUM_IPV6;
2270 else if (ip6->ip6_nxt == IPPROTO_UDP)
2271 opcode = Q8_TX_CMD_OP_XMT_UDP_CHKSUM_IPV6;
2273 //device_printf(dev, "%s: ipv6\n", __func__);
2286 *tcp_hdr_off = (ip_hlen + ehdrlen);
2291 #define QLA_TX_MIN_FREE 2
2294 * Function: Transmits a packet. It first checks if the packet is a
2295 * candidate for Large TCP Segment Offload and then for UDP/TCP checksum
2296 * offload. If either of these creteria are not met, it is transmitted
2297 * as a regular ethernet frame.
2300 ql_hw_send(qla_host_t *ha, bus_dma_segment_t *segs, int nsegs,
2301 uint32_t tx_idx, struct mbuf *mp, uint32_t txr_idx, uint32_t iscsi_pdu)
2303 struct ether_vlan_header *eh;
2304 qla_hw_t *hw = &ha->hw;
2305 q80_tx_cmd_t *tx_cmd, tso_cmd;
2306 bus_dma_segment_t *c_seg;
2307 uint32_t num_tx_cmds, hdr_len = 0;
2308 uint32_t total_length = 0, bytes, tx_cmd_count = 0, txr_next;
2311 uint8_t *src = NULL, *dst = NULL;
2312 uint8_t frame_hdr[QL_FRAME_HDR_SIZE];
2313 uint32_t op_code = 0;
2314 uint32_t tcp_hdr_off = 0;
2319 * Always make sure there is atleast one empty slot in the tx_ring
2320 * tx_ring is considered full when there only one entry available
2322 num_tx_cmds = (nsegs + (Q8_TX_CMD_MAX_SEGMENTS - 1)) >> 2;
2324 total_length = mp->m_pkthdr.len;
2325 if (total_length > QLA_MAX_TSO_FRAME_SIZE) {
2326 device_printf(dev, "%s: total length exceeds maxlen(%d)\n",
2327 __func__, total_length);
2330 eh = mtod(mp, struct ether_vlan_header *);
2332 if (mp->m_pkthdr.csum_flags & CSUM_TSO) {
2334 bzero((void *)&tso_cmd, sizeof(q80_tx_cmd_t));
2337 ret = qla_tx_tso(ha, mp, &tso_cmd, src);
2340 /* find the additional tx_cmd descriptors required */
2342 if (mp->m_flags & M_VLANTAG)
2343 tso_cmd.total_hdr_len += ETHER_VLAN_ENCAP_LEN;
2345 hdr_len = tso_cmd.total_hdr_len;
2347 bytes = sizeof(q80_tx_cmd_t) - Q8_TX_CMD_TSO_ALIGN;
2348 bytes = QL_MIN(bytes, hdr_len);
2354 bytes = QL_MIN((sizeof(q80_tx_cmd_t)), hdr_len);
2358 hdr_len = tso_cmd.total_hdr_len;
2361 src = (uint8_t *)eh;
2365 (void)qla_tx_chksum(ha, mp, &op_code, &tcp_hdr_off);
2368 if (hw->tx_cntxt[txr_idx].txr_free <= (num_tx_cmds + QLA_TX_MIN_FREE)) {
2369 ql_hw_tx_done_locked(ha, txr_idx);
2370 if (hw->tx_cntxt[txr_idx].txr_free <=
2371 (num_tx_cmds + QLA_TX_MIN_FREE)) {
2372 QL_DPRINT8(ha, (dev, "%s: (hw->txr_free <= "
2373 "(num_tx_cmds + QLA_TX_MIN_FREE))\n",
2379 for (i = 0; i < num_tx_cmds; i++) {
2382 j = (tx_idx+i) & (NUM_TX_DESCRIPTORS - 1);
2384 if (NULL != ha->tx_ring[txr_idx].tx_buf[j].m_head) {
2386 ("%s [%d]: txr_idx = %d tx_idx = %d mbuf = %p\n",\
2387 __func__, __LINE__, txr_idx, j,\
2388 ha->tx_ring[txr_idx].tx_buf[j].m_head));
2393 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[tx_idx];
2395 if (!(mp->m_pkthdr.csum_flags & CSUM_TSO)) {
2397 if (nsegs > ha->hw.max_tx_segs)
2398 ha->hw.max_tx_segs = nsegs;
2400 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t));
2403 tx_cmd->flags_opcode = op_code;
2404 tx_cmd->tcp_hdr_off = tcp_hdr_off;
2407 tx_cmd->flags_opcode = Q8_TX_CMD_OP_XMT_ETHER;
2410 bcopy(&tso_cmd, tx_cmd, sizeof(q80_tx_cmd_t));
2411 ha->tx_tso_frames++;
2414 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2415 tx_cmd->flags_opcode |= Q8_TX_CMD_FLAGS_VLAN_TAGGED;
2418 eh->evl_tag |= ha->hw.user_pri_iscsi << 13;
2420 } else if (mp->m_flags & M_VLANTAG) {
2422 if (hdr_len) { /* TSO */
2423 tx_cmd->flags_opcode |= (Q8_TX_CMD_FLAGS_VLAN_TAGGED |
2424 Q8_TX_CMD_FLAGS_HW_VLAN_ID);
2425 tx_cmd->tcp_hdr_off += ETHER_VLAN_ENCAP_LEN;
2427 tx_cmd->flags_opcode |= Q8_TX_CMD_FLAGS_HW_VLAN_ID;
2429 ha->hw_vlan_tx_frames++;
2430 tx_cmd->vlan_tci = mp->m_pkthdr.ether_vtag;
2433 tx_cmd->vlan_tci |= ha->hw.user_pri_iscsi << 13;
2434 mp->m_pkthdr.ether_vtag = tx_cmd->vlan_tci;
2439 tx_cmd->n_bufs = (uint8_t)nsegs;
2440 tx_cmd->data_len_lo = (uint8_t)(total_length & 0xFF);
2441 tx_cmd->data_len_hi = qla_host_to_le16(((uint16_t)(total_length >> 8)));
2442 tx_cmd->cntxtid = Q8_TX_CMD_PORT_CNXTID(ha->pci_func);
2447 for (i = 0; ((i < Q8_TX_CMD_MAX_SEGMENTS) && nsegs); i++) {
2451 tx_cmd->buf1_addr = c_seg->ds_addr;
2452 tx_cmd->buf1_len = c_seg->ds_len;
2456 tx_cmd->buf2_addr = c_seg->ds_addr;
2457 tx_cmd->buf2_len = c_seg->ds_len;
2461 tx_cmd->buf3_addr = c_seg->ds_addr;
2462 tx_cmd->buf3_len = c_seg->ds_len;
2466 tx_cmd->buf4_addr = c_seg->ds_addr;
2467 tx_cmd->buf4_len = c_seg->ds_len;
2475 txr_next = hw->tx_cntxt[txr_idx].txr_next =
2476 (hw->tx_cntxt[txr_idx].txr_next + 1) &
2477 (NUM_TX_DESCRIPTORS - 1);
2483 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[txr_next];
2484 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t));
2487 if (mp->m_pkthdr.csum_flags & CSUM_TSO) {
2489 /* TSO : Copy the header in the following tx cmd descriptors */
2491 txr_next = hw->tx_cntxt[txr_idx].txr_next;
2493 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[txr_next];
2494 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t));
2496 bytes = sizeof(q80_tx_cmd_t) - Q8_TX_CMD_TSO_ALIGN;
2497 bytes = QL_MIN(bytes, hdr_len);
2499 dst = (uint8_t *)tx_cmd + Q8_TX_CMD_TSO_ALIGN;
2501 if (mp->m_flags & M_VLANTAG) {
2502 /* first copy the src/dst MAC addresses */
2503 bcopy(src, dst, (ETHER_ADDR_LEN * 2));
2504 dst += (ETHER_ADDR_LEN * 2);
2505 src += (ETHER_ADDR_LEN * 2);
2507 *((uint16_t *)dst) = htons(ETHERTYPE_VLAN);
2509 *((uint16_t *)dst) = htons(mp->m_pkthdr.ether_vtag);
2512 /* bytes left in src header */
2513 hdr_len -= ((ETHER_ADDR_LEN * 2) +
2514 ETHER_VLAN_ENCAP_LEN);
2516 /* bytes left in TxCmd Entry */
2517 bytes -= ((ETHER_ADDR_LEN * 2) + ETHER_VLAN_ENCAP_LEN);
2520 bcopy(src, dst, bytes);
2524 bcopy(src, dst, bytes);
2529 txr_next = hw->tx_cntxt[txr_idx].txr_next =
2530 (hw->tx_cntxt[txr_idx].txr_next + 1) &
2531 (NUM_TX_DESCRIPTORS - 1);
2535 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[txr_next];
2536 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t));
2538 bytes = QL_MIN((sizeof(q80_tx_cmd_t)), hdr_len);
2540 bcopy(src, tx_cmd, bytes);
2544 txr_next = hw->tx_cntxt[txr_idx].txr_next =
2545 (hw->tx_cntxt[txr_idx].txr_next + 1) &
2546 (NUM_TX_DESCRIPTORS - 1);
2551 hw->tx_cntxt[txr_idx].txr_free =
2552 hw->tx_cntxt[txr_idx].txr_free - tx_cmd_count;
2554 QL_UPDATE_TX_PRODUCER_INDEX(ha, hw->tx_cntxt[txr_idx].txr_next,\
2556 QL_DPRINT8(ha, (dev, "%s: return\n", __func__));
2563 #define Q8_CONFIG_IND_TBL_SIZE 32 /* < Q8_RSS_IND_TBL_SIZE and power of 2 */
2565 qla_config_rss_ind_table(qla_host_t *ha)
2568 uint8_t rss_ind_tbl[Q8_CONFIG_IND_TBL_SIZE];
2571 for (i = 0; i < Q8_CONFIG_IND_TBL_SIZE; i++) {
2572 rss_ind_tbl[i] = i % ha->hw.num_sds_rings;
2575 for (i = 0; i <= Q8_RSS_IND_TBL_MAX_IDX ;
2576 i = i + Q8_CONFIG_IND_TBL_SIZE) {
2578 if ((i + Q8_CONFIG_IND_TBL_SIZE) > Q8_RSS_IND_TBL_MAX_IDX) {
2579 count = Q8_RSS_IND_TBL_MAX_IDX - i + 1;
2581 count = Q8_CONFIG_IND_TBL_SIZE;
2584 if (qla_set_rss_ind_table(ha, i, count, ha->hw.rcv_cntxt_id,
2593 qla_config_soft_lro(qla_host_t *ha)
2596 qla_hw_t *hw = &ha->hw;
2597 struct lro_ctrl *lro;
2599 for (i = 0; i < hw->num_sds_rings; i++) {
2600 lro = &hw->sds[i].lro;
2602 bzero(lro, sizeof(struct lro_ctrl));
2604 #if (__FreeBSD_version >= 1100101)
2605 if (tcp_lro_init_args(lro, ha->ifp, 0, NUM_RX_DESCRIPTORS)) {
2606 device_printf(ha->pci_dev,
2607 "%s: tcp_lro_init_args [%d] failed\n",
2612 if (tcp_lro_init(lro)) {
2613 device_printf(ha->pci_dev,
2614 "%s: tcp_lro_init [%d] failed\n",
2618 #endif /* #if (__FreeBSD_version >= 1100101) */
2623 QL_DPRINT2(ha, (ha->pci_dev, "%s: LRO initialized\n", __func__));
2628 qla_drain_soft_lro(qla_host_t *ha)
2631 qla_hw_t *hw = &ha->hw;
2632 struct lro_ctrl *lro;
2634 for (i = 0; i < hw->num_sds_rings; i++) {
2635 lro = &hw->sds[i].lro;
2637 #if (__FreeBSD_version >= 1100101)
2638 tcp_lro_flush_all(lro);
2640 struct lro_entry *queued;
2642 while ((!SLIST_EMPTY(&lro->lro_active))) {
2643 queued = SLIST_FIRST(&lro->lro_active);
2644 SLIST_REMOVE_HEAD(&lro->lro_active, next);
2645 tcp_lro_flush(lro, queued);
2647 #endif /* #if (__FreeBSD_version >= 1100101) */
2654 qla_free_soft_lro(qla_host_t *ha)
2657 qla_hw_t *hw = &ha->hw;
2658 struct lro_ctrl *lro;
2660 for (i = 0; i < hw->num_sds_rings; i++) {
2661 lro = &hw->sds[i].lro;
2670 * Name: ql_del_hw_if
2671 * Function: Destroys the hardware specific entities corresponding to an
2672 * Ethernet Interface
2675 ql_del_hw_if(qla_host_t *ha)
2680 (void)qla_stop_nic_func(ha);
2682 qla_del_rcv_cntxt(ha);
2684 qla_del_xmt_cntxt(ha);
2686 if (ha->hw.flags.init_intr_cnxt) {
2687 for (i = 0; i < ha->hw.num_sds_rings; ) {
2689 if ((i + Q8_MAX_INTR_VECTORS) < ha->hw.num_sds_rings)
2690 num_msix = Q8_MAX_INTR_VECTORS;
2692 num_msix = ha->hw.num_sds_rings - i;
2693 qla_config_intr_cntxt(ha, i, num_msix, 0);
2698 ha->hw.flags.init_intr_cnxt = 0;
2701 if (ha->hw.enable_soft_lro) {
2702 qla_drain_soft_lro(ha);
2703 qla_free_soft_lro(ha);
2710 qla_confirm_9kb_enable(qla_host_t *ha)
2712 uint32_t supports_9kb = 0;
2714 ha->hw.mbx_intr_mask_offset = READ_REG32(ha, Q8_MBOX_INT_MASK_MSIX);
2716 /* Use MSI-X vector 0; Enable Firmware Mailbox Interrupt */
2717 WRITE_REG32(ha, Q8_MBOX_INT_ENABLE, BIT_2);
2718 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
2720 qla_get_nic_partition(ha, &supports_9kb, NULL);
2723 ha->hw.enable_9kb = 0;
2729 * Name: ql_init_hw_if
2730 * Function: Creates the hardware specific entities corresponding to an
2731 * Ethernet Interface - Transmit and Receive Contexts. Sets the MAC Address
2732 * corresponding to the interface. Enables LRO if allowed.
2735 ql_init_hw_if(qla_host_t *ha)
2739 uint8_t bcast_mac[6];
2745 for (i = 0; i < ha->hw.num_sds_rings; i++) {
2746 bzero(ha->hw.dma_buf.sds_ring[i].dma_b,
2747 ha->hw.dma_buf.sds_ring[i].size);
2750 for (i = 0; i < ha->hw.num_sds_rings; ) {
2752 if ((i + Q8_MAX_INTR_VECTORS) < ha->hw.num_sds_rings)
2753 num_msix = Q8_MAX_INTR_VECTORS;
2755 num_msix = ha->hw.num_sds_rings - i;
2757 if (qla_config_intr_cntxt(ha, i, num_msix, 1)) {
2763 for (i = 0; i < num_msix; ) {
2764 qla_config_intr_cntxt(ha, i,
2765 Q8_MAX_INTR_VECTORS, 0);
2766 i += Q8_MAX_INTR_VECTORS;
2775 ha->hw.flags.init_intr_cnxt = 1;
2778 * Create Receive Context
2780 if (qla_init_rcv_cntxt(ha)) {
2784 for (i = 0; i < ha->hw.num_rds_rings; i++) {
2785 rdesc = &ha->hw.rds[i];
2786 rdesc->rx_next = NUM_RX_DESCRIPTORS - 2;
2788 /* Update the RDS Producer Indices */
2789 QL_UPDATE_RDS_PRODUCER_INDEX(ha, rdesc->prod_std,\
2794 * Create Transmit Context
2796 if (qla_init_xmt_cntxt(ha)) {
2797 qla_del_rcv_cntxt(ha);
2800 ha->hw.max_tx_segs = 0;
2802 if (qla_config_mac_addr(ha, ha->hw.mac_addr, 1, 1))
2805 ha->hw.flags.unicast_mac = 1;
2807 bcast_mac[0] = 0xFF; bcast_mac[1] = 0xFF; bcast_mac[2] = 0xFF;
2808 bcast_mac[3] = 0xFF; bcast_mac[4] = 0xFF; bcast_mac[5] = 0xFF;
2810 if (qla_config_mac_addr(ha, bcast_mac, 1, 1))
2813 ha->hw.flags.bcast_mac = 1;
2816 * program any cached multicast addresses
2818 if (qla_hw_add_all_mcast(ha))
2821 if (ql_set_max_mtu(ha, ha->max_frame_size, ha->hw.rcv_cntxt_id))
2824 if (qla_config_rss(ha, ha->hw.rcv_cntxt_id))
2827 if (qla_config_rss_ind_table(ha))
2830 if (qla_config_intr_coalesce(ha, ha->hw.rcv_cntxt_id, 0, 1))
2833 if (qla_link_event_req(ha, ha->hw.rcv_cntxt_id))
2836 if (ha->ifp->if_capenable & IFCAP_LRO) {
2837 if (ha->hw.enable_hw_lro) {
2838 ha->hw.enable_soft_lro = 0;
2840 if (qla_config_fw_lro(ha, ha->hw.rcv_cntxt_id))
2843 ha->hw.enable_soft_lro = 1;
2845 if (qla_config_soft_lro(ha))
2850 if (qla_init_nic_func(ha))
2853 if (qla_query_fw_dcbx_caps(ha))
2856 for (i = 0; i < ha->hw.num_sds_rings; i++)
2857 QL_ENABLE_INTERRUPTS(ha, i);
2863 qla_map_sds_to_rds(qla_host_t *ha, uint32_t start_idx, uint32_t num_idx)
2865 device_t dev = ha->pci_dev;
2866 q80_rq_map_sds_to_rds_t *map_rings;
2867 q80_rsp_map_sds_to_rds_t *map_rings_rsp;
2869 qla_hw_t *hw = &ha->hw;
2871 map_rings = (q80_rq_map_sds_to_rds_t *)ha->hw.mbox;
2872 bzero(map_rings, sizeof(q80_rq_map_sds_to_rds_t));
2874 map_rings->opcode = Q8_MBX_MAP_SDS_TO_RDS;
2875 map_rings->count_version = (sizeof (q80_rq_map_sds_to_rds_t) >> 2);
2876 map_rings->count_version |= Q8_MBX_CMD_VERSION;
2878 map_rings->cntxt_id = hw->rcv_cntxt_id;
2879 map_rings->num_rings = num_idx;
2881 for (i = 0; i < num_idx; i++) {
2882 map_rings->sds_rds[i].sds_ring = i + start_idx;
2883 map_rings->sds_rds[i].rds_ring = i + start_idx;
2886 if (qla_mbx_cmd(ha, (uint32_t *)map_rings,
2887 (sizeof (q80_rq_map_sds_to_rds_t) >> 2),
2888 ha->hw.mbox, (sizeof(q80_rsp_add_rcv_rings_t) >> 2), 0)) {
2889 device_printf(dev, "%s: failed0\n", __func__);
2893 map_rings_rsp = (q80_rsp_map_sds_to_rds_t *)ha->hw.mbox;
2895 err = Q8_MBX_RSP_STATUS(map_rings_rsp->regcnt_status);
2898 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
2906 * Name: qla_init_rcv_cntxt
2907 * Function: Creates the Receive Context.
2910 qla_init_rcv_cntxt(qla_host_t *ha)
2912 q80_rq_rcv_cntxt_t *rcntxt;
2913 q80_rsp_rcv_cntxt_t *rcntxt_rsp;
2914 q80_stat_desc_t *sdesc;
2916 qla_hw_t *hw = &ha->hw;
2919 uint32_t rcntxt_sds_rings;
2920 uint32_t rcntxt_rds_rings;
2926 * Create Receive Context
2929 for (i = 0; i < hw->num_sds_rings; i++) {
2930 sdesc = (q80_stat_desc_t *)&hw->sds[i].sds_ring_base[0];
2932 for (j = 0; j < NUM_STATUS_DESCRIPTORS; j++) {
2933 sdesc->data[0] = 1ULL;
2934 sdesc->data[1] = 1ULL;
2938 rcntxt_sds_rings = hw->num_sds_rings;
2939 if (hw->num_sds_rings > MAX_RCNTXT_SDS_RINGS)
2940 rcntxt_sds_rings = MAX_RCNTXT_SDS_RINGS;
2942 rcntxt_rds_rings = hw->num_rds_rings;
2944 if (hw->num_rds_rings > MAX_RDS_RING_SETS)
2945 rcntxt_rds_rings = MAX_RDS_RING_SETS;
2947 rcntxt = (q80_rq_rcv_cntxt_t *)ha->hw.mbox;
2948 bzero(rcntxt, (sizeof (q80_rq_rcv_cntxt_t)));
2950 rcntxt->opcode = Q8_MBX_CREATE_RX_CNTXT;
2951 rcntxt->count_version = (sizeof (q80_rq_rcv_cntxt_t) >> 2);
2952 rcntxt->count_version |= Q8_MBX_CMD_VERSION;
2954 rcntxt->cap0 = Q8_RCV_CNTXT_CAP0_BASEFW |
2955 Q8_RCV_CNTXT_CAP0_LRO |
2956 Q8_RCV_CNTXT_CAP0_HW_LRO |
2957 Q8_RCV_CNTXT_CAP0_RSS |
2958 Q8_RCV_CNTXT_CAP0_SGL_LRO;
2960 if (ha->hw.enable_9kb)
2961 rcntxt->cap0 |= Q8_RCV_CNTXT_CAP0_SINGLE_JUMBO;
2963 rcntxt->cap0 |= Q8_RCV_CNTXT_CAP0_SGL_JUMBO;
2965 if (ha->hw.num_rds_rings > 1) {
2966 rcntxt->nrds_sets_rings = rcntxt_rds_rings | (1 << 5);
2967 rcntxt->cap0 |= Q8_RCV_CNTXT_CAP0_MULTI_RDS;
2969 rcntxt->nrds_sets_rings = 0x1 | (1 << 5);
2971 rcntxt->nsds_rings = rcntxt_sds_rings;
2973 rcntxt->rds_producer_mode = Q8_RCV_CNTXT_RDS_PROD_MODE_UNIQUE;
2975 rcntxt->rcv_vpid = 0;
2977 for (i = 0; i < rcntxt_sds_rings; i++) {
2978 rcntxt->sds[i].paddr =
2979 qla_host_to_le64(hw->dma_buf.sds_ring[i].dma_addr);
2980 rcntxt->sds[i].size =
2981 qla_host_to_le32(NUM_STATUS_DESCRIPTORS);
2982 rcntxt->sds[i].intr_id = qla_host_to_le16(hw->intr_id[i]);
2983 rcntxt->sds[i].intr_src_bit = qla_host_to_le16(0);
2986 for (i = 0; i < rcntxt_rds_rings; i++) {
2987 rcntxt->rds[i].paddr_std =
2988 qla_host_to_le64(hw->dma_buf.rds_ring[i].dma_addr);
2990 if (ha->hw.enable_9kb)
2991 rcntxt->rds[i].std_bsize =
2992 qla_host_to_le64(MJUM9BYTES);
2994 rcntxt->rds[i].std_bsize = qla_host_to_le64(MCLBYTES);
2996 rcntxt->rds[i].std_nentries =
2997 qla_host_to_le32(NUM_RX_DESCRIPTORS);
3000 if (qla_mbx_cmd(ha, (uint32_t *)rcntxt,
3001 (sizeof (q80_rq_rcv_cntxt_t) >> 2),
3002 ha->hw.mbox, (sizeof(q80_rsp_rcv_cntxt_t) >> 2), 0)) {
3003 device_printf(dev, "%s: failed0\n", __func__);
3007 rcntxt_rsp = (q80_rsp_rcv_cntxt_t *)ha->hw.mbox;
3009 err = Q8_MBX_RSP_STATUS(rcntxt_rsp->regcnt_status);
3012 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
3016 for (i = 0; i < rcntxt_sds_rings; i++) {
3017 hw->sds[i].sds_consumer = rcntxt_rsp->sds_cons[i];
3020 for (i = 0; i < rcntxt_rds_rings; i++) {
3021 hw->rds[i].prod_std = rcntxt_rsp->rds[i].prod_std;
3024 hw->rcv_cntxt_id = rcntxt_rsp->cntxt_id;
3026 ha->hw.flags.init_rx_cnxt = 1;
3028 if (hw->num_sds_rings > MAX_RCNTXT_SDS_RINGS) {
3030 for (i = MAX_RCNTXT_SDS_RINGS; i < hw->num_sds_rings;) {
3032 if ((i + MAX_RCNTXT_SDS_RINGS) < hw->num_sds_rings)
3033 max_idx = MAX_RCNTXT_SDS_RINGS;
3035 max_idx = hw->num_sds_rings - i;
3037 err = qla_add_rcv_rings(ha, i, max_idx);
3045 if (hw->num_rds_rings > 1) {
3047 for (i = 0; i < hw->num_rds_rings; ) {
3049 if ((i + MAX_SDS_TO_RDS_MAP) < hw->num_rds_rings)
3050 max_idx = MAX_SDS_TO_RDS_MAP;
3052 max_idx = hw->num_rds_rings - i;
3054 err = qla_map_sds_to_rds(ha, i, max_idx);
3066 qla_add_rcv_rings(qla_host_t *ha, uint32_t sds_idx, uint32_t nsds)
3068 device_t dev = ha->pci_dev;
3069 q80_rq_add_rcv_rings_t *add_rcv;
3070 q80_rsp_add_rcv_rings_t *add_rcv_rsp;
3072 qla_hw_t *hw = &ha->hw;
3074 add_rcv = (q80_rq_add_rcv_rings_t *)ha->hw.mbox;
3075 bzero(add_rcv, sizeof (q80_rq_add_rcv_rings_t));
3077 add_rcv->opcode = Q8_MBX_ADD_RX_RINGS;
3078 add_rcv->count_version = (sizeof (q80_rq_add_rcv_rings_t) >> 2);
3079 add_rcv->count_version |= Q8_MBX_CMD_VERSION;
3081 add_rcv->nrds_sets_rings = nsds | (1 << 5);
3082 add_rcv->nsds_rings = nsds;
3083 add_rcv->cntxt_id = hw->rcv_cntxt_id;
3085 for (i = 0; i < nsds; i++) {
3089 add_rcv->sds[i].paddr =
3090 qla_host_to_le64(hw->dma_buf.sds_ring[j].dma_addr);
3092 add_rcv->sds[i].size =
3093 qla_host_to_le32(NUM_STATUS_DESCRIPTORS);
3095 add_rcv->sds[i].intr_id = qla_host_to_le16(hw->intr_id[j]);
3096 add_rcv->sds[i].intr_src_bit = qla_host_to_le16(0);
3100 for (i = 0; (i < nsds); i++) {
3103 add_rcv->rds[i].paddr_std =
3104 qla_host_to_le64(hw->dma_buf.rds_ring[j].dma_addr);
3106 if (ha->hw.enable_9kb)
3107 add_rcv->rds[i].std_bsize =
3108 qla_host_to_le64(MJUM9BYTES);
3110 add_rcv->rds[i].std_bsize = qla_host_to_le64(MCLBYTES);
3112 add_rcv->rds[i].std_nentries =
3113 qla_host_to_le32(NUM_RX_DESCRIPTORS);
3117 if (qla_mbx_cmd(ha, (uint32_t *)add_rcv,
3118 (sizeof (q80_rq_add_rcv_rings_t) >> 2),
3119 ha->hw.mbox, (sizeof(q80_rsp_add_rcv_rings_t) >> 2), 0)) {
3120 device_printf(dev, "%s: failed0\n", __func__);
3124 add_rcv_rsp = (q80_rsp_add_rcv_rings_t *)ha->hw.mbox;
3126 err = Q8_MBX_RSP_STATUS(add_rcv_rsp->regcnt_status);
3129 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
3133 for (i = 0; i < nsds; i++) {
3134 hw->sds[(i + sds_idx)].sds_consumer = add_rcv_rsp->sds_cons[i];
3137 for (i = 0; i < nsds; i++) {
3138 hw->rds[(i + sds_idx)].prod_std = add_rcv_rsp->rds[i].prod_std;
3145 * Name: qla_del_rcv_cntxt
3146 * Function: Destroys the Receive Context.
3149 qla_del_rcv_cntxt(qla_host_t *ha)
3151 device_t dev = ha->pci_dev;
3152 q80_rcv_cntxt_destroy_t *rcntxt;
3153 q80_rcv_cntxt_destroy_rsp_t *rcntxt_rsp;
3155 uint8_t bcast_mac[6];
3157 if (!ha->hw.flags.init_rx_cnxt)
3160 if (qla_hw_del_all_mcast(ha))
3163 if (ha->hw.flags.bcast_mac) {
3165 bcast_mac[0] = 0xFF; bcast_mac[1] = 0xFF; bcast_mac[2] = 0xFF;
3166 bcast_mac[3] = 0xFF; bcast_mac[4] = 0xFF; bcast_mac[5] = 0xFF;
3168 if (qla_config_mac_addr(ha, bcast_mac, 0, 1))
3170 ha->hw.flags.bcast_mac = 0;
3174 if (ha->hw.flags.unicast_mac) {
3175 if (qla_config_mac_addr(ha, ha->hw.mac_addr, 0, 1))
3177 ha->hw.flags.unicast_mac = 0;
3180 rcntxt = (q80_rcv_cntxt_destroy_t *)ha->hw.mbox;
3181 bzero(rcntxt, (sizeof (q80_rcv_cntxt_destroy_t)));
3183 rcntxt->opcode = Q8_MBX_DESTROY_RX_CNTXT;
3184 rcntxt->count_version = (sizeof (q80_rcv_cntxt_destroy_t) >> 2);
3185 rcntxt->count_version |= Q8_MBX_CMD_VERSION;
3187 rcntxt->cntxt_id = ha->hw.rcv_cntxt_id;
3189 if (qla_mbx_cmd(ha, (uint32_t *)rcntxt,
3190 (sizeof (q80_rcv_cntxt_destroy_t) >> 2),
3191 ha->hw.mbox, (sizeof(q80_rcv_cntxt_destroy_rsp_t) >> 2), 0)) {
3192 device_printf(dev, "%s: failed0\n", __func__);
3195 rcntxt_rsp = (q80_rcv_cntxt_destroy_rsp_t *)ha->hw.mbox;
3197 err = Q8_MBX_RSP_STATUS(rcntxt_rsp->regcnt_status);
3200 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
3203 ha->hw.flags.init_rx_cnxt = 0;
3208 * Name: qla_init_xmt_cntxt
3209 * Function: Creates the Transmit Context.
3212 qla_init_xmt_cntxt_i(qla_host_t *ha, uint32_t txr_idx)
3215 qla_hw_t *hw = &ha->hw;
3216 q80_rq_tx_cntxt_t *tcntxt;
3217 q80_rsp_tx_cntxt_t *tcntxt_rsp;
3219 qla_hw_tx_cntxt_t *hw_tx_cntxt;
3222 hw_tx_cntxt = &hw->tx_cntxt[txr_idx];
3227 * Create Transmit Context
3229 tcntxt = (q80_rq_tx_cntxt_t *)ha->hw.mbox;
3230 bzero(tcntxt, (sizeof (q80_rq_tx_cntxt_t)));
3232 tcntxt->opcode = Q8_MBX_CREATE_TX_CNTXT;
3233 tcntxt->count_version = (sizeof (q80_rq_tx_cntxt_t) >> 2);
3234 tcntxt->count_version |= Q8_MBX_CMD_VERSION;
3238 #ifdef QL_ENABLE_ISCSI_TLV
3240 tcntxt->cap0 = Q8_TX_CNTXT_CAP0_BASEFW | Q8_TX_CNTXT_CAP0_LSO |
3241 Q8_TX_CNTXT_CAP0_TC;
3243 if (txr_idx >= (ha->hw.num_tx_rings >> 1)) {
3244 tcntxt->traffic_class = 1;
3247 intr_idx = txr_idx % (ha->hw.num_tx_rings >> 1);
3250 tcntxt->cap0 = Q8_TX_CNTXT_CAP0_BASEFW | Q8_TX_CNTXT_CAP0_LSO;
3252 #endif /* #ifdef QL_ENABLE_ISCSI_TLV */
3254 tcntxt->ntx_rings = 1;
3256 tcntxt->tx_ring[0].paddr =
3257 qla_host_to_le64(hw_tx_cntxt->tx_ring_paddr);
3258 tcntxt->tx_ring[0].tx_consumer =
3259 qla_host_to_le64(hw_tx_cntxt->tx_cons_paddr);
3260 tcntxt->tx_ring[0].nentries = qla_host_to_le16(NUM_TX_DESCRIPTORS);
3262 tcntxt->tx_ring[0].intr_id = qla_host_to_le16(hw->intr_id[intr_idx]);
3263 tcntxt->tx_ring[0].intr_src_bit = qla_host_to_le16(0);
3265 hw_tx_cntxt->txr_free = NUM_TX_DESCRIPTORS;
3266 hw_tx_cntxt->txr_next = hw_tx_cntxt->txr_comp = 0;
3267 *(hw_tx_cntxt->tx_cons) = 0;
3269 if (qla_mbx_cmd(ha, (uint32_t *)tcntxt,
3270 (sizeof (q80_rq_tx_cntxt_t) >> 2),
3272 (sizeof(q80_rsp_tx_cntxt_t) >> 2), 0)) {
3273 device_printf(dev, "%s: failed0\n", __func__);
3276 tcntxt_rsp = (q80_rsp_tx_cntxt_t *)ha->hw.mbox;
3278 err = Q8_MBX_RSP_STATUS(tcntxt_rsp->regcnt_status);
3281 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
3285 hw_tx_cntxt->tx_prod_reg = tcntxt_rsp->tx_ring[0].prod_index;
3286 hw_tx_cntxt->tx_cntxt_id = tcntxt_rsp->tx_ring[0].cntxt_id;
3288 if (qla_config_intr_coalesce(ha, hw_tx_cntxt->tx_cntxt_id, 0, 0))
3296 * Name: qla_del_xmt_cntxt
3297 * Function: Destroys the Transmit Context.
3300 qla_del_xmt_cntxt_i(qla_host_t *ha, uint32_t txr_idx)
3302 device_t dev = ha->pci_dev;
3303 q80_tx_cntxt_destroy_t *tcntxt;
3304 q80_tx_cntxt_destroy_rsp_t *tcntxt_rsp;
3307 tcntxt = (q80_tx_cntxt_destroy_t *)ha->hw.mbox;
3308 bzero(tcntxt, (sizeof (q80_tx_cntxt_destroy_t)));
3310 tcntxt->opcode = Q8_MBX_DESTROY_TX_CNTXT;
3311 tcntxt->count_version = (sizeof (q80_tx_cntxt_destroy_t) >> 2);
3312 tcntxt->count_version |= Q8_MBX_CMD_VERSION;
3314 tcntxt->cntxt_id = ha->hw.tx_cntxt[txr_idx].tx_cntxt_id;
3316 if (qla_mbx_cmd(ha, (uint32_t *)tcntxt,
3317 (sizeof (q80_tx_cntxt_destroy_t) >> 2),
3318 ha->hw.mbox, (sizeof (q80_tx_cntxt_destroy_rsp_t) >> 2), 0)) {
3319 device_printf(dev, "%s: failed0\n", __func__);
3322 tcntxt_rsp = (q80_tx_cntxt_destroy_rsp_t *)ha->hw.mbox;
3324 err = Q8_MBX_RSP_STATUS(tcntxt_rsp->regcnt_status);
3327 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err);
3334 qla_del_xmt_cntxt(qla_host_t *ha)
3338 if (!ha->hw.flags.init_tx_cnxt)
3341 for (i = 0; i < ha->hw.num_tx_rings; i++) {
3342 if (qla_del_xmt_cntxt_i(ha, i))
3345 ha->hw.flags.init_tx_cnxt = 0;
3349 qla_init_xmt_cntxt(qla_host_t *ha)
3353 for (i = 0; i < ha->hw.num_tx_rings; i++) {
3354 if (qla_init_xmt_cntxt_i(ha, i) != 0) {
3355 for (j = 0; j < i; j++)
3356 qla_del_xmt_cntxt_i(ha, j);
3360 ha->hw.flags.init_tx_cnxt = 1;
3365 qla_hw_all_mcast(qla_host_t *ha, uint32_t add_mcast)
3371 nmcast = ha->hw.nmcast;
3373 QL_DPRINT2(ha, (ha->pci_dev,
3374 "%s:[0x%x] enter nmcast = %d \n", __func__, add_mcast, nmcast));
3376 mcast = ha->hw.mac_addr_arr;
3377 memset(mcast, 0, (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN));
3379 for (i = 0 ; ((i < Q8_MAX_NUM_MULTICAST_ADDRS) && nmcast); i++) {
3380 if ((ha->hw.mcast[i].addr[0] != 0) ||
3381 (ha->hw.mcast[i].addr[1] != 0) ||
3382 (ha->hw.mcast[i].addr[2] != 0) ||
3383 (ha->hw.mcast[i].addr[3] != 0) ||
3384 (ha->hw.mcast[i].addr[4] != 0) ||
3385 (ha->hw.mcast[i].addr[5] != 0)) {
3387 bcopy(ha->hw.mcast[i].addr, mcast, ETHER_ADDR_LEN);
3388 mcast = mcast + ETHER_ADDR_LEN;
3391 if (count == Q8_MAX_MAC_ADDRS) {
3392 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr,
3393 add_mcast, count)) {
3394 device_printf(ha->pci_dev,
3395 "%s: failed\n", __func__);
3400 mcast = ha->hw.mac_addr_arr;
3402 (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN));
3410 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr, add_mcast,
3412 device_printf(ha->pci_dev, "%s: failed\n", __func__);
3416 QL_DPRINT2(ha, (ha->pci_dev,
3417 "%s:[0x%x] exit nmcast = %d \n", __func__, add_mcast, nmcast));
3423 qla_hw_add_all_mcast(qla_host_t *ha)
3427 ret = qla_hw_all_mcast(ha, 1);
3433 qla_hw_del_all_mcast(qla_host_t *ha)
3437 ret = qla_hw_all_mcast(ha, 0);
3439 bzero(ha->hw.mcast, (sizeof (qla_mcast_t) * Q8_MAX_NUM_MULTICAST_ADDRS));
3446 qla_hw_mac_addr_present(qla_host_t *ha, uint8_t *mta)
3450 for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) {
3451 if (QL_MAC_CMP(ha->hw.mcast[i].addr, mta) == 0)
3452 return (0); /* its been already added */
3458 qla_hw_add_mcast(qla_host_t *ha, uint8_t *mta, uint32_t nmcast)
3462 for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) {
3464 if ((ha->hw.mcast[i].addr[0] == 0) &&
3465 (ha->hw.mcast[i].addr[1] == 0) &&
3466 (ha->hw.mcast[i].addr[2] == 0) &&
3467 (ha->hw.mcast[i].addr[3] == 0) &&
3468 (ha->hw.mcast[i].addr[4] == 0) &&
3469 (ha->hw.mcast[i].addr[5] == 0)) {
3471 bcopy(mta, ha->hw.mcast[i].addr, Q8_MAC_ADDR_LEN);
3474 mta = mta + ETHER_ADDR_LEN;
3486 qla_hw_del_mcast(qla_host_t *ha, uint8_t *mta, uint32_t nmcast)
3490 for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) {
3491 if (QL_MAC_CMP(ha->hw.mcast[i].addr, mta) == 0) {
3493 ha->hw.mcast[i].addr[0] = 0;
3494 ha->hw.mcast[i].addr[1] = 0;
3495 ha->hw.mcast[i].addr[2] = 0;
3496 ha->hw.mcast[i].addr[3] = 0;
3497 ha->hw.mcast[i].addr[4] = 0;
3498 ha->hw.mcast[i].addr[5] = 0;
3502 mta = mta + ETHER_ADDR_LEN;
3513 * Name: ql_hw_set_multi
3514 * Function: Sets the Multicast Addresses provided by the host O.S into the
3515 * hardware (for the given interface)
3518 ql_hw_set_multi(qla_host_t *ha, uint8_t *mcast_addr, uint32_t mcnt,
3521 uint8_t *mta = mcast_addr;
3527 mcast = ha->hw.mac_addr_arr;
3528 memset(mcast, 0, (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN));
3530 for (i = 0; i < mcnt; i++) {
3531 if (mta[0] || mta[1] || mta[2] || mta[3] || mta[4] || mta[5]) {
3533 if (qla_hw_mac_addr_present(ha, mta) != 0) {
3534 bcopy(mta, mcast, ETHER_ADDR_LEN);
3535 mcast = mcast + ETHER_ADDR_LEN;
3539 if (qla_hw_mac_addr_present(ha, mta) == 0) {
3540 bcopy(mta, mcast, ETHER_ADDR_LEN);
3541 mcast = mcast + ETHER_ADDR_LEN;
3546 if (count == Q8_MAX_MAC_ADDRS) {
3547 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr,
3549 device_printf(ha->pci_dev, "%s: failed\n",
3555 qla_hw_add_mcast(ha, ha->hw.mac_addr_arr,
3558 qla_hw_del_mcast(ha, ha->hw.mac_addr_arr,
3563 mcast = ha->hw.mac_addr_arr;
3564 memset(mcast, 0, (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN));
3567 mta += Q8_MAC_ADDR_LEN;
3571 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr, add_mac,
3573 device_printf(ha->pci_dev, "%s: failed\n", __func__);
3577 qla_hw_add_mcast(ha, ha->hw.mac_addr_arr, count);
3579 qla_hw_del_mcast(ha, ha->hw.mac_addr_arr, count);
3587 * Name: ql_hw_tx_done_locked
3588 * Function: Handle Transmit Completions
3591 ql_hw_tx_done_locked(qla_host_t *ha, uint32_t txr_idx)
3594 qla_hw_t *hw = &ha->hw;
3595 uint32_t comp_idx, comp_count = 0;
3596 qla_hw_tx_cntxt_t *hw_tx_cntxt;
3598 hw_tx_cntxt = &hw->tx_cntxt[txr_idx];
3600 /* retrieve index of last entry in tx ring completed */
3601 comp_idx = qla_le32_to_host(*(hw_tx_cntxt->tx_cons));
3603 while (comp_idx != hw_tx_cntxt->txr_comp) {
3605 txb = &ha->tx_ring[txr_idx].tx_buf[hw_tx_cntxt->txr_comp];
3607 hw_tx_cntxt->txr_comp++;
3608 if (hw_tx_cntxt->txr_comp == NUM_TX_DESCRIPTORS)
3609 hw_tx_cntxt->txr_comp = 0;
3614 if_inc_counter(ha->ifp, IFCOUNTER_OPACKETS, 1);
3616 bus_dmamap_sync(ha->tx_tag, txb->map,
3617 BUS_DMASYNC_POSTWRITE);
3618 bus_dmamap_unload(ha->tx_tag, txb->map);
3619 m_freem(txb->m_head);
3625 hw_tx_cntxt->txr_free += comp_count;
3630 ql_update_link_state(qla_host_t *ha)
3632 uint32_t link_state;
3633 uint32_t prev_link_state;
3635 if (!(ha->ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3639 link_state = READ_REG32(ha, Q8_LINK_STATE);
3641 prev_link_state = ha->hw.link_up;
3643 if (ha->pci_func == 0)
3644 ha->hw.link_up = (((link_state & 0xF) == 1)? 1 : 0);
3646 ha->hw.link_up = ((((link_state >> 4)& 0xF) == 1)? 1 : 0);
3648 if (prev_link_state != ha->hw.link_up) {
3649 if (ha->hw.link_up) {
3650 if_link_state_change(ha->ifp, LINK_STATE_UP);
3652 if_link_state_change(ha->ifp, LINK_STATE_DOWN);
3659 ql_hw_check_health(qla_host_t *ha)
3663 ha->hw.health_count++;
3665 if (ha->hw.health_count < 500)
3668 ha->hw.health_count = 0;
3670 val = READ_REG32(ha, Q8_ASIC_TEMPERATURE);
3672 if (((val & 0xFFFF) == 2) || ((val & 0xFFFF) == 3) ||
3673 (QL_ERR_INJECT(ha, INJCT_TEMPERATURE_FAILURE))) {
3674 device_printf(ha->pci_dev, "%s: Temperature Alert [0x%08x]\n",
3679 val = READ_REG32(ha, Q8_FIRMWARE_HEARTBEAT);
3681 if ((val != ha->hw.hbeat_value) &&
3682 (!(QL_ERR_INJECT(ha, INJCT_HEARTBEAT_FAILURE)))) {
3683 ha->hw.hbeat_value = val;
3684 ha->hw.hbeat_failure = 0;
3688 ha->hw.hbeat_failure++;
3691 if ((ha->dbg_level & 0x8000) && (ha->hw.hbeat_failure == 1))
3692 device_printf(ha->pci_dev, "%s: Heartbeat Failue 1[0x%08x]\n",
3694 if (ha->hw.hbeat_failure < 2) /* we ignore the first failure */
3697 device_printf(ha->pci_dev, "%s: Heartbeat Failue [0x%08x]\n",
3704 qla_init_nic_func(qla_host_t *ha)
3707 q80_init_nic_func_t *init_nic;
3708 q80_init_nic_func_rsp_t *init_nic_rsp;
3713 init_nic = (q80_init_nic_func_t *)ha->hw.mbox;
3714 bzero(init_nic, sizeof(q80_init_nic_func_t));
3716 init_nic->opcode = Q8_MBX_INIT_NIC_FUNC;
3717 init_nic->count_version = (sizeof (q80_init_nic_func_t) >> 2);
3718 init_nic->count_version |= Q8_MBX_CMD_VERSION;
3720 init_nic->options = Q8_INIT_NIC_REG_DCBX_CHNG_AEN;
3721 init_nic->options |= Q8_INIT_NIC_REG_SFP_CHNG_AEN;
3722 init_nic->options |= Q8_INIT_NIC_REG_IDC_AEN;
3724 //qla_dump_buf8(ha, __func__, init_nic, sizeof (q80_init_nic_func_t));
3725 if (qla_mbx_cmd(ha, (uint32_t *)init_nic,
3726 (sizeof (q80_init_nic_func_t) >> 2),
3727 ha->hw.mbox, (sizeof (q80_init_nic_func_rsp_t) >> 2), 0)) {
3728 device_printf(dev, "%s: failed\n", __func__);
3732 init_nic_rsp = (q80_init_nic_func_rsp_t *)ha->hw.mbox;
3733 // qla_dump_buf8(ha, __func__, init_nic_rsp, sizeof (q80_init_nic_func_rsp_t));
3735 err = Q8_MBX_RSP_STATUS(init_nic_rsp->regcnt_status);
3738 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
3745 qla_stop_nic_func(qla_host_t *ha)
3748 q80_stop_nic_func_t *stop_nic;
3749 q80_stop_nic_func_rsp_t *stop_nic_rsp;
3754 stop_nic = (q80_stop_nic_func_t *)ha->hw.mbox;
3755 bzero(stop_nic, sizeof(q80_stop_nic_func_t));
3757 stop_nic->opcode = Q8_MBX_STOP_NIC_FUNC;
3758 stop_nic->count_version = (sizeof (q80_stop_nic_func_t) >> 2);
3759 stop_nic->count_version |= Q8_MBX_CMD_VERSION;
3761 stop_nic->options = Q8_STOP_NIC_DEREG_DCBX_CHNG_AEN;
3762 stop_nic->options |= Q8_STOP_NIC_DEREG_SFP_CHNG_AEN;
3764 //qla_dump_buf8(ha, __func__, stop_nic, sizeof (q80_stop_nic_func_t));
3765 if (qla_mbx_cmd(ha, (uint32_t *)stop_nic,
3766 (sizeof (q80_stop_nic_func_t) >> 2),
3767 ha->hw.mbox, (sizeof (q80_stop_nic_func_rsp_t) >> 2), 0)) {
3768 device_printf(dev, "%s: failed\n", __func__);
3772 stop_nic_rsp = (q80_stop_nic_func_rsp_t *)ha->hw.mbox;
3773 //qla_dump_buf8(ha, __func__, stop_nic_rsp, sizeof (q80_stop_nic_func_rsp_ t));
3775 err = Q8_MBX_RSP_STATUS(stop_nic_rsp->regcnt_status);
3778 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
3785 qla_query_fw_dcbx_caps(qla_host_t *ha)
3788 q80_query_fw_dcbx_caps_t *fw_dcbx;
3789 q80_query_fw_dcbx_caps_rsp_t *fw_dcbx_rsp;
3794 fw_dcbx = (q80_query_fw_dcbx_caps_t *)ha->hw.mbox;
3795 bzero(fw_dcbx, sizeof(q80_query_fw_dcbx_caps_t));
3797 fw_dcbx->opcode = Q8_MBX_GET_FW_DCBX_CAPS;
3798 fw_dcbx->count_version = (sizeof (q80_query_fw_dcbx_caps_t) >> 2);
3799 fw_dcbx->count_version |= Q8_MBX_CMD_VERSION;
3801 ql_dump_buf8(ha, __func__, fw_dcbx, sizeof (q80_query_fw_dcbx_caps_t));
3802 if (qla_mbx_cmd(ha, (uint32_t *)fw_dcbx,
3803 (sizeof (q80_query_fw_dcbx_caps_t) >> 2),
3804 ha->hw.mbox, (sizeof (q80_query_fw_dcbx_caps_rsp_t) >> 2), 0)) {
3805 device_printf(dev, "%s: failed\n", __func__);
3809 fw_dcbx_rsp = (q80_query_fw_dcbx_caps_rsp_t *)ha->hw.mbox;
3810 ql_dump_buf8(ha, __func__, fw_dcbx_rsp,
3811 sizeof (q80_query_fw_dcbx_caps_rsp_t));
3813 err = Q8_MBX_RSP_STATUS(fw_dcbx_rsp->regcnt_status);
3816 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
3823 qla_idc_ack(qla_host_t *ha, uint32_t aen_mb1, uint32_t aen_mb2,
3824 uint32_t aen_mb3, uint32_t aen_mb4)
3827 q80_idc_ack_t *idc_ack;
3828 q80_idc_ack_rsp_t *idc_ack_rsp;
3834 idc_ack = (q80_idc_ack_t *)ha->hw.mbox;
3835 bzero(idc_ack, sizeof(q80_idc_ack_t));
3837 idc_ack->opcode = Q8_MBX_IDC_ACK;
3838 idc_ack->count_version = (sizeof (q80_idc_ack_t) >> 2);
3839 idc_ack->count_version |= Q8_MBX_CMD_VERSION;
3841 idc_ack->aen_mb1 = aen_mb1;
3842 idc_ack->aen_mb2 = aen_mb2;
3843 idc_ack->aen_mb3 = aen_mb3;
3844 idc_ack->aen_mb4 = aen_mb4;
3846 ha->hw.imd_compl= 0;
3848 if (qla_mbx_cmd(ha, (uint32_t *)idc_ack,
3849 (sizeof (q80_idc_ack_t) >> 2),
3850 ha->hw.mbox, (sizeof (q80_idc_ack_rsp_t) >> 2), 0)) {
3851 device_printf(dev, "%s: failed\n", __func__);
3855 idc_ack_rsp = (q80_idc_ack_rsp_t *)ha->hw.mbox;
3857 err = Q8_MBX_RSP_STATUS(idc_ack_rsp->regcnt_status);
3860 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
3864 while (count && !ha->hw.imd_compl) {
3865 qla_mdelay(__func__, 100);
3872 device_printf(dev, "%s: count %d\n", __func__, count);
3878 qla_set_port_config(qla_host_t *ha, uint32_t cfg_bits)
3881 q80_set_port_cfg_t *pcfg;
3882 q80_set_port_cfg_rsp_t *pfg_rsp;
3888 pcfg = (q80_set_port_cfg_t *)ha->hw.mbox;
3889 bzero(pcfg, sizeof(q80_set_port_cfg_t));
3891 pcfg->opcode = Q8_MBX_SET_PORT_CONFIG;
3892 pcfg->count_version = (sizeof (q80_set_port_cfg_t) >> 2);
3893 pcfg->count_version |= Q8_MBX_CMD_VERSION;
3895 pcfg->cfg_bits = cfg_bits;
3897 device_printf(dev, "%s: cfg_bits"
3898 " [STD_PAUSE_DIR, PAUSE_TYPE, DCBX]"
3899 " [0x%x, 0x%x, 0x%x]\n", __func__,
3900 ((cfg_bits & Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK)>>20),
3901 ((cfg_bits & Q8_PORT_CFG_BITS_PAUSE_CFG_MASK) >> 5),
3902 ((cfg_bits & Q8_PORT_CFG_BITS_DCBX_ENABLE) ? 1: 0));
3904 ha->hw.imd_compl= 0;
3906 if (qla_mbx_cmd(ha, (uint32_t *)pcfg,
3907 (sizeof (q80_set_port_cfg_t) >> 2),
3908 ha->hw.mbox, (sizeof (q80_set_port_cfg_rsp_t) >> 2), 0)) {
3909 device_printf(dev, "%s: failed\n", __func__);
3913 pfg_rsp = (q80_set_port_cfg_rsp_t *)ha->hw.mbox;
3915 err = Q8_MBX_RSP_STATUS(pfg_rsp->regcnt_status);
3917 if (err == Q8_MBX_RSP_IDC_INTRMD_RSP) {
3918 while (count && !ha->hw.imd_compl) {
3919 qla_mdelay(__func__, 100);
3923 device_printf(dev, "%s: count %d\n", __func__, count);
3930 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
3939 qla_get_minidump_tmplt_size(qla_host_t *ha, uint32_t *size)
3942 device_t dev = ha->pci_dev;
3943 q80_config_md_templ_size_t *md_size;
3944 q80_config_md_templ_size_rsp_t *md_size_rsp;
3946 #ifndef QL_LDFLASH_FW
3948 ql_minidump_template_hdr_t *hdr;
3950 hdr = (ql_minidump_template_hdr_t *)ql83xx_minidump;
3951 *size = hdr->size_of_template;
3954 #endif /* #ifdef QL_LDFLASH_FW */
3956 md_size = (q80_config_md_templ_size_t *) ha->hw.mbox;
3957 bzero(md_size, sizeof(q80_config_md_templ_size_t));
3959 md_size->opcode = Q8_MBX_GET_MINIDUMP_TMPLT_SIZE;
3960 md_size->count_version = (sizeof (q80_config_md_templ_size_t) >> 2);
3961 md_size->count_version |= Q8_MBX_CMD_VERSION;
3963 if (qla_mbx_cmd(ha, (uint32_t *) md_size,
3964 (sizeof(q80_config_md_templ_size_t) >> 2), ha->hw.mbox,
3965 (sizeof(q80_config_md_templ_size_rsp_t) >> 2), 0)) {
3967 device_printf(dev, "%s: failed\n", __func__);
3972 md_size_rsp = (q80_config_md_templ_size_rsp_t *) ha->hw.mbox;
3974 err = Q8_MBX_RSP_STATUS(md_size_rsp->regcnt_status);
3977 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
3981 *size = md_size_rsp->templ_size;
3987 qla_get_port_config(qla_host_t *ha, uint32_t *cfg_bits)
3990 q80_get_port_cfg_t *pcfg;
3991 q80_get_port_cfg_rsp_t *pcfg_rsp;
3996 pcfg = (q80_get_port_cfg_t *)ha->hw.mbox;
3997 bzero(pcfg, sizeof(q80_get_port_cfg_t));
3999 pcfg->opcode = Q8_MBX_GET_PORT_CONFIG;
4000 pcfg->count_version = (sizeof (q80_get_port_cfg_t) >> 2);
4001 pcfg->count_version |= Q8_MBX_CMD_VERSION;
4003 if (qla_mbx_cmd(ha, (uint32_t *)pcfg,
4004 (sizeof (q80_get_port_cfg_t) >> 2),
4005 ha->hw.mbox, (sizeof (q80_get_port_cfg_rsp_t) >> 2), 0)) {
4006 device_printf(dev, "%s: failed\n", __func__);
4010 pcfg_rsp = (q80_get_port_cfg_rsp_t *)ha->hw.mbox;
4012 err = Q8_MBX_RSP_STATUS(pcfg_rsp->regcnt_status);
4015 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
4019 device_printf(dev, "%s: [cfg_bits, port type]"
4020 " [0x%08x, 0x%02x] [STD_PAUSE_DIR, PAUSE_TYPE, DCBX]"
4021 " [0x%x, 0x%x, 0x%x]\n", __func__,
4022 pcfg_rsp->cfg_bits, pcfg_rsp->phys_port_type,
4023 ((pcfg_rsp->cfg_bits & Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK)>>20),
4024 ((pcfg_rsp->cfg_bits & Q8_PORT_CFG_BITS_PAUSE_CFG_MASK) >> 5),
4025 ((pcfg_rsp->cfg_bits & Q8_PORT_CFG_BITS_DCBX_ENABLE) ? 1: 0)
4028 *cfg_bits = pcfg_rsp->cfg_bits;
4034 ql_iscsi_pdu(qla_host_t *ha, struct mbuf *mp)
4036 struct ether_vlan_header *eh;
4038 struct ip *ip = NULL;
4039 struct ip6_hdr *ip6 = NULL;
4040 struct tcphdr *th = NULL;
4043 uint8_t buf[sizeof(struct ip6_hdr)];
4045 eh = mtod(mp, struct ether_vlan_header *);
4047 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
4048 hdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
4049 etype = ntohs(eh->evl_proto);
4051 hdrlen = ETHER_HDR_LEN;
4052 etype = ntohs(eh->evl_encap_proto);
4055 if (etype == ETHERTYPE_IP) {
4057 offset = (hdrlen + sizeof (struct ip));
4059 if (mp->m_len >= offset) {
4060 ip = (struct ip *)(mp->m_data + hdrlen);
4062 m_copydata(mp, hdrlen, sizeof (struct ip), buf);
4063 ip = (struct ip *)buf;
4066 if (ip->ip_p == IPPROTO_TCP) {
4068 hdrlen += ip->ip_hl << 2;
4069 offset = hdrlen + 4;
4071 if (mp->m_len >= offset) {
4072 th = (struct tcphdr *)(mp->m_data + hdrlen);;
4074 m_copydata(mp, hdrlen, 4, buf);
4075 th = (struct tcphdr *)buf;
4079 } else if (etype == ETHERTYPE_IPV6) {
4081 offset = (hdrlen + sizeof (struct ip6_hdr));
4083 if (mp->m_len >= offset) {
4084 ip6 = (struct ip6_hdr *)(mp->m_data + hdrlen);
4086 m_copydata(mp, hdrlen, sizeof (struct ip6_hdr), buf);
4087 ip6 = (struct ip6_hdr *)buf;
4090 if (ip6->ip6_nxt == IPPROTO_TCP) {
4092 hdrlen += sizeof(struct ip6_hdr);
4093 offset = hdrlen + 4;
4095 if (mp->m_len >= offset) {
4096 th = (struct tcphdr *)(mp->m_data + hdrlen);;
4098 m_copydata(mp, hdrlen, 4, buf);
4099 th = (struct tcphdr *)buf;
4105 if ((th->th_sport == htons(3260)) ||
4106 (th->th_dport == htons(3260)))
4113 qla_hw_async_event(qla_host_t *ha)
4115 switch (ha->hw.aen_mb0) {
4117 (void)qla_idc_ack(ha, ha->hw.aen_mb1, ha->hw.aen_mb2,
4118 ha->hw.aen_mb3, ha->hw.aen_mb4);
4129 #ifdef QL_LDFLASH_FW
4131 ql_get_minidump_template(qla_host_t *ha)
4134 device_t dev = ha->pci_dev;
4135 q80_config_md_templ_cmd_t *md_templ;
4136 q80_config_md_templ_cmd_rsp_t *md_templ_rsp;
4138 md_templ = (q80_config_md_templ_cmd_t *) ha->hw.mbox;
4139 bzero(md_templ, (sizeof (q80_config_md_templ_cmd_t)));
4141 md_templ->opcode = Q8_MBX_GET_MINIDUMP_TMPLT;
4142 md_templ->count_version = ( sizeof(q80_config_md_templ_cmd_t) >> 2);
4143 md_templ->count_version |= Q8_MBX_CMD_VERSION;
4145 md_templ->buf_addr = ha->hw.dma_buf.minidump.dma_addr;
4146 md_templ->buff_size = ha->hw.dma_buf.minidump.size;
4148 if (qla_mbx_cmd(ha, (uint32_t *) md_templ,
4149 (sizeof(q80_config_md_templ_cmd_t) >> 2),
4151 (sizeof(q80_config_md_templ_cmd_rsp_t) >> 2), 0)) {
4153 device_printf(dev, "%s: failed\n", __func__);
4158 md_templ_rsp = (q80_config_md_templ_cmd_rsp_t *) ha->hw.mbox;
4160 err = Q8_MBX_RSP_STATUS(md_templ_rsp->regcnt_status);
4163 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err);
4170 #endif /* #ifdef QL_LDFLASH_FW */
4173 * Minidump related functionality
4176 static int ql_parse_template(qla_host_t *ha);
4178 static uint32_t ql_rdcrb(qla_host_t *ha,
4179 ql_minidump_entry_rdcrb_t *crb_entry,
4180 uint32_t * data_buff);
4182 static uint32_t ql_pollrd(qla_host_t *ha,
4183 ql_minidump_entry_pollrd_t *entry,
4184 uint32_t * data_buff);
4186 static uint32_t ql_pollrd_modify_write(qla_host_t *ha,
4187 ql_minidump_entry_rd_modify_wr_with_poll_t *entry,
4188 uint32_t *data_buff);
4190 static uint32_t ql_L2Cache(qla_host_t *ha,
4191 ql_minidump_entry_cache_t *cacheEntry,
4192 uint32_t * data_buff);
4194 static uint32_t ql_L1Cache(qla_host_t *ha,
4195 ql_minidump_entry_cache_t *cacheEntry,
4196 uint32_t *data_buff);
4198 static uint32_t ql_rdocm(qla_host_t *ha,
4199 ql_minidump_entry_rdocm_t *ocmEntry,
4200 uint32_t *data_buff);
4202 static uint32_t ql_rdmem(qla_host_t *ha,
4203 ql_minidump_entry_rdmem_t *mem_entry,
4204 uint32_t *data_buff);
4206 static uint32_t ql_rdrom(qla_host_t *ha,
4207 ql_minidump_entry_rdrom_t *romEntry,
4208 uint32_t *data_buff);
4210 static uint32_t ql_rdmux(qla_host_t *ha,
4211 ql_minidump_entry_mux_t *muxEntry,
4212 uint32_t *data_buff);
4214 static uint32_t ql_rdmux2(qla_host_t *ha,
4215 ql_minidump_entry_mux2_t *muxEntry,
4216 uint32_t *data_buff);
4218 static uint32_t ql_rdqueue(qla_host_t *ha,
4219 ql_minidump_entry_queue_t *queueEntry,
4220 uint32_t *data_buff);
4222 static uint32_t ql_cntrl(qla_host_t *ha,
4223 ql_minidump_template_hdr_t *template_hdr,
4224 ql_minidump_entry_cntrl_t *crbEntry);
4228 ql_minidump_size(qla_host_t *ha)
4232 ql_minidump_template_hdr_t *hdr;
4234 hdr = (ql_minidump_template_hdr_t *)ha->hw.dma_buf.minidump.dma_b;
4238 for (k = 1; k < QL_DBG_CAP_SIZE_ARRAY_LEN; k++) {
4239 if (i & ha->hw.mdump_capture_mask)
4240 size += hdr->capture_size_array[k];
4247 ql_free_minidump_buffer(qla_host_t *ha)
4249 if (ha->hw.mdump_buffer != NULL) {
4250 free(ha->hw.mdump_buffer, M_QLA83XXBUF);
4251 ha->hw.mdump_buffer = NULL;
4252 ha->hw.mdump_buffer_size = 0;
4258 ql_alloc_minidump_buffer(qla_host_t *ha)
4260 ha->hw.mdump_buffer_size = ql_minidump_size(ha);
4262 if (!ha->hw.mdump_buffer_size)
4265 ha->hw.mdump_buffer = malloc(ha->hw.mdump_buffer_size, M_QLA83XXBUF,
4268 if (ha->hw.mdump_buffer == NULL)
4275 ql_free_minidump_template_buffer(qla_host_t *ha)
4277 if (ha->hw.mdump_template != NULL) {
4278 free(ha->hw.mdump_template, M_QLA83XXBUF);
4279 ha->hw.mdump_template = NULL;
4280 ha->hw.mdump_template_size = 0;
4286 ql_alloc_minidump_template_buffer(qla_host_t *ha)
4288 ha->hw.mdump_template_size = ha->hw.dma_buf.minidump.size;
4290 ha->hw.mdump_template = malloc(ha->hw.mdump_template_size,
4291 M_QLA83XXBUF, M_NOWAIT);
4293 if (ha->hw.mdump_template == NULL)
4300 ql_alloc_minidump_buffers(qla_host_t *ha)
4304 ret = ql_alloc_minidump_template_buffer(ha);
4309 ret = ql_alloc_minidump_buffer(ha);
4312 ql_free_minidump_template_buffer(ha);
4319 ql_validate_minidump_checksum(qla_host_t *ha)
4323 uint32_t *template_buff;
4325 count = ha->hw.dma_buf.minidump.size / sizeof (uint32_t);
4326 template_buff = ha->hw.dma_buf.minidump.dma_b;
4328 while (count-- > 0) {
4329 sum += *template_buff++;
4333 sum = (sum & 0xFFFFFFFF) + (sum >> 32);
4340 ql_minidump_init(qla_host_t *ha)
4343 uint32_t template_size = 0;
4344 device_t dev = ha->pci_dev;
4347 * Get Minidump Template Size
4349 ret = qla_get_minidump_tmplt_size(ha, &template_size);
4351 if (ret || (template_size == 0)) {
4352 device_printf(dev, "%s: failed [%d, %d]\n", __func__, ret,
4358 * Allocate Memory for Minidump Template
4361 ha->hw.dma_buf.minidump.alignment = 8;
4362 ha->hw.dma_buf.minidump.size = template_size;
4364 #ifdef QL_LDFLASH_FW
4365 if (ql_alloc_dmabuf(ha, &ha->hw.dma_buf.minidump)) {
4367 device_printf(dev, "%s: minidump dma alloc failed\n", __func__);
4371 ha->hw.dma_buf.flags.minidump = 1;
4374 * Retrieve Minidump Template
4376 ret = ql_get_minidump_template(ha);
4378 ha->hw.dma_buf.minidump.dma_b = ql83xx_minidump;
4380 #endif /* #ifdef QL_LDFLASH_FW */
4384 ret = ql_validate_minidump_checksum(ha);
4388 ret = ql_alloc_minidump_buffers(ha);
4391 ha->hw.mdump_init = 1;
4394 "%s: ql_alloc_minidump_buffers"
4395 " failed\n", __func__);
4397 device_printf(dev, "%s: ql_validate_minidump_checksum"
4398 " failed\n", __func__);
4401 device_printf(dev, "%s: ql_get_minidump_template failed\n",
4406 ql_minidump_free(ha);
4412 ql_minidump_free(qla_host_t *ha)
4414 ha->hw.mdump_init = 0;
4415 if (ha->hw.dma_buf.flags.minidump) {
4416 ha->hw.dma_buf.flags.minidump = 0;
4417 ql_free_dmabuf(ha, &ha->hw.dma_buf.minidump);
4420 ql_free_minidump_template_buffer(ha);
4421 ql_free_minidump_buffer(ha);
4427 ql_minidump(qla_host_t *ha)
4429 if (!ha->hw.mdump_init)
4432 if (ha->hw.mdump_done)
4435 ha->hw.mdump_start_seq_index = ql_stop_sequence(ha);
4437 bzero(ha->hw.mdump_buffer, ha->hw.mdump_buffer_size);
4438 bzero(ha->hw.mdump_template, ha->hw.mdump_template_size);
4440 bcopy(ha->hw.dma_buf.minidump.dma_b, ha->hw.mdump_template,
4441 ha->hw.mdump_template_size);
4443 ql_parse_template(ha);
4445 ql_start_sequence(ha, ha->hw.mdump_start_seq_index);
4447 ha->hw.mdump_done = 1;
4457 ql_entry_err_chk(ql_minidump_entry_t *entry, uint32_t esize)
4459 if (esize != entry->hdr.entry_capture_size) {
4460 entry->hdr.entry_capture_size = esize;
4461 entry->hdr.driver_flags |= QL_DBG_SIZE_ERR_FLAG;
4468 ql_parse_template(qla_host_t *ha)
4470 uint32_t num_of_entries, buff_level, e_cnt, esize;
4471 uint32_t end_cnt, rv = 0;
4472 char *dump_buff, *dbuff;
4473 int sane_start = 0, sane_end = 0;
4474 ql_minidump_template_hdr_t *template_hdr;
4475 ql_minidump_entry_t *entry;
4476 uint32_t capture_mask;
4479 /* Setup parameters */
4480 template_hdr = (ql_minidump_template_hdr_t *)ha->hw.mdump_template;
4482 if (template_hdr->entry_type == TLHDR)
4485 dump_buff = (char *) ha->hw.mdump_buffer;
4487 num_of_entries = template_hdr->num_of_entries;
4489 entry = (ql_minidump_entry_t *) ((char *)template_hdr
4490 + template_hdr->first_entry_offset );
4492 template_hdr->saved_state_array[QL_OCM0_ADDR_INDX] =
4493 template_hdr->ocm_window_array[ha->pci_func];
4494 template_hdr->saved_state_array[QL_PCIE_FUNC_INDX] = ha->pci_func;
4496 capture_mask = ha->hw.mdump_capture_mask;
4497 dump_size = ha->hw.mdump_buffer_size;
4499 template_hdr->driver_capture_mask = capture_mask;
4501 QL_DPRINT80(ha, (ha->pci_dev,
4502 "%s: sane_start = %d num_of_entries = %d "
4503 "capture_mask = 0x%x dump_size = %d \n",
4504 __func__, sane_start, num_of_entries, capture_mask, dump_size));
4506 for (buff_level = 0, e_cnt = 0; e_cnt < num_of_entries; e_cnt++) {
4509 * If the capture_mask of the entry does not match capture mask
4510 * skip the entry after marking the driver_flags indicator.
4513 if (!(entry->hdr.entry_capture_mask & capture_mask)) {
4515 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG;
4516 entry = (ql_minidump_entry_t *) ((char *) entry
4517 + entry->hdr.entry_size);
4522 * This is ONLY needed in implementations where
4523 * the capture buffer allocated is too small to capture
4524 * all of the required entries for a given capture mask.
4525 * We need to empty the buffer contents to a file
4526 * if possible, before processing the next entry
4527 * If the buff_full_flag is set, no further capture will happen
4528 * and all remaining non-control entries will be skipped.
4530 if (entry->hdr.entry_capture_size != 0) {
4531 if ((buff_level + entry->hdr.entry_capture_size) >
4533 /* Try to recover by emptying buffer to file */
4534 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG;
4535 entry = (ql_minidump_entry_t *) ((char *) entry
4536 + entry->hdr.entry_size);
4542 * Decode the entry type and process it accordingly
4545 switch (entry->hdr.entry_type) {
4550 if (sane_end == 0) {
4557 dbuff = dump_buff + buff_level;
4558 esize = ql_rdcrb(ha, (void *)entry, (void *)dbuff);
4559 ql_entry_err_chk(entry, esize);
4560 buff_level += esize;
4564 dbuff = dump_buff + buff_level;
4565 esize = ql_pollrd(ha, (void *)entry, (void *)dbuff);
4566 ql_entry_err_chk(entry, esize);
4567 buff_level += esize;
4571 dbuff = dump_buff + buff_level;
4572 esize = ql_pollrd_modify_write(ha, (void *)entry,
4574 ql_entry_err_chk(entry, esize);
4575 buff_level += esize;
4582 dbuff = dump_buff + buff_level;
4583 esize = ql_L2Cache(ha, (void *)entry, (void *)dbuff);
4585 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG;
4587 ql_entry_err_chk(entry, esize);
4588 buff_level += esize;
4594 dbuff = dump_buff + buff_level;
4595 esize = ql_L1Cache(ha, (void *)entry, (void *)dbuff);
4596 ql_entry_err_chk(entry, esize);
4597 buff_level += esize;
4601 dbuff = dump_buff + buff_level;
4602 esize = ql_rdocm(ha, (void *)entry, (void *)dbuff);
4603 ql_entry_err_chk(entry, esize);
4604 buff_level += esize;
4608 dbuff = dump_buff + buff_level;
4609 esize = ql_rdmem(ha, (void *)entry, (void *)dbuff);
4610 ql_entry_err_chk(entry, esize);
4611 buff_level += esize;
4616 dbuff = dump_buff + buff_level;
4617 esize = ql_rdrom(ha, (void *)entry, (void *)dbuff);
4618 ql_entry_err_chk(entry, esize);
4619 buff_level += esize;
4623 dbuff = dump_buff + buff_level;
4624 esize = ql_rdmux(ha, (void *)entry, (void *)dbuff);
4625 ql_entry_err_chk(entry, esize);
4626 buff_level += esize;
4630 dbuff = dump_buff + buff_level;
4631 esize = ql_rdmux2(ha, (void *)entry, (void *)dbuff);
4632 ql_entry_err_chk(entry, esize);
4633 buff_level += esize;
4637 dbuff = dump_buff + buff_level;
4638 esize = ql_rdqueue(ha, (void *)entry, (void *)dbuff);
4639 ql_entry_err_chk(entry, esize);
4640 buff_level += esize;
4644 if ((rv = ql_cntrl(ha, template_hdr, (void *)entry))) {
4645 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG;
4649 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG;
4652 /* next entry in the template */
4653 entry = (ql_minidump_entry_t *) ((char *) entry
4654 + entry->hdr.entry_size);
4657 if (!sane_start || (sane_end > 1)) {
4658 device_printf(ha->pci_dev,
4659 "\n%s: Template configuration error. Check Template\n",
4663 QL_DPRINT80(ha, (ha->pci_dev, "%s: Minidump num of entries = %d\n",
4664 __func__, template_hdr->num_of_entries));
4670 * Read CRB operation.
4673 ql_rdcrb(qla_host_t *ha, ql_minidump_entry_rdcrb_t * crb_entry,
4674 uint32_t * data_buff)
4678 uint32_t op_count, addr, stride, value = 0;
4680 addr = crb_entry->addr;
4681 op_count = crb_entry->op_count;
4682 stride = crb_entry->addr_stride;
4684 for (loop_cnt = 0; loop_cnt < op_count; loop_cnt++) {
4686 ret = ql_rdwr_indreg32(ha, addr, &value, 1);
4691 *data_buff++ = addr;
4692 *data_buff++ = value;
4693 addr = addr + stride;
4697 * for testing purpose we return amount of data written
4699 return (op_count * (2 * sizeof(uint32_t)));
4707 ql_L2Cache(qla_host_t *ha, ql_minidump_entry_cache_t *cacheEntry,
4708 uint32_t * data_buff)
4714 uint32_t read_value;
4715 uint32_t addr, read_addr, cntrl_addr, tag_reg_addr, cntl_value_w;
4716 uint32_t tag_value, read_cnt;
4717 volatile uint8_t cntl_value_r;
4721 loop_cnt = cacheEntry->op_count;
4723 read_addr = cacheEntry->read_addr;
4724 cntrl_addr = cacheEntry->control_addr;
4725 cntl_value_w = (uint32_t) cacheEntry->write_value;
4727 tag_reg_addr = cacheEntry->tag_reg_addr;
4729 tag_value = cacheEntry->init_tag_value;
4730 read_cnt = cacheEntry->read_addr_cnt;
4732 for (i = 0; i < loop_cnt; i++) {
4734 ret = ql_rdwr_indreg32(ha, tag_reg_addr, &tag_value, 0);
4738 if (cacheEntry->write_value != 0) {
4740 ret = ql_rdwr_indreg32(ha, cntrl_addr,
4746 if (cacheEntry->poll_mask != 0) {
4748 timeout = cacheEntry->poll_wait;
4750 ret = ql_rdwr_indreg32(ha, cntrl_addr, &data, 1);
4754 cntl_value_r = (uint8_t)data;
4756 while ((cntl_value_r & cacheEntry->poll_mask) != 0) {
4759 qla_mdelay(__func__, 1);
4764 ret = ql_rdwr_indreg32(ha, cntrl_addr,
4769 cntl_value_r = (uint8_t)data;
4772 /* Report timeout error.
4773 * core dump capture failed
4774 * Skip remaining entries.
4775 * Write buffer out to file
4776 * Use driver specific fields in template header
4777 * to report this error.
4784 for (k = 0; k < read_cnt; k++) {
4786 ret = ql_rdwr_indreg32(ha, addr, &read_value, 1);
4790 *data_buff++ = read_value;
4791 addr += cacheEntry->read_addr_stride;
4794 tag_value += cacheEntry->tag_value_stride;
4797 return (read_cnt * loop_cnt * sizeof(uint32_t));
4805 ql_L1Cache(qla_host_t *ha,
4806 ql_minidump_entry_cache_t *cacheEntry,
4807 uint32_t *data_buff)
4813 uint32_t read_value;
4814 uint32_t addr, read_addr, cntrl_addr, tag_reg_addr;
4815 uint32_t tag_value, read_cnt;
4816 uint32_t cntl_value_w;
4818 loop_cnt = cacheEntry->op_count;
4820 read_addr = cacheEntry->read_addr;
4821 cntrl_addr = cacheEntry->control_addr;
4822 cntl_value_w = (uint32_t) cacheEntry->write_value;
4824 tag_reg_addr = cacheEntry->tag_reg_addr;
4826 tag_value = cacheEntry->init_tag_value;
4827 read_cnt = cacheEntry->read_addr_cnt;
4829 for (i = 0; i < loop_cnt; i++) {
4831 ret = ql_rdwr_indreg32(ha, tag_reg_addr, &tag_value, 0);
4835 ret = ql_rdwr_indreg32(ha, cntrl_addr, &cntl_value_w, 0);
4840 for (k = 0; k < read_cnt; k++) {
4842 ret = ql_rdwr_indreg32(ha, addr, &read_value, 1);
4846 *data_buff++ = read_value;
4847 addr += cacheEntry->read_addr_stride;
4850 tag_value += cacheEntry->tag_value_stride;
4853 return (read_cnt * loop_cnt * sizeof(uint32_t));
4857 * Reading OCM memory
4861 ql_rdocm(qla_host_t *ha,
4862 ql_minidump_entry_rdocm_t *ocmEntry,
4863 uint32_t *data_buff)
4866 volatile uint32_t addr;
4867 volatile uint32_t value;
4869 addr = ocmEntry->read_addr;
4870 loop_cnt = ocmEntry->op_count;
4872 for (i = 0; i < loop_cnt; i++) {
4873 value = READ_REG32(ha, addr);
4874 *data_buff++ = value;
4875 addr += ocmEntry->read_addr_stride;
4877 return (loop_cnt * sizeof(value));
4885 ql_rdmem(qla_host_t *ha,
4886 ql_minidump_entry_rdmem_t *mem_entry,
4887 uint32_t *data_buff)
4891 volatile uint32_t addr;
4892 q80_offchip_mem_val_t val;
4894 addr = mem_entry->read_addr;
4896 /* size in bytes / 16 */
4897 loop_cnt = mem_entry->read_data_size / (sizeof(uint32_t) * 4);
4899 for (i = 0; i < loop_cnt; i++) {
4901 ret = ql_rdwr_offchip_mem(ha, (addr & 0x0ffffffff), &val, 1);
4905 *data_buff++ = val.data_lo;
4906 *data_buff++ = val.data_hi;
4907 *data_buff++ = val.data_ulo;
4908 *data_buff++ = val.data_uhi;
4910 addr += (sizeof(uint32_t) * 4);
4913 return (loop_cnt * (sizeof(uint32_t) * 4));
4921 ql_rdrom(qla_host_t *ha,
4922 ql_minidump_entry_rdrom_t *romEntry,
4923 uint32_t *data_buff)
4930 addr = romEntry->read_addr;
4931 loop_cnt = romEntry->read_data_size; /* This is size in bytes */
4932 loop_cnt /= sizeof(value);
4934 for (i = 0; i < loop_cnt; i++) {
4936 ret = ql_rd_flash32(ha, addr, &value);
4940 *data_buff++ = value;
4941 addr += sizeof(value);
4944 return (loop_cnt * sizeof(value));
4952 ql_rdmux(qla_host_t *ha,
4953 ql_minidump_entry_mux_t *muxEntry,
4954 uint32_t *data_buff)
4958 uint32_t read_value, sel_value;
4959 uint32_t read_addr, select_addr;
4961 select_addr = muxEntry->select_addr;
4962 sel_value = muxEntry->select_value;
4963 read_addr = muxEntry->read_addr;
4965 for (loop_cnt = 0; loop_cnt < muxEntry->op_count; loop_cnt++) {
4967 ret = ql_rdwr_indreg32(ha, select_addr, &sel_value, 0);
4971 ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1);
4975 *data_buff++ = sel_value;
4976 *data_buff++ = read_value;
4978 sel_value += muxEntry->select_value_stride;
4981 return (loop_cnt * (2 * sizeof(uint32_t)));
4985 ql_rdmux2(qla_host_t *ha,
4986 ql_minidump_entry_mux2_t *muxEntry,
4987 uint32_t *data_buff)
4992 uint32_t select_addr_1, select_addr_2;
4993 uint32_t select_value_1, select_value_2;
4994 uint32_t select_value_count, select_value_mask;
4995 uint32_t read_addr, read_value;
4997 select_addr_1 = muxEntry->select_addr_1;
4998 select_addr_2 = muxEntry->select_addr_2;
4999 select_value_1 = muxEntry->select_value_1;
5000 select_value_2 = muxEntry->select_value_2;
5001 select_value_count = muxEntry->select_value_count;
5002 select_value_mask = muxEntry->select_value_mask;
5004 read_addr = muxEntry->read_addr;
5006 for (loop_cnt = 0; loop_cnt < muxEntry->select_value_count;
5009 uint32_t temp_sel_val;
5011 ret = ql_rdwr_indreg32(ha, select_addr_1, &select_value_1, 0);
5015 temp_sel_val = select_value_1 & select_value_mask;
5017 ret = ql_rdwr_indreg32(ha, select_addr_2, &temp_sel_val, 0);
5021 ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1);
5025 *data_buff++ = temp_sel_val;
5026 *data_buff++ = read_value;
5028 ret = ql_rdwr_indreg32(ha, select_addr_1, &select_value_2, 0);
5032 temp_sel_val = select_value_2 & select_value_mask;
5034 ret = ql_rdwr_indreg32(ha, select_addr_2, &temp_sel_val, 0);
5038 ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1);
5042 *data_buff++ = temp_sel_val;
5043 *data_buff++ = read_value;
5045 select_value_1 += muxEntry->select_value_stride;
5046 select_value_2 += muxEntry->select_value_stride;
5049 return (loop_cnt * (4 * sizeof(uint32_t)));
5053 * Handling Queue State Reads.
5057 ql_rdqueue(qla_host_t *ha,
5058 ql_minidump_entry_queue_t *queueEntry,
5059 uint32_t *data_buff)
5063 uint32_t read_value;
5064 uint32_t read_addr, read_stride, select_addr;
5065 uint32_t queue_id, read_cnt;
5067 read_cnt = queueEntry->read_addr_cnt;
5068 read_stride = queueEntry->read_addr_stride;
5069 select_addr = queueEntry->select_addr;
5071 for (loop_cnt = 0, queue_id = 0; loop_cnt < queueEntry->op_count;
5074 ret = ql_rdwr_indreg32(ha, select_addr, &queue_id, 0);
5078 read_addr = queueEntry->read_addr;
5080 for (k = 0; k < read_cnt; k++) {
5082 ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1);
5086 *data_buff++ = read_value;
5087 read_addr += read_stride;
5090 queue_id += queueEntry->queue_id_stride;
5093 return (loop_cnt * (read_cnt * sizeof(uint32_t)));
5097 * Handling control entries.
5101 ql_cntrl(qla_host_t *ha,
5102 ql_minidump_template_hdr_t *template_hdr,
5103 ql_minidump_entry_cntrl_t *crbEntry)
5107 uint32_t opcode, read_value, addr, entry_addr;
5110 entry_addr = crbEntry->addr;
5112 for (count = 0; count < crbEntry->op_count; count++) {
5113 opcode = crbEntry->opcode;
5115 if (opcode & QL_DBG_OPCODE_WR) {
5117 ret = ql_rdwr_indreg32(ha, entry_addr,
5118 &crbEntry->value_1, 0);
5122 opcode &= ~QL_DBG_OPCODE_WR;
5125 if (opcode & QL_DBG_OPCODE_RW) {
5127 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 1);
5131 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 0);
5135 opcode &= ~QL_DBG_OPCODE_RW;
5138 if (opcode & QL_DBG_OPCODE_AND) {
5140 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 1);
5144 read_value &= crbEntry->value_2;
5145 opcode &= ~QL_DBG_OPCODE_AND;
5147 if (opcode & QL_DBG_OPCODE_OR) {
5148 read_value |= crbEntry->value_3;
5149 opcode &= ~QL_DBG_OPCODE_OR;
5152 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 0);
5157 if (opcode & QL_DBG_OPCODE_OR) {
5159 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 1);
5163 read_value |= crbEntry->value_3;
5165 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 0);
5169 opcode &= ~QL_DBG_OPCODE_OR;
5172 if (opcode & QL_DBG_OPCODE_POLL) {
5174 opcode &= ~QL_DBG_OPCODE_POLL;
5175 timeout = crbEntry->poll_timeout;
5178 ret = ql_rdwr_indreg32(ha, addr, &read_value, 1);
5182 while ((read_value & crbEntry->value_2)
5183 != crbEntry->value_1) {
5186 qla_mdelay(__func__, 1);
5191 ret = ql_rdwr_indreg32(ha, addr,
5199 * Report timeout error.
5200 * core dump capture failed
5201 * Skip remaining entries.
5202 * Write buffer out to file
5203 * Use driver specific fields in template header
5204 * to report this error.
5210 if (opcode & QL_DBG_OPCODE_RDSTATE) {
5212 * decide which address to use.
5214 if (crbEntry->state_index_a) {
5215 addr = template_hdr->saved_state_array[
5216 crbEntry-> state_index_a];
5221 ret = ql_rdwr_indreg32(ha, addr, &read_value, 1);
5225 template_hdr->saved_state_array[crbEntry->state_index_v]
5227 opcode &= ~QL_DBG_OPCODE_RDSTATE;
5230 if (opcode & QL_DBG_OPCODE_WRSTATE) {
5232 * decide which value to use.
5234 if (crbEntry->state_index_v) {
5235 read_value = template_hdr->saved_state_array[
5236 crbEntry->state_index_v];
5238 read_value = crbEntry->value_1;
5241 * decide which address to use.
5243 if (crbEntry->state_index_a) {
5244 addr = template_hdr->saved_state_array[
5245 crbEntry-> state_index_a];
5250 ret = ql_rdwr_indreg32(ha, addr, &read_value, 0);
5254 opcode &= ~QL_DBG_OPCODE_WRSTATE;
5257 if (opcode & QL_DBG_OPCODE_MDSTATE) {
5258 /* Read value from saved state using index */
5259 read_value = template_hdr->saved_state_array[
5260 crbEntry->state_index_v];
5262 read_value <<= crbEntry->shl; /*Shift left operation */
5263 read_value >>= crbEntry->shr; /*Shift right operation */
5265 if (crbEntry->value_2) {
5266 /* check if AND mask is provided */
5267 read_value &= crbEntry->value_2;
5270 read_value |= crbEntry->value_3; /* OR operation */
5271 read_value += crbEntry->value_1; /* increment op */
5273 /* Write value back to state area. */
5275 template_hdr->saved_state_array[crbEntry->state_index_v]
5277 opcode &= ~QL_DBG_OPCODE_MDSTATE;
5280 entry_addr += crbEntry->addr_stride;
5287 * Handling rd poll entry.
5291 ql_pollrd(qla_host_t *ha, ql_minidump_entry_pollrd_t *entry,
5292 uint32_t *data_buff)
5296 uint32_t op_count, select_addr, select_value_stride, select_value;
5297 uint32_t read_addr, poll, mask, data_size, data;
5298 uint32_t wait_count = 0;
5300 select_addr = entry->select_addr;
5301 read_addr = entry->read_addr;
5302 select_value = entry->select_value;
5303 select_value_stride = entry->select_value_stride;
5304 op_count = entry->op_count;
5307 data_size = entry->data_size;
5309 for (loop_cnt = 0; loop_cnt < op_count; loop_cnt++) {
5311 ret = ql_rdwr_indreg32(ha, select_addr, &select_value, 0);
5317 while (wait_count < poll) {
5321 ret = ql_rdwr_indreg32(ha, select_addr, &temp, 1);
5325 if ( (temp & mask) != 0 ) {
5331 if (wait_count == poll) {
5332 device_printf(ha->pci_dev,
5333 "%s: Error in processing entry\n", __func__);
5334 device_printf(ha->pci_dev,
5335 "%s: wait_count <0x%x> poll <0x%x>\n",
5336 __func__, wait_count, poll);
5340 ret = ql_rdwr_indreg32(ha, read_addr, &data, 1);
5344 *data_buff++ = select_value;
5345 *data_buff++ = data;
5346 select_value = select_value + select_value_stride;
5350 * for testing purpose we return amount of data written
5352 return (loop_cnt * (2 * sizeof(uint32_t)));
5357 * Handling rd modify write poll entry.
5361 ql_pollrd_modify_write(qla_host_t *ha,
5362 ql_minidump_entry_rd_modify_wr_with_poll_t *entry,
5363 uint32_t *data_buff)
5366 uint32_t addr_1, addr_2, value_1, value_2, data;
5367 uint32_t poll, mask, data_size, modify_mask;
5368 uint32_t wait_count = 0;
5370 addr_1 = entry->addr_1;
5371 addr_2 = entry->addr_2;
5372 value_1 = entry->value_1;
5373 value_2 = entry->value_2;
5377 modify_mask = entry->modify_mask;
5378 data_size = entry->data_size;
5381 ret = ql_rdwr_indreg32(ha, addr_1, &value_1, 0);
5386 while (wait_count < poll) {
5390 ret = ql_rdwr_indreg32(ha, addr_1, &temp, 1);
5394 if ( (temp & mask) != 0 ) {
5400 if (wait_count == poll) {
5401 device_printf(ha->pci_dev, "%s Error in processing entry\n",
5405 ret = ql_rdwr_indreg32(ha, addr_2, &data, 1);
5409 data = (data & modify_mask);
5411 ret = ql_rdwr_indreg32(ha, addr_2, &data, 0);
5415 ret = ql_rdwr_indreg32(ha, addr_1, &value_2, 0);
5421 while (wait_count < poll) {
5425 ret = ql_rdwr_indreg32(ha, addr_1, &temp, 1);
5429 if ( (temp & mask) != 0 ) {
5434 *data_buff++ = addr_2;
5435 *data_buff++ = data;
5439 * for testing purpose we return amount of data written
5441 return (2 * sizeof(uint32_t));