2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013-2016 Qlogic Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
33 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
39 * PCIe Registers; Direct Mapped; Offsets from BAR0
43 * Register offsets for QLE8030
47 * Firmware Mailbox Registers
48 * 0 thru 511; offsets 0x800 thru 0xFFC; 32bits each
50 #define Q8_FW_MBOX0 0x00000800
51 #define Q8_FW_MBOX511 0x00000FFC
54 * Host Mailbox Registers
55 * 0 thru 511; offsets 0x000 thru 0x7FC; 32bits each
57 #define Q8_HOST_MBOX0 0x00000000
58 #define Q8_HOST_MBOX511 0x000007FC
60 #define Q8_MBOX_INT_ENABLE 0x00001000
61 #define Q8_MBOX_INT_MASK_MSIX 0x00001200
62 #define Q8_MBOX_INT_LEGACY 0x00003010
64 #define Q8_HOST_MBOX_CNTRL 0x00003038
65 #define Q8_FW_MBOX_CNTRL 0x0000303C
67 #define Q8_PEG_HALT_STATUS1 0x000034A8
68 #define Q8_PEG_HALT_STATUS2 0x000034AC
69 #define Q8_FIRMWARE_HEARTBEAT 0x000034B0
71 #define Q8_FLASH_LOCK_ID 0x00003500
72 #define Q8_DRIVER_LOCK_ID 0x00003504
73 #define Q8_FW_CAPABILITIES 0x00003528
75 #define Q8_FW_VER_MAJOR 0x00003550
76 #define Q8_FW_VER_MINOR 0x00003554
77 #define Q8_FW_VER_SUB 0x00003558
79 #define Q8_BOOTLD_ADDR 0x0000355C
80 #define Q8_BOOTLD_SIZE 0x00003560
82 #define Q8_FW_IMAGE_ADDR 0x00003564
83 #define Q8_FW_BUILD_NUMBER 0x00003568
84 #define Q8_FW_IMAGE_VALID 0x000035FC
86 #define Q8_CMDPEG_STATE 0x00003650
88 #define Q8_LINK_STATE 0x00003698
89 #define Q8_LINK_STATE_2 0x0000369C
91 #define Q8_LINK_SPEED_0 0x000036E0
92 #define Q8_LINK_SPEED_1 0x000036E4
93 #define Q8_LINK_SPEED_2 0x000036E8
94 #define Q8_LINK_SPEED_3 0x000036EC
96 #define Q8_MAX_LINK_SPEED_0 0x000036F0
97 #define Q8_MAX_LINK_SPEED_1 0x000036F4
98 #define Q8_MAX_LINK_SPEED_2 0x000036F8
99 #define Q8_MAX_LINK_SPEED_3 0x000036FC
101 #define Q8_ASIC_TEMPERATURE 0x000037B4
104 * CRB Window Registers
105 * 0 thru 15; offsets 0x3800 thru 0x383C; 32bits each
107 #define Q8_CRB_WINDOW_PF0 0x00003800
108 #define Q8_CRB_WINDOW_PF15 0x0000383C
110 #define Q8_FLASH_LOCK 0x00003850
111 #define Q8_FLASH_UNLOCK 0x00003854
113 #define Q8_DRIVER_LOCK 0x00003868
114 #define Q8_DRIVER_UNLOCK 0x0000386C
116 #define Q8_LEGACY_INT_PTR 0x000038C0
117 #define Q8_LEGACY_INT_TRIG 0x000038C4
118 #define Q8_LEGACY_INT_MASK 0x000038C8
120 #define Q8_WILD_CARD 0x000038F0
121 #define Q8_INFORMANT 0x000038FC
124 * Ethernet Interface Specific Registers
126 #define Q8_DRIVER_OP_MODE 0x00003570
127 #define Q8_API_VERSION 0x0000356C
128 #define Q8_NPAR_STATE 0x0000359C
131 * End of PCIe Registers; Direct Mapped; Offsets from BAR0
137 #define Q8_LED_DUAL_0 0x28084C80
138 #define Q8_LED_SINGLE_0 0x28084C90
140 #define Q8_LED_DUAL_1 0x28084CA0
141 #define Q8_LED_SINGLE_1 0x28084CB0
143 #define Q8_LED_DUAL_2 0x28084CC0
144 #define Q8_LED_SINGLE_2 0x28084CD0
146 #define Q8_LED_DUAL_3 0x28084CE0
147 #define Q8_LED_SINGLE_3 0x28084CF0
149 #define Q8_GPIO_1 0x28084D00
150 #define Q8_GPIO_2 0x28084D10
151 #define Q8_GPIO_3 0x28084D20
152 #define Q8_GPIO_4 0x28084D40
153 #define Q8_GPIO_5 0x28084D50
154 #define Q8_GPIO_6 0x28084D60
155 #define Q8_GPIO_7 0x42100060
156 #define Q8_GPIO_8 0x42100064
158 #define Q8_FLASH_SPI_STATUS 0x2808E010
159 #define Q8_FLASH_SPI_CONTROL 0x2808E014
161 #define Q8_FLASH_STATUS 0x42100004
162 #define Q8_FLASH_CONTROL 0x42110004
163 #define Q8_FLASH_ADDRESS 0x42110008
164 #define Q8_FLASH_WR_DATA 0x4211000C
165 #define Q8_FLASH_RD_DATA 0x42110018
167 #define Q8_FLASH_DIRECT_WINDOW 0x42110030
168 #define Q8_FLASH_DIRECT_DATA 0x42150000
170 #define Q8_MS_CNTRL 0x41000090
172 #define Q8_MS_ADDR_LO 0x41000094
173 #define Q8_MS_ADDR_HI 0x41000098
175 #define Q8_MS_WR_DATA_0_31 0x410000A0
176 #define Q8_MS_WR_DATA_32_63 0x410000A4
177 #define Q8_MS_WR_DATA_64_95 0x410000B0
178 #define Q8_MS_WR_DATA_96_127 0x410000B4
180 #define Q8_MS_RD_DATA_0_31 0x410000A8
181 #define Q8_MS_RD_DATA_32_63 0x410000AC
182 #define Q8_MS_RD_DATA_64_95 0x410000B8
183 #define Q8_MS_RD_DATA_96_127 0x410000BC
185 #define Q8_CRB_PEG_0 0x3400003c
186 #define Q8_CRB_PEG_1 0x3410003c
187 #define Q8_CRB_PEG_2 0x3420003c
188 #define Q8_CRB_PEG_3 0x3430003c
189 #define Q8_CRB_PEG_4 0x34B0003c
192 * Macros for reading and writing registers
195 #if defined(__i386__) || defined(__amd64__)
196 #define Q8_MB() __asm volatile("mfence" ::: "memory")
197 #define Q8_WMB() __asm volatile("sfence" ::: "memory")
198 #define Q8_RMB() __asm volatile("lfence" ::: "memory")
205 #define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg)
207 #define WRITE_REG32(ha, reg, val) \
209 bus_write_4((ha->pci_reg), reg, val);\
210 bus_read_4((ha->pci_reg), reg);\
213 #define Q8_NUM_MBOX 512
215 #define Q8_MAX_NUM_MULTICAST_ADDRS 1022
216 #define Q8_MAC_ADDR_LEN 6
223 * Command Response Interface - Commands
226 #define Q8_MBX_CONFIG_IP_ADDRESS 0x0001
227 #define Q8_MBX_CONFIG_INTR 0x0002
228 #define Q8_MBX_MAP_INTR_SRC 0x0003
229 #define Q8_MBX_MAP_SDS_TO_RDS 0x0006
230 #define Q8_MBX_CREATE_RX_CNTXT 0x0007
231 #define Q8_MBX_DESTROY_RX_CNTXT 0x0008
232 #define Q8_MBX_CREATE_TX_CNTXT 0x0009
233 #define Q8_MBX_DESTROY_TX_CNTXT 0x000A
234 #define Q8_MBX_ADD_RX_RINGS 0x000B
235 #define Q8_MBX_CONFIG_LRO_FLOW 0x000C
236 #define Q8_MBX_CONFIG_MAC_LEARNING 0x000D
237 #define Q8_MBX_GET_STATS 0x000F
238 #define Q8_MBX_GENERATE_INTR 0x0011
239 #define Q8_MBX_SET_MAX_MTU 0x0012
240 #define Q8_MBX_MAC_ADDR_CNTRL 0x001F
241 #define Q8_MBX_GET_PCI_CONFIG 0x0020
242 #define Q8_MBX_GET_NIC_PARTITION 0x0021
243 #define Q8_MBX_SET_NIC_PARTITION 0x0022
244 #define Q8_MBX_QUERY_WOL_CAP 0x002C
245 #define Q8_MBX_SET_WOL_CONFIG 0x002D
246 #define Q8_MBX_GET_MINIDUMP_TMPLT_SIZE 0x002F
247 #define Q8_MBX_GET_MINIDUMP_TMPLT 0x0030
248 #define Q8_MBX_GET_FW_DCBX_CAPS 0x0034
249 #define Q8_MBX_QUERY_DCBX_SETTINGS 0x0035
250 #define Q8_MBX_CONFIG_RSS 0x0041
251 #define Q8_MBX_CONFIG_RSS_TABLE 0x0042
252 #define Q8_MBX_CONFIG_INTR_COALESCE 0x0043
253 #define Q8_MBX_CONFIG_LED 0x0044
254 #define Q8_MBX_CONFIG_MAC_ADDR 0x0045
255 #define Q8_MBX_CONFIG_STATISTICS 0x0046
256 #define Q8_MBX_CONFIG_LOOPBACK 0x0047
257 #define Q8_MBX_LINK_EVENT_REQ 0x0048
258 #define Q8_MBX_CONFIG_MAC_RX_MODE 0x0049
259 #define Q8_MBX_CONFIG_FW_LRO 0x004A
260 #define Q8_MBX_HW_CONFIG 0x004C
261 #define Q8_MBX_INIT_NIC_FUNC 0x0060
262 #define Q8_MBX_STOP_NIC_FUNC 0x0061
263 #define Q8_MBX_IDC_REQ 0x0062
264 #define Q8_MBX_IDC_ACK 0x0063
265 #define Q8_MBX_SET_PORT_CONFIG 0x0066
266 #define Q8_MBX_GET_PORT_CONFIG 0x0067
267 #define Q8_MBX_GET_LINK_STATUS 0x0068
272 * Mailbox Command Response
274 #define Q8_MBX_RSP_SUCCESS 0x0001
275 #define Q8_MBX_RSP_RESPONSE_FAILURE 0x0002
276 #define Q8_MBX_RSP_NO_CARD_CRB 0x0003
277 #define Q8_MBX_RSP_NO_CARD_MEM 0x0004
278 #define Q8_MBX_RSP_NO_CARD_RSRC 0x0005
279 #define Q8_MBX_RSP_INVALID_ARGS 0x0006
280 #define Q8_MBX_RSP_INVALID_ACTION 0x0007
281 #define Q8_MBX_RSP_INVALID_STATE 0x0008
282 #define Q8_MBX_RSP_NOT_SUPPORTED 0x0009
283 #define Q8_MBX_RSP_NOT_PERMITTED 0x000A
284 #define Q8_MBX_RSP_NOT_READY 0x000B
285 #define Q8_MBX_RSP_DOES_NOT_EXIST 0x000C
286 #define Q8_MBX_RSP_ALREADY_EXISTS 0x000D
287 #define Q8_MBX_RSP_BAD_SIGNATURE 0x000E
288 #define Q8_MBX_RSP_CMD_NOT_IMPLEMENTED 0x000F
289 #define Q8_MBX_RSP_CMD_INVALID 0x0010
290 #define Q8_MBX_RSP_TIMEOUT 0x0011
291 #define Q8_MBX_RSP_CMD_FAILED 0x0012
292 #define Q8_MBX_RSP_FATAL_TEMP 0x0013
293 #define Q8_MBX_RSP_MAX_EXCEEDED 0x0014
294 #define Q8_MBX_RSP_UNSPECIFIED 0x0015
295 #define Q8_MBX_RSP_INTR_CREATE_FAILED 0x0017
296 #define Q8_MBX_RSP_INTR_DELETE_FAILED 0x0018
297 #define Q8_MBX_RSP_INTR_INVALID_OP 0x0019
298 #define Q8_MBX_RSP_IDC_INTRMD_RSP 0x001A
300 #define Q8_MBX_CMD_VERSION (0x2 << 13)
301 #define Q8_MBX_RSP_STATUS(x) (((!(x >> 9)) || ((x >> 9) == 1)) ? 0: (x >> 9))
303 * Configure IP Address
305 typedef struct _q80_config_ip_addr {
307 uint16_t count_version;
310 #define Q8_MBX_CONFIG_IP_ADD_IP 0x1
311 #define Q8_MBX_CONFIG_IP_DEL_IP 0x2
314 #define Q8_MBX_CONFIG_IP_V4 0x0
315 #define Q8_MBX_CONFIG_IP_V6 0x1
323 uint8_t ipv6_addr[16];
325 } __packed q80_config_ip_addr_t;
327 typedef struct _q80_config_ip_addr_rsp {
329 uint16_t regcnt_status;
330 } __packed q80_config_ip_addr_rsp_t;
333 * Configure Interrupt Command
335 typedef struct _q80_intr {
337 #define Q8_MBX_CONFIG_INTR_CREATE 0x1
338 #define Q8_MBX_CONFIG_INTR_DELETE 0x2
339 #define Q8_MBX_CONFIG_INTR_TYPE_LINE (0x1 << 4)
340 #define Q8_MBX_CONFIG_INTR_TYPE_MSI_X (0x3 << 4)
344 } __packed q80_intr_t;
346 #define Q8_MAX_INTR_VECTORS 16
347 typedef struct _q80_config_intr {
349 uint16_t count_version;
352 q80_intr_t intr[Q8_MAX_INTR_VECTORS];
353 } __packed q80_config_intr_t;
355 typedef struct _q80_intr_rsp {
362 typedef struct _q80_config_intr_rsp {
364 uint16_t regcnt_status;
367 q80_intr_rsp_t intr[Q8_MAX_INTR_VECTORS];
368 } __packed q80_config_intr_rsp_t;
371 * Configure LRO Flow Command
373 typedef struct _q80_config_lro_flow {
375 uint16_t count_version;
378 #define Q8_MBX_CONFIG_LRO_FLOW_ADD 0x01
379 #define Q8_MBX_CONFIG_LRO_FLOW_DELETE 0x02
382 #define Q8_MBX_CONFIG_LRO_FLOW_IPV4 0x00
383 #define Q8_MBX_CONFIG_LRO_FLOW_IPV6 0x01
384 #define Q8_MBX_CONFIG_LRO_FLOW_TS_ABSENT 0x00
385 #define Q8_MBX_CONFIG_LRO_FLOW_TS_PRESENT 0x02
393 uint8_t ipv6_addr[16];
400 uint8_t ipv6_addr[16];
404 } __packed q80_config_lro_flow_t;
406 typedef struct _q80_config_lro_flow_rsp {
408 uint16_t regcnt_status;
409 } __packed q80_config_lro_flow_rsp_t;
411 typedef struct _q80_set_max_mtu {
413 uint16_t count_version;
416 } __packed q80_set_max_mtu_t;
418 typedef struct _q80_set_max_mtu_rsp {
420 uint16_t regcnt_status;
421 } __packed q80_set_max_mtu_rsp_t;
426 typedef struct _q80_config_rss {
428 uint16_t count_version;
434 #define Q8_MBX_RSS_HASH_TYPE_IPV4_IP (0x1 << 4)
435 #define Q8_MBX_RSS_HASH_TYPE_IPV4_TCP (0x2 << 4)
436 #define Q8_MBX_RSS_HASH_TYPE_IPV4_TCP_IP (0x3 << 4)
437 #define Q8_MBX_RSS_HASH_TYPE_IPV6_IP (0x1 << 6)
438 #define Q8_MBX_RSS_HASH_TYPE_IPV6_TCP (0x2 << 6)
439 #define Q8_MBX_RSS_HASH_TYPE_IPV6_TCP_IP (0x3 << 6)
442 #define Q8_MBX_RSS_FLAGS_ENABLE_RSS (0x1)
443 #define Q8_MBX_RSS_FLAGS_USE_IND_TABLE (0x2)
444 #define Q8_MBX_RSS_FLAGS_TYPE_CRSS (0x4)
446 uint16_t indtbl_mask;
447 #define Q8_MBX_RSS_INDTBL_MASK 0x7F
448 #define Q8_MBX_RSS_FLAGS_MULTI_RSS_VALID 0x8000
451 #define Q8_MBX_RSS_MULTI_RSS_ENGINE_ASSIGN BIT_30
452 #define Q8_MBX_RSS_USE_MULTI_RSS_ENGINES BIT_31
455 } __packed q80_config_rss_t;
457 typedef struct _q80_config_rss_rsp {
459 uint16_t regcnt_status;
460 } __packed q80_config_rss_rsp_t;
463 * Configure RSS Indirection Table
465 #define Q8_RSS_IND_TBL_SIZE 40
466 #define Q8_RSS_IND_TBL_MIN_IDX 0
467 #define Q8_RSS_IND_TBL_MAX_IDX 127
469 typedef struct _q80_config_rss_ind_table {
471 uint16_t count_version;
475 uint8_t ind_table[Q8_RSS_IND_TBL_SIZE];
476 } __packed q80_config_rss_ind_table_t;
478 typedef struct _q80_config_rss_ind_table_rsp {
480 uint16_t regcnt_status;
481 } __packed q80_config_rss_ind_table_rsp_t;
484 * Configure Interrupt Coalescing and Generation
486 typedef struct _q80_config_intr_coalesc {
488 uint16_t count_version;
490 #define Q8_MBX_INTRC_FLAGS_RCV 1
491 #define Q8_MBX_INTRC_FLAGS_XMT 2
492 #define Q8_MBX_INTRC_FLAGS_PERIODIC (1 << 3)
498 #define Q8_MBX_INTRC_TIMER_NONE 0
499 #define Q8_MBX_INTRC_TIMER_SINGLE 1
500 #define Q8_MBX_INTRC_TIMER_PERIODIC 2
502 uint16_t sds_ring_mask;
506 } __packed q80_config_intr_coalesc_t;
508 typedef struct _q80_config_intr_coalesc_rsp {
510 uint16_t regcnt_status;
511 } __packed q80_config_intr_coalesc_rsp_t;
514 * Configure MAC Address
516 #define Q8_ETHER_ADDR_LEN 6
517 typedef struct _q80_mac_addr {
518 uint8_t addr[Q8_ETHER_ADDR_LEN];
520 } __packed q80_mac_addr_t;
522 #define Q8_MAX_MAC_ADDRS 64
524 typedef struct _q80_config_mac_addr {
526 uint16_t count_version;
528 #define Q8_MBX_CMAC_CMD_ADD_MAC_ADDR 1
529 #define Q8_MBX_CMAC_CMD_DEL_MAC_ADDR 2
531 #define Q8_MBX_CMAC_CMD_CAM_BOTH (0x0 << 6)
532 #define Q8_MBX_CMAC_CMD_CAM_INGRESS (0x1 << 6)
533 #define Q8_MBX_CMAC_CMD_CAM_EGRESS (0x2 << 6)
535 uint8_t nmac_entries;
537 q80_mac_addr_t mac_addr[Q8_MAX_MAC_ADDRS];
538 } __packed q80_config_mac_addr_t;
540 typedef struct _q80_config_mac_addr_rsp {
542 uint16_t regcnt_status;
544 uint8_t nmac_entries;
546 uint32_t status[Q8_MAX_MAC_ADDRS];
547 } __packed q80_config_mac_addr_rsp_t;
550 * Configure MAC Receive Mode
552 typedef struct _q80_config_mac_rcv_mode {
554 uint16_t count_version;
557 #define Q8_MBX_MAC_RCV_PROMISC_ENABLE 0x1
558 #define Q8_MBX_MAC_ALL_MULTI_ENABLE 0x2
562 } __packed q80_config_mac_rcv_mode_t;
564 typedef struct _q80_config_mac_rcv_mode_rsp {
566 uint16_t regcnt_status;
567 } __packed q80_config_mac_rcv_mode_rsp_t;
570 * Configure Firmware Controlled LRO
572 typedef struct _q80_config_fw_lro {
574 uint16_t count_version;
577 #define Q8_MBX_FW_LRO_IPV4 0x1
578 #define Q8_MBX_FW_LRO_IPV6 0x2
579 #define Q8_MBX_FW_LRO_IPV4_WO_DST_IP_CHK 0x4
580 #define Q8_MBX_FW_LRO_IPV6_WO_DST_IP_CHK 0x8
581 #define Q8_MBX_FW_LRO_LOW_THRESHOLD 0x10
586 uint16_t low_threshold;
588 } __packed q80_config_fw_lro_t;
590 typedef struct _q80_config_fw_lro_rsp {
592 uint16_t regcnt_status;
593 } __packed q80_config_fw_lro_rsp_t;
596 * Minidump mailbox commands
598 typedef struct _q80_config_md_templ_size {
600 uint16_t count_version;
601 } __packed q80_config_md_templ_size_t;
603 typedef struct _q80_config_md_templ_size_rsp {
605 uint16_t regcnt_status;
608 uint32_t templ_version;
609 } __packed q80_config_md_templ_size_rsp_t;
611 typedef struct _q80_config_md_templ_cmd {
613 uint16_t count_version;
614 uint64_t buf_addr; /* physical address of buffer */
617 } __packed q80_config_md_templ_cmd_t;
619 typedef struct _q80_config_md_templ_cmd_rsp {
621 uint16_t regcnt_status;
626 } __packed q80_config_md_templ_cmd_rsp_t;
629 * Hardware Configuration Commands
632 typedef struct _q80_hw_config {
634 uint16_t count_version;
635 #define Q8_HW_CONFIG_SET_MDIO_REG_COUNT 0x06
636 #define Q8_HW_CONFIG_GET_MDIO_REG_COUNT 0x05
637 #define Q8_HW_CONFIG_SET_CAM_SEARCH_MODE_COUNT 0x03
638 #define Q8_HW_CONFIG_GET_CAM_SEARCH_MODE_COUNT 0x02
639 #define Q8_HW_CONFIG_SET_TEMP_THRESHOLD_COUNT 0x03
640 #define Q8_HW_CONFIG_GET_TEMP_THRESHOLD_COUNT 0x02
641 #define Q8_HW_CONFIG_GET_ECC_COUNTS_COUNT 0x02
644 #define Q8_HW_CONFIG_SET_MDIO_REG 0x01
645 #define Q8_HW_CONFIG_GET_MDIO_REG 0x02
646 #define Q8_HW_CONFIG_SET_CAM_SEARCH_MODE 0x03
647 #define Q8_HW_CONFIG_GET_CAM_SEARCH_MODE 0x04
648 #define Q8_HW_CONFIG_SET_TEMP_THRESHOLD 0x07
649 #define Q8_HW_CONFIG_GET_TEMP_THRESHOLD 0x08
650 #define Q8_HW_CONFIG_GET_ECC_COUNTS 0x0A
654 uint32_t phys_port_number;
655 uint32_t phy_dev_addr;
661 uint32_t phys_port_number;
662 uint32_t phy_dev_addr;
668 #define Q8_HW_CONFIG_CAM_SEARCH_MODE_INTERNAL 0x1
669 #define Q8_HW_CONFIG_CAM_SEARCH_MODE_AUTO 0x2
671 } set_cam_search_mode;
675 } set_temp_threshold;
677 } __packed q80_hw_config_t;
679 typedef struct _q80_hw_config_rsp {
681 uint16_t regcnt_status;
690 } get_cam_search_mode;
695 uint32_t osc_ring_rate;
696 uint32_t core_voltage;
697 } get_temp_threshold;
700 uint32_t ddr_ecc_error_count;
701 uint32_t ocm_ecc_error_count;
702 uint32_t l2_dcache_ecc_error_count;
703 uint32_t l2_icache_ecc_error_count;
704 uint32_t eport_ecc_error_count;
707 } __packed q80_hw_config_rsp_t;
710 * Link Event Request Command
712 typedef struct _q80_link_event {
714 uint16_t count_version;
716 #define Q8_LINK_EVENT_CMD_STOP_PERIODIC 0
717 #define Q8_LINK_EVENT_CMD_ENABLE_ASYNC 1
720 #define Q8_LINK_EVENT_FLAGS_SEND_RSP 1
723 } __packed q80_link_event_t;
725 typedef struct _q80_link_event_rsp {
727 uint16_t regcnt_status;
728 } __packed q80_link_event_rsp_t;
731 * Get Statistics Command
733 typedef struct _q80_rcv_stats {
734 uint64_t total_bytes;
736 uint64_t lro_pkt_count;
737 uint64_t sw_pkt_count;
738 uint64_t ip_chksum_err;
739 uint64_t pkts_wo_acntxts;
740 uint64_t pkts_dropped_no_sds_card;
741 uint64_t pkts_dropped_no_sds_host;
742 uint64_t oversized_pkts;
743 uint64_t pkts_dropped_no_rds;
744 uint64_t unxpctd_mcast_pkts;
745 uint64_t re1_fbq_error;
746 uint64_t invalid_mac_addr;
747 uint64_t rds_prime_trys;
748 uint64_t rds_prime_success;
749 uint64_t lro_flows_added;
750 uint64_t lro_flows_deleted;
751 uint64_t lro_flows_active;
752 uint64_t pkts_droped_unknown;
753 uint64_t pkts_cnt_oversized;
754 } __packed q80_rcv_stats_t;
756 typedef struct _q80_xmt_stats {
757 uint64_t total_bytes;
760 uint64_t pkts_dropped;
761 uint64_t switch_pkts;
762 uint64_t num_buffers;
763 } __packed q80_xmt_stats_t;
765 typedef struct _q80_mac_stats {
768 uint64_t xmt_mcast_pkts;
769 uint64_t xmt_bcast_pkts;
770 uint64_t xmt_pause_frames;
771 uint64_t xmt_cntrl_pkts;
772 uint64_t xmt_pkt_lt_64bytes;
773 uint64_t xmt_pkt_lt_127bytes;
774 uint64_t xmt_pkt_lt_255bytes;
775 uint64_t xmt_pkt_lt_511bytes;
776 uint64_t xmt_pkt_lt_1023bytes;
777 uint64_t xmt_pkt_lt_1518bytes;
778 uint64_t xmt_pkt_gt_1518bytes;
782 uint64_t rcv_mcast_pkts;
783 uint64_t rcv_bcast_pkts;
784 uint64_t rcv_pause_frames;
785 uint64_t rcv_cntrl_pkts;
786 uint64_t rcv_pkt_lt_64bytes;
787 uint64_t rcv_pkt_lt_127bytes;
788 uint64_t rcv_pkt_lt_255bytes;
789 uint64_t rcv_pkt_lt_511bytes;
790 uint64_t rcv_pkt_lt_1023bytes;
791 uint64_t rcv_pkt_lt_1518bytes;
792 uint64_t rcv_pkt_gt_1518bytes;
794 uint64_t rcv_len_error;
795 uint64_t rcv_len_small;
796 uint64_t rcv_len_large;
798 uint64_t rcv_dropped;
800 uint64_t align_error;
801 uint64_t eswitched_frames;
802 uint64_t eswitched_bytes;
803 uint64_t eswitched_mcast_frames;
804 uint64_t eswitched_bcast_frames;
805 uint64_t eswitched_ucast_frames;
806 uint64_t eswitched_err_free_frames;
807 uint64_t eswitched_err_free_bytes;
808 } __packed q80_mac_stats_t;
810 typedef struct _q80_get_stats {
812 uint16_t count_version;
815 #define Q8_GET_STATS_CMD_CLEAR 0x01
816 #define Q8_GET_STATS_CMD_RCV 0x00
817 #define Q8_GET_STATS_CMD_XMT 0x02
818 #define Q8_GET_STATS_CMD_TYPE_CNTXT 0x00
819 #define Q8_GET_STATS_CMD_TYPE_MAC 0x04
820 #define Q8_GET_STATS_CMD_TYPE_FUNC 0x08
821 #define Q8_GET_STATS_CMD_TYPE_VPORT 0x0C
822 #define Q8_GET_STATS_CMD_TYPE_ALL (0x7 << 2)
824 } __packed q80_get_stats_t;
826 typedef struct _q80_get_stats_rsp {
828 uint16_t regcnt_status;
835 } __packed q80_get_stats_rsp_t;
837 typedef struct _q80_get_mac_rcv_xmt_stats_rsp {
839 uint16_t regcnt_status;
844 } __packed q80_get_mac_rcv_xmt_stats_rsp_t;
848 * Used to Register DCBX Configuration Change AEN
850 typedef struct _q80_init_nic_func {
852 uint16_t count_version;
855 #define Q8_INIT_NIC_REG_IDC_AEN 0x01
856 #define Q8_INIT_NIC_REG_DCBX_CHNG_AEN 0x02
857 #define Q8_INIT_NIC_REG_SFP_CHNG_AEN 0x04
859 } __packed q80_init_nic_func_t;
861 typedef struct _q80_init_nic_func_rsp {
863 uint16_t regcnt_status;
864 } __packed q80_init_nic_func_rsp_t;
868 * Used to DeRegister DCBX Configuration Change AEN
870 typedef struct _q80_stop_nic_func {
872 uint16_t count_version;
875 #define Q8_STOP_NIC_DEREG_DCBX_CHNG_AEN 0x02
876 #define Q8_STOP_NIC_DEREG_SFP_CHNG_AEN 0x04
878 } __packed q80_stop_nic_func_t;
880 typedef struct _q80_stop_nic_func_rsp {
882 uint16_t regcnt_status;
883 } __packed q80_stop_nic_func_rsp_t;
886 * Query Firmware DCBX Capabilities
888 typedef struct _q80_query_fw_dcbx_caps {
890 uint16_t count_version;
891 } __packed q80_query_fw_dcbx_caps_t;
893 typedef struct _q80_query_fw_dcbx_caps_rsp {
895 uint16_t regcnt_status;
898 #define Q8_QUERY_FW_DCBX_CAPS_TSA 0x00000001
899 #define Q8_QUERY_FW_DCBX_CAPS_ETS 0x00000002
900 #define Q8_QUERY_FW_DCBX_CAPS_DCBX_CEE_1_01 0x00000004
901 #define Q8_QUERY_FW_DCBX_CAPS_DCBX_IEEE_1_0 0x00000008
902 #define Q8_QUERY_FW_DCBX_MAX_TC_MASK 0x00F00000
903 #define Q8_QUERY_FW_DCBX_MAX_ETS_TC_MASK 0x0F000000
904 #define Q8_QUERY_FW_DCBX_MAX_PFC_TC_MASK 0xF0000000
906 } __packed q80_query_fw_dcbx_caps_rsp_t;
912 typedef struct _q80_idc_ack {
914 uint16_t count_version;
921 } __packed q80_idc_ack_t;
923 typedef struct _q80_idc_ack_rsp {
925 uint16_t regcnt_status;
926 } __packed q80_idc_ack_rsp_t;
930 * Set Port Configuration command
931 * Used to set Ethernet Standard Pause values
934 typedef struct _q80_set_port_cfg {
936 uint16_t count_version;
940 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_MASK (0x7 << 1)
941 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_NONE (0x0 << 1)
942 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_HSS (0x2 << 1)
943 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_PHY (0x3 << 1)
944 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_EXT (0x4 << 1)
946 #define Q8_VALID_LOOPBACK_MODE(mode) \
947 (((mode) == Q8_PORT_CFG_BITS_LOOPBACK_MODE_NONE) || \
948 (((mode) >= Q8_PORT_CFG_BITS_LOOPBACK_MODE_HSS) && \
949 ((mode) <= Q8_PORT_CFG_BITS_LOOPBACK_MODE_EXT)))
951 #define Q8_PORT_CFG_BITS_DCBX_ENABLE BIT_4
953 #define Q8_PORT_CFG_BITS_PAUSE_CFG_MASK (0x3 << 5)
954 #define Q8_PORT_CFG_BITS_PAUSE_DISABLED (0x0 << 5)
955 #define Q8_PORT_CFG_BITS_PAUSE_STD (0x1 << 5)
956 #define Q8_PORT_CFG_BITS_PAUSE_PPM (0x2 << 5)
958 #define Q8_PORT_CFG_BITS_LNKCAP_10MB BIT_8
959 #define Q8_PORT_CFG_BITS_LNKCAP_100MB BIT_9
960 #define Q8_PORT_CFG_BITS_LNKCAP_1GB BIT_10
961 #define Q8_PORT_CFG_BITS_LNKCAP_10GB BIT_11
963 #define Q8_PORT_CFG_BITS_AUTONEG BIT_15
964 #define Q8_PORT_CFG_BITS_XMT_DISABLE BIT_17
965 #define Q8_PORT_CFG_BITS_FEC_RQSTD BIT_18
966 #define Q8_PORT_CFG_BITS_EEE_RQSTD BIT_19
968 #define Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK (0x3 << 20)
969 #define Q8_PORT_CFG_BITS_STDPAUSE_XMT_RCV (0x0 << 20)
970 #define Q8_PORT_CFG_BITS_STDPAUSE_XMT (0x1 << 20)
971 #define Q8_PORT_CFG_BITS_STDPAUSE_RCV (0x2 << 20)
973 } __packed q80_set_port_cfg_t;
975 typedef struct _q80_set_port_cfg_rsp {
977 uint16_t regcnt_status;
978 } __packed q80_set_port_cfg_rsp_t;
981 * Get Port Configuration Command
984 typedef struct _q80_get_port_cfg {
986 uint16_t count_version;
987 } __packed q80_get_port_cfg_t;
989 typedef struct _q80_get_port_cfg_rsp {
991 uint16_t regcnt_status;
993 uint32_t cfg_bits; /* same as in q80_set_port_cfg_t */
995 uint8_t phys_port_type;
997 } __packed q80_get_port_cfg_rsp_t;
1000 * Get Link Status Command
1001 * Used to get current PAUSE values for the port
1004 typedef struct _q80_get_link_status {
1006 uint16_t count_version;
1007 } __packed q80_get_link_status_t;
1009 typedef struct _q80_get_link_status_rsp {
1011 uint16_t regcnt_status;
1014 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_UP BIT_0
1016 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_MASK (0x7 << 3)
1017 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_UNKNOWN (0x0 << 3)
1018 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_10MB (0x1 << 3)
1019 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_100MB (0x2 << 3)
1020 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_1GB (0x3 << 3)
1021 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_10GB (0x4 << 3)
1023 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_MASK (0x3 << 6)
1024 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_DISABLE (0x0 << 6)
1025 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_STD (0x1 << 6)
1026 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_PPM (0x2 << 6)
1028 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_MASK (0x7 << 8)
1029 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_NONE (0x0 << 6)
1030 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_HSS (0x2 << 6)
1031 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_PHY (0x3 << 6)
1033 #define Q8_GET_LINK_STAT_CFG_BITS_FEC_ENABLED BIT_12
1034 #define Q8_GET_LINK_STAT_CFG_BITS_EEE_ENABLED BIT_13
1036 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_DIR_MASK (0x3 << 20)
1037 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_NONE (0x0 << 20)
1038 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_XMT (0x1 << 20)
1039 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_RCV (0x2 << 20)
1040 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_XMT_RCV (0x3 << 20)
1042 uint32_t link_state;
1043 #define Q8_GET_LINK_STAT_LOSS_OF_SIGNAL BIT_0
1044 #define Q8_GET_LINK_STAT_PORT_RST_DONE BIT_3
1045 #define Q8_GET_LINK_STAT_PHY_LINK_DOWN BIT_4
1046 #define Q8_GET_LINK_STAT_PCS_LINK_DOWN BIT_5
1047 #define Q8_GET_LINK_STAT_MAC_LOCAL_FAULT BIT_6
1048 #define Q8_GET_LINK_STAT_MAC_REMOTE_FAULT BIT_7
1049 #define Q8_GET_LINK_STAT_XMT_DISABLED BIT_9
1050 #define Q8_GET_LINK_STAT_SFP_XMT_FAULT BIT_10
1053 #define Q8_GET_LINK_STAT_SFP_TRNCVR_MASK 0x3
1054 #define Q8_GET_LINK_STAT_SFP_TRNCVR_NOT_EXPECTED 0x0
1055 #define Q8_GET_LINK_STAT_SFP_TRNCVR_NONE 0x1
1056 #define Q8_GET_LINK_STAT_SFP_TRNCVR_INVALID 0x2
1057 #define Q8_GET_LINK_STAT_SFP_TRNCVR_VALID 0x3
1059 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_MASK (0x3 << 2)
1060 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_UNREC_TRSVR (0x0 << 2)
1061 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_NOT_QLOGIC (0x1 << 2)
1062 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_SPEED_FAILED (0x2 << 2)
1063 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_ACCESS_ERROR (0x3 << 2)
1065 #define Q8_GET_LINK_STAT_SFP_MOD_TYPE_MASK (0x1F << 4)
1066 #define Q8_GET_LINK_STAT_SFP_MOD_NONE (0x00 << 4)
1067 #define Q8_GET_LINK_STAT_SFP_MOD_10GBLRM (0x01 << 4)
1068 #define Q8_GET_LINK_STAT_SFP_MOD_10GBLR (0x02 << 4)
1069 #define Q8_GET_LINK_STAT_SFP_MOD_10GBSR (0x03 << 4)
1070 #define Q8_GET_LINK_STAT_SFP_MOD_10GBC_P (0x04 << 4)
1071 #define Q8_GET_LINK_STAT_SFP_MOD_10GBC_AL (0x05 << 4)
1072 #define Q8_GET_LINK_STAT_SFP_MOD_10GBC_PL (0x06 << 4)
1073 #define Q8_GET_LINK_STAT_SFP_MOD_1GBSX (0x07 << 4)
1074 #define Q8_GET_LINK_STAT_SFP_MOD_1GBLX (0x08 << 4)
1075 #define Q8_GET_LINK_STAT_SFP_MOD_1GBCX (0x09 << 4)
1076 #define Q8_GET_LINK_STAT_SFP_MOD_1GBT (0x0A << 4)
1077 #define Q8_GET_LINK_STAT_SFP_MOD_1GBC_PL (0x0B << 4)
1078 #define Q8_GET_LINK_STAT_SFP_MOD_UNKNOWN (0x0F << 4)
1080 #define Q8_GET_LINK_STAT_SFP_MULTI_RATE_MOD BIT_9
1081 #define Q8_GET_LINK_STAT_SFP_XMT_FAULT BIT_10
1082 #define Q8_GET_LINK_STAT_SFP_COPPER_CBL_LENGTH_MASK (0xFF << 16)
1084 } __packed q80_get_link_status_rsp_t;
1088 * Transmit Related Definitions
1090 /* Max# of TX Rings per Tx Create Cntxt Mbx Cmd*/
1091 #define MAX_TCNTXT_RINGS 8
1094 * Transmit Context - Q8_CMD_CREATE_TX_CNTXT Command Configuration Data
1097 typedef struct _q80_rq_tx_ring {
1099 uint64_t tx_consumer;
1102 uint8_t intr_src_bit;
1104 } __packed q80_rq_tx_ring_t;
1106 typedef struct _q80_rq_tx_cntxt {
1108 uint16_t count_version;
1111 #define Q8_TX_CNTXT_CAP0_BASEFW (1 << 0)
1112 #define Q8_TX_CNTXT_CAP0_LSO (1 << 6)
1113 #define Q8_TX_CNTXT_CAP0_TC (1 << 25)
1119 uint8_t traffic_class; /* bits 8-10; others reserved */
1121 q80_rq_tx_ring_t tx_ring[MAX_TCNTXT_RINGS];
1122 } __packed q80_rq_tx_cntxt_t;
1124 typedef struct _q80_rsp_tx_ring {
1125 uint32_t prod_index;
1129 } q80_rsp_tx_ring_t;
1131 typedef struct _q80_rsp_tx_cntxt {
1133 uint16_t regcnt_status;
1138 q80_rsp_tx_ring_t tx_ring[MAX_TCNTXT_RINGS];
1139 } __packed q80_rsp_tx_cntxt_t;
1141 typedef struct _q80_tx_cntxt_destroy {
1143 uint16_t count_version;
1145 } __packed q80_tx_cntxt_destroy_t;
1147 typedef struct _q80_tx_cntxt_destroy_rsp {
1149 uint16_t regcnt_status;
1150 } __packed q80_tx_cntxt_destroy_rsp_t;
1153 * Transmit Command Descriptor
1154 * These commands are issued on the Transmit Ring associated with a Transmit
1157 typedef struct _q80_tx_cmd {
1158 uint8_t tcp_hdr_off; /* TCP Header Offset */
1159 uint8_t ip_hdr_off; /* IP Header Offset */
1160 uint16_t flags_opcode; /* Bits 0-6: flags; 7-12: opcode */
1163 #define Q8_TX_CMD_FLAGS_MULTICAST 0x01
1164 #define Q8_TX_CMD_FLAGS_LSO_TSO 0x02
1165 #define Q8_TX_CMD_FLAGS_VLAN_TAGGED 0x10
1166 #define Q8_TX_CMD_FLAGS_HW_VLAN_ID 0x40
1169 #define Q8_TX_CMD_OP_XMT_UDP_CHKSUM_IPV6 (0xC << 7)
1170 #define Q8_TX_CMD_OP_XMT_TCP_CHKSUM_IPV6 (0xB << 7)
1171 #define Q8_TX_CMD_OP_XMT_TCP_LSO_IPV6 (0x6 << 7)
1172 #define Q8_TX_CMD_OP_XMT_TCP_LSO (0x5 << 7)
1173 #define Q8_TX_CMD_OP_XMT_UDP_CHKSUM (0x3 << 7)
1174 #define Q8_TX_CMD_OP_XMT_TCP_CHKSUM (0x2 << 7)
1175 #define Q8_TX_CMD_OP_XMT_ETHER (0x1 << 7)
1177 uint8_t n_bufs; /* # of data segs in data buffer */
1178 uint8_t data_len_lo; /* data length lower 8 bits */
1179 uint16_t data_len_hi; /* data length upper 16 bits */
1181 uint64_t buf2_addr; /* buffer 2 address */
1184 uint16_t mss; /* MSS for this packet */
1185 uint8_t cntxtid; /* Bits 7-4: ContextId; 3-0: reserved */
1187 #define Q8_TX_CMD_PORT_CNXTID(c_id) ((c_id & 0xF) << 4)
1189 uint8_t total_hdr_len; /* MAC+IP+TCP Header Length for LSO */
1192 uint64_t buf3_addr; /* buffer 3 address */
1193 uint64_t buf1_addr; /* buffer 1 address */
1195 uint16_t buf1_len; /* length of buffer 1 */
1196 uint16_t buf2_len; /* length of buffer 2 */
1197 uint16_t buf3_len; /* length of buffer 3 */
1198 uint16_t buf4_len; /* length of buffer 4 */
1200 uint64_t buf4_addr; /* buffer 4 address */
1204 uint16_t vlan_tci; /* VLAN TCI when hw tagging is enabled*/
1206 } __packed q80_tx_cmd_t; /* 64 bytes */
1208 #define Q8_TX_CMD_MAX_SEGMENTS 4
1209 #define Q8_TX_CMD_TSO_ALIGN 2
1210 #define Q8_TX_MAX_NON_TSO_SEGS 62
1214 * Receive Related Definitions
1216 #define MAX_RDS_RING_SETS 8 /* Max# of Receive Descriptor Rings */
1218 #ifdef QL_ENABLE_ISCSI_TLV
1219 #define MAX_SDS_RINGS 32 /* Max# of Status Descriptor Rings */
1220 #define NUM_TX_RINGS (MAX_SDS_RINGS * 2)
1222 #define MAX_SDS_RINGS 32 /* Max# of Status Descriptor Rings */
1223 #define NUM_TX_RINGS MAX_SDS_RINGS
1224 #endif /* #ifdef QL_ENABLE_ISCSI_TLV */
1225 #define MAX_RDS_RINGS MAX_SDS_RINGS /* Max# of Rcv Descriptor Rings */
1228 typedef struct _q80_rq_sds_ring {
1229 uint64_t paddr; /* physical addr of status ring in system memory */
1230 uint64_t hdr_split1;
1231 uint64_t hdr_split2;
1232 uint16_t size; /* number of entries in status ring */
1233 uint16_t hdr_split1_size;
1234 uint16_t hdr_split2_size;
1235 uint16_t hdr_split_count;
1237 uint8_t intr_src_bit;
1239 } __packed q80_rq_sds_ring_t; /* 10 32bit words */
1241 typedef struct _q80_rq_rds_ring {
1242 uint64_t paddr_std; /* physical addr of rcv ring in system memory */
1243 uint64_t paddr_jumbo; /* physical addr of rcv ring in system memory */
1245 uint16_t std_nentries;
1246 uint16_t jumbo_bsize;
1247 uint16_t jumbo_nentries;
1248 } __packed q80_rq_rds_ring_t; /* 6 32bit words */
1250 #define MAX_RCNTXT_SDS_RINGS 8
1252 typedef struct _q80_rq_rcv_cntxt {
1254 uint16_t count_version;
1256 #define Q8_RCV_CNTXT_CAP0_BASEFW (1 << 0)
1257 #define Q8_RCV_CNTXT_CAP0_MULTI_RDS (1 << 1)
1258 #define Q8_RCV_CNTXT_CAP0_LRO (1 << 5)
1259 #define Q8_RCV_CNTXT_CAP0_HW_LRO (1 << 10)
1260 #define Q8_RCV_CNTXT_CAP0_VLAN_ALIGN (1 << 14)
1261 #define Q8_RCV_CNTXT_CAP0_RSS (1 << 15)
1262 #define Q8_RCV_CNTXT_CAP0_MSFT_RSS (1 << 16)
1263 #define Q8_RCV_CNTXT_CAP0_SGL_JUMBO (1 << 18)
1264 #define Q8_RCV_CNTXT_CAP0_SGL_LRO (1 << 19)
1265 #define Q8_RCV_CNTXT_CAP0_SINGLE_JUMBO (1 << 26)
1270 uint8_t nrds_sets_rings;
1272 uint16_t rds_producer_mode;
1273 #define Q8_RCV_CNTXT_RDS_PROD_MODE_UNIQUE 0
1274 #define Q8_RCV_CNTXT_RDS_PROD_MODE_SHARED 1
1279 q80_rq_sds_ring_t sds[MAX_RCNTXT_SDS_RINGS];
1280 q80_rq_rds_ring_t rds[MAX_RDS_RING_SETS];
1281 } __packed q80_rq_rcv_cntxt_t;
1283 typedef struct _q80_rsp_rds_ring {
1285 uint32_t prod_jumbo;
1286 } __packed q80_rsp_rds_ring_t; /* 8 bytes */
1288 typedef struct _q80_rsp_rcv_cntxt {
1290 uint16_t regcnt_status;
1291 uint8_t nrds_sets_rings;
1298 uint32_t sds_cons[MAX_RCNTXT_SDS_RINGS];
1299 q80_rsp_rds_ring_t rds[MAX_RDS_RING_SETS];
1300 } __packed q80_rsp_rcv_cntxt_t;
1302 typedef struct _q80_rcv_cntxt_destroy {
1304 uint16_t count_version;
1306 } __packed q80_rcv_cntxt_destroy_t;
1308 typedef struct _q80_rcv_cntxt_destroy_rsp {
1310 uint16_t regcnt_status;
1311 } __packed q80_rcv_cntxt_destroy_rsp_t;
1317 typedef struct _q80_rq_add_rcv_rings {
1319 uint16_t count_version;
1320 uint8_t nrds_sets_rings;
1323 q80_rq_sds_ring_t sds[MAX_RCNTXT_SDS_RINGS];
1324 q80_rq_rds_ring_t rds[MAX_RDS_RING_SETS];
1325 } __packed q80_rq_add_rcv_rings_t;
1327 typedef struct _q80_rsp_add_rcv_rings {
1329 uint16_t regcnt_status;
1330 uint8_t nrds_sets_rings;
1333 uint32_t sds_cons[MAX_RCNTXT_SDS_RINGS];
1334 q80_rsp_rds_ring_t rds[MAX_RDS_RING_SETS];
1335 } __packed q80_rsp_add_rcv_rings_t;
1338 * Map Status Ring to Receive Descriptor Set
1341 #define MAX_SDS_TO_RDS_MAP 16
1343 typedef struct _q80_sds_rds_map_e {
1348 } __packed q80_sds_rds_map_e_t;
1350 typedef struct _q80_rq_map_sds_to_rds {
1352 uint16_t count_version;
1355 q80_sds_rds_map_e_t sds_rds[MAX_SDS_TO_RDS_MAP];
1356 } __packed q80_rq_map_sds_to_rds_t;
1359 typedef struct _q80_rsp_map_sds_to_rds {
1361 uint16_t regcnt_status;
1364 q80_sds_rds_map_e_t sds_rds[MAX_SDS_TO_RDS_MAP];
1365 } __packed q80_rsp_map_sds_to_rds_t;
1369 * Receive Descriptor corresponding to each entry in the receive ring
1371 typedef struct _q80_rcv_desc {
1374 uint32_t buf_size; /* buffer size in bytes */
1375 uint64_t buf_addr; /* physical address of buffer */
1376 } __packed q80_recv_desc_t;
1379 * Status Descriptor corresponding to each entry in the Status ring
1381 typedef struct _q80_stat_desc {
1383 } __packed q80_stat_desc_t;
1386 * definitions for data[0] field of Status Descriptor
1388 #define Q8_STAT_DESC_RSS_HASH(data) (data & 0xFFFFFFFF)
1389 #define Q8_STAT_DESC_TOTAL_LENGTH(data) ((data >> 32) & 0x3FFF)
1390 #define Q8_STAT_DESC_TOTAL_LENGTH_SGL_RCV(data) ((data >> 32) & 0xFFFF)
1391 #define Q8_STAT_DESC_HANDLE(data) ((data >> 48) & 0xFFFF)
1393 * definitions for data[1] field of Status Descriptor
1396 #define Q8_STAT_DESC_OPCODE(data) ((data >> 42) & 0xF)
1397 #define Q8_STAT_DESC_OPCODE_RCV_PKT 0x01
1398 #define Q8_STAT_DESC_OPCODE_LRO_PKT 0x02
1399 #define Q8_STAT_DESC_OPCODE_SGL_LRO 0x04
1400 #define Q8_STAT_DESC_OPCODE_SGL_RCV 0x05
1401 #define Q8_STAT_DESC_OPCODE_CONT 0x06
1404 * definitions for data[1] field of Status Descriptor for standard frames
1405 * status descriptor opcode equals 0x04
1407 #define Q8_STAT_DESC_STATUS(data) ((data >> 39) & 0x0007)
1408 #define Q8_STAT_DESC_STATUS_CHKSUM_NOT_DONE 0x00
1409 #define Q8_STAT_DESC_STATUS_NO_CHKSUM 0x01
1410 #define Q8_STAT_DESC_STATUS_CHKSUM_OK 0x02
1411 #define Q8_STAT_DESC_STATUS_CHKSUM_ERR 0x03
1413 #define Q8_STAT_DESC_VLAN(data) ((data >> 47) & 1)
1414 #define Q8_STAT_DESC_VLAN_ID(data) ((data >> 48) & 0xFFFF)
1416 #define Q8_STAT_DESC_PROTOCOL(data) ((data >> 44) & 0x000F)
1417 #define Q8_STAT_DESC_L2_OFFSET(data) ((data >> 48) & 0x001F)
1418 #define Q8_STAT_DESC_COUNT(data) ((data >> 37) & 0x0007)
1421 * definitions for data[0-1] fields of Status Descriptor for LRO
1422 * status descriptor opcode equals 0x04
1425 /* definitions for data[1] field */
1426 #define Q8_LRO_STAT_DESC_SEQ_NUM(data) (uint32_t)(data)
1429 * definitions specific to opcode 0x04 data[1]
1431 #define Q8_STAT_DESC_COUNT_SGL_LRO(data) ((data >> 13) & 0x0007)
1432 #define Q8_SGL_LRO_STAT_L2_OFFSET(data) ((data >> 16) & 0xFF)
1433 #define Q8_SGL_LRO_STAT_L4_OFFSET(data) ((data >> 24) & 0xFF)
1434 #define Q8_SGL_LRO_STAT_TS(data) ((data >> 40) & 0x1)
1435 #define Q8_SGL_LRO_STAT_PUSH_BIT(data) ((data >> 41) & 0x1)
1439 * definitions specific to opcode 0x05 data[1]
1441 #define Q8_STAT_DESC_COUNT_SGL_RCV(data) ((data >> 37) & 0x0003)
1444 * definitions for opcode 0x06
1446 /* definitions for data[0] field */
1447 #define Q8_SGL_STAT_DESC_HANDLE1(data) (data & 0xFFFF)
1448 #define Q8_SGL_STAT_DESC_HANDLE2(data) ((data >> 16) & 0xFFFF)
1449 #define Q8_SGL_STAT_DESC_HANDLE3(data) ((data >> 32) & 0xFFFF)
1450 #define Q8_SGL_STAT_DESC_HANDLE4(data) ((data >> 48) & 0xFFFF)
1452 /* definitions for data[1] field */
1453 #define Q8_SGL_STAT_DESC_HANDLE5(data) (data & 0xFFFF)
1454 #define Q8_SGL_STAT_DESC_HANDLE6(data) ((data >> 16) & 0xFFFF)
1455 #define Q8_SGL_STAT_DESC_NUM_HANDLES(data) ((data >> 32) & 0x7)
1456 #define Q8_SGL_STAT_DESC_HANDLE7(data) ((data >> 48) & 0xFFFF)
1458 /** Driver Related Definitions Begin **/
1460 #define TX_SMALL_PKT_SIZE 128 /* size in bytes of small packets */
1462 /* The number of descriptors should be a power of 2 */
1463 #define NUM_TX_DESCRIPTORS 1024
1464 #define NUM_STATUS_DESCRIPTORS 1024
1467 #define NUM_RX_DESCRIPTORS 2048
1470 * structure describing various dma buffers
1473 typedef struct qla_dmabuf {
1475 uint32_t tx_ring :1,
1482 qla_dma_t rds_ring[MAX_RDS_RINGS];
1483 qla_dma_t sds_ring[MAX_SDS_RINGS];
1487 typedef struct _qla_sds {
1488 q80_stat_desc_t *sds_ring_base; /* start of sds ring */
1489 uint32_t sdsr_next; /* next entry in SDS ring to process */
1490 struct lro_ctrl lro;
1493 volatile uint32_t rcv_active;
1494 uint32_t sds_consumer;
1495 uint64_t intr_count;
1496 uint64_t spurious_intr_count;
1499 #define Q8_MAX_LRO_CONT_DESC 7
1500 #define Q8_MAX_HANDLES_LRO (1 + (Q8_MAX_LRO_CONT_DESC * 7))
1501 #define Q8_MAX_HANDLES_NON_LRO 8
1503 typedef struct _qla_sgl_rcv {
1504 uint16_t pkt_length;
1505 uint16_t num_handles;
1506 uint16_t chksum_status;
1508 uint16_t rss_hash_flags;
1510 uint16_t handle[Q8_MAX_HANDLES_NON_LRO];
1513 typedef struct _qla_sgl_lro {
1515 #define Q8_LRO_COMP_TS 0x1
1516 #define Q8_LRO_COMP_PUSH_BIT 0x2
1520 uint16_t payload_length;
1521 uint16_t num_handles;
1523 uint16_t rss_hash_flags;
1525 uint16_t handle[Q8_MAX_HANDLES_LRO];
1533 #define QL_FRAME_HDR_SIZE (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +\
1534 sizeof (struct ip6_hdr) + sizeof (struct tcphdr) + 16)
1536 typedef struct _qla_hw_tx_cntxt {
1537 q80_tx_cmd_t *tx_ring_base;
1538 bus_addr_t tx_ring_paddr;
1540 volatile uint32_t *tx_cons; /* tx consumer shadow reg */
1541 bus_addr_t tx_cons_paddr;
1543 volatile uint32_t txr_free; /* # of free entries in tx ring */
1544 volatile uint32_t txr_next; /* # next available tx ring entry */
1545 volatile uint32_t txr_comp; /* index of last tx entry completed */
1547 uint32_t tx_prod_reg;
1548 uint16_t tx_cntxt_id;
1550 } qla_hw_tx_cntxt_t;
1552 typedef struct _qla_mcast {
1554 uint8_t addr[ETHER_ADDR_LEN];
1555 } __packed qla_mcast_t;
1557 typedef struct _qla_rdesc {
1558 volatile uint32_t prod_std;
1559 volatile uint32_t prod_jumbo;
1560 volatile uint32_t rx_next; /* next standard rcv ring to arm fw */
1561 volatile int32_t rx_in; /* next standard rcv ring to add mbufs */
1563 uint64_t lro_pkt_count;
1567 typedef struct _qla_flash_desc_table {
1568 uint32_t flash_valid;
1571 uint16_t flash_cksum;
1572 uint16_t flash_unused;
1573 uint8_t flash_model[16];
1574 uint16_t flash_manuf;
1578 uint8_t alt_erase_cmd;
1579 uint8_t write_enable_cmd;
1580 uint8_t write_enable_bits;
1581 uint8_t write_statusreg_cmd;
1582 uint8_t unprotected_sec_cmd;
1583 uint8_t read_manuf_cmd;
1584 uint32_t block_size;
1585 uint32_t alt_block_size;
1586 uint32_t flash_size;
1587 uint32_t write_enable_data;
1588 uint8_t readid_addr_len;
1589 uint8_t write_disable_bits;
1590 uint8_t read_dev_id_len;
1591 uint8_t chip_erase_cmd;
1592 uint16_t read_timeo;
1593 uint8_t protected_sec_cmd;
1595 } __packed qla_flash_desc_table_t;
1598 * struct for storing hardware specific information for a given interface
1600 typedef struct _qla_hw {
1615 uint16_t link_speed;
1616 uint16_t cable_length;
1619 uint8_t module_type;
1620 uint8_t link_faults;
1622 uint8_t mac_rcv_mode;
1626 uint8_t mac_addr[ETHER_ADDR_LEN];
1628 uint32_t num_sds_rings;
1629 uint32_t num_rds_rings;
1630 uint32_t num_tx_rings;
1632 qla_dmabuf_t dma_buf;
1636 qla_hw_tx_cntxt_t tx_cntxt[NUM_TX_RINGS];
1640 uint16_t rcv_cntxt_id;
1642 uint32_t mbx_intr_mask_offset;
1644 uint16_t intr_id[MAX_SDS_RINGS];
1645 uint32_t intr_src[MAX_SDS_RINGS];
1647 qla_sds_t sds[MAX_SDS_RINGS];
1648 uint32_t mbox[Q8_NUM_MBOX];
1649 qla_rdesc_t rds[MAX_RDS_RINGS];
1651 uint32_t rds_pidx_thres;
1652 uint32_t sds_cidx_thres;
1654 uint32_t rcv_intr_coalesce;
1655 uint32_t xmt_intr_coalesce;
1657 /* Immediate Completion */
1658 volatile uint32_t imd_compl;
1659 volatile uint32_t aen_mb0;
1660 volatile uint32_t aen_mb1;
1661 volatile uint32_t aen_mb2;
1662 volatile uint32_t aen_mb3;
1663 volatile uint32_t aen_mb4;
1665 /* multicast address list */
1667 qla_mcast_t mcast[Q8_MAX_NUM_MULTICAST_ADDRS];
1668 uint8_t mac_addr_arr[(Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN)];
1670 /* reset sequence */
1671 #define Q8_MAX_RESET_SEQ_IDX 16
1672 uint32_t rst_seq[Q8_MAX_RESET_SEQ_IDX];
1673 uint32_t rst_seq_idx;
1675 /* heart beat register value */
1676 uint32_t hbeat_value;
1677 uint32_t health_count;
1678 uint32_t hbeat_failure;
1680 uint32_t max_tx_segs;
1681 uint32_t min_lro_pkt_size;
1683 uint32_t enable_hw_lro;
1684 uint32_t enable_soft_lro;
1685 uint32_t enable_9kb;
1687 uint32_t user_pri_nic;
1688 uint32_t user_pri_iscsi;
1690 /* Flash Descriptor Table */
1691 qla_flash_desc_table_t fdt;
1694 q80_mac_stats_t mac;
1695 q80_rcv_stats_t rcv;
1696 q80_xmt_stats_t xmt[NUM_TX_RINGS];
1698 /* Minidump Related */
1699 uint32_t mdump_init;
1700 uint32_t mdump_done;
1701 uint32_t mdump_active;
1702 uint32_t mdump_capture_mask;
1703 uint32_t mdump_start_seq_index;
1705 uint32_t mdump_buffer_size;
1706 void *mdump_template;
1707 uint32_t mdump_template_size;
1709 /* driver state related */
1713 #define QL_UPDATE_RDS_PRODUCER_INDEX(ha, prod_reg, val) \
1714 bus_write_4((ha->pci_reg), prod_reg, val);
1716 #define QL_UPDATE_TX_PRODUCER_INDEX(ha, val, i) \
1717 WRITE_REG32(ha, ha->hw.tx_cntxt[i].tx_prod_reg, val)
1719 #define QL_UPDATE_SDS_CONSUMER_INDEX(ha, i, val) \
1720 bus_write_4((ha->pci_reg), (ha->hw.sds[i].sds_consumer), val);
1722 #define QL_ENABLE_INTERRUPTS(ha, i) \
1723 bus_write_4((ha->pci_reg), (ha->hw.intr_src[i]), 0);
1725 #define QL_BUFFER_ALIGN 16
1729 * Flash Configuration
1731 #define Q8_BOARD_CONFIG_OFFSET 0x370000
1732 #define Q8_BOARD_CONFIG_LENGTH 0x2000
1734 #define Q8_BOARD_CONFIG_MAC0_LO 0x400
1736 #define Q8_FDT_LOCK_MAGIC_ID 0x00FD00FD
1737 #define Q8_FDT_FLASH_ADDR_VAL 0xFD009F
1738 #define Q8_FDT_FLASH_CTRL_VAL 0x3F
1739 #define Q8_FDT_MASK_VAL 0xFF
1741 #define Q8_WR_ENABLE_FL_ADDR 0xFD0100
1742 #define Q8_WR_ENABLE_FL_CTRL 0x5
1744 #define Q8_ERASE_LOCK_MAGIC_ID 0x00EF00EF
1745 #define Q8_ERASE_FL_ADDR_MASK 0xFD0300
1746 #define Q8_ERASE_FL_CTRL_MASK 0x3D
1748 #define Q8_WR_FL_LOCK_MAGIC_ID 0xABCDABCD
1749 #define Q8_WR_FL_ADDR_MASK 0x800000
1750 #define Q8_WR_FL_CTRL_MASK 0x3D
1752 #define QL_FDT_OFFSET 0x3F0000
1753 #define Q8_FLASH_SECTOR_SIZE 0x10000
1756 * Off Chip Memory Access
1759 typedef struct _q80_offchip_mem_val {
1764 } q80_offchip_mem_val_t;
1766 #endif /* #ifndef _QL_HW_H_ */