sys/dev/qlxgbe/ql_hw.h

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2013-2016 Qlogic Corporation
   5  * All rights reserved.
   6  *
   7  *  Redistribution and use in source and binary forms, with or without
   8  *  modification, are permitted provided that the following conditions
   9  *  are met:
  10  *
  11  *  1. Redistributions of source code must retain the above copyright
  12  *     notice, this list of conditions and the following disclaimer.
  13  *  2. Redistributions in binary form must reproduce the above copyright
  14  *     notice, this list of conditions and the following disclaimer in the
  15  *     documentation and/or other materials provided with the distribution.
  16  *
  17  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  18  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  21  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  22  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  23  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  24  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  25  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  26  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  27  *  POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * $FreeBSD$
  30  */
  31 /*
  32  * File: ql_hw.h
  33  * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
  34  */
  35 #ifndef _QL_HW_H_
  36 #define _QL_HW_H_
  37
  38 /*
  39  * PCIe Registers; Direct Mapped; Offsets from BAR0
  40  */
  41
  42 /*
  43  * Register offsets for QLE8030
  44  */
  45
  46 /*
  47  * Firmware Mailbox Registers
  48  *      0 thru 511; offsets 0x800 thru 0xFFC; 32bits each
  49  */
  50 #define Q8_FW_MBOX0                     0x00000800
  51 #define Q8_FW_MBOX511                   0x00000FFC
  52
  53 /*
  54  * Host Mailbox Registers
  55  *      0 thru 511; offsets 0x000 thru 0x7FC; 32bits each
  56  */
  57 #define Q8_HOST_MBOX0                   0x00000000
  58 #define Q8_HOST_MBOX511                 0x000007FC
  59
  60 #define Q8_MBOX_INT_ENABLE              0x00001000
  61 #define Q8_MBOX_INT_MASK_MSIX           0x00001200
  62 #define Q8_MBOX_INT_LEGACY              0x00003010
  63
  64 #define Q8_HOST_MBOX_CNTRL              0x00003038
  65 #define Q8_FW_MBOX_CNTRL                0x0000303C
  66
  67 #define Q8_PEG_HALT_STATUS1             0x000034A8
  68 #define Q8_PEG_HALT_STATUS2             0x000034AC
  69 #define Q8_FIRMWARE_HEARTBEAT           0x000034B0
  70
  71 #define Q8_FLASH_LOCK_ID                0x00003500
  72 #define Q8_DRIVER_LOCK_ID               0x00003504
  73 #define Q8_FW_CAPABILITIES              0x00003528
  74
  75 #define Q8_FW_VER_MAJOR                 0x00003550
  76 #define Q8_FW_VER_MINOR                 0x00003554
  77 #define Q8_FW_VER_SUB                   0x00003558
  78
  79 #define Q8_BOOTLD_ADDR                  0x0000355C
  80 #define Q8_BOOTLD_SIZE                  0x00003560
  81
  82 #define Q8_FW_IMAGE_ADDR                0x00003564
  83 #define Q8_FW_BUILD_NUMBER              0x00003568
  84 #define Q8_FW_IMAGE_VALID               0x000035FC
  85
  86 #define Q8_CMDPEG_STATE                 0x00003650
  87
  88 #define Q8_LINK_STATE                   0x00003698
  89 #define Q8_LINK_STATE_2                 0x0000369C
  90
  91 #define Q8_LINK_SPEED_0                 0x000036E0
  92 #define Q8_LINK_SPEED_1                 0x000036E4
  93 #define Q8_LINK_SPEED_2                 0x000036E8
  94 #define Q8_LINK_SPEED_3                 0x000036EC
  95
  96 #define Q8_MAX_LINK_SPEED_0             0x000036F0
  97 #define Q8_MAX_LINK_SPEED_1             0x000036F4
  98 #define Q8_MAX_LINK_SPEED_2             0x000036F8
  99 #define Q8_MAX_LINK_SPEED_3             0x000036FC
 100
 101 #define Q8_ASIC_TEMPERATURE             0x000037B4
 102
 103 /*
 104  * CRB Window Registers
 105  *      0 thru 15; offsets 0x3800 thru 0x383C; 32bits each
 106  */
 107 #define Q8_CRB_WINDOW_PF0               0x00003800
 108 #define Q8_CRB_WINDOW_PF15              0x0000383C
 109
 110 #define Q8_FLASH_LOCK                   0x00003850
 111 #define Q8_FLASH_UNLOCK                 0x00003854
 112
 113 #define Q8_DRIVER_LOCK                  0x00003868
 114 #define Q8_DRIVER_UNLOCK                0x0000386C
 115
 116 #define Q8_LEGACY_INT_PTR               0x000038C0
 117 #define Q8_LEGACY_INT_TRIG              0x000038C4
 118 #define Q8_LEGACY_INT_MASK              0x000038C8
 119
 120 #define Q8_WILD_CARD                    0x000038F0
 121 #define Q8_INFORMANT                    0x000038FC
 122
 123 /*
 124  * Ethernet Interface Specific Registers
 125  */
 126 #define Q8_DRIVER_OP_MODE               0x00003570
 127 #define Q8_API_VERSION                  0x0000356C
 128 #define Q8_NPAR_STATE                   0x0000359C
 129
 130 /*
 131  * End of PCIe Registers; Direct Mapped; Offsets from BAR0
 132  */
 133
 134 /*
 135  * Indirect Registers
 136  */
 137 #define Q8_LED_DUAL_0                   0x28084C80
 138 #define Q8_LED_SINGLE_0                 0x28084C90
 139
 140 #define Q8_LED_DUAL_1                   0x28084CA0
 141 #define Q8_LED_SINGLE_1                 0x28084CB0
 142
 143 #define Q8_LED_DUAL_2                   0x28084CC0
 144 #define Q8_LED_SINGLE_2                 0x28084CD0
 145
 146 #define Q8_LED_DUAL_3                   0x28084CE0
 147 #define Q8_LED_SINGLE_3                 0x28084CF0
 148
 149 #define Q8_GPIO_1                       0x28084D00
 150 #define Q8_GPIO_2                       0x28084D10
 151 #define Q8_GPIO_3                       0x28084D20
 152 #define Q8_GPIO_4                       0x28084D40
 153 #define Q8_GPIO_5                       0x28084D50
 154 #define Q8_GPIO_6                       0x28084D60
 155 #define Q8_GPIO_7                       0x42100060
 156 #define Q8_GPIO_8                       0x42100064
 157
 158 #define Q8_FLASH_SPI_STATUS             0x2808E010
 159 #define Q8_FLASH_SPI_CONTROL            0x2808E014
 160
 161 #define Q8_FLASH_STATUS                 0x42100004
 162 #define Q8_FLASH_CONTROL                0x42110004
 163 #define Q8_FLASH_ADDRESS                0x42110008
 164 #define Q8_FLASH_WR_DATA                0x4211000C
 165 #define Q8_FLASH_RD_DATA                0x42110018
 166
 167 #define Q8_FLASH_DIRECT_WINDOW          0x42110030
 168 #define Q8_FLASH_DIRECT_DATA            0x42150000
 169
 170 #define Q8_MS_CNTRL                     0x41000090
 171
 172 #define Q8_MS_ADDR_LO                   0x41000094
 173 #define Q8_MS_ADDR_HI                   0x41000098
 174
 175 #define Q8_MS_WR_DATA_0_31              0x410000A0
 176 #define Q8_MS_WR_DATA_32_63             0x410000A4
 177 #define Q8_MS_WR_DATA_64_95             0x410000B0
 178 #define Q8_MS_WR_DATA_96_127            0x410000B4
 179
 180 #define Q8_MS_RD_DATA_0_31              0x410000A8
 181 #define Q8_MS_RD_DATA_32_63             0x410000AC
 182 #define Q8_MS_RD_DATA_64_95             0x410000B8
 183 #define Q8_MS_RD_DATA_96_127            0x410000BC
 184
 185 #define Q8_CRB_PEG_0                    0x3400003c
 186 #define Q8_CRB_PEG_1                    0x3410003c
 187 #define Q8_CRB_PEG_2                    0x3420003c
 188 #define Q8_CRB_PEG_3                    0x3430003c
 189 #define Q8_CRB_PEG_4                    0x34B0003c
 190
 191 /*
 192  * Macros for reading and writing registers
 193  */
 194
 195 #if defined(__i386__) || defined(__amd64__)
 196 #define Q8_MB()    __asm volatile("mfence" ::: "memory")
 197 #define Q8_WMB()   __asm volatile("sfence" ::: "memory")
 198 #define Q8_RMB()   __asm volatile("lfence" ::: "memory")
 199 #else
 200 #define Q8_MB()
 201 #define Q8_WMB()
 202 #define Q8_RMB()
 203 #endif
 204
 205 #define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg)
 206
 207 #define WRITE_REG32(ha, reg, val) \
 208         {\
 209                 bus_write_4((ha->pci_reg), reg, val);\
 210                 bus_read_4((ha->pci_reg), reg);\
 211         }
 212
 213 #define Q8_NUM_MBOX     512
 214
 215 #define Q8_MAX_NUM_MULTICAST_ADDRS      1022
 216 #define Q8_MAC_ADDR_LEN                 6
 217
 218 /*
 219  * Firmware Interface
 220  */
 221
 222 /*
 223  * Command Response Interface - Commands
 224  */
 225
 226 #define Q8_MBX_CONFIG_IP_ADDRESS                0x0001
 227 #define Q8_MBX_CONFIG_INTR                      0x0002
 228 #define Q8_MBX_MAP_INTR_SRC                     0x0003
 229 #define Q8_MBX_MAP_SDS_TO_RDS                   0x0006
 230 #define Q8_MBX_CREATE_RX_CNTXT                  0x0007
 231 #define Q8_MBX_DESTROY_RX_CNTXT                 0x0008
 232 #define Q8_MBX_CREATE_TX_CNTXT                  0x0009
 233 #define Q8_MBX_DESTROY_TX_CNTXT                 0x000A
 234 #define Q8_MBX_ADD_RX_RINGS                     0x000B
 235 #define Q8_MBX_CONFIG_LRO_FLOW                  0x000C
 236 #define Q8_MBX_CONFIG_MAC_LEARNING              0x000D
 237 #define Q8_MBX_GET_STATS                        0x000F
 238 #define Q8_MBX_GENERATE_INTR                    0x0011
 239 #define Q8_MBX_SET_MAX_MTU                      0x0012
 240 #define Q8_MBX_MAC_ADDR_CNTRL                   0x001F
 241 #define Q8_MBX_GET_PCI_CONFIG                   0x0020
 242 #define Q8_MBX_GET_NIC_PARTITION                0x0021
 243 #define Q8_MBX_SET_NIC_PARTITION                0x0022
 244 #define Q8_MBX_QUERY_WOL_CAP                    0x002C
 245 #define Q8_MBX_SET_WOL_CONFIG                   0x002D
 246 #define Q8_MBX_GET_MINIDUMP_TMPLT_SIZE          0x002F
 247 #define Q8_MBX_GET_MINIDUMP_TMPLT               0x0030
 248 #define Q8_MBX_GET_FW_DCBX_CAPS                 0x0034
 249 #define Q8_MBX_QUERY_DCBX_SETTINGS              0x0035
 250 #define Q8_MBX_CONFIG_RSS                       0x0041
 251 #define Q8_MBX_CONFIG_RSS_TABLE                 0x0042
 252 #define Q8_MBX_CONFIG_INTR_COALESCE             0x0043
 253 #define Q8_MBX_CONFIG_LED                       0x0044
 254 #define Q8_MBX_CONFIG_MAC_ADDR                  0x0045
 255 #define Q8_MBX_CONFIG_STATISTICS                0x0046
 256 #define Q8_MBX_CONFIG_LOOPBACK                  0x0047
 257 #define Q8_MBX_LINK_EVENT_REQ                   0x0048
 258 #define Q8_MBX_CONFIG_MAC_RX_MODE               0x0049
 259 #define Q8_MBX_CONFIG_FW_LRO                    0x004A
 260 #define Q8_MBX_HW_CONFIG                        0x004C
 261 #define Q8_MBX_INIT_NIC_FUNC                    0x0060
 262 #define Q8_MBX_STOP_NIC_FUNC                    0x0061
 263 #define Q8_MBX_IDC_REQ                          0x0062
 264 #define Q8_MBX_IDC_ACK                          0x0063
 265 #define Q8_MBX_SET_PORT_CONFIG                  0x0066
 266 #define Q8_MBX_GET_PORT_CONFIG                  0x0067
 267 #define Q8_MBX_GET_LINK_STATUS                  0x0068
 268
 269
 270
 271 /*
 272  * Mailbox Command Response
 273  */
 274 #define Q8_MBX_RSP_SUCCESS                      0x0001
 275 #define Q8_MBX_RSP_RESPONSE_FAILURE             0x0002
 276 #define Q8_MBX_RSP_NO_CARD_CRB                  0x0003
 277 #define Q8_MBX_RSP_NO_CARD_MEM                  0x0004
 278 #define Q8_MBX_RSP_NO_CARD_RSRC                 0x0005
 279 #define Q8_MBX_RSP_INVALID_ARGS                 0x0006
 280 #define Q8_MBX_RSP_INVALID_ACTION               0x0007
 281 #define Q8_MBX_RSP_INVALID_STATE                0x0008
 282 #define Q8_MBX_RSP_NOT_SUPPORTED                0x0009
 283 #define Q8_MBX_RSP_NOT_PERMITTED                0x000A
 284 #define Q8_MBX_RSP_NOT_READY                    0x000B
 285 #define Q8_MBX_RSP_DOES_NOT_EXIST               0x000C
 286 #define Q8_MBX_RSP_ALREADY_EXISTS               0x000D
 287 #define Q8_MBX_RSP_BAD_SIGNATURE                0x000E
 288 #define Q8_MBX_RSP_CMD_NOT_IMPLEMENTED          0x000F
 289 #define Q8_MBX_RSP_CMD_INVALID                  0x0010
 290 #define Q8_MBX_RSP_TIMEOUT                      0x0011
 291 #define Q8_MBX_RSP_CMD_FAILED                   0x0012
 292 #define Q8_MBX_RSP_FATAL_TEMP                   0x0013
 293 #define Q8_MBX_RSP_MAX_EXCEEDED                 0x0014
 294 #define Q8_MBX_RSP_UNSPECIFIED                  0x0015
 295 #define Q8_MBX_RSP_INTR_CREATE_FAILED           0x0017
 296 #define Q8_MBX_RSP_INTR_DELETE_FAILED           0x0018
 297 #define Q8_MBX_RSP_INTR_INVALID_OP              0x0019
 298 #define Q8_MBX_RSP_IDC_INTRMD_RSP               0x001A
 299
 300 #define Q8_MBX_CMD_VERSION      (0x2 << 13)
 301 #define Q8_MBX_RSP_STATUS(x) (((!(x >> 9)) || ((x >> 9) == 1)) ? 0: (x >> 9))
 302 /*
 303  * Configure IP Address
 304  */
 305 typedef struct _q80_config_ip_addr {
 306         uint16_t        opcode;
 307         uint16_t        count_version;
 308
 309         uint8_t         cmd;
 310 #define         Q8_MBX_CONFIG_IP_ADD_IP 0x1
 311 #define         Q8_MBX_CONFIG_IP_DEL_IP 0x2
 312
 313         uint8_t         ip_type;
 314 #define         Q8_MBX_CONFIG_IP_V4     0x0
 315 #define         Q8_MBX_CONFIG_IP_V6     0x1
 316
 317         uint16_t        rsrvd;
 318         union {
 319                 struct {
 320                         uint32_t addr;
 321                         uint32_t rsrvd[3];
 322                 } ipv4;
 323                 uint8_t ipv6_addr[16];
 324         } u;
 325 } __packed q80_config_ip_addr_t;
 326
 327 typedef struct _q80_config_ip_addr_rsp {
 328         uint16_t        opcode;
 329         uint16_t        regcnt_status;
 330 } __packed q80_config_ip_addr_rsp_t;
 331
 332 /*
 333  * Configure Interrupt Command
 334  */
 335 typedef struct _q80_intr {
 336         uint8_t         cmd_type;
 337 #define         Q8_MBX_CONFIG_INTR_CREATE       0x1
 338 #define         Q8_MBX_CONFIG_INTR_DELETE       0x2
 339 #define         Q8_MBX_CONFIG_INTR_TYPE_LINE    (0x1 << 4)
 340 #define         Q8_MBX_CONFIG_INTR_TYPE_MSI_X   (0x3 << 4)
 341
 342         uint8_t         rsrvd;
 343         uint16_t        msix_index;
 344 } __packed q80_intr_t;
 345
 346 #define Q8_MAX_INTR_VECTORS     16
 347 typedef struct _q80_config_intr {
 348         uint16_t        opcode;
 349         uint16_t        count_version;
 350         uint8_t         nentries;
 351         uint8_t         rsrvd[3];
 352         q80_intr_t      intr[Q8_MAX_INTR_VECTORS];
 353 } __packed q80_config_intr_t;
 354
 355 typedef struct _q80_intr_rsp {
 356         uint8_t         status;
 357         uint8_t         cmd;
 358         uint16_t        intr_id;
 359         uint32_t        intr_src;
 360 } q80_intr_rsp_t;
 361
 362 typedef struct _q80_config_intr_rsp {
 363         uint16_t        opcode;
 364         uint16_t        regcnt_status;
 365         uint8_t         nentries;
 366         uint8_t         rsrvd[3];
 367         q80_intr_rsp_t  intr[Q8_MAX_INTR_VECTORS];
 368 } __packed q80_config_intr_rsp_t;
 369
 370 /*
 371  * Configure LRO Flow Command
 372  */
 373 typedef struct _q80_config_lro_flow {
 374         uint16_t        opcode;
 375         uint16_t        count_version;
 376
 377         uint8_t         cmd;
 378 #define Q8_MBX_CONFIG_LRO_FLOW_ADD      0x01
 379 #define Q8_MBX_CONFIG_LRO_FLOW_DELETE   0x02
 380
 381         uint8_t         type_ts;
 382 #define Q8_MBX_CONFIG_LRO_FLOW_IPV4             0x00
 383 #define Q8_MBX_CONFIG_LRO_FLOW_IPV6             0x01
 384 #define Q8_MBX_CONFIG_LRO_FLOW_TS_ABSENT        0x00
 385 #define Q8_MBX_CONFIG_LRO_FLOW_TS_PRESENT       0x02
 386
 387         uint16_t        rsrvd;
 388         union {
 389                 struct {
 390                         uint32_t addr;
 391                         uint32_t rsrvd[3];
 392                 } ipv4;
 393                 uint8_t ipv6_addr[16];
 394         } dst;
 395         union {
 396                 struct {
 397                         uint32_t addr;
 398                         uint32_t rsrvd[3];
 399                 } ipv4;
 400                 uint8_t ipv6_addr[16];
 401         } src;
 402         uint16_t        dst_port;
 403         uint16_t        src_port;
 404 } __packed q80_config_lro_flow_t;
 405
 406 typedef struct _q80_config_lro_flow_rsp {
 407         uint16_t        opcode;
 408         uint16_t        regcnt_status;
 409 } __packed q80_config_lro_flow_rsp_t;
 410
 411 typedef struct _q80_set_max_mtu {
 412         uint16_t        opcode;
 413         uint16_t        count_version;
 414         uint32_t        cntxt_id;
 415         uint32_t        mtu;
 416 } __packed q80_set_max_mtu_t;
 417
 418 typedef struct _q80_set_max_mtu_rsp {
 419         uint16_t        opcode;
 420         uint16_t        regcnt_status;
 421 } __packed q80_set_max_mtu_rsp_t;
 422
 423 /*
 424  * Configure RSS
 425  */
 426 typedef struct _q80_config_rss {
 427         uint16_t        opcode;
 428         uint16_t        count_version;
 429
 430         uint16_t        cntxt_id;
 431         uint16_t        rsrvd;
 432
 433         uint8_t         hash_type;
 434 #define Q8_MBX_RSS_HASH_TYPE_IPV4_IP            (0x1 << 4)
 435 #define Q8_MBX_RSS_HASH_TYPE_IPV4_TCP           (0x2 << 4)
 436 #define Q8_MBX_RSS_HASH_TYPE_IPV4_TCP_IP        (0x3 << 4)
 437 #define Q8_MBX_RSS_HASH_TYPE_IPV6_IP            (0x1 << 6)
 438 #define Q8_MBX_RSS_HASH_TYPE_IPV6_TCP           (0x2 << 6)
 439 #define Q8_MBX_RSS_HASH_TYPE_IPV6_TCP_IP        (0x3 << 6)
 440
 441         uint8_t         flags;
 442 #define Q8_MBX_RSS_FLAGS_ENABLE_RSS             (0x1)
 443 #define Q8_MBX_RSS_FLAGS_USE_IND_TABLE          (0x2)
 444 #define Q8_MBX_RSS_FLAGS_TYPE_CRSS              (0x4)
 445
 446         uint16_t        indtbl_mask;
 447 #define Q8_MBX_RSS_INDTBL_MASK                  0x7F
 448 #define Q8_MBX_RSS_FLAGS_MULTI_RSS_VALID        0x8000
 449
 450         uint32_t        multi_rss;
 451 #define Q8_MBX_RSS_MULTI_RSS_ENGINE_ASSIGN      BIT_30
 452 #define Q8_MBX_RSS_USE_MULTI_RSS_ENGINES        BIT_31
 453
 454         uint64_t        rss_key[5];
 455 } __packed q80_config_rss_t;
 456
 457 typedef struct _q80_config_rss_rsp {
 458         uint16_t        opcode;
 459         uint16_t        regcnt_status;
 460 } __packed q80_config_rss_rsp_t;
 461
 462 /*
 463  * Configure RSS Indirection Table
 464  */
 465 #define Q8_RSS_IND_TBL_SIZE     40
 466 #define Q8_RSS_IND_TBL_MIN_IDX  0
 467 #define Q8_RSS_IND_TBL_MAX_IDX  127
 468
 469 typedef struct _q80_config_rss_ind_table {
 470         uint16_t        opcode;
 471         uint16_t        count_version;
 472         uint8_t         start_idx;
 473         uint8_t         end_idx;
 474         uint16_t        cntxt_id;
 475         uint8_t         ind_table[Q8_RSS_IND_TBL_SIZE];
 476 } __packed q80_config_rss_ind_table_t;
 477
 478 typedef struct _q80_config_rss_ind_table_rsp {
 479         uint16_t        opcode;
 480         uint16_t        regcnt_status;
 481 } __packed q80_config_rss_ind_table_rsp_t;
 482
 483 /*
 484  * Configure Interrupt Coalescing and Generation
 485  */
 486 typedef struct _q80_config_intr_coalesc {
 487         uint16_t        opcode;
 488         uint16_t        count_version;
 489         uint16_t        flags;
 490 #define Q8_MBX_INTRC_FLAGS_RCV          1
 491 #define Q8_MBX_INTRC_FLAGS_XMT          2
 492 #define Q8_MBX_INTRC_FLAGS_PERIODIC     (1 << 3)
 493
 494         uint16_t        cntxt_id;
 495         uint16_t        max_pkts;
 496         uint16_t        max_mswait;
 497         uint8_t         timer_type;
 498 #define Q8_MBX_INTRC_TIMER_NONE                 0
 499 #define Q8_MBX_INTRC_TIMER_SINGLE               1
 500 #define Q8_MBX_INTRC_TIMER_PERIODIC             2
 501
 502         uint16_t        sds_ring_mask;
 503
 504         uint8_t         rsrvd;
 505         uint32_t        ms_timeout;
 506 } __packed q80_config_intr_coalesc_t;
 507
 508 typedef struct _q80_config_intr_coalesc_rsp {
 509         uint16_t        opcode;
 510         uint16_t        regcnt_status;
 511 } __packed q80_config_intr_coalesc_rsp_t;
 512
 513 /*
 514  * Configure MAC Address
 515  */
 516 #define Q8_ETHER_ADDR_LEN               6
 517 typedef struct _q80_mac_addr {
 518         uint8_t         addr[Q8_ETHER_ADDR_LEN];
 519         uint16_t        vlan_tci;
 520 } __packed q80_mac_addr_t;
 521
 522 #define Q8_MAX_MAC_ADDRS        64
 523
 524 typedef struct _q80_config_mac_addr {
 525         uint16_t        opcode;
 526         uint16_t        count_version;
 527         uint8_t         cmd;
 528 #define Q8_MBX_CMAC_CMD_ADD_MAC_ADDR    1
 529 #define Q8_MBX_CMAC_CMD_DEL_MAC_ADDR    2
 530
 531 #define Q8_MBX_CMAC_CMD_CAM_BOTH        (0x0 << 6)
 532 #define Q8_MBX_CMAC_CMD_CAM_INGRESS     (0x1 << 6)
 533 #define Q8_MBX_CMAC_CMD_CAM_EGRESS      (0x2 << 6)
 534
 535         uint8_t         nmac_entries;
 536         uint16_t        cntxt_id;
 537         q80_mac_addr_t  mac_addr[Q8_MAX_MAC_ADDRS];
 538 } __packed q80_config_mac_addr_t;
 539
 540 typedef struct _q80_config_mac_addr_rsp {
 541         uint16_t        opcode;
 542         uint16_t        regcnt_status;
 543         uint8_t         cmd;
 544         uint8_t         nmac_entries;
 545         uint16_t        cntxt_id;
 546         uint32_t        status[Q8_MAX_MAC_ADDRS];
 547 } __packed q80_config_mac_addr_rsp_t;
 548
 549 /*
 550  * Configure MAC Receive Mode
 551  */
 552 typedef struct _q80_config_mac_rcv_mode {
 553         uint16_t        opcode;
 554         uint16_t        count_version;
 555
 556         uint8_t         mode;
 557 #define Q8_MBX_MAC_RCV_PROMISC_ENABLE   0x1
 558 #define Q8_MBX_MAC_ALL_MULTI_ENABLE     0x2
 559
 560         uint8_t         rsrvd;
 561         uint16_t        cntxt_id;
 562 } __packed q80_config_mac_rcv_mode_t;
 563
 564 typedef struct _q80_config_mac_rcv_mode_rsp {
 565         uint16_t        opcode;
 566         uint16_t        regcnt_status;
 567 } __packed q80_config_mac_rcv_mode_rsp_t;
 568
 569 /*
 570  * Configure Firmware Controlled LRO
 571  */
 572 typedef struct _q80_config_fw_lro {
 573         uint16_t        opcode;
 574         uint16_t        count_version;
 575
 576         uint8_t         flags;
 577 #define Q8_MBX_FW_LRO_IPV4                     0x1
 578 #define Q8_MBX_FW_LRO_IPV6                     0x2
 579 #define Q8_MBX_FW_LRO_IPV4_WO_DST_IP_CHK       0x4
 580 #define Q8_MBX_FW_LRO_IPV6_WO_DST_IP_CHK       0x8
 581 #define Q8_MBX_FW_LRO_LOW_THRESHOLD            0x10
 582
 583         uint8_t         rsrvd;
 584         uint16_t        cntxt_id;
 585
 586         uint16_t        low_threshold;
 587         uint16_t        rsrvd0;
 588 } __packed q80_config_fw_lro_t;
 589
 590 typedef struct _q80_config_fw_lro_rsp {
 591         uint16_t        opcode;
 592         uint16_t        regcnt_status;
 593 } __packed q80_config_fw_lro_rsp_t;
 594
 595 /*
 596  * Minidump mailbox commands
 597  */
 598 typedef struct _q80_config_md_templ_size {
 599         uint16_t        opcode;
 600         uint16_t        count_version;
 601 } __packed q80_config_md_templ_size_t;
 602
 603 typedef struct _q80_config_md_templ_size_rsp {
 604         uint16_t        opcode;
 605         uint16_t        regcnt_status;
 606         uint32_t        rsrvd;
 607         uint32_t        templ_size;
 608         uint32_t        templ_version;
 609 } __packed q80_config_md_templ_size_rsp_t;
 610
 611 typedef struct _q80_config_md_templ_cmd {
 612         uint16_t        opcode;
 613         uint16_t        count_version;
 614         uint64_t        buf_addr; /* physical address of buffer */
 615         uint32_t        buff_size;
 616         uint32_t        offset;
 617 } __packed q80_config_md_templ_cmd_t;
 618
 619 typedef struct _q80_config_md_templ_cmd_rsp {
 620         uint16_t        opcode;
 621         uint16_t        regcnt_status;
 622         uint32_t        rsrvd;
 623         uint32_t        templ_size;
 624         uint32_t        buff_size;
 625         uint32_t        offset;
 626 } __packed q80_config_md_templ_cmd_rsp_t;
 627
 628 /*
 629  * Hardware Configuration Commands
 630  */
 631
 632 typedef struct _q80_hw_config {
 633        uint16_t        opcode;
 634        uint16_t        count_version;
 635 #define Q8_HW_CONFIG_SET_MDIO_REG_COUNT                0x06
 636 #define Q8_HW_CONFIG_GET_MDIO_REG_COUNT                0x05
 637 #define Q8_HW_CONFIG_SET_CAM_SEARCH_MODE_COUNT 0x03
 638 #define Q8_HW_CONFIG_GET_CAM_SEARCH_MODE_COUNT 0x02
 639 #define Q8_HW_CONFIG_SET_TEMP_THRESHOLD_COUNT  0x03
 640 #define Q8_HW_CONFIG_GET_TEMP_THRESHOLD_COUNT  0x02
 641 #define Q8_HW_CONFIG_GET_ECC_COUNTS_COUNT      0x02
 642
 643        uint32_t        cmd;
 644 #define Q8_HW_CONFIG_SET_MDIO_REG              0x01
 645 #define Q8_HW_CONFIG_GET_MDIO_REG              0x02
 646 #define Q8_HW_CONFIG_SET_CAM_SEARCH_MODE       0x03
 647 #define Q8_HW_CONFIG_GET_CAM_SEARCH_MODE       0x04
 648 #define Q8_HW_CONFIG_SET_TEMP_THRESHOLD                0x07
 649 #define Q8_HW_CONFIG_GET_TEMP_THRESHOLD                0x08
 650 #define Q8_HW_CONFIG_GET_ECC_COUNTS            0x0A
 651
 652        union {
 653                struct {
 654                        uint32_t phys_port_number;
 655                        uint32_t phy_dev_addr;
 656                        uint32_t reg_addr;
 657                        uint32_t data;
 658                } set_mdio;
 659
 660                struct {
 661                        uint32_t phys_port_number;
 662                        uint32_t phy_dev_addr;
 663                        uint32_t reg_addr;
 664                } get_mdio;
 665
 666                struct {
 667                        uint32_t mode;
 668 #define Q8_HW_CONFIG_CAM_SEARCH_MODE_INTERNAL  0x1
 669 #define Q8_HW_CONFIG_CAM_SEARCH_MODE_AUTO      0x2
 670
 671                } set_cam_search_mode;
 672
 673                struct {
 674                        uint32_t value;
 675                } set_temp_threshold;
 676        } u;
 677 } __packed q80_hw_config_t;
 678
 679 typedef struct _q80_hw_config_rsp {
 680         uint16_t       opcode;
 681         uint16_t       regcnt_status;
 682
 683        union {
 684                struct {
 685                        uint32_t value;
 686                } get_mdio;
 687
 688                struct {
 689                        uint32_t mode;
 690                } get_cam_search_mode;
 691
 692                struct {
 693                        uint32_t temp_warn;
 694                        uint32_t curr_temp;
 695                        uint32_t osc_ring_rate;
 696                        uint32_t core_voltage;
 697                } get_temp_threshold;
 698
 699                struct {
 700                        uint32_t ddr_ecc_error_count;
 701                        uint32_t ocm_ecc_error_count;
 702                        uint32_t l2_dcache_ecc_error_count;
 703                        uint32_t l2_icache_ecc_error_count;
 704                        uint32_t eport_ecc_error_count;
 705                } get_ecc_counts;
 706        } u;
 707 } __packed q80_hw_config_rsp_t;
 708
 709 /*
 710  * Link Event Request Command
 711  */
 712 typedef struct _q80_link_event {
 713         uint16_t        opcode;
 714         uint16_t        count_version;
 715         uint8_t         cmd;
 716 #define Q8_LINK_EVENT_CMD_STOP_PERIODIC 0
 717 #define Q8_LINK_EVENT_CMD_ENABLE_ASYNC  1
 718
 719         uint8_t         flags;
 720 #define Q8_LINK_EVENT_FLAGS_SEND_RSP    1
 721
 722         uint16_t        cntxt_id;
 723 } __packed q80_link_event_t;
 724
 725 typedef struct _q80_link_event_rsp {
 726         uint16_t        opcode;
 727         uint16_t        regcnt_status;
 728 } __packed q80_link_event_rsp_t;
 729
 730 /*
 731  * Get Statistics Command
 732  */
 733 typedef struct _q80_rcv_stats {
 734         uint64_t        total_bytes;
 735         uint64_t        total_pkts;
 736         uint64_t        lro_pkt_count;
 737         uint64_t        sw_pkt_count;
 738         uint64_t        ip_chksum_err;
 739         uint64_t        pkts_wo_acntxts;
 740         uint64_t        pkts_dropped_no_sds_card;
 741         uint64_t        pkts_dropped_no_sds_host;
 742         uint64_t        oversized_pkts;
 743         uint64_t        pkts_dropped_no_rds;
 744         uint64_t        unxpctd_mcast_pkts;
 745         uint64_t        re1_fbq_error;
 746         uint64_t        invalid_mac_addr;
 747         uint64_t        rds_prime_trys;
 748         uint64_t        rds_prime_success;
 749         uint64_t        lro_flows_added;
 750         uint64_t        lro_flows_deleted;
 751         uint64_t        lro_flows_active;
 752         uint64_t        pkts_droped_unknown;
 753         uint64_t        pkts_cnt_oversized;
 754 } __packed q80_rcv_stats_t;
 755
 756 typedef struct _q80_xmt_stats {
 757         uint64_t        total_bytes;
 758         uint64_t        total_pkts;
 759         uint64_t        errors;
 760         uint64_t        pkts_dropped;
 761         uint64_t        switch_pkts;
 762         uint64_t        num_buffers;
 763 } __packed q80_xmt_stats_t;
 764
 765 typedef struct _q80_mac_stats {
 766         uint64_t        xmt_frames;
 767         uint64_t        xmt_bytes;
 768         uint64_t        xmt_mcast_pkts;
 769         uint64_t        xmt_bcast_pkts;
 770         uint64_t        xmt_pause_frames;
 771         uint64_t        xmt_cntrl_pkts;
 772         uint64_t        xmt_pkt_lt_64bytes;
 773         uint64_t        xmt_pkt_lt_127bytes;
 774         uint64_t        xmt_pkt_lt_255bytes;
 775         uint64_t        xmt_pkt_lt_511bytes;
 776         uint64_t        xmt_pkt_lt_1023bytes;
 777         uint64_t        xmt_pkt_lt_1518bytes;
 778         uint64_t        xmt_pkt_gt_1518bytes;
 779         uint64_t        rsrvd0[3];
 780         uint64_t        rcv_frames;
 781         uint64_t        rcv_bytes;
 782         uint64_t        rcv_mcast_pkts;
 783         uint64_t        rcv_bcast_pkts;
 784         uint64_t        rcv_pause_frames;
 785         uint64_t        rcv_cntrl_pkts;
 786         uint64_t        rcv_pkt_lt_64bytes;
 787         uint64_t        rcv_pkt_lt_127bytes;
 788         uint64_t        rcv_pkt_lt_255bytes;
 789         uint64_t        rcv_pkt_lt_511bytes;
 790         uint64_t        rcv_pkt_lt_1023bytes;
 791         uint64_t        rcv_pkt_lt_1518bytes;
 792         uint64_t        rcv_pkt_gt_1518bytes;
 793         uint64_t        rsrvd1[3];
 794         uint64_t        rcv_len_error;
 795         uint64_t        rcv_len_small;
 796         uint64_t        rcv_len_large;
 797         uint64_t        rcv_jabber;
 798         uint64_t        rcv_dropped;
 799         uint64_t        fcs_error;
 800         uint64_t        align_error;
 801         uint64_t        eswitched_frames;
 802         uint64_t        eswitched_bytes;
 803         uint64_t        eswitched_mcast_frames;
 804         uint64_t        eswitched_bcast_frames;
 805         uint64_t        eswitched_ucast_frames;
 806         uint64_t        eswitched_err_free_frames;
 807         uint64_t        eswitched_err_free_bytes;
 808 } __packed q80_mac_stats_t;
 809
 810 typedef struct _q80_get_stats {
 811         uint16_t        opcode;
 812         uint16_t        count_version;
 813
 814         uint32_t        cmd;
 815 #define Q8_GET_STATS_CMD_CLEAR          0x01
 816 #define Q8_GET_STATS_CMD_RCV            0x00
 817 #define Q8_GET_STATS_CMD_XMT            0x02
 818 #define Q8_GET_STATS_CMD_TYPE_CNTXT     0x00
 819 #define Q8_GET_STATS_CMD_TYPE_MAC       0x04
 820 #define Q8_GET_STATS_CMD_TYPE_FUNC      0x08
 821 #define Q8_GET_STATS_CMD_TYPE_VPORT     0x0C
 822 #define Q8_GET_STATS_CMD_TYPE_ALL      (0x7 << 2)
 823
 824 } __packed q80_get_stats_t;
 825
 826 typedef struct _q80_get_stats_rsp {
 827         uint16_t        opcode;
 828         uint16_t        regcnt_status;
 829         uint32_t        cmd;
 830         union {
 831                 q80_rcv_stats_t rcv;
 832                 q80_xmt_stats_t xmt;
 833                 q80_mac_stats_t mac;
 834         } u;
 835 } __packed q80_get_stats_rsp_t;
 836
 837 typedef struct _q80_get_mac_rcv_xmt_stats_rsp {
 838         uint16_t        opcode;
 839         uint16_t        regcnt_status;
 840         uint32_t        cmd;
 841         q80_mac_stats_t mac;
 842         q80_rcv_stats_t rcv;
 843         q80_xmt_stats_t xmt;
 844 } __packed q80_get_mac_rcv_xmt_stats_rsp_t;
 845
 846 /*
 847  * Init NIC Function
 848  * Used to Register DCBX Configuration Change AEN
 849  */
 850 typedef struct _q80_init_nic_func {
 851         uint16_t        opcode;
 852         uint16_t        count_version;
 853
 854         uint32_t        options;
 855 #define Q8_INIT_NIC_REG_IDC_AEN         0x01
 856 #define Q8_INIT_NIC_REG_DCBX_CHNG_AEN   0x02
 857 #define Q8_INIT_NIC_REG_SFP_CHNG_AEN    0x04
 858
 859 } __packed q80_init_nic_func_t;
 860
 861 typedef struct _q80_init_nic_func_rsp {
 862         uint16_t        opcode;
 863         uint16_t        regcnt_status;
 864 } __packed q80_init_nic_func_rsp_t;
 865
 866 /*
 867  * Stop NIC Function
 868  * Used to DeRegister DCBX Configuration Change AEN
 869  */
 870 typedef struct _q80_stop_nic_func {
 871         uint16_t        opcode;
 872         uint16_t        count_version;
 873
 874         uint32_t        options;
 875 #define Q8_STOP_NIC_DEREG_DCBX_CHNG_AEN 0x02
 876 #define Q8_STOP_NIC_DEREG_SFP_CHNG_AEN  0x04
 877
 878 } __packed q80_stop_nic_func_t;
 879
 880 typedef struct _q80_stop_nic_func_rsp {
 881         uint16_t        opcode;
 882         uint16_t        regcnt_status;
 883 } __packed q80_stop_nic_func_rsp_t;
 884
 885 /*
 886  * Query Firmware DCBX Capabilities
 887  */
 888 typedef struct _q80_query_fw_dcbx_caps {
 889         uint16_t        opcode;
 890         uint16_t        count_version;
 891 } __packed q80_query_fw_dcbx_caps_t;
 892
 893 typedef struct _q80_query_fw_dcbx_caps_rsp {
 894         uint16_t        opcode;
 895         uint16_t        regcnt_status;
 896
 897         uint32_t        dcbx_caps;
 898 #define Q8_QUERY_FW_DCBX_CAPS_TSA               0x00000001
 899 #define Q8_QUERY_FW_DCBX_CAPS_ETS               0x00000002
 900 #define Q8_QUERY_FW_DCBX_CAPS_DCBX_CEE_1_01     0x00000004
 901 #define Q8_QUERY_FW_DCBX_CAPS_DCBX_IEEE_1_0     0x00000008
 902 #define Q8_QUERY_FW_DCBX_MAX_TC_MASK            0x00F00000
 903 #define Q8_QUERY_FW_DCBX_MAX_ETS_TC_MASK        0x0F000000
 904 #define Q8_QUERY_FW_DCBX_MAX_PFC_TC_MASK        0xF0000000
 905
 906 } __packed q80_query_fw_dcbx_caps_rsp_t;
 907
 908 /*
 909  * IDC Ack Cmd
 910  */
 911
 912 typedef struct _q80_idc_ack {
 913         uint16_t        opcode;
 914         uint16_t        count_version;
 915
 916         uint32_t        aen_mb1;
 917         uint32_t        aen_mb2;
 918         uint32_t        aen_mb3;
 919         uint32_t        aen_mb4;
 920
 921 } __packed q80_idc_ack_t;
 922
 923 typedef struct _q80_idc_ack_rsp {
 924         uint16_t        opcode;
 925         uint16_t        regcnt_status;
 926 } __packed q80_idc_ack_rsp_t;
 927
 928
 929 /*
 930  * Set Port Configuration command
 931  * Used to set Ethernet Standard Pause values
 932  */
 933
 934 typedef struct _q80_set_port_cfg {
 935         uint16_t        opcode;
 936         uint16_t        count_version;
 937
 938         uint32_t        cfg_bits;
 939
 940 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_MASK     (0x7 << 1)
 941 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_NONE     (0x0 << 1)
 942 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_HSS      (0x2 << 1)
 943 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_PHY      (0x3 << 1)
 944 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_EXT      (0x4 << 1)
 945
 946 #define Q8_VALID_LOOPBACK_MODE(mode) \
 947              (((mode) == Q8_PORT_CFG_BITS_LOOPBACK_MODE_NONE) || \
 948                 (((mode) >= Q8_PORT_CFG_BITS_LOOPBACK_MODE_HSS) && \
 949                  ((mode) <= Q8_PORT_CFG_BITS_LOOPBACK_MODE_EXT)))
 950
 951 #define Q8_PORT_CFG_BITS_DCBX_ENABLE            BIT_4
 952
 953 #define Q8_PORT_CFG_BITS_PAUSE_CFG_MASK         (0x3 << 5)
 954 #define Q8_PORT_CFG_BITS_PAUSE_DISABLED         (0x0 << 5)
 955 #define Q8_PORT_CFG_BITS_PAUSE_STD              (0x1 << 5)
 956 #define Q8_PORT_CFG_BITS_PAUSE_PPM              (0x2 << 5)
 957
 958 #define Q8_PORT_CFG_BITS_LNKCAP_10MB            BIT_8
 959 #define Q8_PORT_CFG_BITS_LNKCAP_100MB           BIT_9
 960 #define Q8_PORT_CFG_BITS_LNKCAP_1GB             BIT_10
 961 #define Q8_PORT_CFG_BITS_LNKCAP_10GB            BIT_11
 962
 963 #define Q8_PORT_CFG_BITS_AUTONEG                BIT_15
 964 #define Q8_PORT_CFG_BITS_XMT_DISABLE            BIT_17
 965 #define Q8_PORT_CFG_BITS_FEC_RQSTD              BIT_18
 966 #define Q8_PORT_CFG_BITS_EEE_RQSTD              BIT_19
 967
 968 #define Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK      (0x3 << 20)
 969 #define Q8_PORT_CFG_BITS_STDPAUSE_XMT_RCV       (0x0 << 20)
 970 #define Q8_PORT_CFG_BITS_STDPAUSE_XMT           (0x1 << 20)
 971 #define Q8_PORT_CFG_BITS_STDPAUSE_RCV           (0x2 << 20)
 972
 973 } __packed q80_set_port_cfg_t;
 974
 975 typedef struct _q80_set_port_cfg_rsp {
 976         uint16_t        opcode;
 977         uint16_t        regcnt_status;
 978 } __packed q80_set_port_cfg_rsp_t;
 979
 980 /*
 981  * Get Port Configuration Command
 982  */
 983
 984 typedef struct _q80_get_port_cfg {
 985         uint16_t        opcode;
 986         uint16_t        count_version;
 987 } __packed q80_get_port_cfg_t;
 988
 989 typedef struct _q80_get_port_cfg_rsp {
 990         uint16_t        opcode;
 991         uint16_t        regcnt_status;
 992
 993         uint32_t        cfg_bits; /* same as in q80_set_port_cfg_t */
 994
 995         uint8_t         phys_port_type;
 996         uint8_t         rsvd[3];
 997 } __packed q80_get_port_cfg_rsp_t;
 998
 999 /*
1000  * Get Link Status Command
1001  * Used to get current PAUSE values for the port
1002  */
1003
1004 typedef struct _q80_get_link_status {
1005         uint16_t        opcode;
1006         uint16_t        count_version;
1007 } __packed q80_get_link_status_t;
1008
1009 typedef struct _q80_get_link_status_rsp {
1010         uint16_t        opcode;
1011         uint16_t        regcnt_status;
1012
1013         uint32_t        cfg_bits;
1014 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_UP               BIT_0
1015
1016 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_MASK       (0x7 << 3)
1017 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_UNKNOWN    (0x0 << 3)
1018 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_10MB       (0x1 << 3)
1019 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_100MB      (0x2 << 3)
1020 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_1GB        (0x3 << 3)
1021 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_10GB       (0x4 << 3)
1022
1023 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_MASK        (0x3 << 6)
1024 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_DISABLE     (0x0 << 6)
1025 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_STD         (0x1 << 6)
1026 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_PPM         (0x2 << 6)
1027
1028 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_MASK         (0x7 << 8)
1029 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_NONE         (0x0 << 6)
1030 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_HSS          (0x2 << 6)
1031 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_PHY          (0x3 << 6)
1032
1033 #define Q8_GET_LINK_STAT_CFG_BITS_FEC_ENABLED           BIT_12
1034 #define Q8_GET_LINK_STAT_CFG_BITS_EEE_ENABLED           BIT_13
1035
1036 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_DIR_MASK     (0x3 << 20)
1037 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_NONE         (0x0 << 20)
1038 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_XMT          (0x1 << 20)
1039 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_RCV          (0x2 << 20)
1040 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_XMT_RCV      (0x3 << 20)
1041
1042         uint32_t        link_state;
1043 #define Q8_GET_LINK_STAT_LOSS_OF_SIGNAL                 BIT_0
1044 #define Q8_GET_LINK_STAT_PORT_RST_DONE                  BIT_3
1045 #define Q8_GET_LINK_STAT_PHY_LINK_DOWN                  BIT_4
1046 #define Q8_GET_LINK_STAT_PCS_LINK_DOWN                  BIT_5
1047 #define Q8_GET_LINK_STAT_MAC_LOCAL_FAULT                BIT_6
1048 #define Q8_GET_LINK_STAT_MAC_REMOTE_FAULT               BIT_7
1049 #define Q8_GET_LINK_STAT_XMT_DISABLED                   BIT_9
1050 #define Q8_GET_LINK_STAT_SFP_XMT_FAULT                  BIT_10
1051
1052         uint32_t        sfp_info;
1053 #define Q8_GET_LINK_STAT_SFP_TRNCVR_MASK                0x3
1054 #define Q8_GET_LINK_STAT_SFP_TRNCVR_NOT_EXPECTED        0x0
1055 #define Q8_GET_LINK_STAT_SFP_TRNCVR_NONE                0x1
1056 #define Q8_GET_LINK_STAT_SFP_TRNCVR_INVALID             0x2
1057 #define Q8_GET_LINK_STAT_SFP_TRNCVR_VALID               0x3
1058
1059 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_MASK            (0x3 << 2)
1060 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_UNREC_TRSVR     (0x0 << 2)
1061 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_NOT_QLOGIC      (0x1 << 2)
1062 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_SPEED_FAILED    (0x2 << 2)
1063 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_ACCESS_ERROR    (0x3 << 2)
1064
1065 #define Q8_GET_LINK_STAT_SFP_MOD_TYPE_MASK              (0x1F << 4)
1066 #define Q8_GET_LINK_STAT_SFP_MOD_NONE                   (0x00 << 4)
1067 #define Q8_GET_LINK_STAT_SFP_MOD_10GBLRM                (0x01 << 4)
1068 #define Q8_GET_LINK_STAT_SFP_MOD_10GBLR                 (0x02 << 4)
1069 #define Q8_GET_LINK_STAT_SFP_MOD_10GBSR                 (0x03 << 4)
1070 #define Q8_GET_LINK_STAT_SFP_MOD_10GBC_P                (0x04 << 4)
1071 #define Q8_GET_LINK_STAT_SFP_MOD_10GBC_AL               (0x05 << 4)
1072 #define Q8_GET_LINK_STAT_SFP_MOD_10GBC_PL               (0x06 << 4)
1073 #define Q8_GET_LINK_STAT_SFP_MOD_1GBSX                  (0x07 << 4)
1074 #define Q8_GET_LINK_STAT_SFP_MOD_1GBLX                  (0x08 << 4)
1075 #define Q8_GET_LINK_STAT_SFP_MOD_1GBCX                  (0x09 << 4)
1076 #define Q8_GET_LINK_STAT_SFP_MOD_1GBT                   (0x0A << 4)
1077 #define Q8_GET_LINK_STAT_SFP_MOD_1GBC_PL                (0x0B << 4)
1078 #define Q8_GET_LINK_STAT_SFP_MOD_UNKNOWN                (0x0F << 4)
1079
1080 #define Q8_GET_LINK_STAT_SFP_MULTI_RATE_MOD             BIT_9
1081 #define Q8_GET_LINK_STAT_SFP_XMT_FAULT                  BIT_10
1082 #define Q8_GET_LINK_STAT_SFP_COPPER_CBL_LENGTH_MASK     (0xFF << 16)
1083
1084 } __packed q80_get_link_status_rsp_t;
1085
1086
1087 /*
1088  * Transmit Related Definitions
1089  */
1090 /* Max# of TX Rings per Tx Create Cntxt Mbx Cmd*/
1091 #define MAX_TCNTXT_RINGS           8
1092
1093 /*
1094  * Transmit Context - Q8_CMD_CREATE_TX_CNTXT Command Configuration Data
1095  */
1096
1097 typedef struct _q80_rq_tx_ring {
1098         uint64_t        paddr;
1099         uint64_t        tx_consumer;
1100         uint16_t        nentries;
1101         uint16_t        intr_id;
1102         uint8_t         intr_src_bit;
1103         uint8_t         rsrvd[3];
1104 } __packed q80_rq_tx_ring_t;
1105
1106 typedef struct _q80_rq_tx_cntxt {
1107         uint16_t                opcode;
1108         uint16_t                count_version;
1109
1110         uint32_t                cap0;
1111 #define Q8_TX_CNTXT_CAP0_BASEFW         (1 << 0)
1112 #define Q8_TX_CNTXT_CAP0_LSO            (1 << 6)
1113 #define Q8_TX_CNTXT_CAP0_TC             (1 << 25)
1114
1115         uint32_t                cap1;
1116         uint32_t                cap2;
1117         uint32_t                cap3;
1118         uint8_t                 ntx_rings;
1119         uint8_t                 traffic_class; /* bits 8-10; others reserved */
1120         uint16_t                tx_vpid;
1121         q80_rq_tx_ring_t        tx_ring[MAX_TCNTXT_RINGS];
1122 } __packed q80_rq_tx_cntxt_t;
1123
1124 typedef struct _q80_rsp_tx_ring {
1125         uint32_t                prod_index;
1126         uint16_t                cntxt_id;
1127         uint8_t                 state;
1128         uint8_t                 rsrvd;
1129 } q80_rsp_tx_ring_t;
1130
1131 typedef struct _q80_rsp_tx_cntxt {
1132         uint16_t                opcode;
1133         uint16_t                regcnt_status;
1134         uint8_t                 ntx_rings;
1135         uint8_t                 phy_port;
1136         uint8_t                 virt_port;
1137         uint8_t                 rsrvd;
1138         q80_rsp_tx_ring_t       tx_ring[MAX_TCNTXT_RINGS];
1139 } __packed q80_rsp_tx_cntxt_t;
1140
1141 typedef struct _q80_tx_cntxt_destroy {
1142         uint16_t        opcode;
1143         uint16_t        count_version;
1144         uint32_t        cntxt_id;
1145 } __packed q80_tx_cntxt_destroy_t;
1146
1147 typedef struct _q80_tx_cntxt_destroy_rsp {
1148         uint16_t        opcode;
1149         uint16_t        regcnt_status;
1150 } __packed q80_tx_cntxt_destroy_rsp_t;
1151
1152 /*
1153  * Transmit Command Descriptor
1154  * These commands are issued on the Transmit Ring associated with a Transmit
1155  * context
1156  */
1157 typedef struct _q80_tx_cmd {
1158         uint8_t         tcp_hdr_off;    /* TCP Header Offset */
1159         uint8_t         ip_hdr_off;     /* IP Header Offset */
1160         uint16_t        flags_opcode;   /* Bits 0-6: flags; 7-12: opcode */
1161
1162         /* flags field */
1163 #define Q8_TX_CMD_FLAGS_MULTICAST       0x01
1164 #define Q8_TX_CMD_FLAGS_LSO_TSO         0x02
1165 #define Q8_TX_CMD_FLAGS_VLAN_TAGGED     0x10
1166 #define Q8_TX_CMD_FLAGS_HW_VLAN_ID      0x40
1167
1168         /* opcode field */
1169 #define Q8_TX_CMD_OP_XMT_UDP_CHKSUM_IPV6        (0xC << 7)
1170 #define Q8_TX_CMD_OP_XMT_TCP_CHKSUM_IPV6        (0xB << 7)
1171 #define Q8_TX_CMD_OP_XMT_TCP_LSO_IPV6           (0x6 << 7)
1172 #define Q8_TX_CMD_OP_XMT_TCP_LSO                (0x5 << 7)
1173 #define Q8_TX_CMD_OP_XMT_UDP_CHKSUM             (0x3 << 7)
1174 #define Q8_TX_CMD_OP_XMT_TCP_CHKSUM             (0x2 << 7)
1175 #define Q8_TX_CMD_OP_XMT_ETHER                  (0x1 << 7)
1176
1177         uint8_t         n_bufs;         /* # of data segs in data buffer */
1178         uint8_t         data_len_lo;    /* data length lower 8 bits */
1179         uint16_t        data_len_hi;    /* data length upper 16 bits */
1180
1181         uint64_t        buf2_addr;      /* buffer 2 address */
1182
1183         uint16_t        rsrvd0;
1184         uint16_t        mss;            /* MSS for this packet */
1185         uint8_t         cntxtid;        /* Bits 7-4: ContextId; 3-0: reserved */
1186
1187 #define Q8_TX_CMD_PORT_CNXTID(c_id) ((c_id & 0xF) << 4)
1188
1189         uint8_t         total_hdr_len;  /* MAC+IP+TCP Header Length for LSO */
1190         uint16_t        rsrvd1;
1191
1192         uint64_t        buf3_addr;      /* buffer 3 address */
1193         uint64_t        buf1_addr;      /* buffer 1 address */
1194
1195         uint16_t        buf1_len;       /* length of buffer 1 */
1196         uint16_t        buf2_len;       /* length of buffer 2 */
1197         uint16_t        buf3_len;       /* length of buffer 3 */
1198         uint16_t        buf4_len;       /* length of buffer 4 */
1199
1200         uint64_t        buf4_addr;      /* buffer 4 address */
1201
1202         uint32_t        rsrvd2;
1203         uint16_t        rsrvd3;
1204         uint16_t        vlan_tci;       /* VLAN TCI when hw tagging is enabled*/
1205
1206 } __packed q80_tx_cmd_t; /* 64 bytes */
1207
1208 #define Q8_TX_CMD_MAX_SEGMENTS          4
1209 #define Q8_TX_CMD_TSO_ALIGN             2
1210 #define Q8_TX_MAX_NON_TSO_SEGS          62
1211
1212
1213 /*
1214  * Receive Related Definitions
1215  */
1216 #define MAX_RDS_RING_SETS       8 /* Max# of Receive Descriptor Rings */
1217
1218 #ifdef QL_ENABLE_ISCSI_TLV
1219 #define MAX_SDS_RINGS           32 /* Max# of Status Descriptor Rings */
1220 #define NUM_TX_RINGS            (MAX_SDS_RINGS * 2)
1221 #else
1222 #define MAX_SDS_RINGS           32 /* Max# of Status Descriptor Rings */
1223 #define NUM_TX_RINGS            MAX_SDS_RINGS
1224 #endif /* #ifdef QL_ENABLE_ISCSI_TLV */
1225 #define MAX_RDS_RINGS           MAX_SDS_RINGS /* Max# of Rcv Descriptor Rings */
1226
1227
1228 typedef struct _q80_rq_sds_ring {
1229         uint64_t paddr; /* physical addr of status ring in system memory */
1230         uint64_t hdr_split1;
1231         uint64_t hdr_split2;
1232         uint16_t size; /* number of entries in status ring */
1233         uint16_t hdr_split1_size;
1234         uint16_t hdr_split2_size;
1235         uint16_t hdr_split_count;
1236         uint16_t intr_id;
1237         uint8_t  intr_src_bit;
1238         uint8_t  rsrvd[5];
1239 } __packed q80_rq_sds_ring_t; /* 10 32bit words */
1240
1241 typedef struct _q80_rq_rds_ring {
1242         uint64_t paddr_std;     /* physical addr of rcv ring in system memory */
1243         uint64_t paddr_jumbo;   /* physical addr of rcv ring in system memory */
1244         uint16_t std_bsize;
1245         uint16_t std_nentries;
1246         uint16_t jumbo_bsize;
1247         uint16_t jumbo_nentries;
1248 } __packed q80_rq_rds_ring_t; /* 6 32bit words */
1249
1250 #define MAX_RCNTXT_SDS_RINGS    8
1251
1252 typedef struct _q80_rq_rcv_cntxt {
1253         uint16_t                opcode;
1254         uint16_t                count_version;
1255         uint32_t                cap0;
1256 #define Q8_RCV_CNTXT_CAP0_BASEFW        (1 << 0)
1257 #define Q8_RCV_CNTXT_CAP0_MULTI_RDS     (1 << 1)
1258 #define Q8_RCV_CNTXT_CAP0_LRO           (1 << 5)
1259 #define Q8_RCV_CNTXT_CAP0_HW_LRO        (1 << 10)
1260 #define Q8_RCV_CNTXT_CAP0_VLAN_ALIGN    (1 << 14)
1261 #define Q8_RCV_CNTXT_CAP0_RSS           (1 << 15)
1262 #define Q8_RCV_CNTXT_CAP0_MSFT_RSS      (1 << 16)
1263 #define Q8_RCV_CNTXT_CAP0_SGL_JUMBO     (1 << 18)
1264 #define Q8_RCV_CNTXT_CAP0_SGL_LRO       (1 << 19)
1265 #define Q8_RCV_CNTXT_CAP0_SINGLE_JUMBO  (1 << 26)
1266
1267         uint32_t                cap1;
1268         uint32_t                cap2;
1269         uint32_t                cap3;
1270         uint8_t                 nrds_sets_rings;
1271         uint8_t                 nsds_rings;
1272         uint16_t                rds_producer_mode;
1273 #define Q8_RCV_CNTXT_RDS_PROD_MODE_UNIQUE       0
1274 #define Q8_RCV_CNTXT_RDS_PROD_MODE_SHARED       1
1275
1276         uint16_t                rcv_vpid;
1277         uint16_t                rsrvd0;
1278         uint32_t                rsrvd1;
1279         q80_rq_sds_ring_t       sds[MAX_RCNTXT_SDS_RINGS];
1280         q80_rq_rds_ring_t       rds[MAX_RDS_RING_SETS];
1281 } __packed q80_rq_rcv_cntxt_t;
1282
1283 typedef struct _q80_rsp_rds_ring {
1284         uint32_t prod_std;
1285         uint32_t prod_jumbo;
1286 } __packed q80_rsp_rds_ring_t; /* 8 bytes */
1287
1288 typedef struct _q80_rsp_rcv_cntxt {
1289         uint16_t                opcode;
1290         uint16_t                regcnt_status;
1291         uint8_t                 nrds_sets_rings;
1292         uint8_t                 nsds_rings;
1293         uint16_t                cntxt_id;
1294         uint8_t                 state;
1295         uint8_t                 num_funcs;
1296         uint8_t                 phy_port;
1297         uint8_t                 virt_port;
1298         uint32_t                sds_cons[MAX_RCNTXT_SDS_RINGS];
1299         q80_rsp_rds_ring_t      rds[MAX_RDS_RING_SETS];
1300 } __packed q80_rsp_rcv_cntxt_t;
1301
1302 typedef struct _q80_rcv_cntxt_destroy {
1303         uint16_t        opcode;
1304         uint16_t        count_version;
1305         uint32_t        cntxt_id;
1306 } __packed q80_rcv_cntxt_destroy_t;
1307
1308 typedef struct _q80_rcv_cntxt_destroy_rsp {
1309         uint16_t        opcode;
1310         uint16_t        regcnt_status;
1311 } __packed q80_rcv_cntxt_destroy_rsp_t;
1312
1313
1314 /*
1315  * Add Receive Rings
1316  */
1317 typedef struct _q80_rq_add_rcv_rings {
1318         uint16_t                opcode;
1319         uint16_t                count_version;
1320         uint8_t                 nrds_sets_rings;
1321         uint8_t                 nsds_rings;
1322         uint16_t                cntxt_id;
1323         q80_rq_sds_ring_t       sds[MAX_RCNTXT_SDS_RINGS];
1324         q80_rq_rds_ring_t       rds[MAX_RDS_RING_SETS];
1325 } __packed q80_rq_add_rcv_rings_t;
1326
1327 typedef struct _q80_rsp_add_rcv_rings {
1328         uint16_t                opcode;
1329         uint16_t                regcnt_status;
1330         uint8_t                 nrds_sets_rings;
1331         uint8_t                 nsds_rings;
1332         uint16_t                cntxt_id;
1333         uint32_t                sds_cons[MAX_RCNTXT_SDS_RINGS];
1334         q80_rsp_rds_ring_t      rds[MAX_RDS_RING_SETS];
1335 } __packed q80_rsp_add_rcv_rings_t;
1336
1337 /*
1338  * Map Status Ring to Receive Descriptor Set
1339  */
1340
1341 #define MAX_SDS_TO_RDS_MAP      16
1342
1343 typedef struct _q80_sds_rds_map_e {
1344         uint8_t sds_ring;
1345         uint8_t rsrvd0;
1346         uint8_t rds_ring;
1347         uint8_t rsrvd1;
1348 } __packed q80_sds_rds_map_e_t;
1349
1350 typedef struct _q80_rq_map_sds_to_rds {
1351         uint16_t                opcode;
1352         uint16_t                count_version;
1353         uint16_t                cntxt_id;
1354         uint16_t                num_rings;
1355         q80_sds_rds_map_e_t     sds_rds[MAX_SDS_TO_RDS_MAP];
1356 } __packed q80_rq_map_sds_to_rds_t;
1357
1358
1359 typedef struct _q80_rsp_map_sds_to_rds {
1360         uint16_t                opcode;
1361         uint16_t                regcnt_status;
1362         uint16_t                cntxt_id;
1363         uint16_t                num_rings;
1364         q80_sds_rds_map_e_t     sds_rds[MAX_SDS_TO_RDS_MAP];
1365 } __packed q80_rsp_map_sds_to_rds_t;
1366
1367
1368 /*
1369  * Receive Descriptor corresponding to each entry in the receive ring
1370  */
1371 typedef struct _q80_rcv_desc {
1372         uint16_t handle;
1373         uint16_t rsrvd;
1374         uint32_t buf_size; /* buffer size in bytes */
1375         uint64_t buf_addr; /* physical address of buffer */
1376 } __packed q80_recv_desc_t;
1377
1378 /*
1379  * Status Descriptor corresponding to each entry in the Status ring
1380  */
1381 typedef struct _q80_stat_desc {
1382         uint64_t data[2];
1383 } __packed q80_stat_desc_t;
1384
1385 /*
1386  * definitions for data[0] field of Status Descriptor
1387  */
1388 #define Q8_STAT_DESC_RSS_HASH(data)             (data & 0xFFFFFFFF)
1389 #define Q8_STAT_DESC_TOTAL_LENGTH(data)         ((data >> 32) & 0x3FFF)
1390 #define Q8_STAT_DESC_TOTAL_LENGTH_SGL_RCV(data) ((data >> 32) & 0xFFFF)
1391 #define Q8_STAT_DESC_HANDLE(data)               ((data >> 48) & 0xFFFF)
1392 /*
1393  * definitions for data[1] field of Status Descriptor
1394  */
1395
1396 #define Q8_STAT_DESC_OPCODE(data)               ((data >> 42) & 0xF)
1397 #define         Q8_STAT_DESC_OPCODE_RCV_PKT             0x01
1398 #define         Q8_STAT_DESC_OPCODE_LRO_PKT             0x02
1399 #define         Q8_STAT_DESC_OPCODE_SGL_LRO             0x04
1400 #define         Q8_STAT_DESC_OPCODE_SGL_RCV             0x05
1401 #define         Q8_STAT_DESC_OPCODE_CONT                0x06
1402
1403 /*
1404  * definitions for data[1] field of Status Descriptor for standard frames
1405  * status descriptor opcode equals 0x04
1406  */
1407 #define Q8_STAT_DESC_STATUS(data)               ((data >> 39) & 0x0007)
1408 #define         Q8_STAT_DESC_STATUS_CHKSUM_NOT_DONE     0x00
1409 #define         Q8_STAT_DESC_STATUS_NO_CHKSUM           0x01
1410 #define         Q8_STAT_DESC_STATUS_CHKSUM_OK           0x02
1411 #define         Q8_STAT_DESC_STATUS_CHKSUM_ERR          0x03
1412
1413 #define Q8_STAT_DESC_VLAN(data)                 ((data >> 47) & 1)
1414 #define Q8_STAT_DESC_VLAN_ID(data)              ((data >> 48) & 0xFFFF)
1415
1416 #define Q8_STAT_DESC_PROTOCOL(data)             ((data >> 44) & 0x000F)
1417 #define Q8_STAT_DESC_L2_OFFSET(data)            ((data >> 48) & 0x001F)
1418 #define Q8_STAT_DESC_COUNT(data)                ((data >> 37) & 0x0007)
1419
1420 /*
1421  * definitions for data[0-1] fields of Status Descriptor for LRO
1422  * status descriptor opcode equals 0x04
1423  */
1424
1425 /* definitions for data[1] field */
1426 #define Q8_LRO_STAT_DESC_SEQ_NUM(data)          (uint32_t)(data)
1427
1428 /*
1429  * definitions specific to opcode 0x04 data[1]
1430  */
1431 #define Q8_STAT_DESC_COUNT_SGL_LRO(data)        ((data >> 13) & 0x0007)
1432 #define Q8_SGL_LRO_STAT_L2_OFFSET(data)         ((data >> 16) & 0xFF)
1433 #define Q8_SGL_LRO_STAT_L4_OFFSET(data)         ((data >> 24) & 0xFF)
1434 #define Q8_SGL_LRO_STAT_TS(data)                ((data >> 40) & 0x1)
1435 #define Q8_SGL_LRO_STAT_PUSH_BIT(data)          ((data >> 41) & 0x1)
1436
1437
1438 /*
1439  * definitions specific to opcode 0x05 data[1]
1440  */
1441 #define Q8_STAT_DESC_COUNT_SGL_RCV(data)        ((data >> 37) & 0x0003)
1442
1443 /*
1444  * definitions for opcode 0x06
1445  */
1446 /* definitions for data[0] field */
1447 #define Q8_SGL_STAT_DESC_HANDLE1(data)          (data & 0xFFFF)
1448 #define Q8_SGL_STAT_DESC_HANDLE2(data)          ((data >> 16) & 0xFFFF)
1449 #define Q8_SGL_STAT_DESC_HANDLE3(data)          ((data >> 32) & 0xFFFF)
1450 #define Q8_SGL_STAT_DESC_HANDLE4(data)          ((data >> 48) & 0xFFFF)
1451
1452 /* definitions for data[1] field */
1453 #define Q8_SGL_STAT_DESC_HANDLE5(data)          (data & 0xFFFF)
1454 #define Q8_SGL_STAT_DESC_HANDLE6(data)          ((data >> 16) & 0xFFFF)
1455 #define Q8_SGL_STAT_DESC_NUM_HANDLES(data)      ((data >> 32) & 0x7)
1456 #define Q8_SGL_STAT_DESC_HANDLE7(data)          ((data >> 48) & 0xFFFF)
1457
1458 /** Driver Related Definitions Begin **/
1459
1460 #define TX_SMALL_PKT_SIZE       128 /* size in bytes of small packets */
1461
1462 /* The number of descriptors should be a power of 2 */
1463 #define NUM_TX_DESCRIPTORS              1024
1464 #define NUM_STATUS_DESCRIPTORS          1024
1465
1466
1467 #define NUM_RX_DESCRIPTORS      2048
1468
1469 /*
1470  * structure describing various dma buffers
1471  */
1472
1473 typedef struct qla_dmabuf {
1474         volatile struct {
1475                 uint32_t        tx_ring         :1,
1476                                 rds_ring        :1,
1477                                 sds_ring        :1,
1478                                 minidump        :1;
1479         } flags;
1480
1481         qla_dma_t               tx_ring;
1482         qla_dma_t               rds_ring[MAX_RDS_RINGS];
1483         qla_dma_t               sds_ring[MAX_SDS_RINGS];
1484         qla_dma_t               minidump;
1485 } qla_dmabuf_t;
1486
1487 typedef struct _qla_sds {
1488         q80_stat_desc_t *sds_ring_base; /* start of sds ring */
1489         uint32_t        sdsr_next; /* next entry in SDS ring to process */
1490         struct lro_ctrl lro;
1491         void            *rxb_free;
1492         uint32_t        rx_free;
1493         volatile uint32_t rcv_active;
1494         uint32_t        sds_consumer;
1495         uint64_t        intr_count;
1496         uint64_t        spurious_intr_count;
1497 } qla_sds_t;
1498
1499 #define Q8_MAX_LRO_CONT_DESC    7
1500 #define Q8_MAX_HANDLES_LRO      (1 + (Q8_MAX_LRO_CONT_DESC * 7))
1501 #define Q8_MAX_HANDLES_NON_LRO  8
1502
1503 typedef struct _qla_sgl_rcv {
1504         uint16_t        pkt_length;
1505         uint16_t        num_handles;
1506         uint16_t        chksum_status;
1507         uint32_t        rss_hash;
1508         uint16_t        rss_hash_flags;
1509         uint16_t        vlan_tag;
1510         uint16_t        handle[Q8_MAX_HANDLES_NON_LRO];
1511 } qla_sgl_rcv_t;
1512
1513 typedef struct _qla_sgl_lro {
1514         uint16_t        flags;
1515 #define Q8_LRO_COMP_TS          0x1
1516 #define Q8_LRO_COMP_PUSH_BIT    0x2
1517         uint16_t        l2_offset;
1518         uint16_t        l4_offset;
1519
1520         uint16_t        payload_length;
1521         uint16_t        num_handles;
1522         uint32_t        rss_hash;
1523         uint16_t        rss_hash_flags;
1524         uint16_t        vlan_tag;
1525         uint16_t        handle[Q8_MAX_HANDLES_LRO];
1526 } qla_sgl_lro_t;
1527
1528 typedef union {
1529         qla_sgl_rcv_t   rcv;
1530         qla_sgl_lro_t   lro;
1531 } qla_sgl_comp_t;
1532
1533 #define QL_FRAME_HDR_SIZE (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +\
1534                 sizeof (struct ip6_hdr) + sizeof (struct tcphdr) + 16)
1535
1536 typedef struct _qla_hw_tx_cntxt {
1537         q80_tx_cmd_t    *tx_ring_base;
1538         bus_addr_t      tx_ring_paddr;
1539
1540         volatile uint32_t *tx_cons; /* tx consumer shadow reg */
1541         bus_addr_t      tx_cons_paddr;
1542
1543         volatile uint32_t txr_free; /* # of free entries in tx ring */
1544         volatile uint32_t txr_next; /* # next available tx ring entry */
1545         volatile uint32_t txr_comp; /* index of last tx entry completed */
1546
1547         uint32_t        tx_prod_reg;
1548         uint16_t        tx_cntxt_id;
1549
1550 } qla_hw_tx_cntxt_t;
1551
1552 typedef struct _qla_mcast {
1553         uint16_t        rsrvd;
1554         uint8_t         addr[ETHER_ADDR_LEN];
1555 } __packed qla_mcast_t;
1556
1557 typedef struct _qla_rdesc {
1558         volatile uint32_t prod_std;
1559         volatile uint32_t prod_jumbo;
1560         volatile uint32_t rx_next; /* next standard rcv ring to arm fw */
1561         volatile int32_t  rx_in; /* next standard rcv ring to add mbufs */
1562         uint64_t count;
1563         uint64_t lro_pkt_count;
1564         uint64_t lro_bytes;
1565 } qla_rdesc_t;
1566
1567 typedef struct _qla_flash_desc_table {
1568         uint32_t        flash_valid;
1569         uint16_t        flash_ver;
1570         uint16_t        flash_len;
1571         uint16_t        flash_cksum;
1572         uint16_t        flash_unused;
1573         uint8_t         flash_model[16];
1574         uint16_t        flash_manuf;
1575         uint16_t        flash_id;
1576         uint8_t         flash_flag;
1577         uint8_t         erase_cmd;
1578         uint8_t         alt_erase_cmd;
1579         uint8_t         write_enable_cmd;
1580         uint8_t         write_enable_bits;
1581         uint8_t         write_statusreg_cmd;
1582         uint8_t         unprotected_sec_cmd;
1583         uint8_t         read_manuf_cmd;
1584         uint32_t        block_size;
1585         uint32_t        alt_block_size;
1586         uint32_t        flash_size;
1587         uint32_t        write_enable_data;
1588         uint8_t         readid_addr_len;
1589         uint8_t         write_disable_bits;
1590         uint8_t         read_dev_id_len;
1591         uint8_t         chip_erase_cmd;
1592         uint16_t        read_timeo;
1593         uint8_t         protected_sec_cmd;
1594         uint8_t         resvd[65];
1595 } __packed qla_flash_desc_table_t;
1596
1597 /*
1598  * struct for storing hardware specific information for a given interface
1599  */
1600 typedef struct _qla_hw {
1601         struct {
1602                 uint32_t
1603                         unicast_mac     :1,
1604                         bcast_mac       :1,
1605                         init_tx_cnxt    :1,
1606                         init_rx_cnxt    :1,
1607                         init_intr_cnxt  :1,
1608                         fdt_valid       :1;
1609         } flags;
1610
1611
1612         volatile uint16_t       link_speed;
1613         volatile uint16_t       cable_length;
1614         volatile uint32_t       cable_oui;
1615         volatile uint8_t        link_up;
1616         volatile uint8_t        module_type;
1617         volatile uint8_t        link_faults;
1618         volatile uint8_t        loopback_mode;
1619         volatile uint8_t        fduplex;
1620         volatile uint8_t        autoneg;
1621
1622         volatile uint8_t        mac_rcv_mode;
1623
1624         volatile uint32_t       max_mtu;
1625
1626         uint8_t         mac_addr[ETHER_ADDR_LEN];
1627
1628         uint32_t        num_sds_rings;
1629         uint32_t        num_rds_rings;
1630         uint32_t        num_tx_rings;
1631
1632         qla_dmabuf_t    dma_buf;
1633
1634         /* Transmit Side */
1635
1636         qla_hw_tx_cntxt_t tx_cntxt[NUM_TX_RINGS];
1637
1638         /* Receive Side */
1639
1640         uint16_t        rcv_cntxt_id;
1641
1642         uint32_t        mbx_intr_mask_offset;
1643
1644         uint16_t        intr_id[MAX_SDS_RINGS];
1645         uint32_t        intr_src[MAX_SDS_RINGS];
1646
1647         qla_sds_t       sds[MAX_SDS_RINGS];
1648         uint32_t        mbox[Q8_NUM_MBOX];
1649         qla_rdesc_t     rds[MAX_RDS_RINGS];
1650
1651         uint32_t        rds_pidx_thres;
1652         uint32_t        sds_cidx_thres;
1653
1654         uint32_t        rcv_intr_coalesce;
1655         uint32_t        xmt_intr_coalesce;
1656
1657         /* Immediate Completion */
1658         volatile uint32_t imd_compl;
1659         volatile uint32_t aen_mb0;
1660         volatile uint32_t aen_mb1;
1661         volatile uint32_t aen_mb2;
1662         volatile uint32_t aen_mb3;
1663         volatile uint32_t aen_mb4;
1664
1665         /* multicast address list */
1666         uint32_t        nmcast;
1667         qla_mcast_t     mcast[Q8_MAX_NUM_MULTICAST_ADDRS];
1668         uint8_t         mac_addr_arr[(Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN)];
1669
1670         /* reset sequence */
1671 #define Q8_MAX_RESET_SEQ_IDX    16
1672         uint32_t        rst_seq[Q8_MAX_RESET_SEQ_IDX];
1673         uint32_t        rst_seq_idx;
1674
1675         /* heart beat register value */
1676         uint32_t        hbeat_value;
1677         uint32_t        health_count;
1678         uint32_t        hbeat_failure;
1679
1680         uint32_t        max_tx_segs;
1681         uint32_t        min_lro_pkt_size;
1682
1683         uint32_t        enable_hw_lro;
1684         uint32_t        enable_soft_lro;
1685         uint32_t        enable_9kb;
1686
1687         uint32_t        user_pri_nic;
1688         uint32_t        user_pri_iscsi;
1689
1690         /* Flash Descriptor Table */
1691         qla_flash_desc_table_t fdt;
1692
1693         /* stats */
1694         q80_mac_stats_t mac;
1695         q80_rcv_stats_t rcv;
1696         q80_xmt_stats_t xmt[NUM_TX_RINGS];
1697
1698         /* Minidump Related */
1699         uint32_t        mdump_init;
1700         uint32_t        mdump_done;
1701         uint32_t        mdump_active;
1702         uint32_t        mdump_capture_mask;
1703         uint32_t        mdump_start_seq_index;
1704         void            *mdump_buffer;
1705         uint32_t        mdump_buffer_size;
1706         void            *mdump_template;
1707         uint32_t        mdump_template_size;
1708         uint64_t        mdump_usec_ts;
1709
1710 #define Q8_MBX_COMP_MSECS       (19)
1711         uint64_t        mbx_comp_msecs[Q8_MBX_COMP_MSECS];
1712         /* driver state related */
1713         void            *drvr_state;
1714
1715         /* slow path trace */
1716         uint32_t        sp_log_stop_events;
1717 #define Q8_SP_LOG_STOP_HBEAT_FAILURE            0x001
1718 #define Q8_SP_LOG_STOP_TEMP_FAILURE             0x002
1719 #define Q8_SP_LOG_STOP_HW_INIT_FAILURE          0x004
1720 #define Q8_SP_LOG_STOP_IF_START_FAILURE         0x008
1721 #define Q8_SP_LOG_STOP_ERR_RECOVERY_FAILURE     0x010
1722
1723         uint32_t        sp_log_stop;
1724         uint32_t        sp_log_index;
1725         uint32_t        sp_log_num_entries;
1726         void            *sp_log;
1727 } qla_hw_t;
1728
1729 #define QL_UPDATE_RDS_PRODUCER_INDEX(ha, prod_reg, val) \
1730                 bus_write_4((ha->pci_reg), prod_reg, val);
1731
1732 #define QL_UPDATE_TX_PRODUCER_INDEX(ha, val, i) \
1733                 WRITE_REG32(ha, ha->hw.tx_cntxt[i].tx_prod_reg, val)
1734
1735 #define QL_UPDATE_SDS_CONSUMER_INDEX(ha, i, val) \
1736         bus_write_4((ha->pci_reg), (ha->hw.sds[i].sds_consumer), val);
1737
1738 #define QL_ENABLE_INTERRUPTS(ha, i) \
1739                 bus_write_4((ha->pci_reg), (ha->hw.intr_src[i]), 0);
1740
1741 #define QL_BUFFER_ALIGN                16
1742
1743
1744 /*
1745  * Flash Configuration
1746  */
1747 #define Q8_BOARD_CONFIG_OFFSET          0x370000
1748 #define Q8_BOARD_CONFIG_LENGTH          0x2000
1749
1750 #define Q8_BOARD_CONFIG_MAC0_LO         0x400
1751
1752 #define Q8_FDT_LOCK_MAGIC_ID            0x00FD00FD
1753 #define Q8_FDT_FLASH_ADDR_VAL           0xFD009F
1754 #define Q8_FDT_FLASH_CTRL_VAL           0x3F
1755 #define Q8_FDT_MASK_VAL                 0xFF
1756
1757 #define Q8_WR_ENABLE_FL_ADDR            0xFD0100
1758 #define Q8_WR_ENABLE_FL_CTRL            0x5
1759
1760 #define Q8_ERASE_LOCK_MAGIC_ID          0x00EF00EF
1761 #define Q8_ERASE_FL_ADDR_MASK           0xFD0300
1762 #define Q8_ERASE_FL_CTRL_MASK           0x3D
1763
1764 #define Q8_WR_FL_LOCK_MAGIC_ID          0xABCDABCD
1765 #define Q8_WR_FL_ADDR_MASK              0x800000
1766 #define Q8_WR_FL_CTRL_MASK              0x3D
1767
1768 #define QL_FDT_OFFSET                   0x3F0000
1769 #define Q8_FLASH_SECTOR_SIZE            0x10000
1770
1771 /*
1772  * Off Chip Memory Access
1773  */
1774
1775 typedef struct _q80_offchip_mem_val {
1776         uint32_t data_lo;
1777         uint32_t data_hi;
1778         uint32_t data_ulo;
1779         uint32_t data_uhi;
1780 } q80_offchip_mem_val_t;
1781
1782 #endif /* #ifndef _QL_HW_H_ */