2 * Copyright (c) 2013-2016 Qlogic Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
31 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
37 #include <sys/ioccom.h>
45 typedef struct qla_reg_val qla_reg_val_t;
51 typedef struct qla_rd_flash qla_rd_flash_t;
59 typedef struct qla_wr_flash qla_wr_flash_t;
61 struct qla_erase_flash {
65 typedef struct qla_erase_flash qla_erase_flash_t;
67 struct qla_rd_pci_ids {
70 uint16_t subsys_ven_id;
71 uint16_t subsys_dev_id;
74 typedef struct qla_rd_pci_ids qla_rd_pci_ids_t;
77 * structure encapsulating the value to read/write from/to offchip (MS) memory
79 struct qla_offchip_mem_val {
87 typedef struct qla_offchip_mem_val qla_offchip_mem_val_t;
89 struct qla_rd_fw_dump {
91 uint32_t minidump_size;
94 typedef struct qla_rd_fw_dump qla_rd_fw_dump_t;
96 struct qla_drvr_state_tx {
100 uint32_t tx_cntxt_id;
105 typedef struct qla_drvr_state_tx qla_drvr_state_tx_t;
107 struct qla_drvr_state_sds {
108 uint32_t sdsr_next; /* next entry in SDS ring to process */
109 uint32_t sds_consumer;
111 typedef struct qla_drvr_state_sds qla_drvr_state_sds_t;
113 struct qla_drvr_state_rx {
115 uint32_t rx_next; /* next standard rcv ring to arm fw */;
117 typedef struct qla_drvr_state_rx qla_drvr_state_rx_t;
119 struct qla_drvr_state_hdr {
120 uint32_t drvr_version_major;
121 uint32_t drvr_version_minor;
122 uint32_t drvr_version_build;
124 uint8_t mac_addr[ETHER_ADDR_LEN];
126 uint16_t cable_length;
131 uint32_t rcv_intr_coalesce;
132 uint32_t xmt_intr_coalesce;
134 uint32_t tx_state_offset;/* size = sizeof (qla_drvr_state_tx_t) * num_tx_rings */
135 uint32_t rx_state_offset;/* size = sizeof (qla_drvr_state_rx_t) * num_rx_rings */
136 uint32_t sds_state_offset;/* size = sizeof (qla_drvr_state_sds_t) * num_sds_rings */
138 uint32_t num_tx_rings; /* number of tx rings */
139 uint32_t txr_size; /* size of each tx ring in bytes */
140 uint32_t txr_entries; /* number of descriptors in each tx ring */
141 uint32_t txr_offset; /* start of tx ring [0 - #rings] content */
143 uint32_t num_rx_rings; /* number of rx rings */
144 uint32_t rxr_size; /* size of each rx ring in bytes */
145 uint32_t rxr_entries; /* number of descriptors in each rx ring */
146 uint32_t rxr_offset; /* start of rx ring [0 - #rings] content */
148 uint32_t num_sds_rings; /* number of sds rings */
149 uint32_t sds_ring_size; /* size of each sds ring in bytes */
150 uint32_t sds_entries; /* number of descriptors in each sds ring */
151 uint32_t sds_offset; /* start of sds ring [0 - #rings] content */
154 typedef struct qla_drvr_state_hdr qla_drvr_state_hdr_t;
156 struct qla_driver_state {
160 typedef struct qla_driver_state qla_driver_state_t;
163 * Read/Write Register
165 #define QLA_RDWR_REG _IOWR('q', 1, qla_reg_val_t)
170 #define QLA_RD_FLASH _IOWR('q', 2, qla_rd_flash_t)
175 #define QLA_WR_FLASH _IOWR('q', 3, qla_wr_flash_t)
178 * Read Offchip (MS) Memory
180 #define QLA_RDWR_MS_MEM _IOWR('q', 4, qla_offchip_mem_val_t)
185 #define QLA_ERASE_FLASH _IOWR('q', 5, qla_erase_flash_t)
190 #define QLA_RD_PCI_IDS _IOWR('q', 6, qla_rd_pci_ids_t)
193 * Read Minidump Template Size
195 #define QLA_RD_FW_DUMP_SIZE _IOWR('q', 7, qla_rd_fw_dump_t)
198 * Read Minidump Template
200 #define QLA_RD_FW_DUMP _IOWR('q', 8, qla_rd_fw_dump_t)
205 #define QLA_RD_DRVR_STATE _IOWR('q', 9, qla_driver_state_t)
208 #endif /* #ifndef _QL_IOCTL_H_ */