2 * Copyright (c) 2013-2014 Qlogic Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
30 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
40 #include "ql_inline.h"
45 static void qla_replenish_normal_rx(qla_host_t *ha, qla_sds_t *sdsp,
49 qla_rcv_error(qla_host_t *ha)
51 ha->flags.stop_rcv = 1;
52 ha->qla_initiate_recovery = 1;
58 * Function: Handles normal ethernet frames received
61 qla_rx_intr(qla_host_t *ha, qla_sgl_rcv_t *sgc, uint32_t sds_idx)
64 struct mbuf *mp = NULL, *mpf = NULL, *mpl = NULL;
65 struct ifnet *ifp = ha->ifp;
67 struct ether_vlan_header *eh;
68 uint32_t i, rem_len = 0;
70 qla_rx_ring_t *rx_ring;
72 if (ha->hw.num_rds_rings > 1)
75 ha->hw.rds[r_idx].count++;
77 sdsp = &ha->hw.sds[sds_idx];
78 rx_ring = &ha->rx_ring[r_idx];
80 for (i = 0; i < sgc->num_handles; i++) {
81 rxb = &rx_ring->rx_buf[sgc->handle[i] & 0x7FFF];
83 QL_ASSERT(ha, (rxb != NULL),
84 ("%s: [sds_idx]=[%d] rxb != NULL\n", __func__,\
87 if ((rxb == NULL) || QL_ERR_INJECT(ha, INJCT_RX_RXB_INVAL)) {
89 device_printf(ha->pci_dev,
90 "%s invalid rxb[%d, %d, 0x%04x]\n",
91 __func__, sds_idx, i, sgc->handle[i]);
100 QL_ASSERT(ha, (mp != NULL),
101 ("%s: [sds_idx]=[%d] mp != NULL\n", __func__,\
104 bus_dmamap_sync(ha->rx_tag, rxb->map, BUS_DMASYNC_POSTREAD);
107 rxb->next = sdsp->rxb_free;
108 sdsp->rxb_free = rxb;
111 if ((mp == NULL) || QL_ERR_INJECT(ha, INJCT_RX_MP_NULL)) {
113 device_printf(ha->pci_dev,
114 "%s mp == NULL [%d, %d, 0x%04x]\n",
115 __func__, sds_idx, i, sgc->handle[i]);
122 mp->m_flags |= M_PKTHDR;
123 mp->m_pkthdr.len = sgc->pkt_length;
124 mp->m_pkthdr.rcvif = ifp;
125 rem_len = mp->m_pkthdr.len;
127 mp->m_flags &= ~M_PKTHDR;
130 rem_len = rem_len - mp->m_len;
134 mpl->m_len = rem_len;
136 eh = mtod(mpf, struct ether_vlan_header *);
138 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
139 uint32_t *data = (uint32_t *)eh;
141 mpf->m_pkthdr.ether_vtag = ntohs(eh->evl_tag);
142 mpf->m_flags |= M_VLANTAG;
144 *(data + 3) = *(data + 2);
145 *(data + 2) = *(data + 1);
148 m_adj(mpf, ETHER_VLAN_ENCAP_LEN);
151 if (sgc->chksum_status == Q8_STAT_DESC_STATUS_CHKSUM_OK) {
152 mpf->m_pkthdr.csum_flags = CSUM_IP_CHECKED | CSUM_IP_VALID |
153 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
154 mpf->m_pkthdr.csum_data = 0xFFFF;
156 mpf->m_pkthdr.csum_flags = 0;
161 mpf->m_pkthdr.flowid = sgc->rss_hash;
162 mpf->m_flags |= M_FLOWID;
164 (*ifp->if_input)(ifp, mpf);
166 if (sdsp->rx_free > ha->std_replenish)
167 qla_replenish_normal_rx(ha, sdsp, r_idx);
172 #define QLA_TCP_HDR_SIZE 20
173 #define QLA_TCP_TS_OPTION_SIZE 12
177 * Function: Handles normal ethernet frames received
180 qla_lro_intr(qla_host_t *ha, qla_sgl_lro_t *sgc, uint32_t sds_idx)
183 struct mbuf *mp = NULL, *mpf = NULL, *mpl = NULL;
184 struct ifnet *ifp = ha->ifp;
186 struct ether_vlan_header *eh;
187 uint32_t i, rem_len = 0, pkt_length, iplen;
189 struct ip *ip = NULL;
190 struct ip6_hdr *ip6 = NULL;
193 qla_rx_ring_t *rx_ring;
195 if (ha->hw.num_rds_rings > 1)
198 ha->hw.rds[r_idx].count++;
200 rx_ring = &ha->rx_ring[r_idx];
204 sdsp = &ha->hw.sds[sds_idx];
206 pkt_length = sgc->payload_length + sgc->l4_offset;
208 if (sgc->flags & Q8_LRO_COMP_TS) {
209 pkt_length += QLA_TCP_HDR_SIZE + QLA_TCP_TS_OPTION_SIZE;
211 pkt_length += QLA_TCP_HDR_SIZE;
213 ha->lro_bytes += pkt_length;
215 for (i = 0; i < sgc->num_handles; i++) {
216 rxb = &rx_ring->rx_buf[sgc->handle[i] & 0x7FFF];
218 QL_ASSERT(ha, (rxb != NULL),
219 ("%s: [sds_idx]=[%d] rxb != NULL\n", __func__,\
222 if ((rxb == NULL) || QL_ERR_INJECT(ha, INJCT_LRO_RXB_INVAL)) {
224 device_printf(ha->pci_dev,
225 "%s invalid rxb[%d, %d, 0x%04x]\n",
226 __func__, sds_idx, i, sgc->handle[i]);
235 QL_ASSERT(ha, (mp != NULL),
236 ("%s: [sds_idx]=[%d] mp != NULL\n", __func__,\
239 bus_dmamap_sync(ha->rx_tag, rxb->map, BUS_DMASYNC_POSTREAD);
242 rxb->next = sdsp->rxb_free;
243 sdsp->rxb_free = rxb;
246 if ((mp == NULL) || QL_ERR_INJECT(ha, INJCT_LRO_MP_NULL)) {
248 device_printf(ha->pci_dev,
249 "%s mp == NULL [%d, %d, 0x%04x]\n",
250 __func__, sds_idx, i, sgc->handle[i]);
257 mp->m_flags |= M_PKTHDR;
258 mp->m_pkthdr.len = pkt_length;
259 mp->m_pkthdr.rcvif = ifp;
260 rem_len = mp->m_pkthdr.len;
262 mp->m_flags &= ~M_PKTHDR;
265 rem_len = rem_len - mp->m_len;
269 mpl->m_len = rem_len;
271 th = (struct tcphdr *)(mpf->m_data + sgc->l4_offset);
273 if (sgc->flags & Q8_LRO_COMP_PUSH_BIT)
274 th->th_flags |= TH_PUSH;
276 m_adj(mpf, sgc->l2_offset);
278 eh = mtod(mpf, struct ether_vlan_header *);
280 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
281 uint32_t *data = (uint32_t *)eh;
283 mpf->m_pkthdr.ether_vtag = ntohs(eh->evl_tag);
284 mpf->m_flags |= M_VLANTAG;
286 *(data + 3) = *(data + 2);
287 *(data + 2) = *(data + 1);
290 m_adj(mpf, ETHER_VLAN_ENCAP_LEN);
292 etype = ntohs(eh->evl_proto);
294 etype = ntohs(eh->evl_encap_proto);
297 if (etype == ETHERTYPE_IP) {
298 ip = (struct ip *)(mpf->m_data + ETHER_HDR_LEN);
300 iplen = (ip->ip_hl << 2) + (th->th_off << 2) +
303 ip->ip_len = htons(iplen);
306 } else if (etype == ETHERTYPE_IPV6) {
307 ip6 = (struct ip6_hdr *)(mpf->m_data + ETHER_HDR_LEN);
309 iplen = (th->th_off << 2) + sgc->payload_length;
311 ip6->ip6_plen = htons(iplen);
317 if (sdsp->rx_free > ha->std_replenish)
318 qla_replenish_normal_rx(ha, sdsp, r_idx);
322 mpf->m_pkthdr.csum_flags = CSUM_IP_CHECKED | CSUM_IP_VALID |
323 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
324 mpf->m_pkthdr.csum_data = 0xFFFF;
326 mpf->m_pkthdr.flowid = sgc->rss_hash;
327 mpf->m_flags |= M_FLOWID;
331 (*ifp->if_input)(ifp, mpf);
333 if (sdsp->rx_free > ha->std_replenish)
334 qla_replenish_normal_rx(ha, sdsp, r_idx);
340 qla_rcv_cont_sds(qla_host_t *ha, uint32_t sds_idx, uint32_t comp_idx,
341 uint32_t dcount, uint16_t *handle, uint16_t *nhandles)
344 uint16_t num_handles;
345 q80_stat_desc_t *sdesc;
351 for (i = 0; i < dcount; i++) {
352 comp_idx = (comp_idx + 1) & (NUM_STATUS_DESCRIPTORS-1);
353 sdesc = (q80_stat_desc_t *)
354 &ha->hw.sds[sds_idx].sds_ring_base[comp_idx];
356 opcode = Q8_STAT_DESC_OPCODE((sdesc->data[1]));
359 device_printf(ha->pci_dev, "%s: opcode=0 %p %p\n",
360 __func__, (void *)sdesc->data[0],
361 (void *)sdesc->data[1]);
365 num_handles = Q8_SGL_STAT_DESC_NUM_HANDLES((sdesc->data[1]));
367 device_printf(ha->pci_dev, "%s: opcode=0 %p %p\n",
368 __func__, (void *)sdesc->data[0],
369 (void *)sdesc->data[1]);
373 if (QL_ERR_INJECT(ha, INJCT_NUM_HNDLE_INVALID))
376 switch (num_handles) {
379 *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
383 *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
384 *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
388 *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
389 *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
390 *handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0]));
394 *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
395 *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
396 *handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0]));
397 *handle++ = Q8_SGL_STAT_DESC_HANDLE4((sdesc->data[0]));
401 *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
402 *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
403 *handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0]));
404 *handle++ = Q8_SGL_STAT_DESC_HANDLE4((sdesc->data[0]));
405 *handle++ = Q8_SGL_STAT_DESC_HANDLE5((sdesc->data[1]));
409 *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
410 *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
411 *handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0]));
412 *handle++ = Q8_SGL_STAT_DESC_HANDLE4((sdesc->data[0]));
413 *handle++ = Q8_SGL_STAT_DESC_HANDLE5((sdesc->data[1]));
414 *handle++ = Q8_SGL_STAT_DESC_HANDLE6((sdesc->data[1]));
418 *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
419 *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
420 *handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0]));
421 *handle++ = Q8_SGL_STAT_DESC_HANDLE4((sdesc->data[0]));
422 *handle++ = Q8_SGL_STAT_DESC_HANDLE5((sdesc->data[1]));
423 *handle++ = Q8_SGL_STAT_DESC_HANDLE6((sdesc->data[1]));
424 *handle++ = Q8_SGL_STAT_DESC_HANDLE7((sdesc->data[1]));
428 device_printf(ha->pci_dev,
429 "%s: invalid num handles %p %p\n",
430 __func__, (void *)sdesc->data[0],
431 (void *)sdesc->data[1]);
434 ("%s: %s [nh, sds, d0, d1]=[%d, %d, %p, %p]\n",
435 __func__, "invalid num handles", sds_idx, num_handles,
436 (void *)sdesc->data[0],(void *)sdesc->data[1]));
441 *nhandles = *nhandles + num_handles;
448 * Function: Main Interrupt Service Routine
451 qla_rcv_isr(qla_host_t *ha, uint32_t sds_idx, uint32_t count)
455 uint32_t comp_idx, c_idx = 0, desc_count = 0, opcode;
456 volatile q80_stat_desc_t *sdesc, *sdesc0 = NULL;
460 uint32_t sds_replenish_threshold = 0;
465 hw->sds[sds_idx].rcv_active = 1;
466 if (ha->flags.stop_rcv) {
467 hw->sds[sds_idx].rcv_active = 0;
471 QL_DPRINT2(ha, (dev, "%s: [%d]enter\n", __func__, sds_idx));
476 comp_idx = hw->sds[sds_idx].sdsr_next;
478 while (count-- && !ha->flags.stop_rcv) {
480 sdesc = (q80_stat_desc_t *)
481 &hw->sds[sds_idx].sds_ring_base[comp_idx];
483 opcode = Q8_STAT_DESC_OPCODE((sdesc->data[1]));
488 hw->sds[sds_idx].intr_count++;
491 case Q8_STAT_DESC_OPCODE_RCV_PKT:
495 bzero(&sgc, sizeof(qla_sgl_comp_t));
498 Q8_STAT_DESC_TOTAL_LENGTH((sdesc->data[0]));
499 sgc.rcv.num_handles = 1;
501 Q8_STAT_DESC_HANDLE((sdesc->data[0]));
502 sgc.rcv.chksum_status =
503 Q8_STAT_DESC_STATUS((sdesc->data[1]));
506 Q8_STAT_DESC_RSS_HASH((sdesc->data[0]));
508 if (Q8_STAT_DESC_VLAN((sdesc->data[1]))) {
510 Q8_STAT_DESC_VLAN_ID((sdesc->data[1]));
512 qla_rx_intr(ha, &sgc.rcv, sds_idx);
515 case Q8_STAT_DESC_OPCODE_SGL_RCV:
518 Q8_STAT_DESC_COUNT_SGL_RCV((sdesc->data[1]));
520 if (desc_count > 1) {
521 c_idx = (comp_idx + desc_count -1) &
522 (NUM_STATUS_DESCRIPTORS-1);
523 sdesc0 = (q80_stat_desc_t *)
524 &hw->sds[sds_idx].sds_ring_base[c_idx];
526 if (Q8_STAT_DESC_OPCODE((sdesc0->data[1])) !=
527 Q8_STAT_DESC_OPCODE_CONT) {
533 bzero(&sgc, sizeof(qla_sgl_comp_t));
536 Q8_STAT_DESC_TOTAL_LENGTH_SGL_RCV(\
538 sgc.rcv.chksum_status =
539 Q8_STAT_DESC_STATUS((sdesc->data[1]));
542 Q8_STAT_DESC_RSS_HASH((sdesc->data[0]));
544 if (Q8_STAT_DESC_VLAN((sdesc->data[1]))) {
546 Q8_STAT_DESC_VLAN_ID((sdesc->data[1]));
549 QL_ASSERT(ha, (desc_count <= 2) ,\
550 ("%s: [sds_idx, data0, data1]="\
551 "%d, %p, %p]\n", __func__, sds_idx,\
552 (void *)sdesc->data[0],\
553 (void *)sdesc->data[1]));
555 sgc.rcv.num_handles = 1;
557 Q8_STAT_DESC_HANDLE((sdesc->data[0]));
559 if (qla_rcv_cont_sds(ha, sds_idx, comp_idx, desc_count,
560 &sgc.rcv.handle[1], &nhandles)) {
562 "%s: [sds_idx, dcount, data0, data1]="
563 "[%d, %d, 0x%llx, 0x%llx]\n",
564 __func__, sds_idx, desc_count,
565 (long long unsigned int)sdesc->data[0],
566 (long long unsigned int)sdesc->data[1]);
571 sgc.rcv.num_handles += nhandles;
573 qla_rx_intr(ha, &sgc.rcv, sds_idx);
577 case Q8_STAT_DESC_OPCODE_SGL_LRO:
580 Q8_STAT_DESC_COUNT_SGL_LRO((sdesc->data[1]));
582 if (desc_count > 1) {
583 c_idx = (comp_idx + desc_count -1) &
584 (NUM_STATUS_DESCRIPTORS-1);
585 sdesc0 = (q80_stat_desc_t *)
586 &hw->sds[sds_idx].sds_ring_base[c_idx];
588 if (Q8_STAT_DESC_OPCODE((sdesc0->data[1])) !=
589 Q8_STAT_DESC_OPCODE_CONT) {
594 bzero(&sgc, sizeof(qla_sgl_comp_t));
596 sgc.lro.payload_length =
597 Q8_STAT_DESC_TOTAL_LENGTH_SGL_RCV((sdesc->data[0]));
600 Q8_STAT_DESC_RSS_HASH((sdesc->data[0]));
602 sgc.lro.num_handles = 1;
604 Q8_STAT_DESC_HANDLE((sdesc->data[0]));
606 if (Q8_SGL_LRO_STAT_TS((sdesc->data[1])))
607 sgc.lro.flags |= Q8_LRO_COMP_TS;
609 if (Q8_SGL_LRO_STAT_PUSH_BIT((sdesc->data[1])))
610 sgc.lro.flags |= Q8_LRO_COMP_PUSH_BIT;
613 Q8_SGL_LRO_STAT_L2_OFFSET((sdesc->data[1]));
615 Q8_SGL_LRO_STAT_L4_OFFSET((sdesc->data[1]));
617 if (Q8_STAT_DESC_VLAN((sdesc->data[1]))) {
619 Q8_STAT_DESC_VLAN_ID((sdesc->data[1]));
622 QL_ASSERT(ha, (desc_count <= 7) ,\
623 ("%s: [sds_idx, data0, data1]="\
624 "[%d, 0x%llx, 0x%llx]\n",\
626 (long long unsigned int)sdesc->data[0],\
627 (long long unsigned int)sdesc->data[1]));
629 if (qla_rcv_cont_sds(ha, sds_idx, comp_idx,
630 desc_count, &sgc.lro.handle[1], &nhandles)) {
632 "%s: [sds_idx, data0, data1]="\
633 "[%d, 0x%llx, 0x%llx]\n",\
635 (long long unsigned int)sdesc->data[0],\
636 (long long unsigned int)sdesc->data[1]);
642 sgc.lro.num_handles += nhandles;
644 if (qla_lro_intr(ha, &sgc.lro, sds_idx)) {
646 "%s: [sds_idx, data0, data1]="\
647 "[%d, 0x%llx, 0x%llx]\n",\
649 (long long unsigned int)sdesc->data[0],\
650 (long long unsigned int)sdesc->data[1]);
652 "%s: [comp_idx, c_idx, dcount, nhndls]="\
653 "[%d, %d, %d, %d]\n",\
654 __func__, comp_idx, c_idx, desc_count,
655 sgc.lro.num_handles);
656 if (desc_count > 1) {
658 "%s: [sds_idx, data0, data1]="\
659 "[%d, 0x%llx, 0x%llx]\n",\
661 (long long unsigned int)sdesc0->data[0],\
662 (long long unsigned int)sdesc0->data[1]);
669 device_printf(dev, "%s: default 0x%llx!\n", __func__,
670 (long long unsigned int)sdesc->data[0]);
677 sds_replenish_threshold += desc_count;
680 while (desc_count--) {
681 sdesc->data[0] = 0ULL;
682 sdesc->data[1] = 0ULL;
683 comp_idx = (comp_idx + 1) & (NUM_STATUS_DESCRIPTORS-1);
684 sdesc = (q80_stat_desc_t *)
685 &hw->sds[sds_idx].sds_ring_base[comp_idx];
688 if (sds_replenish_threshold > ha->hw.sds_cidx_thres) {
689 sds_replenish_threshold = 0;
690 if (hw->sds[sds_idx].sdsr_next != comp_idx) {
691 QL_UPDATE_SDS_CONSUMER_INDEX(ha, sds_idx,\
694 hw->sds[sds_idx].sdsr_next = comp_idx;
698 if (ha->flags.stop_rcv)
699 goto qla_rcv_isr_exit;
701 if (hw->sds[sds_idx].sdsr_next != comp_idx) {
702 QL_UPDATE_SDS_CONSUMER_INDEX(ha, sds_idx, comp_idx);
704 hw->sds[sds_idx].sdsr_next = comp_idx;
706 sdesc = (q80_stat_desc_t *)&hw->sds[sds_idx].sds_ring_base[comp_idx];
707 opcode = Q8_STAT_DESC_OPCODE((sdesc->data[1]));
713 hw->sds[sds_idx].rcv_active = 0;
719 ql_mbx_isr(void *arg)
723 uint32_t prev_link_state;
728 device_printf(ha->pci_dev, "%s: arg == NULL\n", __func__);
732 data = READ_REG32(ha, Q8_FW_MBOX_CNTRL);
733 if ((data & 0x3) != 0x1) {
734 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0);
738 data = READ_REG32(ha, Q8_FW_MBOX0);
740 if ((data & 0xF000) != 0x8000)
743 data = data & 0xFFFF;
747 case 0x8001: /* It's an AEN */
749 ha->hw.cable_oui = READ_REG32(ha, (Q8_FW_MBOX0 + 4));
751 data = READ_REG32(ha, (Q8_FW_MBOX0 + 8));
752 ha->hw.cable_length = data & 0xFFFF;
755 ha->hw.link_speed = data & 0xFFF;
757 data = READ_REG32(ha, (Q8_FW_MBOX0 + 12));
759 prev_link_state = ha->hw.link_up;
760 ha->hw.link_up = (((data & 0xFF) == 0) ? 0 : 1);
762 if (prev_link_state != ha->hw.link_up) {
764 if_link_state_change(ha->ifp, LINK_STATE_UP);
766 if_link_state_change(ha->ifp, LINK_STATE_DOWN);
770 ha->hw.module_type = ((data >> 8) & 0xFF);
771 ha->hw.flags.fduplex = (((data & 0xFF0000) == 0) ? 0 : 1);
772 ha->hw.flags.autoneg = (((data & 0xFF000000) == 0) ? 0 : 1);
774 data = READ_REG32(ha, (Q8_FW_MBOX0 + 16));
775 ha->hw.flags.loopback_mode = data & 0x03;
777 ha->hw.link_faults = (data >> 3) & 0xFF;
779 WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0);
780 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
784 device_printf(ha->pci_dev, "%s: AEN[0x%08x]\n", __func__, data);
785 WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0);
786 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
794 qla_replenish_normal_rx(qla_host_t *ha, qla_sds_t *sdsp, uint32_t r_idx)
797 int count = sdsp->rx_free;
801 /* we can play with this value via a sysctl */
802 uint32_t replenish_thresh = ha->hw.rds_pidx_thres;
804 rdesc = &ha->hw.rds[r_idx];
806 rx_next = rdesc->rx_next;
809 rxb = sdsp->rxb_free;
814 sdsp->rxb_free = rxb->next;
817 if (ql_get_mbuf(ha, rxb, NULL) == 0) {
818 qla_set_hw_rcv_desc(ha, r_idx, rdesc->rx_in,
820 rxb->paddr, (rxb->m_head)->m_pkthdr.len);
822 if (rdesc->rx_in == NUM_RX_DESCRIPTORS)
825 if (rdesc->rx_next == NUM_RX_DESCRIPTORS)
828 device_printf(ha->pci_dev,
829 "%s: ql_get_mbuf [0,(%d),(%d)] failed\n",
830 __func__, rdesc->rx_in, rxb->handle);
833 rxb->next = sdsp->rxb_free;
834 sdsp->rxb_free = rxb;
839 if (replenish_thresh-- == 0) {
840 QL_UPDATE_RDS_PRODUCER_INDEX(ha, rdesc->prod_std,
842 rx_next = rdesc->rx_next;
843 replenish_thresh = ha->hw.rds_pidx_thres;
847 if (rx_next != rdesc->rx_next) {
848 QL_UPDATE_RDS_PRODUCER_INDEX(ha, rdesc->prod_std,
856 qla_ivec_t *ivec = arg;
867 if ((idx = ivec->sds_idx) >= ha->hw.num_sds_rings)
871 taskqueue_enqueue(ha->tx_tq, &ha->tx_task);
873 ret = qla_rcv_isr(ha, idx, -1);
876 taskqueue_enqueue(ha->tx_tq, &ha->tx_task);
878 if (!ha->flags.stop_rcv) {
879 QL_ENABLE_INTERRUPTS(ha, idx);