sys/dev/qlxgbe/ql_isr.c

   1 /*
   2  * Copyright (c) 2013-2016 Qlogic Corporation
   3  * All rights reserved.
   4  *
   5  *  Redistribution and use in source and binary forms, with or without
   6  *  modification, are permitted provided that the following conditions
   7  *  are met:
   8  *
   9  *  1. Redistributions of source code must retain the above copyright
  10  *     notice, this list of conditions and the following disclaimer.
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  16  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  19  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  20  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  21  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  22  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  23  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  25  *  POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 /*
  29  * File: ql_isr.c
  30  * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36
  37 #include "ql_os.h"
  38 #include "ql_hw.h"
  39 #include "ql_def.h"
  40 #include "ql_inline.h"
  41 #include "ql_ver.h"
  42 #include "ql_glbl.h"
  43 #include "ql_dbg.h"
  44
  45 static void qla_replenish_normal_rx(qla_host_t *ha, qla_sds_t *sdsp,
  46                 uint32_t r_idx);
  47
  48 static void
  49 qla_rcv_error(qla_host_t *ha)
  50 {
  51         ha->flags.stop_rcv = 1;
  52         ha->qla_initiate_recovery = 1;
  53 }
  54
  55
  56 /*
  57  * Name: qla_rx_intr
  58  * Function: Handles normal ethernet frames received
  59  */
  60 static void
  61 qla_rx_intr(qla_host_t *ha, qla_sgl_rcv_t *sgc, uint32_t sds_idx)
  62 {
  63         qla_rx_buf_t            *rxb;
  64         struct mbuf             *mp = NULL, *mpf = NULL, *mpl = NULL;
  65         struct ifnet            *ifp = ha->ifp;
  66         qla_sds_t               *sdsp;
  67         struct ether_vlan_header *eh;
  68         uint32_t                i, rem_len = 0;
  69         uint32_t                r_idx = 0;
  70         qla_rx_ring_t           *rx_ring;
  71         struct lro_ctrl         *lro;
  72
  73         lro = &ha->hw.sds[sds_idx].lro;
  74
  75         if (ha->hw.num_rds_rings > 1)
  76                 r_idx = sds_idx;
  77
  78         ha->hw.rds[r_idx].count++;
  79
  80         sdsp = &ha->hw.sds[sds_idx];
  81         rx_ring = &ha->rx_ring[r_idx];
  82
  83         for (i = 0; i < sgc->num_handles; i++) {
  84                 rxb = &rx_ring->rx_buf[sgc->handle[i] & 0x7FFF];
  85
  86                 QL_ASSERT(ha, (rxb != NULL),
  87                         ("%s: [sds_idx]=[%d] rxb != NULL\n", __func__,\
  88                         sds_idx));
  89
  90                 if ((rxb == NULL) || QL_ERR_INJECT(ha, INJCT_RX_RXB_INVAL)) {
  91                         /* log the error */
  92                         device_printf(ha->pci_dev,
  93                                 "%s invalid rxb[%d, %d, 0x%04x]\n",
  94                                 __func__, sds_idx, i, sgc->handle[i]);
  95                         qla_rcv_error(ha);
  96                         return;
  97                 }
  98
  99                 mp = rxb->m_head;
 100                 if (i == 0)
 101                         mpf = mp;
 102
 103                 QL_ASSERT(ha, (mp != NULL),
 104                         ("%s: [sds_idx]=[%d] mp != NULL\n", __func__,\
 105                         sds_idx));
 106
 107                 bus_dmamap_sync(ha->rx_tag, rxb->map, BUS_DMASYNC_POSTREAD);
 108
 109                 rxb->m_head = NULL;
 110                 rxb->next = sdsp->rxb_free;
 111                 sdsp->rxb_free = rxb;
 112                 sdsp->rx_free++;
 113
 114                 if ((mp == NULL) || QL_ERR_INJECT(ha, INJCT_RX_MP_NULL)) {
 115                         /* log the error */
 116                         device_printf(ha->pci_dev,
 117                                 "%s mp  == NULL [%d, %d, 0x%04x]\n",
 118                                 __func__, sds_idx, i, sgc->handle[i]);
 119                         qla_rcv_error(ha);
 120                         return;
 121                 }
 122
 123                 if (i == 0) {
 124                         mpl = mpf = mp;
 125                         mp->m_flags |= M_PKTHDR;
 126                         mp->m_pkthdr.len = sgc->pkt_length;
 127                         mp->m_pkthdr.rcvif = ifp;
 128                         rem_len = mp->m_pkthdr.len;
 129                 } else {
 130                         mp->m_flags &= ~M_PKTHDR;
 131                         mpl->m_next = mp;
 132                         mpl = mp;
 133                         rem_len = rem_len - mp->m_len;
 134                 }
 135         }
 136
 137         mpl->m_len = rem_len;
 138
 139         eh = mtod(mpf, struct ether_vlan_header *);
 140
 141         if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
 142                 uint32_t *data = (uint32_t *)eh;
 143
 144                 mpf->m_pkthdr.ether_vtag = ntohs(eh->evl_tag);
 145                 mpf->m_flags |= M_VLANTAG;
 146
 147                 *(data + 3) = *(data + 2);
 148                 *(data + 2) = *(data + 1);
 149                 *(data + 1) = *data;
 150
 151                 m_adj(mpf, ETHER_VLAN_ENCAP_LEN);
 152         }
 153
 154         if (sgc->chksum_status == Q8_STAT_DESC_STATUS_CHKSUM_OK) {
 155                 mpf->m_pkthdr.csum_flags = CSUM_IP_CHECKED | CSUM_IP_VALID |
 156                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
 157                 mpf->m_pkthdr.csum_data = 0xFFFF;
 158         } else {
 159                 mpf->m_pkthdr.csum_flags = 0;
 160         }
 161
 162         if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
 163
 164         mpf->m_pkthdr.flowid = sgc->rss_hash;
 165
 166 #if __FreeBSD_version >= 1100000
 167         M_HASHTYPE_SET(mpf, M_HASHTYPE_OPAQUE_HASH);
 168 #else
 169         M_HASHTYPE_SET(mpf, M_HASHTYPE_NONE);
 170 #endif /* #if __FreeBSD_version >= 1100000 */
 171
 172         if (ha->hw.enable_soft_lro) {
 173
 174 #if (__FreeBSD_version >= 1100101)
 175
 176                 tcp_lro_queue_mbuf(lro, mpf);
 177
 178 #else
 179                 if (tcp_lro_rx(lro, mpf, 0))
 180                         (*ifp->if_input)(ifp, mpf);
 181
 182 #endif /* #if (__FreeBSD_version >= 1100101) */
 183
 184
 185         } else {
 186                 (*ifp->if_input)(ifp, mpf);
 187         }
 188
 189         if (sdsp->rx_free > ha->std_replenish)
 190                 qla_replenish_normal_rx(ha, sdsp, r_idx);
 191
 192         return;
 193 }
 194
 195 #define QLA_TCP_HDR_SIZE        20
 196 #define QLA_TCP_TS_OPTION_SIZE  12
 197
 198 /*
 199  * Name: qla_lro_intr
 200  * Function: Handles normal ethernet frames received
 201  */
 202 static int
 203 qla_lro_intr(qla_host_t *ha, qla_sgl_lro_t *sgc, uint32_t sds_idx)
 204 {
 205         qla_rx_buf_t *rxb;
 206         struct mbuf *mp = NULL, *mpf = NULL, *mpl = NULL;
 207         struct ifnet *ifp = ha->ifp;
 208         qla_sds_t *sdsp;
 209         struct ether_vlan_header *eh;
 210         uint32_t i, rem_len = 0, pkt_length, iplen;
 211         struct tcphdr *th;
 212         struct ip *ip = NULL;
 213         struct ip6_hdr *ip6 = NULL;
 214         uint16_t etype;
 215         uint32_t r_idx = 0;
 216         qla_rx_ring_t *rx_ring;
 217
 218         if (ha->hw.num_rds_rings > 1)
 219                 r_idx = sds_idx;
 220
 221         ha->hw.rds[r_idx].count++;
 222
 223         rx_ring = &ha->rx_ring[r_idx];
 224
 225         ha->lro_pkt_count++;
 226
 227         sdsp = &ha->hw.sds[sds_idx];
 228
 229         pkt_length = sgc->payload_length + sgc->l4_offset;
 230
 231         if (sgc->flags & Q8_LRO_COMP_TS) {
 232                 pkt_length += QLA_TCP_HDR_SIZE + QLA_TCP_TS_OPTION_SIZE;
 233         } else {
 234                 pkt_length += QLA_TCP_HDR_SIZE;
 235         }
 236         ha->lro_bytes += pkt_length;
 237
 238         for (i = 0; i < sgc->num_handles; i++) {
 239                 rxb = &rx_ring->rx_buf[sgc->handle[i] & 0x7FFF];
 240
 241                 QL_ASSERT(ha, (rxb != NULL),
 242                         ("%s: [sds_idx]=[%d] rxb != NULL\n", __func__,\
 243                         sds_idx));
 244
 245                 if ((rxb == NULL) || QL_ERR_INJECT(ha, INJCT_LRO_RXB_INVAL)) {
 246                         /* log the error */
 247                         device_printf(ha->pci_dev,
 248                                 "%s invalid rxb[%d, %d, 0x%04x]\n",
 249                                 __func__, sds_idx, i, sgc->handle[i]);
 250                         qla_rcv_error(ha);
 251                         return (0);
 252                 }
 253
 254                 mp = rxb->m_head;
 255                 if (i == 0)
 256                         mpf = mp;
 257
 258                 QL_ASSERT(ha, (mp != NULL),
 259                         ("%s: [sds_idx]=[%d] mp != NULL\n", __func__,\
 260                         sds_idx));
 261
 262                 bus_dmamap_sync(ha->rx_tag, rxb->map, BUS_DMASYNC_POSTREAD);
 263
 264                 rxb->m_head = NULL;
 265                 rxb->next = sdsp->rxb_free;
 266                 sdsp->rxb_free = rxb;
 267                 sdsp->rx_free++;
 268
 269                 if ((mp == NULL) || QL_ERR_INJECT(ha, INJCT_LRO_MP_NULL)) {
 270                         /* log the error */
 271                         device_printf(ha->pci_dev,
 272                                 "%s mp  == NULL [%d, %d, 0x%04x]\n",
 273                                 __func__, sds_idx, i, sgc->handle[i]);
 274                         qla_rcv_error(ha);
 275                         return (0);
 276                 }
 277
 278                 if (i == 0) {
 279                         mpl = mpf = mp;
 280                         mp->m_flags |= M_PKTHDR;
 281                         mp->m_pkthdr.len = pkt_length;
 282                         mp->m_pkthdr.rcvif = ifp;
 283                         rem_len = mp->m_pkthdr.len;
 284                 } else {
 285                         mp->m_flags &= ~M_PKTHDR;
 286                         mpl->m_next = mp;
 287                         mpl = mp;
 288                         rem_len = rem_len - mp->m_len;
 289                 }
 290         }
 291
 292         mpl->m_len = rem_len;
 293
 294         th = (struct tcphdr *)(mpf->m_data + sgc->l4_offset);
 295
 296         if (sgc->flags & Q8_LRO_COMP_PUSH_BIT)
 297                 th->th_flags |= TH_PUSH;
 298
 299         m_adj(mpf, sgc->l2_offset);
 300
 301         eh = mtod(mpf, struct ether_vlan_header *);
 302
 303         if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
 304                 uint32_t *data = (uint32_t *)eh;
 305
 306                 mpf->m_pkthdr.ether_vtag = ntohs(eh->evl_tag);
 307                 mpf->m_flags |= M_VLANTAG;
 308
 309                 *(data + 3) = *(data + 2);
 310                 *(data + 2) = *(data + 1);
 311                 *(data + 1) = *data;
 312
 313                 m_adj(mpf, ETHER_VLAN_ENCAP_LEN);
 314
 315                 etype = ntohs(eh->evl_proto);
 316         } else {
 317                 etype = ntohs(eh->evl_encap_proto);
 318         }
 319
 320         if (etype == ETHERTYPE_IP) {
 321                 ip = (struct ip *)(mpf->m_data + ETHER_HDR_LEN);
 322
 323                 iplen = (ip->ip_hl << 2) + (th->th_off << 2) +
 324                                 sgc->payload_length;
 325
 326                 ip->ip_len = htons(iplen);
 327
 328                 ha->ipv4_lro++;
 329
 330                 M_HASHTYPE_SET(mpf, M_HASHTYPE_RSS_TCP_IPV4);
 331
 332         } else if (etype == ETHERTYPE_IPV6) {
 333                 ip6 = (struct ip6_hdr *)(mpf->m_data + ETHER_HDR_LEN);
 334
 335                 iplen = (th->th_off << 2) + sgc->payload_length;
 336
 337                 ip6->ip6_plen = htons(iplen);
 338
 339                 ha->ipv6_lro++;
 340
 341                 M_HASHTYPE_SET(mpf, M_HASHTYPE_RSS_TCP_IPV6);
 342
 343         } else {
 344                 m_freem(mpf);
 345
 346                 if (sdsp->rx_free > ha->std_replenish)
 347                         qla_replenish_normal_rx(ha, sdsp, r_idx);
 348                 return 0;
 349         }
 350
 351         mpf->m_pkthdr.csum_flags = CSUM_IP_CHECKED | CSUM_IP_VALID |
 352                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
 353         mpf->m_pkthdr.csum_data = 0xFFFF;
 354
 355         mpf->m_pkthdr.flowid = sgc->rss_hash;
 356
 357         if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
 358
 359         (*ifp->if_input)(ifp, mpf);
 360
 361         if (sdsp->rx_free > ha->std_replenish)
 362                 qla_replenish_normal_rx(ha, sdsp, r_idx);
 363
 364         return (0);
 365 }
 366
 367 static int
 368 qla_rcv_cont_sds(qla_host_t *ha, uint32_t sds_idx, uint32_t comp_idx,
 369         uint32_t dcount, uint16_t *handle, uint16_t *nhandles)
 370 {
 371         uint32_t i;
 372         uint16_t num_handles;
 373         q80_stat_desc_t *sdesc;
 374         uint32_t opcode;
 375
 376         *nhandles = 0;
 377         dcount--;
 378
 379         for (i = 0; i < dcount; i++) {
 380                 comp_idx = (comp_idx + 1) & (NUM_STATUS_DESCRIPTORS-1);
 381                 sdesc = (q80_stat_desc_t *)
 382                                 &ha->hw.sds[sds_idx].sds_ring_base[comp_idx];
 383
 384                 opcode = Q8_STAT_DESC_OPCODE((sdesc->data[1]));
 385
 386                 if (!opcode) {
 387                         device_printf(ha->pci_dev, "%s: opcode=0 %p %p\n",
 388                                 __func__, (void *)sdesc->data[0],
 389                                 (void *)sdesc->data[1]);
 390                         return -1;
 391                 }
 392
 393                 num_handles = Q8_SGL_STAT_DESC_NUM_HANDLES((sdesc->data[1]));
 394                 if (!num_handles) {
 395                         device_printf(ha->pci_dev, "%s: opcode=0 %p %p\n",
 396                                 __func__, (void *)sdesc->data[0],
 397                                 (void *)sdesc->data[1]);
 398                         return -1;
 399                 }
 400
 401                 if (QL_ERR_INJECT(ha, INJCT_NUM_HNDLE_INVALID))
 402                         num_handles = -1;
 403
 404                 switch (num_handles) {
 405
 406                 case 1:
 407                         *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
 408                         break;
 409
 410                 case 2:
 411                         *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
 412                         *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
 413                         break;
 414
 415                 case 3:
 416                         *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
 417                         *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
 418                         *handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0]));
 419                         break;
 420
 421                 case 4:
 422                         *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
 423                         *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
 424                         *handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0]));
 425                         *handle++ = Q8_SGL_STAT_DESC_HANDLE4((sdesc->data[0]));
 426                         break;
 427
 428                 case 5:
 429                         *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
 430                         *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
 431                         *handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0]));
 432                         *handle++ = Q8_SGL_STAT_DESC_HANDLE4((sdesc->data[0]));
 433                         *handle++ = Q8_SGL_STAT_DESC_HANDLE5((sdesc->data[1]));
 434                         break;
 435
 436                 case 6:
 437                         *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
 438                         *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
 439                         *handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0]));
 440                         *handle++ = Q8_SGL_STAT_DESC_HANDLE4((sdesc->data[0]));
 441                         *handle++ = Q8_SGL_STAT_DESC_HANDLE5((sdesc->data[1]));
 442                         *handle++ = Q8_SGL_STAT_DESC_HANDLE6((sdesc->data[1]));
 443                         break;
 444
 445                 case 7:
 446                         *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
 447                         *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
 448                         *handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0]));
 449                         *handle++ = Q8_SGL_STAT_DESC_HANDLE4((sdesc->data[0]));
 450                         *handle++ = Q8_SGL_STAT_DESC_HANDLE5((sdesc->data[1]));
 451                         *handle++ = Q8_SGL_STAT_DESC_HANDLE6((sdesc->data[1]));
 452                         *handle++ = Q8_SGL_STAT_DESC_HANDLE7((sdesc->data[1]));
 453                         break;
 454
 455                 default:
 456                         device_printf(ha->pci_dev,
 457                                 "%s: invalid num handles %p %p\n",
 458                                 __func__, (void *)sdesc->data[0],
 459                                 (void *)sdesc->data[1]);
 460
 461                         QL_ASSERT(ha, (0),\
 462                         ("%s: %s [nh, sds, d0, d1]=[%d, %d, %p, %p]\n",
 463                         __func__, "invalid num handles", sds_idx, num_handles,
 464                         (void *)sdesc->data[0],(void *)sdesc->data[1]));
 465
 466                         qla_rcv_error(ha);
 467                         return 0;
 468                 }
 469                 *nhandles = *nhandles + num_handles;
 470         }
 471         return 0;
 472 }
 473
 474 /*
 475  * Name: ql_rcv_isr
 476  * Function: Main Interrupt Service Routine
 477  */
 478 uint32_t
 479 ql_rcv_isr(qla_host_t *ha, uint32_t sds_idx, uint32_t count)
 480 {
 481         device_t dev;
 482         qla_hw_t *hw;
 483         uint32_t comp_idx, c_idx = 0, desc_count = 0, opcode;
 484         volatile q80_stat_desc_t *sdesc, *sdesc0 = NULL;
 485         uint32_t ret = 0;
 486         qla_sgl_comp_t sgc;
 487         uint16_t nhandles;
 488         uint32_t sds_replenish_threshold = 0;
 489         uint32_t r_idx = 0;
 490         qla_sds_t *sdsp;
 491
 492         dev = ha->pci_dev;
 493         hw = &ha->hw;
 494
 495         hw->sds[sds_idx].rcv_active = 1;
 496         if (ha->flags.stop_rcv) {
 497                 hw->sds[sds_idx].rcv_active = 0;
 498                 return 0;
 499         }
 500
 501         QL_DPRINT2(ha, (dev, "%s: [%d]enter\n", __func__, sds_idx));
 502
 503         /*
 504          * receive interrupts
 505          */
 506         comp_idx = hw->sds[sds_idx].sdsr_next;
 507
 508         while (count-- && !ha->flags.stop_rcv) {
 509
 510                 sdesc = (q80_stat_desc_t *)
 511                                 &hw->sds[sds_idx].sds_ring_base[comp_idx];
 512
 513                 opcode = Q8_STAT_DESC_OPCODE((sdesc->data[1]));
 514
 515                 if (!opcode)
 516                         break;
 517
 518                 hw->sds[sds_idx].intr_count++;
 519                 switch (opcode) {
 520
 521                 case Q8_STAT_DESC_OPCODE_RCV_PKT:
 522
 523                         desc_count = 1;
 524
 525                         bzero(&sgc, sizeof(qla_sgl_comp_t));
 526
 527                         sgc.rcv.pkt_length =
 528                                 Q8_STAT_DESC_TOTAL_LENGTH((sdesc->data[0]));
 529                         sgc.rcv.num_handles = 1;
 530                         sgc.rcv.handle[0] =
 531                                 Q8_STAT_DESC_HANDLE((sdesc->data[0]));
 532                         sgc.rcv.chksum_status =
 533                                 Q8_STAT_DESC_STATUS((sdesc->data[1]));
 534
 535                         sgc.rcv.rss_hash =
 536                                 Q8_STAT_DESC_RSS_HASH((sdesc->data[0]));
 537
 538                         if (Q8_STAT_DESC_VLAN((sdesc->data[1]))) {
 539                                 sgc.rcv.vlan_tag =
 540                                         Q8_STAT_DESC_VLAN_ID((sdesc->data[1]));
 541                         }
 542                         qla_rx_intr(ha, &sgc.rcv, sds_idx);
 543                         break;
 544
 545                 case Q8_STAT_DESC_OPCODE_SGL_RCV:
 546
 547                         desc_count =
 548                                 Q8_STAT_DESC_COUNT_SGL_RCV((sdesc->data[1]));
 549
 550                         if (desc_count > 1) {
 551                                 c_idx = (comp_idx + desc_count -1) &
 552                                                 (NUM_STATUS_DESCRIPTORS-1);
 553                                 sdesc0 = (q80_stat_desc_t *)
 554                                         &hw->sds[sds_idx].sds_ring_base[c_idx];
 555
 556                                 if (Q8_STAT_DESC_OPCODE((sdesc0->data[1])) !=
 557                                                 Q8_STAT_DESC_OPCODE_CONT) {
 558                                         desc_count = 0;
 559                                         break;
 560                                 }
 561                         }
 562
 563                         bzero(&sgc, sizeof(qla_sgl_comp_t));
 564
 565                         sgc.rcv.pkt_length =
 566                                 Q8_STAT_DESC_TOTAL_LENGTH_SGL_RCV(\
 567                                         (sdesc->data[0]));
 568                         sgc.rcv.chksum_status =
 569                                 Q8_STAT_DESC_STATUS((sdesc->data[1]));
 570
 571                         sgc.rcv.rss_hash =
 572                                 Q8_STAT_DESC_RSS_HASH((sdesc->data[0]));
 573
 574                         if (Q8_STAT_DESC_VLAN((sdesc->data[1]))) {
 575                                 sgc.rcv.vlan_tag =
 576                                         Q8_STAT_DESC_VLAN_ID((sdesc->data[1]));
 577                         }
 578
 579                         QL_ASSERT(ha, (desc_count <= 2) ,\
 580                                 ("%s: [sds_idx, data0, data1]="\
 581                                 "%d, %p, %p]\n", __func__, sds_idx,\
 582                                 (void *)sdesc->data[0],\
 583                                 (void *)sdesc->data[1]));
 584
 585                         sgc.rcv.num_handles = 1;
 586                         sgc.rcv.handle[0] =
 587                                 Q8_STAT_DESC_HANDLE((sdesc->data[0]));
 588
 589                         if (qla_rcv_cont_sds(ha, sds_idx, comp_idx, desc_count,
 590                                 &sgc.rcv.handle[1], &nhandles)) {
 591                                 device_printf(dev,
 592                                         "%s: [sds_idx, dcount, data0, data1]="
 593                                          "[%d, %d, 0x%llx, 0x%llx]\n",
 594                                         __func__, sds_idx, desc_count,
 595                                         (long long unsigned int)sdesc->data[0],
 596                                         (long long unsigned int)sdesc->data[1]);
 597                                 desc_count = 0;
 598                                 break;
 599                         }
 600
 601                         sgc.rcv.num_handles += nhandles;
 602
 603                         qla_rx_intr(ha, &sgc.rcv, sds_idx);
 604
 605                         break;
 606
 607                 case Q8_STAT_DESC_OPCODE_SGL_LRO:
 608
 609                         desc_count =
 610                                 Q8_STAT_DESC_COUNT_SGL_LRO((sdesc->data[1]));
 611
 612                         if (desc_count > 1) {
 613                                 c_idx = (comp_idx + desc_count -1) &
 614                                                 (NUM_STATUS_DESCRIPTORS-1);
 615                                 sdesc0 = (q80_stat_desc_t *)
 616                                         &hw->sds[sds_idx].sds_ring_base[c_idx];
 617
 618                                 if (Q8_STAT_DESC_OPCODE((sdesc0->data[1])) !=
 619                                                 Q8_STAT_DESC_OPCODE_CONT) {
 620                                         desc_count = 0;
 621                                         break;
 622                                 }
 623                         }
 624                         bzero(&sgc, sizeof(qla_sgl_comp_t));
 625
 626                         sgc.lro.payload_length =
 627                         Q8_STAT_DESC_TOTAL_LENGTH_SGL_RCV((sdesc->data[0]));
 628
 629                         sgc.lro.rss_hash =
 630                                 Q8_STAT_DESC_RSS_HASH((sdesc->data[0]));
 631
 632                         sgc.lro.num_handles = 1;
 633                         sgc.lro.handle[0] =
 634                                 Q8_STAT_DESC_HANDLE((sdesc->data[0]));
 635
 636                         if (Q8_SGL_LRO_STAT_TS((sdesc->data[1])))
 637                                 sgc.lro.flags |= Q8_LRO_COMP_TS;
 638
 639                         if (Q8_SGL_LRO_STAT_PUSH_BIT((sdesc->data[1])))
 640                                 sgc.lro.flags |= Q8_LRO_COMP_PUSH_BIT;
 641
 642                         sgc.lro.l2_offset =
 643                                 Q8_SGL_LRO_STAT_L2_OFFSET((sdesc->data[1]));
 644                         sgc.lro.l4_offset =
 645                                 Q8_SGL_LRO_STAT_L4_OFFSET((sdesc->data[1]));
 646
 647                         if (Q8_STAT_DESC_VLAN((sdesc->data[1]))) {
 648                                 sgc.lro.vlan_tag =
 649                                         Q8_STAT_DESC_VLAN_ID((sdesc->data[1]));
 650                         }
 651
 652                         QL_ASSERT(ha, (desc_count <= 7) ,\
 653                                 ("%s: [sds_idx, data0, data1]="\
 654                                  "[%d, 0x%llx, 0x%llx]\n",\
 655                                 __func__, sds_idx,\
 656                                 (long long unsigned int)sdesc->data[0],\
 657                                 (long long unsigned int)sdesc->data[1]));
 658
 659                         if (qla_rcv_cont_sds(ha, sds_idx, comp_idx,
 660                                 desc_count, &sgc.lro.handle[1], &nhandles)) {
 661                                 device_printf(dev,
 662                                 "%s: [sds_idx, data0, data1]="\
 663                                  "[%d, 0x%llx, 0x%llx]\n",\
 664                                 __func__, sds_idx,\
 665                                 (long long unsigned int)sdesc->data[0],\
 666                                 (long long unsigned int)sdesc->data[1]);
 667
 668                                 desc_count = 0;
 669                                 break;
 670                         }
 671
 672                         sgc.lro.num_handles += nhandles;
 673
 674                         if (qla_lro_intr(ha, &sgc.lro, sds_idx)) {
 675                                 device_printf(dev,
 676                                 "%s: [sds_idx, data0, data1]="\
 677                                  "[%d, 0x%llx, 0x%llx]\n",\
 678                                 __func__, sds_idx,\
 679                                 (long long unsigned int)sdesc->data[0],\
 680                                 (long long unsigned int)sdesc->data[1]);
 681                                 device_printf(dev,
 682                                 "%s: [comp_idx, c_idx, dcount, nhndls]="\
 683                                  "[%d, %d, %d, %d]\n",\
 684                                 __func__, comp_idx, c_idx, desc_count,
 685                                 sgc.lro.num_handles);
 686                                 if (desc_count > 1) {
 687                                 device_printf(dev,
 688                                 "%s: [sds_idx, data0, data1]="\
 689                                  "[%d, 0x%llx, 0x%llx]\n",\
 690                                 __func__, sds_idx,\
 691                                 (long long unsigned int)sdesc0->data[0],\
 692                                 (long long unsigned int)sdesc0->data[1]);
 693                                 }
 694                         }
 695
 696                         break;
 697
 698                 default:
 699                         device_printf(dev, "%s: default 0x%llx!\n", __func__,
 700                                         (long long unsigned int)sdesc->data[0]);
 701                         break;
 702                 }
 703
 704                 if (desc_count == 0)
 705                         break;
 706
 707                 sds_replenish_threshold += desc_count;
 708
 709
 710                 while (desc_count--) {
 711                         sdesc->data[0] = 0ULL;
 712                         sdesc->data[1] = 0ULL;
 713                         comp_idx = (comp_idx + 1) & (NUM_STATUS_DESCRIPTORS-1);
 714                         sdesc = (q80_stat_desc_t *)
 715                                 &hw->sds[sds_idx].sds_ring_base[comp_idx];
 716                 }
 717
 718                 if (sds_replenish_threshold > ha->hw.sds_cidx_thres) {
 719                         sds_replenish_threshold = 0;
 720                         if (hw->sds[sds_idx].sdsr_next != comp_idx) {
 721                                 QL_UPDATE_SDS_CONSUMER_INDEX(ha, sds_idx,\
 722                                         comp_idx);
 723                         }
 724                         hw->sds[sds_idx].sdsr_next = comp_idx;
 725                 }
 726         }
 727
 728         if (ha->hw.enable_soft_lro) {
 729                 struct lro_ctrl         *lro;
 730
 731                 lro = &ha->hw.sds[sds_idx].lro;
 732
 733 #if (__FreeBSD_version >= 1100101)
 734
 735                 tcp_lro_flush_all(lro);
 736
 737 #else
 738                 struct lro_entry *queued;
 739
 740                 while ((!SLIST_EMPTY(&lro->lro_active))) {
 741                         queued = SLIST_FIRST(&lro->lro_active);
 742                         SLIST_REMOVE_HEAD(&lro->lro_active, next);
 743                         tcp_lro_flush(lro, queued);
 744                 }
 745
 746 #endif /* #if (__FreeBSD_version >= 1100101) */
 747
 748         }
 749
 750         if (ha->flags.stop_rcv)
 751                 goto ql_rcv_isr_exit;
 752
 753         if (hw->sds[sds_idx].sdsr_next != comp_idx) {
 754                 QL_UPDATE_SDS_CONSUMER_INDEX(ha, sds_idx, comp_idx);
 755                 hw->sds[sds_idx].sdsr_next = comp_idx;
 756         } else {
 757                 hw->sds[sds_idx].spurious_intr_count++;
 758
 759                 if (ha->hw.num_rds_rings > 1)
 760                         r_idx = sds_idx;
 761
 762                 sdsp = &ha->hw.sds[sds_idx];
 763
 764                 if (sdsp->rx_free > ha->std_replenish)
 765                         qla_replenish_normal_rx(ha, sdsp, r_idx);
 766         }
 767
 768         sdesc = (q80_stat_desc_t *)&hw->sds[sds_idx].sds_ring_base[comp_idx];
 769         opcode = Q8_STAT_DESC_OPCODE((sdesc->data[1]));
 770
 771         if (opcode)
 772                 ret = -1;
 773
 774 ql_rcv_isr_exit:
 775         hw->sds[sds_idx].rcv_active = 0;
 776
 777         return (ret);
 778 }
 779
 780 void
 781 ql_mbx_isr(void *arg)
 782 {
 783         qla_host_t *ha;
 784         uint32_t data;
 785         uint32_t prev_link_state;
 786
 787         ha = arg;
 788
 789         if (ha == NULL) {
 790                 device_printf(ha->pci_dev, "%s: arg == NULL\n", __func__);
 791                 return;
 792         }
 793
 794         data = READ_REG32(ha, Q8_FW_MBOX_CNTRL);
 795         if ((data & 0x3) != 0x1) {
 796                 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0);
 797                 return;
 798         }
 799
 800         data = READ_REG32(ha, Q8_FW_MBOX0);
 801
 802         if ((data & 0xF000) != 0x8000)
 803                 return;
 804
 805         data = data & 0xFFFF;
 806
 807         switch (data) {
 808
 809         case 0x8001:  /* It's an AEN */
 810
 811                 ha->hw.cable_oui = READ_REG32(ha, (Q8_FW_MBOX0 + 4));
 812
 813                 data = READ_REG32(ha, (Q8_FW_MBOX0 + 8));
 814                 ha->hw.cable_length = data & 0xFFFF;
 815
 816                 data = data >> 16;
 817                 ha->hw.link_speed = data & 0xFFF;
 818
 819                 data = READ_REG32(ha, (Q8_FW_MBOX0 + 12));
 820
 821                 prev_link_state =  ha->hw.link_up;
 822                 ha->hw.link_up = (((data & 0xFF) == 0) ? 0 : 1);
 823
 824                 if (prev_link_state !=  ha->hw.link_up) {
 825                         if (ha->hw.link_up)
 826                                 if_link_state_change(ha->ifp, LINK_STATE_UP);
 827                         else
 828                                 if_link_state_change(ha->ifp, LINK_STATE_DOWN);
 829                 }
 830
 831
 832                 ha->hw.module_type = ((data >> 8) & 0xFF);
 833                 ha->hw.flags.fduplex = (((data & 0xFF0000) == 0) ? 0 : 1);
 834                 ha->hw.flags.autoneg = (((data & 0xFF000000) == 0) ? 0 : 1);
 835
 836                 data = READ_REG32(ha, (Q8_FW_MBOX0 + 16));
 837                 ha->hw.flags.loopback_mode = data & 0x03;
 838
 839                 ha->hw.link_faults = (data >> 3) & 0xFF;
 840
 841                 break;
 842
 843         case 0x8100:
 844                 ha->hw.imd_compl=1;
 845                 break;
 846
 847         case 0x8101:
 848                 ha->async_event = 1;
 849                 ha->hw.aen_mb0 = 0x8101;
 850                 ha->hw.aen_mb1 = READ_REG32(ha, (Q8_FW_MBOX0 + 4));
 851                 ha->hw.aen_mb2 = READ_REG32(ha, (Q8_FW_MBOX0 + 8));
 852                 ha->hw.aen_mb3 = READ_REG32(ha, (Q8_FW_MBOX0 + 12));
 853                 ha->hw.aen_mb4 = READ_REG32(ha, (Q8_FW_MBOX0 + 16));
 854                 break;
 855
 856         case 0x8110:
 857                 /* for now just dump the registers */
 858                 {
 859                         uint32_t ombx[5];
 860
 861                         ombx[0] = READ_REG32(ha, (Q8_FW_MBOX0 + 4));
 862                         ombx[1] = READ_REG32(ha, (Q8_FW_MBOX0 + 8));
 863                         ombx[2] = READ_REG32(ha, (Q8_FW_MBOX0 + 12));
 864                         ombx[3] = READ_REG32(ha, (Q8_FW_MBOX0 + 16));
 865                         ombx[4] = READ_REG32(ha, (Q8_FW_MBOX0 + 20));
 866
 867                         device_printf(ha->pci_dev, "%s: "
 868                                 "0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
 869                                 __func__, data, ombx[0], ombx[1], ombx[2],
 870                                 ombx[3], ombx[4]);
 871                 }
 872
 873                 break;
 874
 875         case 0x8130:
 876                 /* sfp insertion aen */
 877                 device_printf(ha->pci_dev, "%s: sfp inserted [0x%08x]\n",
 878                         __func__, READ_REG32(ha, (Q8_FW_MBOX0 + 4)));
 879                 break;
 880
 881         case 0x8131:
 882                 /* sfp removal aen */
 883                 device_printf(ha->pci_dev, "%s: sfp removed]\n", __func__);
 884                 break;
 885
 886         case 0x8140:
 887                 {
 888                         uint32_t ombx[3];
 889
 890                         ombx[0] = READ_REG32(ha, (Q8_FW_MBOX0 + 4));
 891                         ombx[1] = READ_REG32(ha, (Q8_FW_MBOX0 + 8));
 892                         ombx[2] = READ_REG32(ha, (Q8_FW_MBOX0 + 12));
 893
 894                         device_printf(ha->pci_dev, "%s: "
 895                                 "0x%08x 0x%08x 0x%08x 0x%08x \n",
 896                                 __func__, data, ombx[0], ombx[1], ombx[2]);
 897                 }
 898                 break;
 899
 900         default:
 901                 device_printf(ha->pci_dev, "%s: AEN[0x%08x]\n", __func__, data);
 902                 break;
 903         }
 904         WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0);
 905         WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
 906         return;
 907 }
 908
 909
 910 static void
 911 qla_replenish_normal_rx(qla_host_t *ha, qla_sds_t *sdsp, uint32_t r_idx)
 912 {
 913         qla_rx_buf_t *rxb;
 914         int count = sdsp->rx_free;
 915         uint32_t rx_next;
 916         qla_rdesc_t *rdesc;
 917
 918         /* we can play with this value via a sysctl */
 919         uint32_t replenish_thresh = ha->hw.rds_pidx_thres;
 920
 921         rdesc = &ha->hw.rds[r_idx];
 922
 923         rx_next = rdesc->rx_next;
 924
 925         while (count--) {
 926                 rxb = sdsp->rxb_free;
 927
 928                 if (rxb == NULL)
 929                         break;
 930
 931                 sdsp->rxb_free = rxb->next;
 932                 sdsp->rx_free--;
 933
 934                 if (ql_get_mbuf(ha, rxb, NULL) == 0) {
 935                         qla_set_hw_rcv_desc(ha, r_idx, rdesc->rx_in,
 936                                 rxb->handle,
 937                                 rxb->paddr, (rxb->m_head)->m_pkthdr.len);
 938                         rdesc->rx_in++;
 939                         if (rdesc->rx_in == NUM_RX_DESCRIPTORS)
 940                                 rdesc->rx_in = 0;
 941                         rdesc->rx_next++;
 942                         if (rdesc->rx_next == NUM_RX_DESCRIPTORS)
 943                                 rdesc->rx_next = 0;
 944                 } else {
 945                         device_printf(ha->pci_dev,
 946                                 "%s: qla_get_mbuf [(%d),(%d),(%d)] failed\n",
 947                                 __func__, r_idx, rdesc->rx_in, rxb->handle);
 948
 949                         rxb->m_head = NULL;
 950                         rxb->next = sdsp->rxb_free;
 951                         sdsp->rxb_free = rxb;
 952                         sdsp->rx_free++;
 953
 954                         break;
 955                 }
 956                 if (replenish_thresh-- == 0) {
 957                         QL_UPDATE_RDS_PRODUCER_INDEX(ha, rdesc->prod_std,
 958                                 rdesc->rx_next);
 959                         rx_next = rdesc->rx_next;
 960                         replenish_thresh = ha->hw.rds_pidx_thres;
 961                 }
 962         }
 963
 964         if (rx_next != rdesc->rx_next) {
 965                 QL_UPDATE_RDS_PRODUCER_INDEX(ha, rdesc->prod_std,
 966                         rdesc->rx_next);
 967         }
 968 }
 969
 970 void
 971 ql_isr(void *arg)
 972 {
 973         qla_ivec_t *ivec = arg;
 974         qla_host_t *ha ;
 975         int idx;
 976         qla_hw_t *hw;
 977         struct ifnet *ifp;
 978         qla_tx_fp_t *fp;
 979
 980         ha = ivec->ha;
 981         hw = &ha->hw;
 982         ifp = ha->ifp;
 983
 984         if ((idx = ivec->sds_idx) >= ha->hw.num_sds_rings)
 985                 return;
 986
 987
 988         fp = &ha->tx_fp[idx];
 989
 990         if ((fp->fp_taskqueue != NULL) &&
 991                 (ifp->if_drv_flags & IFF_DRV_RUNNING))
 992                 taskqueue_enqueue(fp->fp_taskqueue, &fp->fp_task);
 993
 994         return;
 995 }
 996