2 * Copyright (c) 2013-2016 Qlogic Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
33 #ifndef _QL_MINIDUMP_H_
34 #define _QL_MINIDUMP_H_
36 #define QL_DBG_STATE_ARRAY_LEN 16
37 #define QL_DBG_CAP_SIZE_ARRAY_LEN 8
38 #define QL_NO_OF_OCM_WINDOWS 16
41 typedef struct ql_mdump_tmplt_hdr {
43 uint32_t first_entry_offset ;
44 uint32_t size_of_template ;
45 uint32_t recommended_capture_mask;
47 uint32_t num_of_entries ;
49 uint32_t driver_timestamp ;
52 uint32_t driver_capture_mask ;
53 uint32_t driver_info_word2 ;
54 uint32_t driver_info_word3 ;
55 uint32_t driver_info_word4 ;
57 uint32_t saved_state_array[QL_DBG_STATE_ARRAY_LEN] ;
58 uint32_t capture_size_array[QL_DBG_CAP_SIZE_ARRAY_LEN] ;
60 uint32_t ocm_window_array[QL_NO_OF_OCM_WINDOWS] ;
61 } ql_minidump_template_hdr_t ;
64 * MIU AGENT ADDRESSES.
67 #define MD_TA_CTL_ENABLE 0x2
68 #define MD_TA_CTL_START 0x1
69 #define MD_TA_CTL_BUSY 0x8
70 #define MD_TA_CTL_CHECK 1000
72 #define MD_MIU_TEST_AGT_CTRL 0x41000090
73 #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094
74 #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098
76 #define MD_MIU_TEST_AGT_RDDATA_0_31 0x410000A8
77 #define MD_MIU_TEST_AGT_RDDATA_32_63 0x410000AC
78 #define MD_MIU_TEST_AGT_RDDATA_64_95 0x410000B8
79 #define MD_MIU_TEST_AGT_RDDATA_96_127 0x410000BC
81 #define MD_MIU_TEST_AGT_WRDATA_0_31 0x410000A0
82 #define MD_MIU_TEST_AGT_WRDATA_32_63 0x410000A4
83 #define MD_MIU_TEST_AGT_WRDATA_64_95 0x410000B0
84 #define MD_MIU_TEST_AGT_WRDATA_96_127 0x410000B4
90 #define MD_DIRECT_ROM_WINDOW 0x42110030
91 #define MD_DIRECT_ROM_READ_BASE 0x42150000
119 * Index of State Table. The Template header maintains
120 * an array of 8 (0..7) words that is used to store some
121 * "State Information" from the board.
124 #define QL_PCIE_FUNC_INDX 0
125 #define QL_CLK_STATE_INDX 1
126 #define QL_SRE_STATE_INDX 2
127 #define QL_OCM0_ADDR_INDX 3
129 #define QL_REVID_STATE_INDX 4
130 #define QL_MAJVER_STATE_INDX 5
131 #define QL_MINVER_STATE_INDX 6
132 #define QL_SUBVER_STATE_INDX 7
135 * Opcodes for Control Entries.
136 * These Flags are bit fields.
139 #define QL_DBG_OPCODE_WR 0x01
140 #define QL_DBG_OPCODE_RW 0x02
141 #define QL_DBG_OPCODE_AND 0x04
142 #define QL_DBG_OPCODE_OR 0x08
143 #define QL_DBG_OPCODE_POLL 0x10
144 #define QL_DBG_OPCODE_RDSTATE 0x20
145 #define QL_DBG_OPCODE_WRSTATE 0x40
146 #define QL_DBG_OPCODE_MDSTATE 0x80
148 typedef struct ql_minidump_entry_hdr_s {
149 uint32_t entry_type ;
150 uint32_t entry_size ;
151 uint32_t entry_capture_size ;
154 uint8_t entry_capture_mask ;
156 uint8_t driver_code ;
157 uint8_t driver_flags ;
159 uint32_t entry_ctrl_word ;
161 } ql_minidump_entry_hdr_t ;
166 #define QL_DBG_SKIPPED_FLAG 0x80 /* driver skipped this entry */
167 #define QL_DBG_SIZE_ERR_FLAG 0x40 /* entry size vs capture size mismatch*/
170 * Generic Entry Including Header
173 typedef struct ql_minidump_entry_s {
174 ql_minidump_entry_hdr_t hdr ;
176 uint32_t entry_data00 ;
177 uint32_t entry_data01 ;
178 uint32_t entry_data02 ;
179 uint32_t entry_data03 ;
181 uint32_t entry_data04 ;
182 uint32_t entry_data05 ;
183 uint32_t entry_data06 ;
184 uint32_t entry_data07 ;
185 } ql_minidump_entry_t;
188 * Read CRB Entry Header
191 typedef struct ql_minidump_entry_rdcrb_s {
192 ql_minidump_entry_hdr_t h;
197 uint8_t addr_stride ;
201 uint32_t addr_cntrl ;
212 } ql_minidump_entry_rdcrb_t ;
218 typedef struct ql_minidump_entry_cache_s {
219 ql_minidump_entry_hdr_t h;
221 uint32_t tag_reg_addr ;
224 uint16_t tag_value_stride ;
225 uint16_t init_tag_value ;
227 uint32_t select_addr_cntrl ;
233 uint32_t control_addr ;
236 uint16_t write_value ;
240 uint32_t control_value ;
246 uint8_t read_addr_stride ;
247 uint8_t read_addr_cnt ;
250 uint32_t read_addr_cntrl ;
252 } ql_minidump_entry_cache_t ;
256 * Read OCM Entry Header
259 typedef struct ql_minidump_entry_rdocm_s {
260 ql_minidump_entry_hdr_t h;
272 uint32_t read_addr_stride ;
274 } ql_minidump_entry_rdocm_t ;
277 * Read MEM Entry Header
280 typedef struct ql_minidump_entry_rdmem_s {
281 ql_minidump_entry_hdr_t h;
286 uint32_t read_data_size ;
288 } ql_minidump_entry_rdmem_t ;
291 * Read ROM Entry Header
294 typedef struct ql_minidump_entry_rdrom_s {
295 ql_minidump_entry_hdr_t h;
300 uint32_t read_data_size ;
302 } ql_minidump_entry_rdrom_t ;
305 * Read MUX Entry Header
308 typedef struct ql_minidump_entry_mux_s {
309 ql_minidump_entry_hdr_t h;
311 uint32_t select_addr ;
316 uint32_t select_addr_cntrl ;
322 uint32_t select_value ;
323 uint32_t select_value_stride ;
328 } ql_minidump_entry_mux_t ;
331 * Read MUX2 Entry Header
334 typedef struct ql_minidump_entry_mux2_s {
335 ql_minidump_entry_hdr_t h;
337 uint32_t select_addr_1;
338 uint32_t select_addr_2;
339 uint32_t select_value_1;
340 uint32_t select_value_2;
341 uint32_t select_value_count;
342 uint32_t select_value_mask;
346 uint8_t select_value_stride;
351 uint32_t select_addr_value_cntrl;
354 } ql_minidump_entry_mux2_t;
357 * Read QUEUE Entry Header
360 typedef struct ql_minidump_entry_queue_s {
361 ql_minidump_entry_hdr_t h;
363 uint32_t select_addr ;
366 uint16_t queue_id_stride ;
369 uint32_t select_addr_cntrl ;
381 uint8_t read_addr_stride ;
382 uint8_t read_addr_cnt ;
385 uint32_t read_addr_cntrl ;
388 } ql_minidump_entry_queue_t ;
391 * Control Entry Header
394 typedef struct ql_minidump_entry_cntrl_s {
395 ql_minidump_entry_hdr_t h;
400 uint8_t addr_stride ;
401 uint8_t state_index_a ;
402 uint16_t poll_timeout ;
404 uint32_t addr_cntrl ;
413 uint8_t state_index_v ;
417 uint32_t control_value ;
423 } ql_minidump_entry_cntrl_t ;
429 typedef struct ql_minidump_entry_rdcrb_with_poll_s {
430 ql_minidump_entry_hdr_t h;
432 uint32_t select_addr;
434 uint32_t select_value;
437 uint16_t select_value_stride;
440 uint32_t select_value_cntrl;
449 } ql_minidump_entry_pollrd_t;
452 * Read_Modify_Write with poll.
455 typedef struct ql_minidump_entry_rd_modify_wr_with_poll_s {
456 ql_minidump_entry_hdr_t h;
464 uint32_t modify_mask;
467 } ql_minidump_entry_rd_modify_wr_with_poll_t;
469 #endif /* #ifndef _QL_MINIDUMP_H_ */