2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2013-2016 Qlogic Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
31 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
40 #include "ql_inline.h"
45 #define QL_FDT_OFFSET 0x3F0000
46 #define Q8_FLASH_SECTOR_SIZE 0x10000
48 static int qla_ld_fw_init(qla_host_t *ha);
51 * structure encapsulating the value to read/write to offchip memory
53 typedef struct _offchip_mem_val {
61 * Name: ql_rdwr_indreg32
62 * Function: Read/Write an Indirect Register
65 ql_rdwr_indreg32(qla_host_t *ha, uint32_t addr, uint32_t *val, uint32_t rd)
70 wnd_reg = (Q8_CRB_WINDOW_PF0 | (ha->pci_func << 2));
72 WRITE_REG32(ha, wnd_reg, addr);
75 if (READ_REG32(ha, wnd_reg) == addr)
77 qla_mdelay(__func__, 1);
79 if (!count || QL_ERR_INJECT(ha, INJCT_RDWR_INDREG_FAILURE)) {
80 device_printf(ha->pci_dev, "%s: [0x%08x, 0x%08x, %d] failed\n",
81 __func__, addr, *val, rd);
82 QL_INITIATE_RECOVERY(ha);
87 *val = READ_REG32(ha, Q8_WILD_CARD);
89 WRITE_REG32(ha, Q8_WILD_CARD, *val);
96 * Name: ql_rdwr_offchip_mem
97 * Function: Read/Write OffChip Memory
100 ql_rdwr_offchip_mem(qla_host_t *ha, uint64_t addr, q80_offchip_mem_val_t *val,
103 uint32_t count = 100;
104 uint32_t data, step = 0;
107 if (QL_ERR_INJECT(ha, INJCT_RDWR_OFFCHIPMEM_FAILURE))
108 goto exit_ql_rdwr_offchip_mem;
110 data = (uint32_t)addr;
111 if (ql_rdwr_indreg32(ha, Q8_MS_ADDR_LO, &data, 0)) {
113 goto exit_ql_rdwr_offchip_mem;
116 data = (uint32_t)(addr >> 32);
117 if (ql_rdwr_indreg32(ha, Q8_MS_ADDR_HI, &data, 0)) {
119 goto exit_ql_rdwr_offchip_mem;
123 if (ql_rdwr_indreg32(ha, Q8_MS_CNTRL, &data, 0)) {
125 goto exit_ql_rdwr_offchip_mem;
130 if (ql_rdwr_indreg32(ha, Q8_MS_WR_DATA_0_31, &data, 0)) {
132 goto exit_ql_rdwr_offchip_mem;
136 if (ql_rdwr_indreg32(ha, Q8_MS_WR_DATA_32_63, &data, 0)) {
138 goto exit_ql_rdwr_offchip_mem;
141 data = val->data_ulo;
142 if (ql_rdwr_indreg32(ha, Q8_MS_WR_DATA_64_95, &data, 0)) {
144 goto exit_ql_rdwr_offchip_mem;
147 data = val->data_uhi;
148 if (ql_rdwr_indreg32(ha, Q8_MS_WR_DATA_96_127, &data, 0)) {
150 goto exit_ql_rdwr_offchip_mem;
153 data = (BIT_2|BIT_1|BIT_0);
154 if (ql_rdwr_indreg32(ha, Q8_MS_CNTRL, &data, 0)) {
156 goto exit_ql_rdwr_offchip_mem;
159 data = (BIT_1|BIT_0);
160 if (ql_rdwr_indreg32(ha, Q8_MS_CNTRL, &data, 0)) {
162 goto exit_ql_rdwr_offchip_mem;
167 if (ql_rdwr_indreg32(ha, Q8_MS_CNTRL, &data, 1)) {
169 goto exit_ql_rdwr_offchip_mem;
172 if (!(data & BIT_3)) {
174 if (ql_rdwr_indreg32(ha, Q8_MS_RD_DATA_0_31,
177 goto exit_ql_rdwr_offchip_mem;
181 if (ql_rdwr_indreg32(ha, Q8_MS_RD_DATA_32_63,
184 goto exit_ql_rdwr_offchip_mem;
188 if (ql_rdwr_indreg32(ha, Q8_MS_RD_DATA_64_95,
191 goto exit_ql_rdwr_offchip_mem;
193 val->data_ulo = data;
195 if (ql_rdwr_indreg32(ha, Q8_MS_RD_DATA_96_127,
198 goto exit_ql_rdwr_offchip_mem;
200 val->data_uhi = data;
204 qla_mdelay(__func__, 1);
207 exit_ql_rdwr_offchip_mem:
209 device_printf(ha->pci_dev,
210 "%s: [0x%08x 0x%08x : 0x%08x 0x%08x 0x%08x 0x%08x]"
211 " [%d] [%d] failed\n", __func__, (uint32_t)(addr >> 32),
212 (uint32_t)(addr), val->data_lo, val->data_hi, val->data_ulo,
213 val->data_uhi, rd, step);
215 QL_INITIATE_RECOVERY(ha);
221 * Name: ql_rd_flash32
222 * Function: Read Flash Memory
225 ql_rd_flash32(qla_host_t *ha, uint32_t addr, uint32_t *data)
229 if (qla_sem_lock(ha, Q8_FLASH_LOCK, Q8_FLASH_LOCK_ID, 0xABCDABCD)) {
230 device_printf(ha->pci_dev, "%s: Q8_FLASH_LOCK failed\n",
236 if (ql_rdwr_indreg32(ha, Q8_FLASH_DIRECT_WINDOW, &data32, 0)) {
237 qla_sem_unlock(ha, Q8_FLASH_UNLOCK);
238 device_printf(ha->pci_dev,
239 "%s: Q8_FLASH_DIRECT_WINDOW[0x%08x] failed\n",
244 data32 = Q8_FLASH_DIRECT_DATA | (addr & 0xFFFF);
245 if (ql_rdwr_indreg32(ha, data32, data, 1)) {
246 qla_sem_unlock(ha, Q8_FLASH_UNLOCK);
247 device_printf(ha->pci_dev,
248 "%s: data32:data [0x%08x] failed\n",
253 qla_sem_unlock(ha, Q8_FLASH_UNLOCK);
258 qla_get_fdt(qla_host_t *ha)
266 for (count = 0; count < sizeof(qla_flash_desc_table_t); count+=4) {
267 if (ql_rd_flash32(ha, QL_FDT_OFFSET + count,
268 (uint32_t *)&hw->fdt + (count >> 2))) {
269 device_printf(ha->pci_dev,
270 "%s: Read QL_FDT_OFFSET + %d failed\n",
276 if (qla_sem_lock(ha, Q8_FLASH_LOCK, Q8_FLASH_LOCK_ID,
277 Q8_FDT_LOCK_MAGIC_ID)) {
278 device_printf(ha->pci_dev, "%s: Q8_FLASH_LOCK failed\n",
283 data32 = Q8_FDT_FLASH_ADDR_VAL;
284 if (ql_rdwr_indreg32(ha, Q8_FLASH_ADDRESS, &data32, 0)) {
285 qla_sem_unlock(ha, Q8_FLASH_UNLOCK);
286 device_printf(ha->pci_dev,
287 "%s: Write to Q8_FLASH_ADDRESS failed\n",
292 data32 = Q8_FDT_FLASH_CTRL_VAL;
293 if (ql_rdwr_indreg32(ha, Q8_FLASH_CONTROL, &data32, 0)) {
294 qla_sem_unlock(ha, Q8_FLASH_UNLOCK);
295 device_printf(ha->pci_dev,
296 "%s: Write to Q8_FLASH_CONTROL failed\n",
308 qla_mdelay(__func__, 1);
314 if (ql_rdwr_indreg32(ha, Q8_FLASH_STATUS, &data32, 1)) {
315 qla_sem_unlock(ha, Q8_FLASH_UNLOCK);
316 device_printf(ha->pci_dev,
317 "%s: Read Q8_FLASH_STATUS failed\n",
324 } while ((count < 10000) && (data32 != 0x6));
327 qla_sem_unlock(ha, Q8_FLASH_UNLOCK);
328 device_printf(ha->pci_dev,
329 "%s: Poll Q8_FLASH_STATUS failed\n",
334 if (ql_rdwr_indreg32(ha, Q8_FLASH_RD_DATA, &data32, 1)) {
335 qla_sem_unlock(ha, Q8_FLASH_UNLOCK);
336 device_printf(ha->pci_dev,
337 "%s: Read Q8_FLASH_RD_DATA failed\n",
342 qla_sem_unlock(ha, Q8_FLASH_UNLOCK);
344 data32 &= Q8_FDT_MASK_VAL;
345 if (hw->fdt.flash_manuf == data32)
352 qla_flash_write_enable(qla_host_t *ha, int enable)
357 data32 = Q8_WR_ENABLE_FL_ADDR | ha->hw.fdt.write_statusreg_cmd;
358 if (ql_rdwr_indreg32(ha, Q8_FLASH_ADDRESS, &data32, 0)) {
359 device_printf(ha->pci_dev,
360 "%s: Write to Q8_FLASH_ADDRESS failed\n",
366 data32 = ha->hw.fdt.write_enable_bits;
368 data32 = ha->hw.fdt.write_disable_bits;
370 if (ql_rdwr_indreg32(ha, Q8_FLASH_WR_DATA, &data32, 0)) {
371 device_printf(ha->pci_dev,
372 "%s: Write to Q8_FLASH_WR_DATA failed\n",
377 data32 = Q8_WR_ENABLE_FL_CTRL;
378 if (ql_rdwr_indreg32(ha, Q8_FLASH_CONTROL, &data32, 0)) {
379 device_printf(ha->pci_dev,
380 "%s: Write to Q8_FLASH_CONTROL failed\n",
390 qla_mdelay(__func__, 1);
395 if (ql_rdwr_indreg32(ha, Q8_FLASH_STATUS, &data32, 1)) {
396 device_printf(ha->pci_dev,
397 "%s: Read Q8_FLASH_STATUS failed\n",
404 } while ((count < 10000) && (data32 != 0x6));
407 device_printf(ha->pci_dev,
408 "%s: Poll Q8_FLASH_STATUS failed\n",
417 qla_erase_flash_sector(qla_host_t *ha, uint32_t start)
423 qla_mdelay(__func__, 1);
426 if (ql_rdwr_indreg32(ha, Q8_FLASH_STATUS, &data32, 1)) {
427 device_printf(ha->pci_dev,
428 "%s: Read Q8_FLASH_STATUS failed\n",
435 } while (((count++) < 1000) && (data32 != 0x6));
438 device_printf(ha->pci_dev,
439 "%s: Poll Q8_FLASH_STATUS failed\n",
444 data32 = (start >> 16) & 0xFF;
445 if (ql_rdwr_indreg32(ha, Q8_FLASH_WR_DATA, &data32, 0)) {
446 device_printf(ha->pci_dev,
447 "%s: Write to Q8_FLASH_WR_DATA failed\n",
452 data32 = Q8_ERASE_FL_ADDR_MASK | ha->hw.fdt.erase_cmd;
453 if (ql_rdwr_indreg32(ha, Q8_FLASH_ADDRESS, &data32, 0)) {
454 device_printf(ha->pci_dev,
455 "%s: Write to Q8_FLASH_ADDRESS failed\n",
460 data32 = Q8_ERASE_FL_CTRL_MASK;
461 if (ql_rdwr_indreg32(ha, Q8_FLASH_CONTROL, &data32, 0)) {
462 device_printf(ha->pci_dev,
463 "%s: Write to Q8_FLASH_CONTROL failed\n",
470 qla_mdelay(__func__, 1);
473 if (ql_rdwr_indreg32(ha, Q8_FLASH_STATUS, &data32, 1)) {
474 device_printf(ha->pci_dev,
475 "%s: Read Q8_FLASH_STATUS failed\n",
482 } while (((count++) < 1000) && (data32 != 0x6));
485 device_printf(ha->pci_dev,
486 "%s: Poll Q8_FLASH_STATUS failed\n",
495 ql_erase_flash(qla_host_t *ha, uint32_t off, uint32_t size)
500 if (off & (Q8_FLASH_SECTOR_SIZE -1))
503 if (qla_sem_lock(ha, Q8_FLASH_LOCK, Q8_FLASH_LOCK_ID,
504 Q8_ERASE_LOCK_MAGIC_ID)) {
505 device_printf(ha->pci_dev, "%s: Q8_FLASH_LOCK failed\n",
510 if (qla_flash_write_enable(ha, 1) != 0) {
512 goto ql_erase_flash_exit;
515 for (start = off; start < (off + size); start = start +
516 Q8_FLASH_SECTOR_SIZE) {
517 if (qla_erase_flash_sector(ha, start)) {
523 rval = qla_flash_write_enable(ha, 0);
526 qla_sem_unlock(ha, Q8_FLASH_UNLOCK);
531 qla_wr_flash32(qla_host_t *ha, uint32_t off, uint32_t *data)
536 data32 = Q8_WR_FL_ADDR_MASK | (off >> 2);
537 if (ql_rdwr_indreg32(ha, Q8_FLASH_ADDRESS, &data32, 0)) {
538 device_printf(ha->pci_dev,
539 "%s: Write to Q8_FLASH_ADDRESS failed\n",
544 if (ql_rdwr_indreg32(ha, Q8_FLASH_WR_DATA, data, 0)) {
545 device_printf(ha->pci_dev,
546 "%s: Write to Q8_FLASH_WR_DATA failed\n",
551 data32 = Q8_WR_FL_CTRL_MASK;
552 if (ql_rdwr_indreg32(ha, Q8_FLASH_CONTROL, &data32, 0)) {
553 device_printf(ha->pci_dev,
554 "%s: Write to Q8_FLASH_CONTROL failed\n",
564 qla_mdelay(__func__, 1);
569 if (ql_rdwr_indreg32(ha, Q8_FLASH_STATUS, &data32, 1)) {
570 device_printf(ha->pci_dev,
571 "%s: Read Q8_FLASH_STATUS failed\n",
578 } while ((count < 10000) && (data32 != 0x6));
581 device_printf(ha->pci_dev,
582 "%s: Poll Q8_FLASH_STATUS failed\n",
591 qla_flash_write_data(qla_host_t *ha, uint32_t off, uint32_t size,
596 uint32_t *data32 = data;
598 if (qla_sem_lock(ha, Q8_FLASH_LOCK, Q8_FLASH_LOCK_ID,
599 Q8_WR_FL_LOCK_MAGIC_ID)) {
600 device_printf(ha->pci_dev, "%s: Q8_FLASH_LOCK failed\n",
603 goto qla_flash_write_data_exit;
606 if ((qla_flash_write_enable(ha, 1) != 0)) {
607 device_printf(ha->pci_dev, "%s: failed\n",
610 goto qla_flash_write_data_unlock_exit;
613 for (start = off; start < (off + size); start = start + 4) {
614 if (*data32 != 0xFFFFFFFF) {
615 if (qla_wr_flash32(ha, start, data32)) {
623 rval = qla_flash_write_enable(ha, 0);
625 qla_flash_write_data_unlock_exit:
626 qla_sem_unlock(ha, Q8_FLASH_UNLOCK);
628 qla_flash_write_data_exit:
633 ql_wr_flash_buffer(qla_host_t *ha, uint32_t off, uint32_t size, void *buf)
646 if ((data = malloc(size, M_QLA83XXBUF, M_NOWAIT)) == NULL) {
647 device_printf(ha->pci_dev, "%s: malloc failed \n", __func__);
649 goto ql_wr_flash_buffer_exit;
652 if ((rval = copyin(buf, data, size))) {
653 device_printf(ha->pci_dev, "%s copyin failed\n", __func__);
654 goto ql_wr_flash_buffer_free_exit;
657 rval = qla_flash_write_data(ha, off, size, data);
659 ql_wr_flash_buffer_free_exit:
660 free(data, M_QLA83XXBUF);
662 ql_wr_flash_buffer_exit:
668 * Name: qla_load_fw_from_flash
669 * Function: Reads the Bootloader from Flash and Loads into Offchip Memory
672 qla_load_fw_from_flash(qla_host_t *ha)
674 uint32_t flash_off = 0x10000;
676 uint32_t count, mem_size;
677 q80_offchip_mem_val_t val;
679 mem_off = (uint64_t)(READ_REG32(ha, Q8_BOOTLD_ADDR));
680 mem_size = READ_REG32(ha, Q8_BOOTLD_SIZE);
682 device_printf(ha->pci_dev, "%s: [0x%08x][0x%08x]\n",
683 __func__, (uint32_t)mem_off, mem_size);
685 /* only bootloader needs to be loaded into memory */
686 for (count = 0; count < mem_size ; ) {
687 ql_rd_flash32(ha, flash_off, &val.data_lo);
689 flash_off = flash_off + 4;
691 ql_rd_flash32(ha, flash_off, &val.data_hi);
693 flash_off = flash_off + 4;
695 ql_rd_flash32(ha, flash_off, &val.data_ulo);
697 flash_off = flash_off + 4;
699 ql_rd_flash32(ha, flash_off, &val.data_uhi);
701 flash_off = flash_off + 4;
703 ql_rdwr_offchip_mem(ha, mem_off, &val, 0);
705 mem_off = mem_off + 16;
710 #endif /* #ifdef QL_LDFLASH_FW */
713 * Name: qla_init_from_flash
714 * Function: Performs Initialization which consists of the following sequence
718 * - Read the Bootloader from Flash and Load into Offchip Memory
719 * - Kick start the bootloader which loads the rest of the firmware
720 * and performs the remaining steps in the initialization process.
723 qla_init_from_flash(qla_host_t *ha)
725 uint32_t delay = 300;
731 data = READ_REG32(ha, Q8_CMDPEG_STATE);
734 (ha->pci_dev, "%s: func[%d] cmdpegstate 0x%08x\n",
735 __func__, ha->pci_func, data));
736 if (data == 0xFF01) {
737 QL_DPRINT2(ha, (ha->pci_dev,
738 "%s: func[%d] init complete\n",
739 __func__, ha->pci_func));
742 qla_mdelay(__func__, 100);
750 * Function: Initializes P3+ hardware.
753 ql_init_hw(qla_host_t *ha)
757 uint32_t val, delay = 300;
761 QL_DPRINT1(ha, (dev, "%s: enter\n", __func__));
763 if (ha->pci_func & 0x1) {
765 while ((ha->pci_func & 0x1) && delay--) {
767 val = READ_REG32(ha, Q8_CMDPEG_STATE);
771 "%s: func = %d init complete\n",
772 __func__, ha->pci_func));
773 qla_mdelay(__func__, 100);
776 qla_mdelay(__func__, 100);
779 goto ql_init_hw_exit;
783 val = READ_REG32(ha, Q8_CMDPEG_STATE);
784 if (!cold || (val != 0xFF01) || ha->qla_initiate_recovery) {
785 ret = qla_init_from_flash(ha);
786 qla_mdelay(__func__, 100);
790 ha->fw_ver_major = READ_REG32(ha, Q8_FW_VER_MAJOR);
791 ha->fw_ver_minor = READ_REG32(ha, Q8_FW_VER_MINOR);
792 ha->fw_ver_sub = READ_REG32(ha, Q8_FW_VER_SUB);
794 if (qla_get_fdt(ha) != 0) {
795 device_printf(dev, "%s: qla_get_fdt failed\n", __func__);
797 ha->hw.flags.fdt_valid = 1;
803 if (ha->hw.sp_log_stop_events & Q8_SP_LOG_STOP_HW_INIT_FAILURE)
804 ha->hw.sp_log_stop = -1;
811 ql_read_mac_addr(qla_host_t *ha)
818 flash_off = Q8_BOARD_CONFIG_OFFSET + Q8_BOARD_CONFIG_MAC0_LO +
820 ql_rd_flash32(ha, flash_off, &mac_lo);
823 ql_rd_flash32(ha, flash_off, &mac_hi);
825 macp = (uint8_t *)&mac_lo;
826 ha->hw.mac_addr[5] = macp[0];
827 ha->hw.mac_addr[4] = macp[1];
828 ha->hw.mac_addr[3] = macp[2];
829 ha->hw.mac_addr[2] = macp[3];
831 macp = (uint8_t *)&mac_hi;
832 ha->hw.mac_addr[1] = macp[0];
833 ha->hw.mac_addr[0] = macp[1];
835 //device_printf(ha->pci_dev, "%s: %02x:%02x:%02x:%02x:%02x:%02x\n",
836 // __func__, ha->hw.mac_addr[0], ha->hw.mac_addr[1],
837 // ha->hw.mac_addr[2], ha->hw.mac_addr[3],
838 // ha->hw.mac_addr[4], ha->hw.mac_addr[5]);
844 * Stop/Start/Initialization Handling
848 qla_tmplt_16bit_checksum(qla_host_t *ha, uint16_t *buf, uint32_t size)
851 uint32_t count = size >> 1; /* size in 16 bit words */
857 sum = (sum & 0xFFFF) + (sum >> 16);
863 qla_wr_list(qla_host_t *ha, q8_ce_hdr_t *ce_hdr)
868 wr_l = (q8_wrl_e_t *)((uint8_t *)ce_hdr + sizeof (q8_ce_hdr_t));
870 for (i = 0; i < ce_hdr->opcount; i++, wr_l++) {
872 if (ql_rdwr_indreg32(ha, wr_l->addr, &wr_l->value, 0)) {
873 device_printf(ha->pci_dev,
874 "%s: [0x%08x 0x%08x] error\n", __func__,
875 wr_l->addr, wr_l->value);
878 if (ce_hdr->delay_to) {
879 DELAY(ce_hdr->delay_to);
886 qla_rd_wr_list(qla_host_t *ha, q8_ce_hdr_t *ce_hdr)
888 q8_rdwrl_e_t *rd_wr_l;
892 rd_wr_l = (q8_rdwrl_e_t *)((uint8_t *)ce_hdr + sizeof (q8_ce_hdr_t));
894 for (i = 0; i < ce_hdr->opcount; i++, rd_wr_l++) {
896 if (ql_rdwr_indreg32(ha, rd_wr_l->rd_addr, &data, 1)) {
897 device_printf(ha->pci_dev, "%s: [0x%08x] error\n",
898 __func__, rd_wr_l->rd_addr);
903 if (ql_rdwr_indreg32(ha, rd_wr_l->wr_addr, &data, 0)) {
904 device_printf(ha->pci_dev,
905 "%s: [0x%08x 0x%08x] error\n", __func__,
906 rd_wr_l->wr_addr, data);
909 if (ce_hdr->delay_to) {
910 DELAY(ce_hdr->delay_to);
917 qla_poll_reg(qla_host_t *ha, uint32_t addr, uint32_t ms_to, uint32_t tmask,
924 if (ql_rdwr_indreg32(ha, addr, &data, 1)) {
925 device_printf(ha->pci_dev, "%s: [0x%08x] error\n",
930 if ((data & tmask) != tvalue) {
935 qla_mdelay(__func__, 1);
937 return ((ms_to ? 0: -1));
941 qla_poll_list(qla_host_t *ha, q8_ce_hdr_t *ce_hdr)
948 phdr = (q8_poll_hdr_t *)((uint8_t *)ce_hdr + sizeof (q8_ce_hdr_t));
949 pe = (q8_poll_e_t *)((uint8_t *)phdr + sizeof(q8_poll_hdr_t));
951 for (i = 0; i < ce_hdr->opcount; i++, pe++) {
952 if (ql_rdwr_indreg32(ha, pe->addr, &data, 1)) {
953 device_printf(ha->pci_dev, "%s: [0x%08x] error\n",
958 if (ce_hdr->delay_to) {
959 if ((data & phdr->tmask) == phdr->tvalue)
961 if (qla_poll_reg(ha, pe->addr, ce_hdr->delay_to,
962 phdr->tmask, phdr->tvalue)) {
964 if (ql_rdwr_indreg32(ha, pe->to_addr, &data,
966 device_printf(ha->pci_dev,
967 "%s: [0x%08x] error\n",
968 __func__, pe->to_addr);
972 if (ql_rdwr_indreg32(ha, pe->addr, &data, 1)) {
973 device_printf(ha->pci_dev,
974 "%s: [0x%08x] error\n",
985 qla_poll_write_list(qla_host_t *ha, q8_ce_hdr_t *ce_hdr)
989 q8_poll_wr_e_t *wr_e;
991 phdr = (q8_poll_hdr_t *)((uint8_t *)ce_hdr + sizeof (q8_ce_hdr_t));
992 wr_e = (q8_poll_wr_e_t *)((uint8_t *)phdr + sizeof(q8_poll_hdr_t));
994 for (i = 0; i < ce_hdr->opcount; i++, wr_e++) {
996 if (ql_rdwr_indreg32(ha, wr_e->dr_addr, &wr_e->dr_value, 0)) {
997 device_printf(ha->pci_dev,
998 "%s: [0x%08x 0x%08x] error\n", __func__,
999 wr_e->dr_addr, wr_e->dr_value);
1002 if (ql_rdwr_indreg32(ha, wr_e->ar_addr, &wr_e->ar_value, 0)) {
1003 device_printf(ha->pci_dev,
1004 "%s: [0x%08x 0x%08x] error\n", __func__,
1005 wr_e->ar_addr, wr_e->ar_value);
1008 if (ce_hdr->delay_to) {
1009 if (qla_poll_reg(ha, wr_e->ar_addr, ce_hdr->delay_to,
1010 phdr->tmask, phdr->tvalue))
1011 device_printf(ha->pci_dev, "%s: "
1012 "[ar_addr, ar_value, delay, tmask,"
1013 "tvalue] [0x%08x 0x%08x 0x%08x 0x%08x"
1015 __func__, wr_e->ar_addr, wr_e->ar_value,
1016 ce_hdr->delay_to, phdr->tmask,
1024 qla_poll_read_list(qla_host_t *ha, q8_ce_hdr_t *ce_hdr)
1027 q8_poll_hdr_t *phdr;
1028 q8_poll_rd_e_t *rd_e;
1031 phdr = (q8_poll_hdr_t *)((uint8_t *)ce_hdr + sizeof (q8_ce_hdr_t));
1032 rd_e = (q8_poll_rd_e_t *)((uint8_t *)phdr + sizeof(q8_poll_hdr_t));
1034 for (i = 0; i < ce_hdr->opcount; i++, rd_e++) {
1035 if (ql_rdwr_indreg32(ha, rd_e->ar_addr, &rd_e->ar_value, 0)) {
1036 device_printf(ha->pci_dev,
1037 "%s: [0x%08x 0x%08x] error\n", __func__,
1038 rd_e->ar_addr, rd_e->ar_value);
1042 if (ce_hdr->delay_to) {
1043 if (qla_poll_reg(ha, rd_e->ar_addr, ce_hdr->delay_to,
1044 phdr->tmask, phdr->tvalue)) {
1047 if (ql_rdwr_indreg32(ha, rd_e->dr_addr,
1049 device_printf(ha->pci_dev,
1050 "%s: [0x%08x] error\n",
1051 __func__, rd_e->ar_addr);
1055 ha->hw.rst_seq[ha->hw.rst_seq_idx++] = value;
1056 if (ha->hw.rst_seq_idx == Q8_MAX_RESET_SEQ_IDX)
1057 ha->hw.rst_seq_idx = 1;
1065 qla_rdmwr(qla_host_t *ha, uint32_t raddr, uint32_t waddr, q8_rdmwr_hdr_t *hdr)
1069 if (hdr->index_a >= Q8_MAX_RESET_SEQ_IDX) {
1070 device_printf(ha->pci_dev, "%s: [0x%08x] error\n", __func__,
1076 value = ha->hw.rst_seq[hdr->index_a];
1078 if (ql_rdwr_indreg32(ha, raddr, &value, 1)) {
1079 device_printf(ha->pci_dev, "%s: [0x%08x] error\n",
1085 value &= hdr->and_value;
1088 value |= hdr->or_value;
1089 value ^= hdr->xor_value;
1091 if (ql_rdwr_indreg32(ha, waddr, &value, 0)) {
1092 device_printf(ha->pci_dev, "%s: [0x%08x] error\n", __func__,
1100 qla_read_modify_write_list(qla_host_t *ha, q8_ce_hdr_t *ce_hdr)
1103 q8_rdmwr_hdr_t *rdmwr_hdr;
1104 q8_rdmwr_e_t *rdmwr_e;
1106 rdmwr_hdr = (q8_rdmwr_hdr_t *)((uint8_t *)ce_hdr +
1107 sizeof (q8_ce_hdr_t));
1108 rdmwr_e = (q8_rdmwr_e_t *)((uint8_t *)rdmwr_hdr +
1109 sizeof(q8_rdmwr_hdr_t));
1111 for (i = 0; i < ce_hdr->opcount; i++, rdmwr_e++) {
1113 if (qla_rdmwr(ha, rdmwr_e->rd_addr, rdmwr_e->wr_addr,
1117 if (ce_hdr->delay_to) {
1118 DELAY(ce_hdr->delay_to);
1125 qla_tmplt_execute(qla_host_t *ha, uint8_t *buf, int start_idx, int *end_idx,
1128 int i, ret = 0, proc_end = 0;
1129 q8_ce_hdr_t *ce_hdr;
1131 for (i = start_idx; ((i < nentries) && (!proc_end)); i++) {
1132 ce_hdr = (q8_ce_hdr_t *)buf;
1135 switch (ce_hdr->opcode) {
1136 case Q8_CE_OPCODE_NOP:
1139 case Q8_CE_OPCODE_WRITE_LIST:
1140 ret = qla_wr_list(ha, ce_hdr);
1141 //printf("qla_wr_list %d\n", ret);
1144 case Q8_CE_OPCODE_READ_WRITE_LIST:
1145 ret = qla_rd_wr_list(ha, ce_hdr);
1146 //printf("qla_rd_wr_list %d\n", ret);
1149 case Q8_CE_OPCODE_POLL_LIST:
1150 ret = qla_poll_list(ha, ce_hdr);
1151 //printf("qla_poll_list %d\n", ret);
1154 case Q8_CE_OPCODE_POLL_WRITE_LIST:
1155 ret = qla_poll_write_list(ha, ce_hdr);
1156 //printf("qla_poll_write_list %d\n", ret);
1159 case Q8_CE_OPCODE_POLL_RD_LIST:
1160 ret = qla_poll_read_list(ha, ce_hdr);
1161 //printf("qla_poll_read_list %d\n", ret);
1164 case Q8_CE_OPCODE_READ_MODIFY_WRITE:
1165 ret = qla_read_modify_write_list(ha, ce_hdr);
1166 //printf("qla_read_modify_write_list %d\n", ret);
1169 case Q8_CE_OPCODE_SEQ_PAUSE:
1170 if (ce_hdr->delay_to) {
1171 qla_mdelay(__func__, ce_hdr->delay_to);
1175 case Q8_CE_OPCODE_SEQ_END:
1179 case Q8_CE_OPCODE_TMPLT_END:
1187 buf += ce_hdr->size;
1194 #ifndef QL_LDFLASH_FW
1196 qla_load_offchip_mem(qla_host_t *ha, uint64_t addr, uint32_t *data32,
1199 q80_offchip_mem_val_t val;
1204 val.data_lo = *data32++;
1205 val.data_hi = *data32++;
1206 val.data_ulo = *data32++;
1207 val.data_uhi = *data32++;
1209 if (ql_rdwr_offchip_mem(ha, addr, &val, 0))
1212 addr += (uint64_t)16;
1218 bzero(&val, sizeof(q80_offchip_mem_val_t));
1222 val.data_lo = *data32++;
1223 val.data_hi = *data32++;
1224 val.data_ulo = *data32++;
1225 ret = ql_rdwr_offchip_mem(ha, addr, &val, 0);
1229 val.data_lo = *data32++;
1230 val.data_hi = *data32++;
1231 ret = ql_rdwr_offchip_mem(ha, addr, &val, 0);
1235 val.data_lo = *data32++;
1236 ret = ql_rdwr_offchip_mem(ha, addr, &val, 0);
1248 qla_load_bootldr(qla_host_t *ha)
1255 addr = (uint64_t)(READ_REG32(ha, Q8_BOOTLD_ADDR));
1256 data32 = (uint32_t *)ql83xx_bootloader;
1257 len32 = ql83xx_bootloader_len >> 2;
1259 ret = qla_load_offchip_mem(ha, addr, data32, len32);
1265 qla_load_fwimage(qla_host_t *ha)
1272 addr = (uint64_t)(READ_REG32(ha, Q8_FW_IMAGE_ADDR));
1273 data32 = (uint32_t *)ql83xx_firmware;
1274 len32 = ql83xx_firmware_len >> 2;
1276 ret = qla_load_offchip_mem(ha, addr, data32, len32);
1280 #endif /* #ifndef QL_LDFLASH_FW */
1283 qla_ld_fw_init(qla_host_t *ha)
1286 uint32_t index = 0, end_idx;
1287 q8_tmplt_hdr_t *hdr;
1289 bzero(ha->hw.rst_seq, sizeof (ha->hw.rst_seq));
1291 hdr = (q8_tmplt_hdr_t *)ql83xx_resetseq;
1293 device_printf(ha->pci_dev, "%s: reset sequence\n", __func__);
1294 if (qla_tmplt_16bit_checksum(ha, (uint16_t *)ql83xx_resetseq,
1295 (uint32_t)hdr->size)) {
1296 device_printf(ha->pci_dev, "%s: reset seq checksum failed\n",
1302 buf = ql83xx_resetseq + hdr->stop_seq_off;
1304 device_printf(ha->pci_dev, "%s: stop sequence\n", __func__);
1305 if (qla_tmplt_execute(ha, buf, index , &end_idx, hdr->nentries)) {
1306 device_printf(ha->pci_dev, "%s: stop seq failed\n", __func__);
1312 buf = ql83xx_resetseq + hdr->init_seq_off;
1314 device_printf(ha->pci_dev, "%s: init sequence\n", __func__);
1315 if (qla_tmplt_execute(ha, buf, index , &end_idx, hdr->nentries)) {
1316 device_printf(ha->pci_dev, "%s: init seq failed\n", __func__);
1320 #ifdef QL_LDFLASH_FW
1321 qla_load_fw_from_flash(ha);
1322 WRITE_REG32(ha, Q8_FW_IMAGE_VALID, 0);
1324 if (qla_load_bootldr(ha))
1327 if (qla_load_fwimage(ha))
1330 WRITE_REG32(ha, Q8_FW_IMAGE_VALID, 0x12345678);
1331 #endif /* #ifdef QL_LDFLASH_FW */
1334 buf = ql83xx_resetseq + hdr->start_seq_off;
1336 device_printf(ha->pci_dev, "%s: start sequence\n", __func__);
1337 if (qla_tmplt_execute(ha, buf, index , &end_idx, hdr->nentries)) {
1338 device_printf(ha->pci_dev, "%s: init seq failed\n", __func__);
1346 ql_stop_sequence(qla_host_t *ha)
1349 uint32_t index = 0, end_idx;
1350 q8_tmplt_hdr_t *hdr;
1352 bzero(ha->hw.rst_seq, sizeof (ha->hw.rst_seq));
1354 hdr = (q8_tmplt_hdr_t *)ql83xx_resetseq;
1356 if (qla_tmplt_16bit_checksum(ha, (uint16_t *)ql83xx_resetseq,
1357 (uint32_t)hdr->size)) {
1358 device_printf(ha->pci_dev, "%s: reset seq checksum failed\n",
1363 buf = ql83xx_resetseq + hdr->stop_seq_off;
1365 device_printf(ha->pci_dev, "%s: stop sequence\n", __func__);
1366 if (qla_tmplt_execute(ha, buf, index , &end_idx, hdr->nentries)) {
1367 device_printf(ha->pci_dev, "%s: stop seq failed\n", __func__);
1375 ql_start_sequence(qla_host_t *ha, uint16_t index)
1379 q8_tmplt_hdr_t *hdr;
1381 bzero(ha->hw.rst_seq, sizeof (ha->hw.rst_seq));
1383 hdr = (q8_tmplt_hdr_t *)ql83xx_resetseq;
1385 if (qla_tmplt_16bit_checksum(ha, (uint16_t *)ql83xx_resetseq,
1386 (uint32_t)hdr->size)) {
1387 device_printf(ha->pci_dev, "%s: reset seq checksum failed\n",
1392 buf = ql83xx_resetseq + hdr->init_seq_off;
1394 device_printf(ha->pci_dev, "%s: init sequence\n", __func__);
1395 if (qla_tmplt_execute(ha, buf, index , &end_idx, hdr->nentries)) {
1396 device_printf(ha->pci_dev, "%s: init seq failed\n", __func__);
1400 #ifdef QL_LDFLASH_FW
1401 qla_load_fw_from_flash(ha);
1402 WRITE_REG32(ha, Q8_FW_IMAGE_VALID, 0);
1404 if (qla_load_bootldr(ha))
1407 if (qla_load_fwimage(ha))
1410 WRITE_REG32(ha, Q8_FW_IMAGE_VALID, 0x12345678);
1411 #endif /* #ifdef QL_LDFLASH_FW */
1415 buf = ql83xx_resetseq + hdr->start_seq_off;
1417 device_printf(ha->pci_dev, "%s: start sequence\n", __func__);
1418 if (qla_tmplt_execute(ha, buf, index , &end_idx, hdr->nentries)) {
1419 device_printf(ha->pci_dev, "%s: init seq failed\n", __func__);