2 * Copyright (c) 2013-2014 Qlogic Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
32 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
39 * structure encapsulating a DMA buffer
47 bus_dma_tag_t dma_tag;
49 typedef struct qla_dma qla_dma_t;
52 * structure encapsulating interrupt vectors
61 typedef struct qla_ivec qla_ivec_t;
64 * Transmit Related Definitions
67 #define MAX_TX_RINGS 1
68 #define NUM_TX_DESCRIPTORS 1024
70 #define QLA_MAX_SEGMENTS 64 /* maximum # of segs in a sg list */
71 #define QLA_OAL_BLK_SIZE (sizeof (q81_txb_desc_t) * QLA_MAX_SEGMENTS)
73 #define QLA_TX_OALB_TOTAL_SIZE (NUM_TX_DESCRIPTORS * QLA_OAL_BLK_SIZE)
75 #define QLA_TX_PRIVATE_BSIZE ((QLA_TX_OALB_TOTAL_SIZE + \
77 (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1))
79 #define QLA_MAX_MTU 9000
80 #define QLA_STD_FRAME_SIZE 1514
81 #define QLA_MAX_TSO_FRAME_SIZE ((64 * 1024 - 1) + 22)
83 #define QL_FRAME_HDR_SIZE (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +\
84 sizeof (struct ip6_hdr) + sizeof (struct tcphdr) + 16)
90 /* The number of entries in the OAL is determined by QLA_MAX_SEGMENTS */
94 typedef struct qla_tx_buf qla_tx_buf_t;
106 qla_tx_buf_t tx_buf[NUM_TX_DESCRIPTORS];
109 struct resource *wq_db_addr;
110 uint32_t wq_db_offset;
112 q81_tx_cmd_t *wq_vaddr;
116 bus_addr_t wq_icb_paddr;
118 uint32_t *txr_cons_vaddr;
119 bus_addr_t txr_cons_paddr;
121 volatile uint32_t txr_free; /* # of free entries in tx ring */
122 volatile uint32_t txr_next; /* # next available tx ring entry */
123 volatile uint32_t txr_done;
126 uint64_t tx_tso_frames;
127 uint64_t tx_vlan_frames;
129 typedef struct qla_tx_ring qla_tx_ring_t;
132 * Receive Related Definitions
135 #define MAX_RX_RINGS MAX_TX_RINGS
137 #define NUM_RX_DESCRIPTORS 1024
138 #define NUM_CQ_ENTRIES NUM_RX_DESCRIPTORS
140 #define QLA_LGB_SIZE (12 * 1024)
141 #define QLA_NUM_LGB_ENTRIES 32
143 #define QLA_LBQ_SIZE (QLA_NUM_LGB_ENTRIES * sizeof(q81_bq_addr_e_t))
145 #define QLA_LGBQ_AND_TABLE_SIZE \
146 ((QLA_LBQ_SIZE + PAGE_SIZE + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1))
149 /* Please note that Small Buffer size is determined by max mtu size */
150 #define QLA_NUM_SMB_ENTRIES NUM_RX_DESCRIPTORS
152 #define QLA_SBQ_SIZE (QLA_NUM_SMB_ENTRIES * sizeof(q81_bq_addr_e_t))
154 #define QLA_SMBQ_AND_TABLE_SIZE \
155 ((QLA_SBQ_SIZE + PAGE_SIZE + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1))
163 typedef struct qla_rx_buf qla_rx_buf_t;
180 qla_rx_buf_t rx_buf[NUM_RX_DESCRIPTORS];
181 qla_rx_buf_t *rxb_free;
185 uint32_t cq_db_offset;
188 bus_addr_t cq_icb_paddr;
191 bus_addr_t cqi_paddr;
194 bus_addr_t cq_base_paddr;
195 uint32_t cq_next; /* next cq entry to process */
197 void *lbq_addr_tbl_vaddr;
198 bus_addr_t lbq_addr_tbl_paddr;
201 bus_addr_t lbq_paddr;
202 uint32_t lbq_next; /* next entry in LBQ to process */
203 uint32_t lbq_free;/* # of entries in LBQ to arm */
204 uint32_t lbq_in; /* next entry in LBQ to arm */
209 void *sbq_addr_tbl_vaddr;
210 bus_addr_t sbq_addr_tbl_paddr;
213 bus_addr_t sbq_paddr;
214 uint32_t sbq_next; /* next entry in SBQ to process */
215 uint32_t sbq_free;/* # of entries in SBQ to arm */
216 uint32_t sbq_in; /* next entry in SBQ to arm */
221 typedef struct qla_rx_ring qla_rx_ring_t;
224 #define QLA_WATCHDOG_CALLOUT_TICKS 1
227 * Multicast Definitions
229 typedef struct _qla_mcast {
232 } __packed qla_mcast_t;
237 #define QLA_PAGE_SIZE 4096
240 * Adapter structure contains the hardware independant information of the
250 qla_watchdog_active :1,
251 qla_watchdog_exit :1,
252 qla_watchdog_pause :1,
258 volatile uint32_t hw_init;
260 volatile uint32_t qla_watchdog_exited;
261 volatile uint32_t qla_watchdog_paused;
262 volatile uint32_t qla_initiate_recovery;
267 uint16_t watchdog_ticks;
271 struct cdev *ioctl_dev;
273 /* register mapping */
274 struct resource *pci_reg;
277 struct resource *pci_reg1;
281 qla_ivec_t irq_vec[MAX_RX_RINGS];
284 bus_dma_tag_t parent_tag;
286 /* interface to o.s */
289 struct ifmedia media;
290 uint16_t max_frame_size;
295 /* hardware access lock */
297 volatile uint32_t hw_lock_held;
300 /* transmit related */
301 uint32_t num_tx_rings;
302 qla_tx_ring_t tx_ring[MAX_TX_RINGS];
304 bus_dma_tag_t tx_tag;
306 struct taskqueue *tx_tq;
307 struct callout tx_callout;
310 /* receive related */
311 uint32_t num_rx_rings;
312 qla_rx_ring_t rx_ring[MAX_RX_RINGS];
313 bus_dma_tag_t rx_tag;
316 uint32_t err_m_getcl;
317 uint32_t err_m_getjcl;
318 uint32_t err_tx_dmamap_create;
319 uint32_t err_tx_dmamap_load;
320 uint32_t err_tx_defrag;
322 /* mac address related */
323 uint8_t mac_rcv_mode;
324 uint8_t mac_addr[ETHER_ADDR_LEN];
326 qla_mcast_t mcast[Q8_MAX_NUM_MULTICAST_ADDRS];
330 uint32_t link_status;
331 uint32_t link_down_info;
332 uint32_t link_hw_info;
333 uint32_t link_dcbx_counters;
334 uint32_t link_change_counters;
340 volatile const char *qla_lock;
341 volatile const char *qla_unlock;
343 /* Error Recovery Related */
345 struct task err_task;
346 struct taskqueue *err_tq;
351 /* mailbox completions */
352 uint32_t aen[Q81_NUM_AEN_REGISTERS];
353 uint32_t mbox[Q81_NUM_MBX_REGISTERS];
354 volatile uint32_t mbx_done;
356 /* mpi dump related */
361 typedef struct qla_host qla_host_t;
363 /* note that align has to be a power of 2 */
364 #define QL_ALIGN(size, align) (size + (align - 1)) & ~(align - 1);
365 #define QL_MIN(x, y) ((x < y) ? x : y)
367 #define QL_RUNNING(ifp) \
368 ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) == \
371 /* Return 0, if identical, else 1 */
373 #define QL_MAC_CMP(mac1, mac2) \
374 ((((*(uint32_t *) mac1) == (*(uint32_t *) mac2) && \
375 (*(uint16_t *)(mac1 + 4)) == (*(uint16_t *)(mac2 + 4)))) ? 0 : 1)
377 #endif /* #ifndef _QLS_DEF_H_ */