sys/dev/qlxge/qls_dump.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2013-2014 Qlogic Corporation
   5  * All rights reserved.
   6  *
   7  *  Redistribution and use in source and binary forms, with or without
   8  *  modification, are permitted provided that the following conditions
   9  *  are met:
  10  *
  11  *  1. Redistributions of source code must retain the above copyright
  12  *     notice, this list of conditions and the following disclaimer.
  13  *  2. Redistributions in binary form must reproduce the above copyright
  14  *     notice, this list of conditions and the following disclaimer in the
  15  *     documentation and/or other materials provided with the distribution.
  16  *
  17  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  18  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  21  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  22  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  23  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  24  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  25  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  26  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  27  *  POSSIBILITY OF SUCH DAMAGE.
  28  */
  29
  30 /*
  31  * File: qls_dump.c
  32  */
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36
  37 #include "qls_os.h"
  38 #include "qls_hw.h"
  39 #include "qls_def.h"
  40 #include "qls_glbl.h"
  41 #include "qls_dump.h"
  42
  43 qls_mpi_coredump_t ql_mpi_coredump;
  44
  45 #define Q81_CORE_SEG_NUM              1
  46 #define Q81_TEST_LOGIC_SEG_NUM        2
  47 #define Q81_RMII_SEG_NUM              3
  48 #define Q81_FCMAC1_SEG_NUM            4
  49 #define Q81_FCMAC2_SEG_NUM            5
  50 #define Q81_FC1_MBOX_SEG_NUM          6
  51 #define Q81_IDE_SEG_NUM               7
  52 #define Q81_NIC1_MBOX_SEG_NUM         8
  53 #define Q81_SMBUS_SEG_NUM             9
  54 #define Q81_FC2_MBOX_SEG_NUM          10
  55 #define Q81_NIC2_MBOX_SEG_NUM         11
  56 #define Q81_I2C_SEG_NUM               12
  57 #define Q81_MEMC_SEG_NUM              13
  58 #define Q81_PBUS_SEG_NUM              14
  59 #define Q81_MDE_SEG_NUM               15
  60 #define Q81_NIC1_CONTROL_SEG_NUM      16
  61 #define Q81_NIC2_CONTROL_SEG_NUM      17
  62 #define Q81_NIC1_XGMAC_SEG_NUM        18
  63 #define Q81_NIC2_XGMAC_SEG_NUM        19
  64 #define Q81_WCS_RAM_SEG_NUM           20
  65 #define Q81_MEMC_RAM_SEG_NUM          21
  66 #define Q81_XAUI1_AN_SEG_NUM          22
  67 #define Q81_XAUI1_HSS_PCS_SEG_NUM     23
  68 #define Q81_XFI1_AN_SEG_NUM           24
  69 #define Q81_XFI1_TRAIN_SEG_NUM        25
  70 #define Q81_XFI1_HSS_PCS_SEG_NUM      26
  71 #define Q81_XFI1_HSS_TX_SEG_NUM       27
  72 #define Q81_XFI1_HSS_RX_SEG_NUM       28
  73 #define Q81_XFI1_HSS_PLL_SEG_NUM      29
  74 #define Q81_INTR_STATES_SEG_NUM       31
  75 #define Q81_ETS_SEG_NUM               34
  76 #define Q81_PROBE_DUMP_SEG_NUM        35
  77 #define Q81_ROUTING_INDEX_SEG_NUM     36
  78 #define Q81_MAC_PROTOCOL_SEG_NUM      37
  79 #define Q81_XAUI2_AN_SEG_NUM          38
  80 #define Q81_XAUI2_HSS_PCS_SEG_NUM     39
  81 #define Q81_XFI2_AN_SEG_NUM           40
  82 #define Q81_XFI2_TRAIN_SEG_NUM        41
  83 #define Q81_XFI2_HSS_PCS_SEG_NUM      42
  84 #define Q81_XFI2_HSS_TX_SEG_NUM       43
  85 #define Q81_XFI2_HSS_RX_SEG_NUM       44
  86 #define Q81_XFI2_HSS_PLL_SEG_NUM      45
  87 #define Q81_WQC1_SEG_NUM              46
  88 #define Q81_CQC1_SEG_NUM              47
  89 #define Q81_WQC2_SEG_NUM              48
  90 #define Q81_CQC2_SEG_NUM              49
  91 #define Q81_SEM_REGS_SEG_NUM          50
  92
  93 enum
  94 {
  95         Q81_PAUSE_SRC_LO               = 0x00000100,
  96         Q81_PAUSE_SRC_HI               = 0x00000104,
  97         Q81_GLOBAL_CFG                 = 0x00000108,
  98         Q81_GLOBAL_CFG_RESET           = (1 << 0),    /*Control*/
  99         Q81_GLOBAL_CFG_JUMBO           = (1 << 6),    /*Control*/
 100         Q81_GLOBAL_CFG_TX_STAT_EN      = (1 << 10),   /*Control*/
 101         Q81_GLOBAL_CFG_RX_STAT_EN      = (1 << 11),   /*Control*/
 102         Q81_TX_CFG                     = 0x0000010c,
 103         Q81_TX_CFG_RESET               = (1 << 0),    /*Control*/
 104         Q81_TX_CFG_EN                  = (1 << 1),    /*Control*/
 105         Q81_TX_CFG_PREAM               = (1 << 2),    /*Control*/
 106         Q81_RX_CFG                     = 0x00000110,
 107         Q81_RX_CFG_RESET               = (1 << 0),    /*Control*/
 108         Q81_RX_CFG_EN                  = (1 << 1),    /*Control*/
 109         Q81_RX_CFG_PREAM               = (1 << 2),    /*Control*/
 110         Q81_FLOW_CTL                   = 0x0000011c,
 111         Q81_PAUSE_OPCODE               = 0x00000120,
 112         Q81_PAUSE_TIMER                = 0x00000124,
 113         Q81_PAUSE_FRM_DEST_LO          = 0x00000128,
 114         Q81_PAUSE_FRM_DEST_HI          = 0x0000012c,
 115         Q81_MAC_TX_PARAMS              = 0x00000134,
 116         Q81_MAC_TX_PARAMS_JUMBO        = (1U << 31),   /*Control*/
 117         Q81_MAC_TX_PARAMS_SIZE_SHIFT   = 16,          /*Control*/
 118         Q81_MAC_RX_PARAMS              = 0x00000138,
 119         Q81_MAC_SYS_INT                = 0x00000144,
 120         Q81_MAC_SYS_INT_MASK           = 0x00000148,
 121         Q81_MAC_MGMT_INT               = 0x0000014c,
 122         Q81_MAC_MGMT_IN_MASK           = 0x00000150,
 123         Q81_EXT_ARB_MODE               = 0x000001fc,
 124         Q81_TX_PKTS                    = 0x00000200,
 125         Q81_TX_PKTS_LO                 = 0x00000204,
 126         Q81_TX_BYTES                   = 0x00000208,
 127         Q81_TX_BYTES_LO                = 0x0000020C,
 128         Q81_TX_MCAST_PKTS              = 0x00000210,
 129         Q81_TX_MCAST_PKTS_LO           = 0x00000214,
 130         Q81_TX_BCAST_PKTS              = 0x00000218,
 131         Q81_TX_BCAST_PKTS_LO           = 0x0000021C,
 132         Q81_TX_UCAST_PKTS              = 0x00000220,
 133         Q81_TX_UCAST_PKTS_LO           = 0x00000224,
 134         Q81_TX_CTL_PKTS                = 0x00000228,
 135         Q81_TX_CTL_PKTS_LO             = 0x0000022c,
 136         Q81_TX_PAUSE_PKTS              = 0x00000230,
 137         Q81_TX_PAUSE_PKTS_LO           = 0x00000234,
 138         Q81_TX_64_PKT                  = 0x00000238,
 139         Q81_TX_64_PKT_LO               = 0x0000023c,
 140         Q81_TX_65_TO_127_PKT           = 0x00000240,
 141         Q81_TX_65_TO_127_PKT_LO        = 0x00000244,
 142         Q81_TX_128_TO_255_PKT          = 0x00000248,
 143         Q81_TX_128_TO_255_PKT_LO       = 0x0000024c,
 144         Q81_TX_256_511_PKT             = 0x00000250,
 145         Q81_TX_256_511_PKT_LO          = 0x00000254,
 146         Q81_TX_512_TO_1023_PKT         = 0x00000258,
 147         Q81_TX_512_TO_1023_PKT_LO      = 0x0000025c,
 148         Q81_TX_1024_TO_1518_PKT        = 0x00000260,
 149         Q81_TX_1024_TO_1518_PKT_LO     = 0x00000264,
 150         Q81_TX_1519_TO_MAX_PKT         = 0x00000268,
 151         Q81_TX_1519_TO_MAX_PKT_LO      = 0x0000026c,
 152         Q81_TX_UNDERSIZE_PKT           = 0x00000270,
 153         Q81_TX_UNDERSIZE_PKT_LO        = 0x00000274,
 154         Q81_TX_OVERSIZE_PKT            = 0x00000278,
 155         Q81_TX_OVERSIZE_PKT_LO         = 0x0000027c,
 156         Q81_RX_HALF_FULL_DET           = 0x000002a0,
 157         Q81_TX_HALF_FULL_DET_LO        = 0x000002a4,
 158         Q81_RX_OVERFLOW_DET            = 0x000002a8,
 159         Q81_TX_OVERFLOW_DET_LO         = 0x000002ac,
 160         Q81_RX_HALF_FULL_MASK          = 0x000002b0,
 161         Q81_TX_HALF_FULL_MASK_LO       = 0x000002b4,
 162         Q81_RX_OVERFLOW_MASK           = 0x000002b8,
 163         Q81_TX_OVERFLOW_MASK_LO        = 0x000002bc,
 164         Q81_STAT_CNT_CTL               = 0x000002c0,
 165         Q81_STAT_CNT_CTL_CLEAR_TX      = (1 << 0),   /*Control*/
 166         Q81_STAT_CNT_CTL_CLEAR_RX      = (1 << 1),   /*Control*/
 167         Q81_AUX_RX_HALF_FULL_DET       = 0x000002d0,
 168         Q81_AUX_TX_HALF_FULL_DET       = 0x000002d4,
 169         Q81_AUX_RX_OVERFLOW_DET        = 0x000002d8,
 170         Q81_AUX_TX_OVERFLOW_DET        = 0x000002dc,
 171         Q81_AUX_RX_HALF_FULL_MASK      = 0x000002f0,
 172         Q81_AUX_TX_HALF_FULL_MASK      = 0x000002f4,
 173         Q81_AUX_RX_OVERFLOW_MASK       = 0x000002f8,
 174         Q81_AUX_TX_OVERFLOW_MASK       = 0x000002fc,
 175         Q81_RX_BYTES                   = 0x00000300,
 176         Q81_RX_BYTES_LO                = 0x00000304,
 177         Q81_RX_BYTES_OK                = 0x00000308,
 178         Q81_RX_BYTES_OK_LO             = 0x0000030c,
 179         Q81_RX_PKTS                    = 0x00000310,
 180         Q81_RX_PKTS_LO                 = 0x00000314,
 181         Q81_RX_PKTS_OK                 = 0x00000318,
 182         Q81_RX_PKTS_OK_LO              = 0x0000031c,
 183         Q81_RX_BCAST_PKTS              = 0x00000320,
 184         Q81_RX_BCAST_PKTS_LO           = 0x00000324,
 185         Q81_RX_MCAST_PKTS              = 0x00000328,
 186         Q81_RX_MCAST_PKTS_LO           = 0x0000032c,
 187         Q81_RX_UCAST_PKTS              = 0x00000330,
 188         Q81_RX_UCAST_PKTS_LO           = 0x00000334,
 189         Q81_RX_UNDERSIZE_PKTS          = 0x00000338,
 190         Q81_RX_UNDERSIZE_PKTS_LO       = 0x0000033c,
 191         Q81_RX_OVERSIZE_PKTS           = 0x00000340,
 192         Q81_RX_OVERSIZE_PKTS_LO        = 0x00000344,
 193         Q81_RX_JABBER_PKTS             = 0x00000348,
 194         Q81_RX_JABBER_PKTS_LO          = 0x0000034c,
 195         Q81_RX_UNDERSIZE_FCERR_PKTS    = 0x00000350,
 196         Q81_RX_UNDERSIZE_FCERR_PKTS_LO = 0x00000354,
 197         Q81_RX_DROP_EVENTS             = 0x00000358,
 198         Q81_RX_DROP_EVENTS_LO          = 0x0000035c,
 199         Q81_RX_FCERR_PKTS              = 0x00000360,
 200         Q81_RX_FCERR_PKTS_LO           = 0x00000364,
 201         Q81_RX_ALIGN_ERR               = 0x00000368,
 202         Q81_RX_ALIGN_ERR_LO            = 0x0000036c,
 203         Q81_RX_SYMBOL_ERR              = 0x00000370,
 204         Q81_RX_SYMBOL_ERR_LO           = 0x00000374,
 205         Q81_RX_MAC_ERR                 = 0x00000378,
 206         Q81_RX_MAC_ERR_LO              = 0x0000037c,
 207         Q81_RX_CTL_PKTS                = 0x00000380,
 208         Q81_RX_CTL_PKTS_LO             = 0x00000384,
 209         Q81_RX_PAUSE_PKTS              = 0x00000388,
 210         Q81_RX_PAUSE_PKTS_LO           = 0x0000038c,
 211         Q81_RX_64_PKTS                 = 0x00000390,
 212         Q81_RX_64_PKTS_LO              = 0x00000394,
 213         Q81_RX_65_TO_127_PKTS          = 0x00000398,
 214         Q81_RX_65_TO_127_PKTS_LO       = 0x0000039c,
 215         Q81_RX_128_255_PKTS            = 0x000003a0,
 216         Q81_RX_128_255_PKTS_LO         = 0x000003a4,
 217         Q81_RX_256_511_PKTS            = 0x000003a8,
 218         Q81_RX_256_511_PKTS_LO         = 0x000003ac,
 219         Q81_RX_512_TO_1023_PKTS        = 0x000003b0,
 220         Q81_RX_512_TO_1023_PKTS_LO     = 0x000003b4,
 221         Q81_RX_1024_TO_1518_PKTS       = 0x000003b8,
 222         Q81_RX_1024_TO_1518_PKTS_LO    = 0x000003bc,
 223         Q81_RX_1519_TO_MAX_PKTS        = 0x000003c0,
 224         Q81_RX_1519_TO_MAX_PKTS_LO     = 0x000003c4,
 225         Q81_RX_LEN_ERR_PKTS            = 0x000003c8,
 226         Q81_RX_LEN_ERR_PKTS_LO         = 0x000003cc,
 227         Q81_MDIO_TX_DATA               = 0x00000400,
 228         Q81_MDIO_RX_DATA               = 0x00000410,
 229         Q81_MDIO_CMD                   = 0x00000420,
 230         Q81_MDIO_PHY_ADDR              = 0x00000430,
 231         Q81_MDIO_PORT                  = 0x00000440,
 232         Q81_MDIO_STATUS                = 0x00000450,
 233         Q81_TX_CBFC_PAUSE_FRAMES0      = 0x00000500,
 234         Q81_TX_CBFC_PAUSE_FRAMES0_LO   = 0x00000504,
 235         Q81_TX_CBFC_PAUSE_FRAMES1      = 0x00000508,
 236         Q81_TX_CBFC_PAUSE_FRAMES1_LO   = 0x0000050C,
 237         Q81_TX_CBFC_PAUSE_FRAMES2      = 0x00000510,
 238         Q81_TX_CBFC_PAUSE_FRAMES2_LO   = 0x00000514,
 239         Q81_TX_CBFC_PAUSE_FRAMES3      = 0x00000518,
 240         Q81_TX_CBFC_PAUSE_FRAMES3_LO   = 0x0000051C,
 241         Q81_TX_CBFC_PAUSE_FRAMES4      = 0x00000520,
 242         Q81_TX_CBFC_PAUSE_FRAMES4_LO   = 0x00000524,
 243         Q81_TX_CBFC_PAUSE_FRAMES5      = 0x00000528,
 244         Q81_TX_CBFC_PAUSE_FRAMES5_LO   = 0x0000052C,
 245         Q81_TX_CBFC_PAUSE_FRAMES6      = 0x00000530,
 246         Q81_TX_CBFC_PAUSE_FRAMES6_LO   = 0x00000534,
 247         Q81_TX_CBFC_PAUSE_FRAMES7      = 0x00000538,
 248         Q81_TX_CBFC_PAUSE_FRAMES7_LO   = 0x0000053C,
 249         Q81_TX_FCOE_PKTS               = 0x00000540,
 250         Q81_TX_FCOE_PKTS_LO            = 0x00000544,
 251         Q81_TX_MGMT_PKTS               = 0x00000548,
 252         Q81_TX_MGMT_PKTS_LO            = 0x0000054C,
 253         Q81_RX_CBFC_PAUSE_FRAMES0      = 0x00000568,
 254         Q81_RX_CBFC_PAUSE_FRAMES0_LO   = 0x0000056C,
 255         Q81_RX_CBFC_PAUSE_FRAMES1      = 0x00000570,
 256         Q81_RX_CBFC_PAUSE_FRAMES1_LO   = 0x00000574,
 257         Q81_RX_CBFC_PAUSE_FRAMES2      = 0x00000578,
 258         Q81_RX_CBFC_PAUSE_FRAMES2_LO   = 0x0000057C,
 259         Q81_RX_CBFC_PAUSE_FRAMES3      = 0x00000580,
 260         Q81_RX_CBFC_PAUSE_FRAMES3_LO   = 0x00000584,
 261         Q81_RX_CBFC_PAUSE_FRAMES4      = 0x00000588,
 262         Q81_RX_CBFC_PAUSE_FRAMES4_LO   = 0x0000058C,
 263         Q81_RX_CBFC_PAUSE_FRAMES5      = 0x00000590,
 264         Q81_RX_CBFC_PAUSE_FRAMES5_LO   = 0x00000594,
 265         Q81_RX_CBFC_PAUSE_FRAMES6      = 0x00000598,
 266         Q81_RX_CBFC_PAUSE_FRAMES6_LO   = 0x0000059C,
 267         Q81_RX_CBFC_PAUSE_FRAMES7      = 0x000005A0,
 268         Q81_RX_CBFC_PAUSE_FRAMES7_LO   = 0x000005A4,
 269         Q81_RX_FCOE_PKTS               = 0x000005A8,
 270         Q81_RX_FCOE_PKTS_LO            = 0x000005AC,
 271         Q81_RX_MGMT_PKTS               = 0x000005B0,
 272         Q81_RX_MGMT_PKTS_LO            = 0x000005B4,
 273         Q81_RX_NIC_FIFO_DROP           = 0x000005B8,
 274         Q81_RX_NIC_FIFO_DROP_LO        = 0x000005BC,
 275         Q81_RX_FCOE_FIFO_DROP          = 0x000005C0,
 276         Q81_RX_FCOE_FIFO_DROP_LO       = 0x000005C4,
 277         Q81_RX_MGMT_FIFO_DROP          = 0x000005C8,
 278         Q81_RX_MGMT_FIFO_DROP_LO       = 0x000005CC,
 279         Q81_RX_PKTS_PRIORITY0          = 0x00000600,
 280         Q81_RX_PKTS_PRIORITY0_LO       = 0x00000604,
 281         Q81_RX_PKTS_PRIORITY1          = 0x00000608,
 282         Q81_RX_PKTS_PRIORITY1_LO       = 0x0000060C,
 283         Q81_RX_PKTS_PRIORITY2          = 0x00000610,
 284         Q81_RX_PKTS_PRIORITY2_LO       = 0x00000614,
 285         Q81_RX_PKTS_PRIORITY3          = 0x00000618,
 286         Q81_RX_PKTS_PRIORITY3_LO       = 0x0000061C,
 287         Q81_RX_PKTS_PRIORITY4          = 0x00000620,
 288         Q81_RX_PKTS_PRIORITY4_LO       = 0x00000624,
 289         Q81_RX_PKTS_PRIORITY5          = 0x00000628,
 290         Q81_RX_PKTS_PRIORITY5_LO       = 0x0000062C,
 291         Q81_RX_PKTS_PRIORITY6          = 0x00000630,
 292         Q81_RX_PKTS_PRIORITY6_LO       = 0x00000634,
 293         Q81_RX_PKTS_PRIORITY7          = 0x00000638,
 294         Q81_RX_PKTS_PRIORITY7_LO       = 0x0000063C,
 295         Q81_RX_OCTETS_PRIORITY0        = 0x00000640,
 296         Q81_RX_OCTETS_PRIORITY0_LO     = 0x00000644,
 297         Q81_RX_OCTETS_PRIORITY1        = 0x00000648,
 298         Q81_RX_OCTETS_PRIORITY1_LO     = 0x0000064C,
 299         Q81_RX_OCTETS_PRIORITY2        = 0x00000650,
 300         Q81_RX_OCTETS_PRIORITY2_LO     = 0x00000654,
 301         Q81_RX_OCTETS_PRIORITY3        = 0x00000658,
 302         Q81_RX_OCTETS_PRIORITY3_LO     = 0x0000065C,
 303         Q81_RX_OCTETS_PRIORITY4        = 0x00000660,
 304         Q81_RX_OCTETS_PRIORITY4_LO     = 0x00000664,
 305         Q81_RX_OCTETS_PRIORITY5        = 0x00000668,
 306         Q81_RX_OCTETS_PRIORITY5_LO     = 0x0000066C,
 307         Q81_RX_OCTETS_PRIORITY6        = 0x00000670,
 308         Q81_RX_OCTETS_PRIORITY6_LO     = 0x00000674,
 309         Q81_RX_OCTETS_PRIORITY7        = 0x00000678,
 310         Q81_RX_OCTETS_PRIORITY7_LO     = 0x0000067C,
 311         Q81_TX_PKTS_PRIORITY0          = 0x00000680,
 312         Q81_TX_PKTS_PRIORITY0_LO       = 0x00000684,
 313         Q81_TX_PKTS_PRIORITY1          = 0x00000688,
 314         Q81_TX_PKTS_PRIORITY1_LO       = 0x0000068C,
 315         Q81_TX_PKTS_PRIORITY2          = 0x00000690,
 316         Q81_TX_PKTS_PRIORITY2_LO       = 0x00000694,
 317         Q81_TX_PKTS_PRIORITY3          = 0x00000698,
 318         Q81_TX_PKTS_PRIORITY3_LO       = 0x0000069C,
 319         Q81_TX_PKTS_PRIORITY4          = 0x000006A0,
 320         Q81_TX_PKTS_PRIORITY4_LO       = 0x000006A4,
 321         Q81_TX_PKTS_PRIORITY5          = 0x000006A8,
 322         Q81_TX_PKTS_PRIORITY5_LO       = 0x000006AC,
 323         Q81_TX_PKTS_PRIORITY6          = 0x000006B0,
 324         Q81_TX_PKTS_PRIORITY6_LO       = 0x000006B4,
 325         Q81_TX_PKTS_PRIORITY7          = 0x000006B8,
 326         Q81_TX_PKTS_PRIORITY7_LO       = 0x000006BC,
 327         Q81_TX_OCTETS_PRIORITY0        = 0x000006C0,
 328         Q81_TX_OCTETS_PRIORITY0_LO     = 0x000006C4,
 329         Q81_TX_OCTETS_PRIORITY1        = 0x000006C8,
 330         Q81_TX_OCTETS_PRIORITY1_LO     = 0x000006CC,
 331         Q81_TX_OCTETS_PRIORITY2        = 0x000006D0,
 332         Q81_TX_OCTETS_PRIORITY2_LO     = 0x000006D4,
 333         Q81_TX_OCTETS_PRIORITY3        = 0x000006D8,
 334         Q81_TX_OCTETS_PRIORITY3_LO     = 0x000006DC,
 335         Q81_TX_OCTETS_PRIORITY4        = 0x000006E0,
 336         Q81_TX_OCTETS_PRIORITY4_LO     = 0x000006E4,
 337         Q81_TX_OCTETS_PRIORITY5        = 0x000006E8,
 338         Q81_TX_OCTETS_PRIORITY5_LO     = 0x000006EC,
 339         Q81_TX_OCTETS_PRIORITY6        = 0x000006F0,
 340         Q81_TX_OCTETS_PRIORITY6_LO     = 0x000006F4,
 341         Q81_TX_OCTETS_PRIORITY7        = 0x000006F8,
 342         Q81_TX_OCTETS_PRIORITY7_LO     = 0x000006FC,
 343         Q81_RX_DISCARD_PRIORITY0       = 0x00000700,
 344         Q81_RX_DISCARD_PRIORITY0_LO    = 0x00000704,
 345         Q81_RX_DISCARD_PRIORITY1       = 0x00000708,
 346         Q81_RX_DISCARD_PRIORITY1_LO    = 0x0000070C,
 347         Q81_RX_DISCARD_PRIORITY2       = 0x00000710,
 348         Q81_RX_DISCARD_PRIORITY2_LO    = 0x00000714,
 349         Q81_RX_DISCARD_PRIORITY3       = 0x00000718,
 350         Q81_RX_DISCARD_PRIORITY3_LO    = 0x0000071C,
 351         Q81_RX_DISCARD_PRIORITY4       = 0x00000720,
 352         Q81_RX_DISCARD_PRIORITY4_LO    = 0x00000724,
 353         Q81_RX_DISCARD_PRIORITY5       = 0x00000728,
 354         Q81_RX_DISCARD_PRIORITY5_LO    = 0x0000072C,
 355         Q81_RX_DISCARD_PRIORITY6       = 0x00000730,
 356         Q81_RX_DISCARD_PRIORITY6_LO    = 0x00000734,
 357         Q81_RX_DISCARD_PRIORITY7       = 0x00000738,
 358         Q81_RX_DISCARD_PRIORITY7_LO    = 0x0000073C
 359 };
 360
 361 static void
 362 qls_mpid_seg_hdr(qls_mpid_seg_hdr_t *seg_hdr, uint32_t seg_num,
 363         uint32_t seg_size, unsigned char *desc)
 364 {
 365         memset(seg_hdr, 0, sizeof(qls_mpid_seg_hdr_t));
 366
 367         seg_hdr->cookie = Q81_MPID_COOKIE;
 368         seg_hdr->seg_num = seg_num;
 369         seg_hdr->seg_size = seg_size;
 370
 371         memcpy(seg_hdr->desc, desc, (sizeof(seg_hdr->desc))-1);
 372
 373         return;
 374 }
 375
 376 static int
 377 qls_wait_reg_rdy(qla_host_t *ha , uint32_t reg, uint32_t bit, uint32_t err_bit)
 378 {
 379         uint32_t data;
 380         int count = 10;
 381
 382         while (count) {
 383
 384                 data = READ_REG32(ha, reg);
 385
 386                 if (data & err_bit)
 387                         return (-1);
 388                 else if (data & bit)
 389                         return (0);
 390
 391                 qls_mdelay(__func__, 10);
 392                 count--;
 393         }
 394         return (-1);
 395 }
 396
 397 static int
 398 qls_rd_mpi_reg(qla_host_t *ha, uint32_t reg, uint32_t *data)
 399 {
 400         int ret;
 401
 402         ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY,
 403                         Q81_CTL_PROC_ADDR_ERR);
 404
 405         if (ret)
 406                 goto exit_qls_rd_mpi_reg;
 407
 408         WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg | Q81_CTL_PROC_ADDR_READ);
 409
 410         ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY,
 411                         Q81_CTL_PROC_ADDR_ERR);
 412
 413         if (ret)
 414                 goto exit_qls_rd_mpi_reg;
 415
 416         *data = READ_REG32(ha, Q81_CTL_PROC_DATA);
 417
 418 exit_qls_rd_mpi_reg:
 419         return (ret);
 420 }
 421
 422 static int
 423 qls_wr_mpi_reg(qla_host_t *ha, uint32_t reg, uint32_t data)
 424 {
 425         int ret = 0;
 426
 427         ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY,
 428                         Q81_CTL_PROC_ADDR_ERR);
 429         if (ret)
 430                 goto exit_qls_wr_mpi_reg;
 431
 432         WRITE_REG32(ha, Q81_CTL_PROC_DATA, data);
 433
 434         WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg);
 435
 436         ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY,
 437                         Q81_CTL_PROC_ADDR_ERR);
 438 exit_qls_wr_mpi_reg:
 439         return (ret);
 440 }
 441
 442
 443 #define Q81_TEST_LOGIC_FUNC_PORT_CONFIG 0x1002
 444 #define Q81_INVALID_NUM         0xFFFFFFFF
 445
 446 #define Q81_NIC1_FUNC_ENABLE    0x00000001
 447 #define Q81_NIC1_FUNC_MASK      0x0000000e
 448 #define Q81_NIC1_FUNC_SHIFT     1
 449 #define Q81_NIC2_FUNC_ENABLE    0x00000010
 450 #define Q81_NIC2_FUNC_MASK      0x000000e0
 451 #define Q81_NIC2_FUNC_SHIFT     5
 452 #define Q81_FUNCTION_SHIFT      6
 453
 454 static uint32_t
 455 qls_get_other_fnum(qla_host_t *ha)
 456 {
 457         int             ret;
 458         uint32_t        o_func;
 459         uint32_t        test_logic;
 460         uint32_t        nic1_fnum = Q81_INVALID_NUM;
 461         uint32_t        nic2_fnum = Q81_INVALID_NUM;
 462
 463         ret = qls_rd_mpi_reg(ha, Q81_TEST_LOGIC_FUNC_PORT_CONFIG, &test_logic);
 464         if (ret)
 465                 return(Q81_INVALID_NUM);
 466
 467         if (test_logic & Q81_NIC1_FUNC_ENABLE)
 468                 nic1_fnum = (test_logic & Q81_NIC1_FUNC_MASK) >>
 469                                         Q81_NIC1_FUNC_SHIFT;
 470
 471         if (test_logic & Q81_NIC2_FUNC_ENABLE)
 472                 nic2_fnum = (test_logic & Q81_NIC2_FUNC_MASK) >>
 473                                         Q81_NIC2_FUNC_SHIFT;
 474
 475         if (ha->pci_func == 0)
 476                 o_func = nic2_fnum;
 477         else
 478                 o_func = nic1_fnum;
 479
 480         return(o_func);
 481 }
 482
 483 static uint32_t
 484 qls_rd_ofunc_reg(qla_host_t *ha, uint32_t reg)
 485 {
 486         uint32_t        ofunc;
 487         uint32_t        data;
 488         int             ret = 0;
 489
 490         ofunc = qls_get_other_fnum(ha);
 491
 492         if (ofunc == Q81_INVALID_NUM)
 493                 return(Q81_INVALID_NUM);
 494
 495         reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (ofunc << Q81_FUNCTION_SHIFT) | reg;
 496
 497         ret = qls_rd_mpi_reg(ha, reg, &data);
 498
 499         if (ret != 0)
 500                 return(Q81_INVALID_NUM);
 501
 502         return(data);
 503 }
 504
 505 static void
 506 qls_wr_ofunc_reg(qla_host_t *ha, uint32_t reg, uint32_t value)
 507 {
 508         uint32_t ofunc;
 509         int ret = 0;
 510
 511         ofunc = qls_get_other_fnum(ha);
 512
 513         if (ofunc == Q81_INVALID_NUM)
 514                 return;
 515
 516         reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (ofunc << Q81_FUNCTION_SHIFT) | reg;
 517
 518         ret = qls_wr_mpi_reg(ha, reg, value);
 519
 520         return;
 521 }
 522
 523 static int
 524 qls_wait_ofunc_reg_rdy(qla_host_t *ha , uint32_t reg, uint32_t bit,
 525         uint32_t err_bit)
 526 {
 527         uint32_t data;
 528         int count = 10;
 529
 530         while (count) {
 531
 532                 data = qls_rd_ofunc_reg(ha, reg);
 533
 534                 if (data & err_bit)
 535                         return (-1);
 536                 else if (data & bit)
 537                         return (0);
 538
 539                 qls_mdelay(__func__, 10);
 540                 count--;
 541         }
 542         return (-1);
 543 }
 544
 545 #define Q81_XG_SERDES_ADDR_RDY  BIT_31
 546 #define Q81_XG_SERDES_ADDR_READ BIT_30
 547
 548 static int
 549 qls_rd_ofunc_serdes_reg(qla_host_t *ha, uint32_t reg, uint32_t *data)
 550 {
 551         int ret;
 552
 553         /* wait for reg to come ready */
 554         ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XG_SERDES_ADDR >> 2),
 555                         Q81_XG_SERDES_ADDR_RDY, 0);
 556         if (ret)
 557                 goto exit_qls_rd_ofunc_serdes_reg;
 558
 559         /* set up for reg read */
 560         qls_wr_ofunc_reg(ha, (Q81_CTL_XG_SERDES_ADDR >> 2),
 561                 (reg | Q81_XG_SERDES_ADDR_READ));
 562
 563         /* wait for reg to come ready */
 564         ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XG_SERDES_ADDR >> 2),
 565                         Q81_XG_SERDES_ADDR_RDY, 0);
 566         if (ret)
 567                 goto exit_qls_rd_ofunc_serdes_reg;
 568
 569         /* get the data */
 570         *data = qls_rd_ofunc_reg(ha, (Q81_CTL_XG_SERDES_DATA >> 2));
 571
 572 exit_qls_rd_ofunc_serdes_reg:
 573         return ret;
 574 }
 575
 576 #define Q81_XGMAC_ADDR_RDY      BIT_31
 577 #define Q81_XGMAC_ADDR_R        BIT_30
 578 #define Q81_XGMAC_ADDR_XME      BIT_29
 579
 580 static int
 581 qls_rd_ofunc_xgmac_reg(qla_host_t *ha, uint32_t reg, uint32_t *data)
 582 {
 583         int ret = 0;
 584
 585         ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XGMAC_ADDR >> 2),
 586                         Q81_XGMAC_ADDR_RDY, Q81_XGMAC_ADDR_XME);
 587
 588         if (ret)
 589                 goto exit_qls_rd_ofunc_xgmac_reg;
 590
 591         qls_wr_ofunc_reg(ha, (Q81_XGMAC_ADDR_RDY >> 2),
 592                 (reg | Q81_XGMAC_ADDR_R));
 593
 594         ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XGMAC_ADDR >> 2),
 595                         Q81_XGMAC_ADDR_RDY, Q81_XGMAC_ADDR_XME);
 596         if (ret)
 597                 goto exit_qls_rd_ofunc_xgmac_reg;
 598
 599         *data = qls_rd_ofunc_reg(ha, Q81_CTL_XGMAC_DATA);
 600
 601 exit_qls_rd_ofunc_xgmac_reg:
 602         return ret;
 603 }
 604
 605 static int
 606 qls_rd_serdes_reg(qla_host_t *ha, uint32_t reg, uint32_t *data)
 607 {
 608         int ret;
 609
 610         ret = qls_wait_reg_rdy(ha, Q81_CTL_XG_SERDES_ADDR,
 611                         Q81_XG_SERDES_ADDR_RDY, 0);
 612
 613         if (ret)
 614                 goto exit_qls_rd_serdes_reg;
 615
 616         WRITE_REG32(ha, Q81_CTL_XG_SERDES_ADDR, \
 617                 (reg | Q81_XG_SERDES_ADDR_READ));
 618
 619         ret = qls_wait_reg_rdy(ha, Q81_CTL_XG_SERDES_ADDR,
 620                         Q81_XG_SERDES_ADDR_RDY, 0);
 621
 622         if (ret)
 623                 goto exit_qls_rd_serdes_reg;
 624
 625         *data = READ_REG32(ha, Q81_CTL_XG_SERDES_DATA);
 626
 627 exit_qls_rd_serdes_reg:
 628
 629         return ret;
 630 }
 631
 632 static void
 633 qls_get_both_serdes(qla_host_t *ha, uint32_t addr, uint32_t *dptr,
 634         uint32_t *ind_ptr, uint32_t dvalid, uint32_t ind_valid)
 635 {
 636         int ret = -1;
 637
 638         if (dvalid)
 639                 ret = qls_rd_serdes_reg(ha, addr, dptr);
 640
 641         if (ret)
 642                 *dptr = Q81_BAD_DATA;
 643
 644         ret = -1;
 645
 646         if(ind_valid)
 647                 ret = qls_rd_ofunc_serdes_reg(ha, addr, ind_ptr);
 648
 649         if (ret)
 650                 *ind_ptr = Q81_BAD_DATA;
 651 }
 652
 653 #define Q81_XFI1_POWERED_UP 0x00000005
 654 #define Q81_XFI2_POWERED_UP 0x0000000A
 655 #define Q81_XAUI_POWERED_UP 0x00000001
 656
 657 static int
 658 qls_rd_serdes_regs(qla_host_t *ha, qls_mpi_coredump_t *mpi_dump)
 659 {
 660         int ret;
 661         uint32_t xfi_d_valid, xfi_ind_valid, xaui_d_valid, xaui_ind_valid;
 662         uint32_t temp, xaui_reg, i;
 663         uint32_t *dptr, *indptr;
 664
 665         xfi_d_valid = xfi_ind_valid = xaui_d_valid = xaui_ind_valid = 0;
 666
 667         xaui_reg = 0x800;
 668
 669         ret = qls_rd_ofunc_serdes_reg(ha, xaui_reg, &temp);
 670         if (ret)
 671                 temp = 0;
 672
 673         if ((temp & Q81_XAUI_POWERED_UP) == Q81_XAUI_POWERED_UP)
 674                 xaui_ind_valid = 1;
 675
 676         ret = qls_rd_serdes_reg(ha, xaui_reg, &temp);
 677         if (ret)
 678                 temp = 0;
 679
 680         if ((temp & Q81_XAUI_POWERED_UP) == Q81_XAUI_POWERED_UP)
 681                 xaui_d_valid = 1;
 682
 683         ret = qls_rd_serdes_reg(ha, 0x1E06, &temp);
 684         if (ret)
 685                 temp = 0;
 686
 687         if ((temp & Q81_XFI1_POWERED_UP) == Q81_XFI1_POWERED_UP) {
 688
 689                 if (ha->pci_func & 1)
 690                         xfi_ind_valid = 1; /* NIC 2, so the indirect
 691                                                  (NIC1) xfi is up*/
 692                 else
 693                         xfi_d_valid = 1;
 694         }
 695
 696         if((temp & Q81_XFI2_POWERED_UP) == Q81_XFI2_POWERED_UP) {
 697
 698                 if(ha->pci_func & 1)
 699                         xfi_d_valid = 1; /* NIC 2, so the indirect (NIC1)
 700                                                 xfi is up */
 701                 else
 702                         xfi_ind_valid = 1;
 703         }
 704
 705         if (ha->pci_func & 1) {
 706                 dptr = (uint32_t *)(&mpi_dump->serdes2_xaui_an);
 707                 indptr = (uint32_t *)(&mpi_dump->serdes1_xaui_an);
 708         } else {
 709                 dptr = (uint32_t *)(&mpi_dump->serdes1_xaui_an);
 710                 indptr = (uint32_t *)(&mpi_dump->serdes2_xaui_an);
 711         }
 712
 713         for (i = 0; i <= 0x000000034; i += 4, dptr ++, indptr ++) {
 714                 qls_get_both_serdes(ha, i, dptr, indptr,
 715                         xaui_d_valid, xaui_ind_valid);
 716         }
 717
 718         if (ha->pci_func & 1) {
 719                 dptr = (uint32_t *)(&mpi_dump->serdes2_xaui_hss_pcs);
 720                 indptr = (uint32_t *)(&mpi_dump->serdes1_xaui_hss_pcs);
 721         } else {
 722                 dptr = (uint32_t *)(&mpi_dump->serdes1_xaui_hss_pcs);
 723                 indptr = (uint32_t *)(&mpi_dump->serdes2_xaui_hss_pcs);
 724         }
 725
 726         for (i = 0x800; i <= 0x880; i += 4, dptr ++, indptr ++) {
 727                 qls_get_both_serdes(ha, i, dptr, indptr,
 728                         xaui_d_valid, xaui_ind_valid);
 729         }
 730
 731         if (ha->pci_func & 1) {
 732                 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_an);
 733                 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_an);
 734         } else {
 735                 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_an);
 736                 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_an);
 737         }
 738
 739         for (i = 0x1000; i <= 0x1034; i += 4, dptr ++, indptr ++) {
 740                 qls_get_both_serdes(ha, i, dptr, indptr,
 741                         xfi_d_valid, xfi_ind_valid);
 742         }
 743
 744         if (ha->pci_func & 1) {
 745                 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_train);
 746                 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_train);
 747         } else {
 748                 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_train);
 749                 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_train);
 750         }
 751
 752         for (i = 0x1050; i <= 0x107c; i += 4, dptr ++, indptr ++) {
 753                 qls_get_both_serdes(ha, i, dptr, indptr,
 754                         xfi_d_valid, xfi_ind_valid);
 755         }
 756
 757         if (ha->pci_func & 1) {
 758                 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pcs);
 759                 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pcs);
 760         } else {
 761                 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pcs);
 762                 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pcs);
 763         }
 764
 765         for (i = 0x1800; i <= 0x1838; i += 4, dptr++, indptr ++) {
 766                 qls_get_both_serdes(ha, i, dptr, indptr,
 767                         xfi_d_valid, xfi_ind_valid);
 768         }
 769
 770         if (ha->pci_func & 1) {
 771                 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_tx);
 772                 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_tx);
 773         } else {
 774                 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_tx);
 775                 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_tx);
 776         }
 777
 778         for (i = 0x1c00; i <= 0x1c1f; i++, dptr ++, indptr ++) {
 779                 qls_get_both_serdes(ha, i, dptr, indptr,
 780                         xfi_d_valid, xfi_ind_valid);
 781         }
 782
 783         if (ha->pci_func & 1) {
 784                 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_rx);
 785                 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_rx);
 786         } else {
 787                 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_rx);
 788                 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_rx);
 789         }
 790
 791         for (i = 0x1c40; i <= 0x1c5f; i++, dptr ++, indptr ++) {
 792                 qls_get_both_serdes(ha, i, dptr, indptr,
 793                         xfi_d_valid, xfi_ind_valid);
 794         }
 795
 796         if (ha->pci_func & 1) {
 797                 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pll);
 798                 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pll);
 799         } else {
 800                 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pll);
 801                 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pll);
 802         }
 803
 804         for (i = 0x1e00; i <= 0x1e1f; i++, dptr ++, indptr ++) {
 805                 qls_get_both_serdes(ha, i, dptr, indptr,
 806                         xfi_d_valid, xfi_ind_valid);
 807         }
 808
 809         return(0);
 810 }
 811
 812 static int
 813 qls_unpause_mpi_risc(qla_host_t *ha)
 814 {
 815         uint32_t data;
 816
 817         data = READ_REG32(ha, Q81_CTL_HOST_CMD_STATUS);
 818
 819         if (!(data & Q81_CTL_HCS_RISC_PAUSED))
 820                 return -1;
 821
 822         WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, \
 823                 Q81_CTL_HCS_CMD_CLR_RISC_PAUSE);
 824
 825         return 0;
 826 }
 827
 828 static int
 829 qls_pause_mpi_risc(qla_host_t *ha)
 830 {
 831         uint32_t data;
 832         int count = 10;
 833
 834         WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, \
 835                 Q81_CTL_HCS_CMD_SET_RISC_PAUSE);
 836
 837         do {
 838                 data = READ_REG32(ha, Q81_CTL_HOST_CMD_STATUS);
 839
 840                 if (data & Q81_CTL_HCS_RISC_PAUSED)
 841                         break;
 842
 843                 qls_mdelay(__func__, 10);
 844
 845                 count--;
 846
 847         } while (count);
 848
 849         return ((count == 0) ? -1 : 0);
 850 }
 851
 852 static void
 853 qls_get_intr_states(qla_host_t *ha, uint32_t *buf)
 854 {
 855         int i;
 856
 857         for (i = 0; i < MAX_RX_RINGS; i++, buf++) {
 858
 859                 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (0x037f0300 + i));
 860
 861                 *buf = READ_REG32(ha, Q81_CTL_INTR_ENABLE);
 862         }
 863 }
 864
 865 static int
 866 qls_rd_xgmac_reg(qla_host_t *ha, uint32_t reg, uint32_t*data)
 867 {
 868         int ret = 0;
 869
 870         ret = qls_wait_reg_rdy(ha, Q81_CTL_XGMAC_ADDR, Q81_XGMAC_ADDR_RDY,
 871                         Q81_XGMAC_ADDR_XME);
 872         if (ret)
 873                 goto exit_qls_rd_xgmac_reg;
 874
 875         WRITE_REG32(ha, Q81_CTL_XGMAC_ADDR, (reg | Q81_XGMAC_ADDR_R));
 876
 877         ret = qls_wait_reg_rdy(ha, Q81_CTL_XGMAC_ADDR, Q81_XGMAC_ADDR_RDY,
 878                         Q81_XGMAC_ADDR_XME);
 879         if (ret)
 880                 goto exit_qls_rd_xgmac_reg;
 881
 882         *data = READ_REG32(ha, Q81_CTL_XGMAC_DATA);
 883
 884 exit_qls_rd_xgmac_reg:
 885         return ret;
 886 }
 887
 888 static int
 889 qls_rd_xgmac_regs(qla_host_t *ha, uint32_t *buf, uint32_t o_func)
 890 {
 891         int ret = 0;
 892         int i;
 893
 894         for (i = 0; i < Q81_XGMAC_REGISTER_END; i += 4, buf ++) {
 895
 896                 switch (i) {
 897                 case  Q81_PAUSE_SRC_LO               :
 898                 case  Q81_PAUSE_SRC_HI               :
 899                 case  Q81_GLOBAL_CFG                 :
 900                 case  Q81_TX_CFG                     :
 901                 case  Q81_RX_CFG                     :
 902                 case  Q81_FLOW_CTL                   :
 903                 case  Q81_PAUSE_OPCODE               :
 904                 case  Q81_PAUSE_TIMER                :
 905                 case  Q81_PAUSE_FRM_DEST_LO          :
 906                 case  Q81_PAUSE_FRM_DEST_HI          :
 907                 case  Q81_MAC_TX_PARAMS              :
 908                 case  Q81_MAC_RX_PARAMS              :
 909                 case  Q81_MAC_SYS_INT                :
 910                 case  Q81_MAC_SYS_INT_MASK           :
 911                 case  Q81_MAC_MGMT_INT               :
 912                 case  Q81_MAC_MGMT_IN_MASK           :
 913                 case  Q81_EXT_ARB_MODE               :
 914                 case  Q81_TX_PKTS                    :
 915                 case  Q81_TX_PKTS_LO                 :
 916                 case  Q81_TX_BYTES                   :
 917                 case  Q81_TX_BYTES_LO                :
 918                 case  Q81_TX_MCAST_PKTS              :
 919                 case  Q81_TX_MCAST_PKTS_LO           :
 920                 case  Q81_TX_BCAST_PKTS              :
 921                 case  Q81_TX_BCAST_PKTS_LO           :
 922                 case  Q81_TX_UCAST_PKTS              :
 923                 case  Q81_TX_UCAST_PKTS_LO           :
 924                 case  Q81_TX_CTL_PKTS                :
 925                 case  Q81_TX_CTL_PKTS_LO             :
 926                 case  Q81_TX_PAUSE_PKTS              :
 927                 case  Q81_TX_PAUSE_PKTS_LO           :
 928                 case  Q81_TX_64_PKT                  :
 929                 case  Q81_TX_64_PKT_LO               :
 930                 case  Q81_TX_65_TO_127_PKT           :
 931                 case  Q81_TX_65_TO_127_PKT_LO        :
 932                 case  Q81_TX_128_TO_255_PKT          :
 933                 case  Q81_TX_128_TO_255_PKT_LO       :
 934                 case  Q81_TX_256_511_PKT             :
 935                 case  Q81_TX_256_511_PKT_LO          :
 936                 case  Q81_TX_512_TO_1023_PKT         :
 937                 case  Q81_TX_512_TO_1023_PKT_LO      :
 938                 case  Q81_TX_1024_TO_1518_PKT        :
 939                 case  Q81_TX_1024_TO_1518_PKT_LO     :
 940                 case  Q81_TX_1519_TO_MAX_PKT         :
 941                 case  Q81_TX_1519_TO_MAX_PKT_LO      :
 942                 case  Q81_TX_UNDERSIZE_PKT           :
 943                 case  Q81_TX_UNDERSIZE_PKT_LO        :
 944                 case  Q81_TX_OVERSIZE_PKT            :
 945                 case  Q81_TX_OVERSIZE_PKT_LO         :
 946                 case  Q81_RX_HALF_FULL_DET           :
 947                 case  Q81_TX_HALF_FULL_DET_LO        :
 948                 case  Q81_RX_OVERFLOW_DET            :
 949                 case  Q81_TX_OVERFLOW_DET_LO         :
 950                 case  Q81_RX_HALF_FULL_MASK          :
 951                 case  Q81_TX_HALF_FULL_MASK_LO       :
 952                 case  Q81_RX_OVERFLOW_MASK           :
 953                 case  Q81_TX_OVERFLOW_MASK_LO        :
 954                 case  Q81_STAT_CNT_CTL               :
 955                 case  Q81_AUX_RX_HALF_FULL_DET       :
 956                 case  Q81_AUX_TX_HALF_FULL_DET       :
 957                 case  Q81_AUX_RX_OVERFLOW_DET        :
 958                 case  Q81_AUX_TX_OVERFLOW_DET        :
 959                 case  Q81_AUX_RX_HALF_FULL_MASK      :
 960                 case  Q81_AUX_TX_HALF_FULL_MASK      :
 961                 case  Q81_AUX_RX_OVERFLOW_MASK       :
 962                 case  Q81_AUX_TX_OVERFLOW_MASK       :
 963                 case  Q81_RX_BYTES                   :
 964                 case  Q81_RX_BYTES_LO                :
 965                 case  Q81_RX_BYTES_OK                :
 966                 case  Q81_RX_BYTES_OK_LO             :
 967                 case  Q81_RX_PKTS                    :
 968                 case  Q81_RX_PKTS_LO                 :
 969                 case  Q81_RX_PKTS_OK                 :
 970                 case  Q81_RX_PKTS_OK_LO              :
 971                 case  Q81_RX_BCAST_PKTS              :
 972                 case  Q81_RX_BCAST_PKTS_LO           :
 973                 case  Q81_RX_MCAST_PKTS              :
 974                 case  Q81_RX_MCAST_PKTS_LO           :
 975                 case  Q81_RX_UCAST_PKTS              :
 976                 case  Q81_RX_UCAST_PKTS_LO           :
 977                 case  Q81_RX_UNDERSIZE_PKTS          :
 978                 case  Q81_RX_UNDERSIZE_PKTS_LO       :
 979                 case  Q81_RX_OVERSIZE_PKTS           :
 980                 case  Q81_RX_OVERSIZE_PKTS_LO        :
 981                 case  Q81_RX_JABBER_PKTS             :
 982                 case  Q81_RX_JABBER_PKTS_LO          :
 983                 case  Q81_RX_UNDERSIZE_FCERR_PKTS    :
 984                 case  Q81_RX_UNDERSIZE_FCERR_PKTS_LO :
 985                 case  Q81_RX_DROP_EVENTS             :
 986                 case  Q81_RX_DROP_EVENTS_LO          :
 987                 case  Q81_RX_FCERR_PKTS              :
 988                 case  Q81_RX_FCERR_PKTS_LO           :
 989                 case  Q81_RX_ALIGN_ERR               :
 990                 case  Q81_RX_ALIGN_ERR_LO            :
 991                 case  Q81_RX_SYMBOL_ERR              :
 992                 case  Q81_RX_SYMBOL_ERR_LO           :
 993                 case  Q81_RX_MAC_ERR                 :
 994                 case  Q81_RX_MAC_ERR_LO              :
 995                 case  Q81_RX_CTL_PKTS                :
 996                 case  Q81_RX_CTL_PKTS_LO             :
 997                 case  Q81_RX_PAUSE_PKTS              :
 998                 case  Q81_RX_PAUSE_PKTS_LO           :
 999                 case  Q81_RX_64_PKTS                 :
1000                 case  Q81_RX_64_PKTS_LO              :
1001                 case  Q81_RX_65_TO_127_PKTS          :
1002                 case  Q81_RX_65_TO_127_PKTS_LO       :
1003                 case  Q81_RX_128_255_PKTS            :
1004                 case  Q81_RX_128_255_PKTS_LO         :
1005                 case  Q81_RX_256_511_PKTS            :
1006                 case  Q81_RX_256_511_PKTS_LO         :
1007                 case  Q81_RX_512_TO_1023_PKTS        :
1008                 case  Q81_RX_512_TO_1023_PKTS_LO     :
1009                 case  Q81_RX_1024_TO_1518_PKTS       :
1010                 case  Q81_RX_1024_TO_1518_PKTS_LO    :
1011                 case  Q81_RX_1519_TO_MAX_PKTS        :
1012                 case  Q81_RX_1519_TO_MAX_PKTS_LO     :
1013                 case  Q81_RX_LEN_ERR_PKTS            :
1014                 case  Q81_RX_LEN_ERR_PKTS_LO         :
1015                 case  Q81_MDIO_TX_DATA               :
1016                 case  Q81_MDIO_RX_DATA               :
1017                 case  Q81_MDIO_CMD                   :
1018                 case  Q81_MDIO_PHY_ADDR              :
1019                 case  Q81_MDIO_PORT                  :
1020                 case  Q81_MDIO_STATUS                :
1021                 case  Q81_TX_CBFC_PAUSE_FRAMES0      :
1022                 case  Q81_TX_CBFC_PAUSE_FRAMES0_LO   :
1023                 case  Q81_TX_CBFC_PAUSE_FRAMES1      :
1024                 case  Q81_TX_CBFC_PAUSE_FRAMES1_LO   :
1025                 case  Q81_TX_CBFC_PAUSE_FRAMES2      :
1026                 case  Q81_TX_CBFC_PAUSE_FRAMES2_LO   :
1027                 case  Q81_TX_CBFC_PAUSE_FRAMES3      :
1028                 case  Q81_TX_CBFC_PAUSE_FRAMES3_LO   :
1029                 case  Q81_TX_CBFC_PAUSE_FRAMES4      :
1030                 case  Q81_TX_CBFC_PAUSE_FRAMES4_LO   :
1031                 case  Q81_TX_CBFC_PAUSE_FRAMES5      :
1032                 case  Q81_TX_CBFC_PAUSE_FRAMES5_LO   :
1033                 case  Q81_TX_CBFC_PAUSE_FRAMES6      :
1034                 case  Q81_TX_CBFC_PAUSE_FRAMES6_LO   :
1035                 case  Q81_TX_CBFC_PAUSE_FRAMES7      :
1036                 case  Q81_TX_CBFC_PAUSE_FRAMES7_LO   :
1037                 case  Q81_TX_FCOE_PKTS               :
1038                 case  Q81_TX_FCOE_PKTS_LO            :
1039                 case  Q81_TX_MGMT_PKTS               :
1040                 case  Q81_TX_MGMT_PKTS_LO            :
1041                 case  Q81_RX_CBFC_PAUSE_FRAMES0      :
1042                 case  Q81_RX_CBFC_PAUSE_FRAMES0_LO   :
1043                 case  Q81_RX_CBFC_PAUSE_FRAMES1      :
1044                 case  Q81_RX_CBFC_PAUSE_FRAMES1_LO   :
1045                 case  Q81_RX_CBFC_PAUSE_FRAMES2      :
1046                 case  Q81_RX_CBFC_PAUSE_FRAMES2_LO   :
1047                 case  Q81_RX_CBFC_PAUSE_FRAMES3      :
1048                 case  Q81_RX_CBFC_PAUSE_FRAMES3_LO   :
1049                 case  Q81_RX_CBFC_PAUSE_FRAMES4      :
1050                 case  Q81_RX_CBFC_PAUSE_FRAMES4_LO   :
1051                 case  Q81_RX_CBFC_PAUSE_FRAMES5      :
1052                 case  Q81_RX_CBFC_PAUSE_FRAMES5_LO   :
1053                 case  Q81_RX_CBFC_PAUSE_FRAMES6      :
1054                 case  Q81_RX_CBFC_PAUSE_FRAMES6_LO   :
1055                 case  Q81_RX_CBFC_PAUSE_FRAMES7      :
1056                 case  Q81_RX_CBFC_PAUSE_FRAMES7_LO   :
1057                 case  Q81_RX_FCOE_PKTS               :
1058                 case  Q81_RX_FCOE_PKTS_LO            :
1059                 case  Q81_RX_MGMT_PKTS               :
1060                 case  Q81_RX_MGMT_PKTS_LO            :
1061                 case  Q81_RX_NIC_FIFO_DROP           :
1062                 case  Q81_RX_NIC_FIFO_DROP_LO        :
1063                 case  Q81_RX_FCOE_FIFO_DROP          :
1064                 case  Q81_RX_FCOE_FIFO_DROP_LO       :
1065                 case  Q81_RX_MGMT_FIFO_DROP          :
1066                 case  Q81_RX_MGMT_FIFO_DROP_LO       :
1067                 case  Q81_RX_PKTS_PRIORITY0          :
1068                 case  Q81_RX_PKTS_PRIORITY0_LO       :
1069                 case  Q81_RX_PKTS_PRIORITY1          :
1070                 case  Q81_RX_PKTS_PRIORITY1_LO       :
1071                 case  Q81_RX_PKTS_PRIORITY2          :
1072                 case  Q81_RX_PKTS_PRIORITY2_LO       :
1073                 case  Q81_RX_PKTS_PRIORITY3          :
1074                 case  Q81_RX_PKTS_PRIORITY3_LO       :
1075                 case  Q81_RX_PKTS_PRIORITY4          :
1076                 case  Q81_RX_PKTS_PRIORITY4_LO       :
1077                 case  Q81_RX_PKTS_PRIORITY5          :
1078                 case  Q81_RX_PKTS_PRIORITY5_LO       :
1079                 case  Q81_RX_PKTS_PRIORITY6          :
1080                 case  Q81_RX_PKTS_PRIORITY6_LO       :
1081                 case  Q81_RX_PKTS_PRIORITY7          :
1082                 case  Q81_RX_PKTS_PRIORITY7_LO       :
1083                 case  Q81_RX_OCTETS_PRIORITY0        :
1084                 case  Q81_RX_OCTETS_PRIORITY0_LO     :
1085                 case  Q81_RX_OCTETS_PRIORITY1        :
1086                 case  Q81_RX_OCTETS_PRIORITY1_LO     :
1087                 case  Q81_RX_OCTETS_PRIORITY2        :
1088                 case  Q81_RX_OCTETS_PRIORITY2_LO     :
1089                 case  Q81_RX_OCTETS_PRIORITY3        :
1090                 case  Q81_RX_OCTETS_PRIORITY3_LO     :
1091                 case  Q81_RX_OCTETS_PRIORITY4        :
1092                 case  Q81_RX_OCTETS_PRIORITY4_LO     :
1093                 case  Q81_RX_OCTETS_PRIORITY5        :
1094                 case  Q81_RX_OCTETS_PRIORITY5_LO     :
1095                 case  Q81_RX_OCTETS_PRIORITY6        :
1096                 case  Q81_RX_OCTETS_PRIORITY6_LO     :
1097                 case  Q81_RX_OCTETS_PRIORITY7        :
1098                 case  Q81_RX_OCTETS_PRIORITY7_LO     :
1099                 case  Q81_TX_PKTS_PRIORITY0          :
1100                 case  Q81_TX_PKTS_PRIORITY0_LO       :
1101                 case  Q81_TX_PKTS_PRIORITY1          :
1102                 case  Q81_TX_PKTS_PRIORITY1_LO       :
1103                 case  Q81_TX_PKTS_PRIORITY2          :
1104                 case  Q81_TX_PKTS_PRIORITY2_LO       :
1105                 case  Q81_TX_PKTS_PRIORITY3          :
1106                 case  Q81_TX_PKTS_PRIORITY3_LO       :
1107                 case  Q81_TX_PKTS_PRIORITY4          :
1108                 case  Q81_TX_PKTS_PRIORITY4_LO       :
1109                 case  Q81_TX_PKTS_PRIORITY5          :
1110                 case  Q81_TX_PKTS_PRIORITY5_LO       :
1111                 case  Q81_TX_PKTS_PRIORITY6          :
1112                 case  Q81_TX_PKTS_PRIORITY6_LO       :
1113                 case  Q81_TX_PKTS_PRIORITY7          :
1114                 case  Q81_TX_PKTS_PRIORITY7_LO       :
1115                 case  Q81_TX_OCTETS_PRIORITY0        :
1116                 case  Q81_TX_OCTETS_PRIORITY0_LO     :
1117                 case  Q81_TX_OCTETS_PRIORITY1        :
1118                 case  Q81_TX_OCTETS_PRIORITY1_LO     :
1119                 case  Q81_TX_OCTETS_PRIORITY2        :
1120                 case  Q81_TX_OCTETS_PRIORITY2_LO     :
1121                 case  Q81_TX_OCTETS_PRIORITY3        :
1122                 case  Q81_TX_OCTETS_PRIORITY3_LO     :
1123                 case  Q81_TX_OCTETS_PRIORITY4        :
1124                 case  Q81_TX_OCTETS_PRIORITY4_LO     :
1125                 case  Q81_TX_OCTETS_PRIORITY5        :
1126                 case  Q81_TX_OCTETS_PRIORITY5_LO     :
1127                 case  Q81_TX_OCTETS_PRIORITY6        :
1128                 case  Q81_TX_OCTETS_PRIORITY6_LO     :
1129                 case  Q81_TX_OCTETS_PRIORITY7        :
1130                 case  Q81_TX_OCTETS_PRIORITY7_LO     :
1131                 case  Q81_RX_DISCARD_PRIORITY0       :
1132                 case  Q81_RX_DISCARD_PRIORITY0_LO    :
1133                 case  Q81_RX_DISCARD_PRIORITY1       :
1134                 case  Q81_RX_DISCARD_PRIORITY1_LO    :
1135                 case  Q81_RX_DISCARD_PRIORITY2       :
1136                 case  Q81_RX_DISCARD_PRIORITY2_LO    :
1137                 case  Q81_RX_DISCARD_PRIORITY3       :
1138                 case  Q81_RX_DISCARD_PRIORITY3_LO    :
1139                 case  Q81_RX_DISCARD_PRIORITY4       :
1140                 case  Q81_RX_DISCARD_PRIORITY4_LO    :
1141                 case  Q81_RX_DISCARD_PRIORITY5       :
1142                 case  Q81_RX_DISCARD_PRIORITY5_LO    :
1143                 case  Q81_RX_DISCARD_PRIORITY6       :
1144                 case  Q81_RX_DISCARD_PRIORITY6_LO    :
1145                 case  Q81_RX_DISCARD_PRIORITY7       :
1146                 case  Q81_RX_DISCARD_PRIORITY7_LO    :
1147
1148                         if (o_func)
1149                                 ret = qls_rd_ofunc_xgmac_reg(ha,
1150                                                 i, buf);
1151                         else
1152                                 ret = qls_rd_xgmac_reg(ha, i, buf);
1153
1154                         if (ret)
1155                                 *buf = Q81_BAD_DATA;
1156
1157                         break;
1158
1159                 default:
1160                         break;
1161
1162                 }
1163         }
1164         return 0;
1165 }
1166
1167 static int
1168 qls_get_mpi_regs(qla_host_t *ha, uint32_t *buf, uint32_t offset, uint32_t count)
1169 {
1170         int i, ret = 0;
1171
1172         for (i = 0; i < count; i++, buf++) {
1173
1174                 ret = qls_rd_mpi_reg(ha, (offset + i), buf);
1175
1176                 if (ret)
1177                         return ret;
1178         }
1179
1180         return (ret);
1181 }
1182
1183 static int
1184 qls_get_mpi_shadow_regs(qla_host_t *ha, uint32_t *buf)
1185 {
1186         uint32_t        i;
1187         int             ret;
1188
1189 #define Q81_RISC_124 0x0000007c
1190 #define Q81_RISC_127 0x0000007f
1191 #define Q81_SHADOW_OFFSET 0xb0000000
1192
1193         for (i = 0; i < Q81_MPI_CORE_SH_REGS_CNT; i++, buf++) {
1194
1195                 ret = qls_wr_mpi_reg(ha,
1196                                 (Q81_CTL_PROC_ADDR_RISC_INT_REG | Q81_RISC_124),
1197                                 (Q81_SHADOW_OFFSET | i << 20));
1198                 if (ret)
1199                         goto exit_qls_get_mpi_shadow_regs;
1200
1201                 ret = qls_mpi_risc_rd_reg(ha,
1202                                 (Q81_CTL_PROC_ADDR_RISC_INT_REG | Q81_RISC_127),
1203                                  buf);
1204                 if (ret)
1205                         goto exit_qls_get_mpi_shadow_regs;
1206         }
1207
1208 exit_qls_get_mpi_shadow_regs:
1209         return ret;
1210 }
1211
1212 #define SYS_CLOCK (0x00)
1213 #define PCI_CLOCK (0x80)
1214 #define FC_CLOCK  (0x140)
1215 #define XGM_CLOCK (0x180)
1216
1217 #define Q81_ADDRESS_REGISTER_ENABLE 0x00010000
1218 #define Q81_UP                      0x00008000
1219 #define Q81_MAX_MUX                 0x40
1220 #define Q81_MAX_MODULES             0x1F
1221
1222 static uint32_t *
1223 qls_get_probe(qla_host_t *ha, uint32_t clock, uint8_t *valid, uint32_t *buf)
1224 {
1225         uint32_t module, mux_sel, probe, lo_val, hi_val;
1226
1227         for (module = 0; module < Q81_MAX_MODULES; module ++) {
1228
1229                 if (valid[module]) {
1230
1231                         for (mux_sel = 0; mux_sel < Q81_MAX_MUX; mux_sel++) {
1232
1233                                 probe = clock | Q81_ADDRESS_REGISTER_ENABLE |
1234                                                 mux_sel | (module << 9);
1235                                 WRITE_REG32(ha, Q81_CTL_XG_PROBE_MUX_ADDR,\
1236                                         probe);
1237
1238                                 lo_val = READ_REG32(ha,\
1239                                                 Q81_CTL_XG_PROBE_MUX_DATA);
1240
1241                                 if (mux_sel == 0) {
1242                                         *buf = probe;
1243                                         buf ++;
1244                                 }
1245
1246                                 probe |= Q81_UP;
1247
1248                                 WRITE_REG32(ha, Q81_CTL_XG_PROBE_MUX_ADDR,\
1249                                         probe);
1250                                 hi_val = READ_REG32(ha,\
1251                                                 Q81_CTL_XG_PROBE_MUX_DATA);
1252
1253                                 *buf = lo_val;
1254                                 buf++;
1255                                 *buf = hi_val;
1256                                 buf++;
1257                         }
1258                 }
1259         }
1260
1261         return(buf);
1262 }
1263
1264 static int
1265 qls_get_probe_dump(qla_host_t *ha, uint32_t *buf)
1266 {
1267
1268         uint8_t sys_clock_valid_modules[0x20] = {
1269                 1,   // 0x00
1270                 1,   // 0x01
1271                 1,   // 0x02
1272                 0,   // 0x03
1273                 1,   // 0x04
1274                 1,   // 0x05
1275                 1,   // 0x06
1276                 1,   // 0x07
1277                 1,   // 0x08
1278                 1,   // 0x09
1279                 1,   // 0x0A
1280                 1,   // 0x0B
1281                 1,   // 0x0C
1282                 1,   // 0x0D
1283                 1,   // 0x0E
1284                 0,   // 0x0F
1285                 1,   // 0x10
1286                 1,   // 0x11
1287                 1,   // 0x12
1288                 1,   // 0x13
1289                 0,   // 0x14
1290                 0,   // 0x15
1291                 0,   // 0x16
1292                 0,   // 0x17
1293                 0,   // 0x18
1294                 0,   // 0x19
1295                 0,   // 0x1A
1296                 0,   // 0x1B
1297                 0,   // 0x1C
1298                 0,   // 0x1D
1299                 0,   // 0x1E
1300                 0    // 0x1F
1301         };
1302
1303
1304         uint8_t pci_clock_valid_modules[0x20] = {
1305                 1,   // 0x00
1306                 0,   // 0x01
1307                 0,   // 0x02
1308                 0,   // 0x03
1309                 0,   // 0x04
1310                 0,   // 0x05
1311                 1,   // 0x06
1312                 1,   // 0x07
1313                 0,   // 0x08
1314                 0,   // 0x09
1315                 0,   // 0x0A
1316                 0,   // 0x0B
1317                 0,   // 0x0C
1318                 0,   // 0x0D
1319                 1,   // 0x0E
1320                 0,   // 0x0F
1321                 0,   // 0x10
1322                 0,   // 0x11
1323                 0,   // 0x12
1324                 0,   // 0x13
1325                 0,   // 0x14
1326                 0,   // 0x15
1327                 0,   // 0x16
1328                 0,   // 0x17
1329                 0,   // 0x18
1330                 0,   // 0x19
1331                 0,   // 0x1A
1332                 0,   // 0x1B
1333                 0,   // 0x1C
1334                 0,   // 0x1D
1335                 0,   // 0x1E
1336                 0    // 0x1F
1337         };
1338
1339
1340         uint8_t xgm_clock_valid_modules[0x20] = {
1341                 1,   // 0x00
1342                 0,   // 0x01
1343                 0,   // 0x02
1344                 1,   // 0x03
1345                 0,   // 0x04
1346                 0,   // 0x05
1347                 0,   // 0x06
1348                 0,   // 0x07
1349                 1,   // 0x08
1350                 1,   // 0x09
1351                 0,   // 0x0A
1352                 0,   // 0x0B
1353                 1,   // 0x0C
1354                 1,   // 0x0D
1355                 1,   // 0x0E
1356                 0,   // 0x0F
1357                 1,   // 0x10
1358                 1,   // 0x11
1359                 0,   // 0x12
1360                 0,   // 0x13
1361                 0,   // 0x14
1362                 0,   // 0x15
1363                 0,   // 0x16
1364                 0,   // 0x17
1365                 0,   // 0x18
1366                 0,   // 0x19
1367                 0,   // 0x1A
1368                 0,   // 0x1B
1369                 0,   // 0x1C
1370                 0,   // 0x1D
1371                 0,   // 0x1E
1372                 0    // 0x1F
1373         };
1374
1375         uint8_t fc_clock_valid_modules[0x20] = {
1376                 1,   // 0x00
1377                 0,   // 0x01
1378                 0,   // 0x02
1379                 0,   // 0x03
1380                 0,   // 0x04
1381                 0,   // 0x05
1382                 0,   // 0x06
1383                 0,   // 0x07
1384                 0,   // 0x08
1385                 0,   // 0x09
1386                 0,   // 0x0A
1387                 0,   // 0x0B
1388                 1,   // 0x0C
1389                 1,   // 0x0D
1390                 0,   // 0x0E
1391                 0,   // 0x0F
1392                 0,   // 0x10
1393                 0,   // 0x11
1394                 0,   // 0x12
1395                 0,   // 0x13
1396                 0,   // 0x14
1397                 0,   // 0x15
1398                 0,   // 0x16
1399                 0,   // 0x17
1400                 0,   // 0x18
1401                 0,   // 0x19
1402                 0,   // 0x1A
1403                 0,   // 0x1B
1404                 0,   // 0x1C
1405                 0,   // 0x1D
1406                 0,   // 0x1E
1407                 0    // 0x1F
1408         };
1409
1410         qls_wr_mpi_reg(ha, 0x100e, 0x18a20000);
1411
1412         buf = qls_get_probe(ha, SYS_CLOCK, sys_clock_valid_modules, buf);
1413
1414         buf = qls_get_probe(ha, PCI_CLOCK, pci_clock_valid_modules, buf);
1415
1416         buf = qls_get_probe(ha, XGM_CLOCK, xgm_clock_valid_modules, buf);
1417
1418         buf = qls_get_probe(ha, FC_CLOCK, fc_clock_valid_modules, buf);
1419
1420         return(0);
1421 }
1422
1423 static void
1424 qls_get_ridx_registers(qla_host_t *ha, uint32_t *buf)
1425 {
1426         uint32_t type, idx, idx_max;
1427         uint32_t r_idx;
1428         uint32_t r_data;
1429         uint32_t val;
1430
1431         for (type = 0; type < 4; type ++) {
1432                 if (type < 2)
1433                         idx_max = 8;
1434                 else
1435                         idx_max = 16;
1436
1437                 for (idx = 0; idx < idx_max; idx ++) {
1438
1439                         val = 0x04000000 | (type << 16) | (idx << 8);
1440                         WRITE_REG32(ha, Q81_CTL_ROUTING_INDEX, val);
1441
1442                         r_idx = 0;
1443                         while ((r_idx & 0x40000000) == 0)
1444                                 r_idx = READ_REG32(ha, Q81_CTL_ROUTING_INDEX);
1445
1446                         r_data = READ_REG32(ha, Q81_CTL_ROUTING_DATA);
1447
1448                         *buf = type;
1449                         buf ++;
1450                         *buf = idx;
1451                         buf ++;
1452                         *buf = r_idx;
1453                         buf ++;
1454                         *buf = r_data;
1455                         buf ++;
1456                 }
1457         }
1458 }
1459
1460 static void
1461 qls_get_mac_proto_regs(qla_host_t *ha, uint32_t* buf)
1462 {
1463
1464 #define Q81_RS_AND_ADR 0x06000000
1465 #define Q81_RS_ONLY    0x04000000
1466 #define Q81_NUM_TYPES  10
1467
1468         uint32_t result_index, result_data;
1469         uint32_t type;
1470         uint32_t index;
1471         uint32_t offset;
1472         uint32_t val;
1473         uint32_t initial_val;
1474         uint32_t max_index;
1475         uint32_t max_offset;
1476
1477         for (type = 0; type < Q81_NUM_TYPES; type ++) {
1478                 switch (type) {
1479
1480                 case 0: // CAM
1481                         initial_val = Q81_RS_AND_ADR;
1482                         max_index = 512;
1483                         max_offset = 3;
1484                         break;
1485
1486                 case 1: // Multicast MAC Address
1487                         initial_val = Q81_RS_ONLY;
1488                         max_index = 32;
1489                         max_offset = 2;
1490                         break;
1491
1492                 case 2: // VLAN filter mask
1493                 case 3: // MC filter mask
1494                         initial_val = Q81_RS_ONLY;
1495                         max_index = 4096;
1496                         max_offset = 1;
1497                         break;
1498
1499                 case 4: // FC MAC addresses
1500                         initial_val = Q81_RS_ONLY;
1501                         max_index = 4;
1502                         max_offset = 2;
1503                         break;
1504
1505                 case 5: // Mgmt MAC addresses
1506                         initial_val = Q81_RS_ONLY;
1507                         max_index = 8;
1508                         max_offset = 2;
1509                         break;
1510
1511                 case 6: // Mgmt VLAN addresses
1512                         initial_val = Q81_RS_ONLY;
1513                         max_index = 16;
1514                         max_offset = 1;
1515                         break;
1516
1517                 case 7: // Mgmt IPv4 address
1518                         initial_val = Q81_RS_ONLY;
1519                         max_index = 4;
1520                         max_offset = 1;
1521                         break;
1522
1523                 case 8: // Mgmt IPv6 address
1524                         initial_val = Q81_RS_ONLY;
1525                         max_index = 4;
1526                         max_offset = 4;
1527                         break;
1528
1529                 case 9: // Mgmt TCP/UDP Dest port
1530                         initial_val = Q81_RS_ONLY;
1531                         max_index = 4;
1532                         max_offset = 1;
1533                         break;
1534
1535                 default:
1536                         printf("Bad type!!! 0x%08x\n", type);
1537                         max_index = 0;
1538                         max_offset = 0;
1539                         break;
1540                 }
1541
1542                 for (index = 0; index < max_index; index ++) {
1543
1544                         for (offset = 0; offset < max_offset; offset ++) {
1545
1546                                 val = initial_val | (type << 16) |
1547                                         (index << 4) | (offset);
1548
1549                                 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX,\
1550                                         val);
1551
1552                                 result_index = 0;
1553
1554                                 while ((result_index & 0x40000000) == 0)
1555                                         result_index =
1556                                                 READ_REG32(ha, \
1557                                                 Q81_CTL_MAC_PROTO_ADDR_INDEX);
1558
1559                                 result_data = READ_REG32(ha,\
1560                                                 Q81_CTL_MAC_PROTO_ADDR_DATA);
1561
1562                                 *buf = result_index;
1563                                 buf ++;
1564
1565                                 *buf = result_data;
1566                                 buf ++;
1567                         }
1568                 }
1569         }
1570 }
1571
1572 static int
1573 qls_get_ets_regs(qla_host_t *ha, uint32_t *buf)
1574 {
1575         int ret = 0;
1576         int i;
1577
1578         for(i = 0; i < 8; i ++, buf ++) {
1579                 WRITE_REG32(ha, Q81_CTL_NIC_ENH_TX_SCHD, \
1580                         ((i << 29) | 0x08000000));
1581                 *buf = READ_REG32(ha, Q81_CTL_NIC_ENH_TX_SCHD);
1582         }
1583
1584         for(i = 0; i < 2; i ++, buf ++) {
1585                 WRITE_REG32(ha, Q81_CTL_CNA_ENH_TX_SCHD, \
1586                         ((i << 29) | 0x08000000));
1587                 *buf = READ_REG32(ha, Q81_CTL_CNA_ENH_TX_SCHD);
1588         }
1589
1590         return ret;
1591 }
1592
1593 int
1594 qls_mpi_core_dump(qla_host_t *ha)
1595 {
1596         int ret;
1597         int i;
1598         uint32_t reg, reg_val;
1599
1600         qls_mpi_coredump_t *mpi_dump = &ql_mpi_coredump;
1601
1602         ret = qls_pause_mpi_risc(ha);
1603         if (ret) {
1604                 printf("Failed RISC pause. Status = 0x%.08x\n",ret);
1605                 return(-1);
1606         }
1607
1608         memset(&(mpi_dump->mpi_global_header), 0,
1609                         sizeof(qls_mpid_glbl_hdr_t));
1610
1611         mpi_dump->mpi_global_header.cookie = Q81_MPID_COOKIE;
1612         mpi_dump->mpi_global_header.hdr_size =
1613                 sizeof(qls_mpid_glbl_hdr_t);
1614         mpi_dump->mpi_global_header.img_size =
1615                 sizeof(qls_mpi_coredump_t);
1616
1617         memcpy(mpi_dump->mpi_global_header.id, "MPI Coredump",
1618                 sizeof(mpi_dump->mpi_global_header.id));
1619
1620         qls_mpid_seg_hdr(&mpi_dump->nic1_regs_seg_hdr,
1621                 Q81_NIC1_CONTROL_SEG_NUM,
1622                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic1_regs)),
1623                 "NIC1 Registers");
1624
1625         qls_mpid_seg_hdr(&mpi_dump->nic2_regs_seg_hdr,
1626                 Q81_NIC2_CONTROL_SEG_NUM,
1627                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic2_regs)),
1628                 "NIC2 Registers");
1629
1630         qls_mpid_seg_hdr(&mpi_dump->xgmac1_seg_hdr,
1631                 Q81_NIC1_XGMAC_SEG_NUM,
1632                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->xgmac1)),
1633                 "NIC1 XGMac Registers");
1634
1635         qls_mpid_seg_hdr(&mpi_dump->xgmac2_seg_hdr,
1636                 Q81_NIC2_XGMAC_SEG_NUM,
1637                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->xgmac2)),
1638                 "NIC2 XGMac Registers");
1639
1640         if (ha->pci_func & 1) {
1641                 for (i = 0; i < 64; i++)
1642                         mpi_dump->nic2_regs[i] =
1643                                 READ_REG32(ha, i * sizeof(uint32_t));
1644
1645                 for (i = 0; i < 64; i++)
1646                         mpi_dump->nic1_regs[i] =
1647                                 qls_rd_ofunc_reg(ha,
1648                                         (i * sizeof(uint32_t)) / 4);
1649
1650                 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac2[0], 0);
1651                 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac1[0], 1);
1652         } else {
1653                 for (i = 0; i < 64; i++)
1654                         mpi_dump->nic1_regs[i] =
1655                                 READ_REG32(ha, i * sizeof(uint32_t));
1656
1657                 for (i = 0; i < 64; i++)
1658                         mpi_dump->nic2_regs[i] =
1659                                 qls_rd_ofunc_reg(ha,
1660                                         (i * sizeof(uint32_t)) / 4);
1661
1662                 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac1[0], 0);
1663                 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac2[0], 1);
1664         }
1665
1666
1667         qls_mpid_seg_hdr(&mpi_dump->xaui1_an_hdr,
1668                 Q81_XAUI1_AN_SEG_NUM,
1669                 (sizeof(qls_mpid_seg_hdr_t) +
1670                         sizeof(mpi_dump->serdes1_xaui_an)),
1671                 "XAUI1 AN Registers");
1672
1673         qls_mpid_seg_hdr(&mpi_dump->xaui1_hss_pcs_hdr,
1674                 Q81_XAUI1_HSS_PCS_SEG_NUM,
1675                 (sizeof(qls_mpid_seg_hdr_t) +
1676                         sizeof(mpi_dump->serdes1_xaui_hss_pcs)),
1677                 "XAUI1 HSS PCS Registers");
1678
1679         qls_mpid_seg_hdr(&mpi_dump->xfi1_an_hdr,
1680                 Q81_XFI1_AN_SEG_NUM,
1681                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->serdes1_xfi_an)),
1682                 "XFI1 AN Registers");
1683
1684         qls_mpid_seg_hdr(&mpi_dump->xfi1_train_hdr,
1685                 Q81_XFI1_TRAIN_SEG_NUM,
1686                 (sizeof(qls_mpid_seg_hdr_t) +
1687                         sizeof(mpi_dump->serdes1_xfi_train)),
1688                 "XFI1 TRAIN Registers");
1689
1690         qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_pcs_hdr,
1691                 Q81_XFI1_HSS_PCS_SEG_NUM,
1692                 (sizeof(qls_mpid_seg_hdr_t) +
1693                         sizeof(mpi_dump->serdes1_xfi_hss_pcs)),
1694                 "XFI1 HSS PCS Registers");
1695
1696         qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_tx_hdr,
1697                 Q81_XFI1_HSS_TX_SEG_NUM,
1698                 (sizeof(qls_mpid_seg_hdr_t) +
1699                         sizeof(mpi_dump->serdes1_xfi_hss_tx)),
1700                 "XFI1 HSS TX Registers");
1701
1702         qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_rx_hdr,
1703                 Q81_XFI1_HSS_RX_SEG_NUM,
1704                 (sizeof(qls_mpid_seg_hdr_t) +
1705                         sizeof(mpi_dump->serdes1_xfi_hss_rx)),
1706                 "XFI1 HSS RX Registers");
1707
1708         qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_pll_hdr,
1709                 Q81_XFI1_HSS_PLL_SEG_NUM,
1710                 (sizeof(qls_mpid_seg_hdr_t) +
1711                         sizeof(mpi_dump->serdes1_xfi_hss_pll)),
1712                 "XFI1 HSS PLL Registers");
1713
1714         qls_mpid_seg_hdr(&mpi_dump->xaui2_an_hdr,
1715                 Q81_XAUI2_AN_SEG_NUM,
1716                 (sizeof(qls_mpid_seg_hdr_t) +
1717                         sizeof(mpi_dump->serdes2_xaui_an)),
1718                 "XAUI2 AN Registers");
1719
1720         qls_mpid_seg_hdr(&mpi_dump->xaui2_hss_pcs_hdr,
1721                 Q81_XAUI2_HSS_PCS_SEG_NUM,
1722                 (sizeof(qls_mpid_seg_hdr_t) +
1723                         sizeof(mpi_dump->serdes2_xaui_hss_pcs)),
1724                 "XAUI2 HSS PCS Registers");
1725
1726         qls_mpid_seg_hdr(&mpi_dump->xfi2_an_hdr,
1727                 Q81_XFI2_AN_SEG_NUM,
1728                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->serdes2_xfi_an)),
1729                 "XFI2 AN Registers");
1730
1731         qls_mpid_seg_hdr(&mpi_dump->xfi2_train_hdr,
1732                 Q81_XFI2_TRAIN_SEG_NUM,
1733                 (sizeof(qls_mpid_seg_hdr_t) +
1734                         sizeof(mpi_dump->serdes2_xfi_train)),
1735                 "XFI2 TRAIN Registers");
1736
1737         qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_pcs_hdr,
1738                 Q81_XFI2_HSS_PCS_SEG_NUM,
1739                 (sizeof(qls_mpid_seg_hdr_t) +
1740                         sizeof(mpi_dump->serdes2_xfi_hss_pcs)),
1741                 "XFI2 HSS PCS Registers");
1742
1743         qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_tx_hdr,
1744                 Q81_XFI2_HSS_TX_SEG_NUM,
1745                 (sizeof(qls_mpid_seg_hdr_t) +
1746                         sizeof(mpi_dump->serdes2_xfi_hss_tx)),
1747                 "XFI2 HSS TX Registers");
1748
1749         qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_rx_hdr,
1750                 Q81_XFI2_HSS_RX_SEG_NUM,
1751                 (sizeof(qls_mpid_seg_hdr_t) +
1752                         sizeof(mpi_dump->serdes2_xfi_hss_rx)),
1753                 "XFI2 HSS RX Registers");
1754
1755         qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_pll_hdr,
1756                 Q81_XFI2_HSS_PLL_SEG_NUM,
1757                 (sizeof(qls_mpid_seg_hdr_t) +
1758                         sizeof(mpi_dump->serdes2_xfi_hss_pll)),
1759                 "XFI2 HSS PLL Registers");
1760
1761         qls_rd_serdes_regs(ha, mpi_dump);
1762
1763         qls_mpid_seg_hdr(&mpi_dump->core_regs_seg_hdr,
1764                 Q81_CORE_SEG_NUM,
1765                 (sizeof(mpi_dump->core_regs_seg_hdr) +
1766                  sizeof(mpi_dump->mpi_core_regs) +
1767                  sizeof(mpi_dump->mpi_core_sh_regs)),
1768                 "Core Registers");
1769
1770         ret = qls_get_mpi_regs(ha, &mpi_dump->mpi_core_regs[0],
1771                         Q81_MPI_CORE_REGS_ADDR, Q81_MPI_CORE_REGS_CNT);
1772
1773         ret = qls_get_mpi_shadow_regs(ha,
1774                         &mpi_dump->mpi_core_sh_regs[0]);
1775
1776         qls_mpid_seg_hdr(&mpi_dump->test_logic_regs_seg_hdr,
1777                 Q81_TEST_LOGIC_SEG_NUM,
1778                 (sizeof(qls_mpid_seg_hdr_t) +
1779                         sizeof(mpi_dump->test_logic_regs)),
1780                 "Test Logic Regs");
1781
1782         ret = qls_get_mpi_regs(ha, &mpi_dump->test_logic_regs[0],
1783                             Q81_TEST_REGS_ADDR, Q81_TEST_REGS_CNT);
1784
1785         qls_mpid_seg_hdr(&mpi_dump->rmii_regs_seg_hdr,
1786                 Q81_RMII_SEG_NUM,
1787                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->rmii_regs)),
1788                 "RMII Registers");
1789
1790         ret = qls_get_mpi_regs(ha, &mpi_dump->rmii_regs[0],
1791                             Q81_RMII_REGS_ADDR, Q81_RMII_REGS_CNT);
1792
1793         qls_mpid_seg_hdr(&mpi_dump->fcmac1_regs_seg_hdr,
1794                 Q81_FCMAC1_SEG_NUM,
1795                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fcmac1_regs)),
1796                 "FCMAC1 Registers");
1797
1798         ret = qls_get_mpi_regs(ha, &mpi_dump->fcmac1_regs[0],
1799                             Q81_FCMAC1_REGS_ADDR, Q81_FCMAC_REGS_CNT);
1800
1801         qls_mpid_seg_hdr(&mpi_dump->fcmac2_regs_seg_hdr,
1802                 Q81_FCMAC2_SEG_NUM,
1803                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fcmac2_regs)),
1804                 "FCMAC2 Registers");
1805
1806         ret = qls_get_mpi_regs(ha, &mpi_dump->fcmac2_regs[0],
1807                             Q81_FCMAC2_REGS_ADDR, Q81_FCMAC_REGS_CNT);
1808
1809         qls_mpid_seg_hdr(&mpi_dump->fc1_mbx_regs_seg_hdr,
1810                 Q81_FC1_MBOX_SEG_NUM,
1811                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fc1_mbx_regs)),
1812                 "FC1 MBox Regs");
1813
1814         ret = qls_get_mpi_regs(ha, &mpi_dump->fc1_mbx_regs[0],
1815                             Q81_FC1_MBX_REGS_ADDR, Q81_FC_MBX_REGS_CNT);
1816
1817         qls_mpid_seg_hdr(&mpi_dump->ide_regs_seg_hdr,
1818                 Q81_IDE_SEG_NUM,
1819                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->ide_regs)),
1820                 "IDE Registers");
1821
1822         ret = qls_get_mpi_regs(ha, &mpi_dump->ide_regs[0],
1823                             Q81_IDE_REGS_ADDR, Q81_IDE_REGS_CNT);
1824
1825         qls_mpid_seg_hdr(&mpi_dump->nic1_mbx_regs_seg_hdr,
1826                 Q81_NIC1_MBOX_SEG_NUM,
1827                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic1_mbx_regs)),
1828                 "NIC1 MBox Regs");
1829
1830         ret = qls_get_mpi_regs(ha, &mpi_dump->nic1_mbx_regs[0],
1831                             Q81_NIC1_MBX_REGS_ADDR, Q81_NIC_MBX_REGS_CNT);
1832
1833         qls_mpid_seg_hdr(&mpi_dump->smbus_regs_seg_hdr,
1834                 Q81_SMBUS_SEG_NUM,
1835                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->smbus_regs)),
1836                 "SMBus Registers");
1837
1838         ret = qls_get_mpi_regs(ha, &mpi_dump->smbus_regs[0],
1839                             Q81_SMBUS_REGS_ADDR, Q81_SMBUS_REGS_CNT);
1840
1841         qls_mpid_seg_hdr(&mpi_dump->fc2_mbx_regs_seg_hdr,
1842                 Q81_FC2_MBOX_SEG_NUM,
1843                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fc2_mbx_regs)),
1844                 "FC2 MBox Regs");
1845
1846         ret = qls_get_mpi_regs(ha, &mpi_dump->fc2_mbx_regs[0],
1847                             Q81_FC2_MBX_REGS_ADDR, Q81_FC_MBX_REGS_CNT);
1848
1849         qls_mpid_seg_hdr(&mpi_dump->nic2_mbx_regs_seg_hdr,
1850                 Q81_NIC2_MBOX_SEG_NUM,
1851                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic2_mbx_regs)),
1852                 "NIC2 MBox Regs");
1853
1854         ret = qls_get_mpi_regs(ha, &mpi_dump->nic2_mbx_regs[0],
1855                             Q81_NIC2_MBX_REGS_ADDR, Q81_NIC_MBX_REGS_CNT);
1856
1857         qls_mpid_seg_hdr(&mpi_dump->i2c_regs_seg_hdr,
1858                 Q81_I2C_SEG_NUM,
1859                 (sizeof(qls_mpid_seg_hdr_t) +
1860                         sizeof(mpi_dump->i2c_regs)),
1861                 "I2C Registers");
1862
1863         ret = qls_get_mpi_regs(ha, &mpi_dump->i2c_regs[0],
1864                             Q81_I2C_REGS_ADDR, Q81_I2C_REGS_CNT);
1865
1866         qls_mpid_seg_hdr(&mpi_dump->memc_regs_seg_hdr,
1867                 Q81_MEMC_SEG_NUM,
1868                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->memc_regs)),
1869                 "MEMC Registers");
1870
1871         ret = qls_get_mpi_regs(ha, &mpi_dump->memc_regs[0],
1872                             Q81_MEMC_REGS_ADDR, Q81_MEMC_REGS_CNT);
1873
1874         qls_mpid_seg_hdr(&mpi_dump->pbus_regs_seg_hdr,
1875                 Q81_PBUS_SEG_NUM,
1876                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->pbus_regs)),
1877                 "PBUS Registers");
1878
1879         ret = qls_get_mpi_regs(ha, &mpi_dump->pbus_regs[0],
1880                             Q81_PBUS_REGS_ADDR, Q81_PBUS_REGS_CNT);
1881
1882         qls_mpid_seg_hdr(&mpi_dump->mde_regs_seg_hdr,
1883                 Q81_MDE_SEG_NUM,
1884                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->mde_regs)),
1885                 "MDE Registers");
1886
1887         ret = qls_get_mpi_regs(ha, &mpi_dump->mde_regs[0],
1888                             Q81_MDE_REGS_ADDR, Q81_MDE_REGS_CNT);
1889
1890         qls_mpid_seg_hdr(&mpi_dump->intr_states_seg_hdr,
1891                 Q81_INTR_STATES_SEG_NUM,
1892                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->intr_states)),
1893                 "INTR States");
1894
1895         qls_get_intr_states(ha, &mpi_dump->intr_states[0]);
1896
1897         qls_mpid_seg_hdr(&mpi_dump->probe_dump_seg_hdr,
1898                 Q81_PROBE_DUMP_SEG_NUM,
1899                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->probe_dump)),
1900                 "Probe Dump");
1901
1902         qls_get_probe_dump(ha, &mpi_dump->probe_dump[0]);
1903
1904         qls_mpid_seg_hdr(&mpi_dump->routing_reg_seg_hdr,
1905                 Q81_ROUTING_INDEX_SEG_NUM,
1906                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->routing_regs)),
1907                 "Routing Regs");
1908
1909         qls_get_ridx_registers(ha, &mpi_dump->routing_regs[0]);
1910
1911         qls_mpid_seg_hdr(&mpi_dump->mac_prot_reg_seg_hdr,
1912                 Q81_MAC_PROTOCOL_SEG_NUM,
1913                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->mac_prot_regs)),
1914                 "MAC Prot Regs");
1915
1916         qls_get_mac_proto_regs(ha, &mpi_dump->mac_prot_regs[0]);
1917
1918         qls_mpid_seg_hdr(&mpi_dump->ets_seg_hdr,
1919                 Q81_ETS_SEG_NUM,
1920                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->ets)),
1921                 "ETS Registers");
1922
1923         ret = qls_get_ets_regs(ha, &mpi_dump->ets[0]);
1924
1925         qls_mpid_seg_hdr(&mpi_dump->sem_regs_seg_hdr,
1926                 Q81_SEM_REGS_SEG_NUM,
1927                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->sem_regs)),
1928                 "Sem Registers");
1929
1930         for(i = 0; i < Q81_MAX_SEMAPHORE_FUNCTIONS ; i ++) {
1931
1932                 reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (i << Q81_FUNCTION_SHIFT) |
1933                                 (Q81_CTL_SEMAPHORE >> 2);
1934
1935                 ret = qls_mpi_risc_rd_reg(ha, reg, &reg_val);
1936                 mpi_dump->sem_regs[i] = reg_val;
1937
1938                 if (ret != 0)
1939                         mpi_dump->sem_regs[i] = Q81_BAD_DATA;
1940         }
1941
1942         ret = qls_unpause_mpi_risc(ha);
1943         if (ret)
1944                 printf("Failed RISC unpause. Status = 0x%.08x\n",ret);
1945
1946         ret = qls_mpi_reset(ha);
1947         if (ret)
1948                 printf("Failed RISC reset. Status = 0x%.08x\n",ret);
1949
1950         WRITE_REG32(ha, Q81_CTL_FUNC_SPECIFIC, 0x80008000);
1951
1952         qls_mpid_seg_hdr(&mpi_dump->memc_ram_seg_hdr,
1953                 Q81_MEMC_RAM_SEG_NUM,
1954                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->memc_ram)),
1955                 "MEMC RAM");
1956
1957         ret = qls_mbx_dump_risc_ram(ha, &mpi_dump->memc_ram[0],
1958                         Q81_MEMC_RAM_ADDR, Q81_MEMC_RAM_CNT);
1959         if (ret)
1960                 printf("Failed Dump of MEMC RAM. Status = 0x%.08x\n",ret);
1961
1962         qls_mpid_seg_hdr(&mpi_dump->code_ram_seg_hdr,
1963                 Q81_WCS_RAM_SEG_NUM,
1964                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->code_ram)),
1965                 "WCS RAM");
1966
1967         ret = qls_mbx_dump_risc_ram(ha, &mpi_dump->memc_ram[0],
1968                         Q81_CODE_RAM_ADDR, Q81_CODE_RAM_CNT);
1969         if (ret)
1970                 printf("Failed Dump of CODE RAM. Status = 0x%.08x\n",ret);
1971
1972         qls_mpid_seg_hdr(&mpi_dump->wqc1_seg_hdr,
1973                 Q81_WQC1_SEG_NUM,
1974                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->wqc1)),
1975                 "WQC 1");
1976
1977         qls_mpid_seg_hdr(&mpi_dump->wqc2_seg_hdr,
1978                 Q81_WQC2_SEG_NUM,
1979                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->wqc2)),
1980                 "WQC 2");
1981
1982         qls_mpid_seg_hdr(&mpi_dump->cqc1_seg_hdr,
1983                 Q81_CQC1_SEG_NUM,
1984                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->cqc1)),
1985                 "CQC 1");
1986
1987         qls_mpid_seg_hdr(&mpi_dump->cqc2_seg_hdr,
1988                 Q81_CQC2_SEG_NUM,
1989                 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->cqc2)),
1990                 "CQC 2");
1991
1992         return 0;
1993 }
1994