5 * Damien Bergamini <damien.bergamini@free.fr>
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <sys/cdefs.h>
21 __FBSDID("$FreeBSD$");
24 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver
25 * http://www.ralinktech.com/
28 #include <sys/param.h>
29 #include <sys/sysctl.h>
30 #include <sys/sockio.h>
32 #include <sys/kernel.h>
33 #include <sys/socket.h>
34 #include <sys/systm.h>
35 #include <sys/malloc.h>
37 #include <sys/mutex.h>
38 #include <sys/module.h>
40 #include <sys/endian.h>
41 #include <sys/firmware.h>
43 #include <machine/bus.h>
44 #include <machine/resource.h>
49 #include <net/if_var.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_dl.h>
53 #include <net/if_media.h>
54 #include <net/if_types.h>
56 #include <net80211/ieee80211_var.h>
57 #include <net80211/ieee80211_radiotap.h>
58 #include <net80211/ieee80211_regdomain.h>
59 #include <net80211/ieee80211_ratectl.h>
61 #include <netinet/in.h>
62 #include <netinet/in_systm.h>
63 #include <netinet/in_var.h>
64 #include <netinet/ip.h>
65 #include <netinet/if_ether.h>
67 #include <dev/ral/rt2661reg.h>
68 #include <dev/ral/rt2661var.h>
72 #define DPRINTF(sc, fmt, ...) do { \
73 if (sc->sc_debug > 0) \
74 printf(fmt, __VA_ARGS__); \
76 #define DPRINTFN(sc, n, fmt, ...) do { \
77 if (sc->sc_debug >= (n)) \
78 printf(fmt, __VA_ARGS__); \
81 #define DPRINTF(sc, fmt, ...)
82 #define DPRINTFN(sc, n, fmt, ...)
85 static struct ieee80211vap *rt2661_vap_create(struct ieee80211com *,
86 const char [IFNAMSIZ], int, enum ieee80211_opmode,
87 int, const uint8_t [IEEE80211_ADDR_LEN],
88 const uint8_t [IEEE80211_ADDR_LEN]);
89 static void rt2661_vap_delete(struct ieee80211vap *);
90 static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int,
92 static int rt2661_alloc_tx_ring(struct rt2661_softc *,
93 struct rt2661_tx_ring *, int);
94 static void rt2661_reset_tx_ring(struct rt2661_softc *,
95 struct rt2661_tx_ring *);
96 static void rt2661_free_tx_ring(struct rt2661_softc *,
97 struct rt2661_tx_ring *);
98 static int rt2661_alloc_rx_ring(struct rt2661_softc *,
99 struct rt2661_rx_ring *, int);
100 static void rt2661_reset_rx_ring(struct rt2661_softc *,
101 struct rt2661_rx_ring *);
102 static void rt2661_free_rx_ring(struct rt2661_softc *,
103 struct rt2661_rx_ring *);
104 static int rt2661_newstate(struct ieee80211vap *,
105 enum ieee80211_state, int);
106 static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t);
107 static void rt2661_rx_intr(struct rt2661_softc *);
108 static void rt2661_tx_intr(struct rt2661_softc *);
109 static void rt2661_tx_dma_intr(struct rt2661_softc *,
110 struct rt2661_tx_ring *);
111 static void rt2661_mcu_beacon_expire(struct rt2661_softc *);
112 static void rt2661_mcu_wakeup(struct rt2661_softc *);
113 static void rt2661_mcu_cmd_intr(struct rt2661_softc *);
114 static void rt2661_scan_start(struct ieee80211com *);
115 static void rt2661_scan_end(struct ieee80211com *);
116 static void rt2661_getradiocaps(struct ieee80211com *, int, int *,
117 struct ieee80211_channel[]);
118 static void rt2661_set_channel(struct ieee80211com *);
119 static void rt2661_setup_tx_desc(struct rt2661_softc *,
120 struct rt2661_tx_desc *, uint32_t, uint16_t, int,
121 int, const bus_dma_segment_t *, int, int);
122 static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *,
123 struct ieee80211_node *, int);
124 static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *,
125 struct ieee80211_node *);
126 static int rt2661_transmit(struct ieee80211com *, struct mbuf *);
127 static void rt2661_start(struct rt2661_softc *);
128 static int rt2661_raw_xmit(struct ieee80211_node *, struct mbuf *,
129 const struct ieee80211_bpf_params *);
130 static void rt2661_watchdog(void *);
131 static void rt2661_parent(struct ieee80211com *);
132 static void rt2661_bbp_write(struct rt2661_softc *, uint8_t,
134 static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t);
135 static void rt2661_rf_write(struct rt2661_softc *, uint8_t,
137 static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t,
139 static void rt2661_select_antenna(struct rt2661_softc *);
140 static void rt2661_enable_mrr(struct rt2661_softc *);
141 static void rt2661_set_txpreamble(struct rt2661_softc *);
142 static void rt2661_set_basicrates(struct rt2661_softc *,
143 const struct ieee80211_rateset *);
144 static void rt2661_select_band(struct rt2661_softc *,
145 struct ieee80211_channel *);
146 static void rt2661_set_chan(struct rt2661_softc *,
147 struct ieee80211_channel *);
148 static void rt2661_set_bssid(struct rt2661_softc *,
150 static void rt2661_set_macaddr(struct rt2661_softc *,
152 static void rt2661_update_promisc(struct ieee80211com *);
153 static int rt2661_wme_update(struct ieee80211com *) __unused;
154 static void rt2661_update_slot(struct ieee80211com *);
155 static const char *rt2661_get_rf(int);
156 static void rt2661_read_eeprom(struct rt2661_softc *,
157 uint8_t macaddr[IEEE80211_ADDR_LEN]);
158 static int rt2661_bbp_init(struct rt2661_softc *);
159 static void rt2661_init_locked(struct rt2661_softc *);
160 static void rt2661_init(void *);
161 static void rt2661_stop_locked(struct rt2661_softc *);
162 static void rt2661_stop(void *);
163 static int rt2661_load_microcode(struct rt2661_softc *);
165 static void rt2661_rx_tune(struct rt2661_softc *);
166 static void rt2661_radar_start(struct rt2661_softc *);
167 static int rt2661_radar_stop(struct rt2661_softc *);
169 static int rt2661_prepare_beacon(struct rt2661_softc *,
170 struct ieee80211vap *);
171 static void rt2661_enable_tsf_sync(struct rt2661_softc *);
172 static void rt2661_enable_tsf(struct rt2661_softc *);
173 static int rt2661_get_rssi(struct rt2661_softc *, uint8_t);
175 static const struct {
178 } rt2661_def_mac[] = {
182 static const struct {
185 } rt2661_def_bbp[] = {
189 static const struct rfprog {
191 uint32_t r1, r2, r3, r4;
192 } rt2661_rf5225_1[] = {
194 }, rt2661_rf5225_2[] = {
198 static const uint8_t rt2661_chan_5ghz[] =
199 { 36, 40, 44, 48, 52, 56, 60, 64,
200 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140,
201 149, 153, 157, 161, 165 };
204 rt2661_attach(device_t dev, int id)
206 struct rt2661_softc *sc = device_get_softc(dev);
207 struct ieee80211com *ic = &sc->sc_ic;
209 int error, ac, ntries;
214 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
215 MTX_DEF | MTX_RECURSE);
217 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0);
218 mbufq_init(&sc->sc_snd, ifqmaxlen);
220 /* wait for NIC to initialize */
221 for (ntries = 0; ntries < 1000; ntries++) {
222 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0)
226 if (ntries == 1000) {
227 device_printf(sc->sc_dev,
228 "timeout waiting for NIC to initialize\n");
233 /* retrieve RF rev. no and various other things from EEPROM */
234 rt2661_read_eeprom(sc, ic->ic_macaddr);
236 device_printf(dev, "MAC/BBP RT%X, RF %s\n", val,
237 rt2661_get_rf(sc->rf_rev));
240 * Allocate Tx and Rx rings.
242 for (ac = 0; ac < 4; ac++) {
243 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac],
244 RT2661_TX_RING_COUNT);
246 device_printf(sc->sc_dev,
247 "could not allocate Tx ring %d\n", ac);
252 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT);
254 device_printf(sc->sc_dev, "could not allocate Mgt ring\n");
258 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT);
260 device_printf(sc->sc_dev, "could not allocate Rx ring\n");
265 ic->ic_name = device_get_nameunit(dev);
266 ic->ic_opmode = IEEE80211_M_STA;
267 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
269 /* set device capabilities */
271 IEEE80211_C_STA /* station mode */
272 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
273 | IEEE80211_C_HOSTAP /* hostap mode */
274 | IEEE80211_C_MONITOR /* monitor mode */
275 | IEEE80211_C_AHDEMO /* adhoc demo mode */
276 | IEEE80211_C_WDS /* 4-address traffic works */
277 | IEEE80211_C_MBSS /* mesh point link mode */
278 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
279 | IEEE80211_C_SHSLOT /* short slot time supported */
280 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
281 | IEEE80211_C_BGSCAN /* capable of bg scanning */
283 | IEEE80211_C_TXFRAG /* handle tx frags */
284 | IEEE80211_C_WME /* 802.11e */
288 rt2661_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans,
291 ieee80211_ifattach(ic);
293 ic->ic_wme.wme_update = rt2661_wme_update;
295 ic->ic_scan_start = rt2661_scan_start;
296 ic->ic_scan_end = rt2661_scan_end;
297 ic->ic_getradiocaps = rt2661_getradiocaps;
298 ic->ic_set_channel = rt2661_set_channel;
299 ic->ic_updateslot = rt2661_update_slot;
300 ic->ic_update_promisc = rt2661_update_promisc;
301 ic->ic_raw_xmit = rt2661_raw_xmit;
302 ic->ic_transmit = rt2661_transmit;
303 ic->ic_parent = rt2661_parent;
304 ic->ic_vap_create = rt2661_vap_create;
305 ic->ic_vap_delete = rt2661_vap_delete;
307 ieee80211_radiotap_attach(ic,
308 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
309 RT2661_TX_RADIOTAP_PRESENT,
310 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
311 RT2661_RX_RADIOTAP_PRESENT);
314 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
315 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
316 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs");
319 ieee80211_announce(ic);
323 fail3: rt2661_free_tx_ring(sc, &sc->mgtq);
324 fail2: while (--ac >= 0)
325 rt2661_free_tx_ring(sc, &sc->txq[ac]);
326 fail1: mtx_destroy(&sc->sc_mtx);
331 rt2661_detach(void *xsc)
333 struct rt2661_softc *sc = xsc;
334 struct ieee80211com *ic = &sc->sc_ic;
337 rt2661_stop_locked(sc);
340 ieee80211_ifdetach(ic);
341 mbufq_drain(&sc->sc_snd);
343 rt2661_free_tx_ring(sc, &sc->txq[0]);
344 rt2661_free_tx_ring(sc, &sc->txq[1]);
345 rt2661_free_tx_ring(sc, &sc->txq[2]);
346 rt2661_free_tx_ring(sc, &sc->txq[3]);
347 rt2661_free_tx_ring(sc, &sc->mgtq);
348 rt2661_free_rx_ring(sc, &sc->rxq);
350 mtx_destroy(&sc->sc_mtx);
355 static struct ieee80211vap *
356 rt2661_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
357 enum ieee80211_opmode opmode, int flags,
358 const uint8_t bssid[IEEE80211_ADDR_LEN],
359 const uint8_t mac[IEEE80211_ADDR_LEN])
361 struct rt2661_softc *sc = ic->ic_softc;
362 struct rt2661_vap *rvp;
363 struct ieee80211vap *vap;
366 case IEEE80211_M_STA:
367 case IEEE80211_M_IBSS:
368 case IEEE80211_M_AHDEMO:
369 case IEEE80211_M_MONITOR:
370 case IEEE80211_M_HOSTAP:
371 case IEEE80211_M_MBSS:
373 if (!TAILQ_EMPTY(&ic->ic_vaps)) {
374 device_printf(sc->sc_dev, "only 1 vap supported\n");
377 if (opmode == IEEE80211_M_STA)
378 flags |= IEEE80211_CLONE_NOBEACONS;
380 case IEEE80211_M_WDS:
381 if (TAILQ_EMPTY(&ic->ic_vaps) ||
382 ic->ic_opmode != IEEE80211_M_HOSTAP) {
383 device_printf(sc->sc_dev,
384 "wds only supported in ap mode\n");
388 * Silently remove any request for a unique
389 * bssid; WDS vap's always share the local
392 flags &= ~IEEE80211_CLONE_BSSID;
395 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode);
398 rvp = malloc(sizeof(struct rt2661_vap), M_80211_VAP, M_WAITOK | M_ZERO);
400 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid);
402 /* override state transition machine */
403 rvp->ral_newstate = vap->iv_newstate;
404 vap->iv_newstate = rt2661_newstate;
406 vap->iv_update_beacon = rt2661_beacon_update;
409 ieee80211_ratectl_init(vap);
411 ieee80211_vap_attach(vap, ieee80211_media_change,
412 ieee80211_media_status, mac);
413 if (TAILQ_FIRST(&ic->ic_vaps) == vap)
414 ic->ic_opmode = opmode;
419 rt2661_vap_delete(struct ieee80211vap *vap)
421 struct rt2661_vap *rvp = RT2661_VAP(vap);
423 ieee80211_ratectl_deinit(vap);
424 ieee80211_vap_detach(vap);
425 free(rvp, M_80211_VAP);
429 rt2661_shutdown(void *xsc)
431 struct rt2661_softc *sc = xsc;
437 rt2661_suspend(void *xsc)
439 struct rt2661_softc *sc = xsc;
445 rt2661_resume(void *xsc)
447 struct rt2661_softc *sc = xsc;
449 if (sc->sc_ic.ic_nrunning > 0)
454 rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
459 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
461 *(bus_addr_t *)arg = segs[0].ds_addr;
465 rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring,
472 ring->cur = ring->next = ring->stat = 0;
474 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0,
475 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
476 count * RT2661_TX_DESC_SIZE, 1, count * RT2661_TX_DESC_SIZE,
477 0, NULL, NULL, &ring->desc_dmat);
479 device_printf(sc->sc_dev, "could not create desc DMA tag\n");
483 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc,
484 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map);
486 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
490 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc,
491 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr,
494 device_printf(sc->sc_dev, "could not load desc DMA map\n");
498 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF,
500 if (ring->data == NULL) {
501 device_printf(sc->sc_dev, "could not allocate soft data\n");
506 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
507 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
508 RT2661_MAX_SCATTER, MCLBYTES, 0, NULL, NULL, &ring->data_dmat);
510 device_printf(sc->sc_dev, "could not create data DMA tag\n");
514 for (i = 0; i < count; i++) {
515 error = bus_dmamap_create(ring->data_dmat, 0,
518 device_printf(sc->sc_dev, "could not create DMA map\n");
525 fail: rt2661_free_tx_ring(sc, ring);
530 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring)
532 struct rt2661_tx_desc *desc;
533 struct rt2661_tx_data *data;
536 for (i = 0; i < ring->count; i++) {
537 desc = &ring->desc[i];
538 data = &ring->data[i];
540 if (data->m != NULL) {
541 bus_dmamap_sync(ring->data_dmat, data->map,
542 BUS_DMASYNC_POSTWRITE);
543 bus_dmamap_unload(ring->data_dmat, data->map);
548 if (data->ni != NULL) {
549 ieee80211_free_node(data->ni);
556 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
559 ring->cur = ring->next = ring->stat = 0;
563 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring)
565 struct rt2661_tx_data *data;
568 if (ring->desc != NULL) {
569 bus_dmamap_sync(ring->desc_dmat, ring->desc_map,
570 BUS_DMASYNC_POSTWRITE);
571 bus_dmamap_unload(ring->desc_dmat, ring->desc_map);
572 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map);
575 if (ring->desc_dmat != NULL)
576 bus_dma_tag_destroy(ring->desc_dmat);
578 if (ring->data != NULL) {
579 for (i = 0; i < ring->count; i++) {
580 data = &ring->data[i];
582 if (data->m != NULL) {
583 bus_dmamap_sync(ring->data_dmat, data->map,
584 BUS_DMASYNC_POSTWRITE);
585 bus_dmamap_unload(ring->data_dmat, data->map);
589 if (data->ni != NULL)
590 ieee80211_free_node(data->ni);
592 if (data->map != NULL)
593 bus_dmamap_destroy(ring->data_dmat, data->map);
596 free(ring->data, M_DEVBUF);
599 if (ring->data_dmat != NULL)
600 bus_dma_tag_destroy(ring->data_dmat);
604 rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring,
607 struct rt2661_rx_desc *desc;
608 struct rt2661_rx_data *data;
613 ring->cur = ring->next = 0;
615 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0,
616 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
617 count * RT2661_RX_DESC_SIZE, 1, count * RT2661_RX_DESC_SIZE,
618 0, NULL, NULL, &ring->desc_dmat);
620 device_printf(sc->sc_dev, "could not create desc DMA tag\n");
624 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc,
625 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map);
627 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
631 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc,
632 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr,
635 device_printf(sc->sc_dev, "could not load desc DMA map\n");
639 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF,
641 if (ring->data == NULL) {
642 device_printf(sc->sc_dev, "could not allocate soft data\n");
648 * Pre-allocate Rx buffers and populate Rx ring.
650 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
651 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
652 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat);
654 device_printf(sc->sc_dev, "could not create data DMA tag\n");
658 for (i = 0; i < count; i++) {
659 desc = &sc->rxq.desc[i];
660 data = &sc->rxq.data[i];
662 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
664 device_printf(sc->sc_dev, "could not create DMA map\n");
668 data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
669 if (data->m == NULL) {
670 device_printf(sc->sc_dev,
671 "could not allocate rx mbuf\n");
676 error = bus_dmamap_load(ring->data_dmat, data->map,
677 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr,
680 device_printf(sc->sc_dev,
681 "could not load rx buf DMA map");
685 desc->flags = htole32(RT2661_RX_BUSY);
686 desc->physaddr = htole32(physaddr);
689 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
693 fail: rt2661_free_rx_ring(sc, ring);
698 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring)
702 for (i = 0; i < ring->count; i++)
703 ring->desc[i].flags = htole32(RT2661_RX_BUSY);
705 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
707 ring->cur = ring->next = 0;
711 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring)
713 struct rt2661_rx_data *data;
716 if (ring->desc != NULL) {
717 bus_dmamap_sync(ring->desc_dmat, ring->desc_map,
718 BUS_DMASYNC_POSTWRITE);
719 bus_dmamap_unload(ring->desc_dmat, ring->desc_map);
720 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map);
723 if (ring->desc_dmat != NULL)
724 bus_dma_tag_destroy(ring->desc_dmat);
726 if (ring->data != NULL) {
727 for (i = 0; i < ring->count; i++) {
728 data = &ring->data[i];
730 if (data->m != NULL) {
731 bus_dmamap_sync(ring->data_dmat, data->map,
732 BUS_DMASYNC_POSTREAD);
733 bus_dmamap_unload(ring->data_dmat, data->map);
737 if (data->map != NULL)
738 bus_dmamap_destroy(ring->data_dmat, data->map);
741 free(ring->data, M_DEVBUF);
744 if (ring->data_dmat != NULL)
745 bus_dma_tag_destroy(ring->data_dmat);
749 rt2661_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
751 struct rt2661_vap *rvp = RT2661_VAP(vap);
752 struct ieee80211com *ic = vap->iv_ic;
753 struct rt2661_softc *sc = ic->ic_softc;
756 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) {
759 /* abort TSF synchronization */
760 tmp = RAL_READ(sc, RT2661_TXRX_CSR9);
761 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff);
764 error = rvp->ral_newstate(vap, nstate, arg);
766 if (error == 0 && nstate == IEEE80211_S_RUN) {
767 struct ieee80211_node *ni = vap->iv_bss;
769 if (vap->iv_opmode != IEEE80211_M_MONITOR) {
770 rt2661_enable_mrr(sc);
771 rt2661_set_txpreamble(sc);
772 rt2661_set_basicrates(sc, &ni->ni_rates);
773 rt2661_set_bssid(sc, ni->ni_bssid);
776 if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
777 vap->iv_opmode == IEEE80211_M_IBSS ||
778 vap->iv_opmode == IEEE80211_M_MBSS) {
779 error = rt2661_prepare_beacon(sc, vap);
783 if (vap->iv_opmode != IEEE80211_M_MONITOR)
784 rt2661_enable_tsf_sync(sc);
786 rt2661_enable_tsf(sc);
792 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or
796 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr)
802 /* clock C once before the first command */
803 RT2661_EEPROM_CTL(sc, 0);
805 RT2661_EEPROM_CTL(sc, RT2661_S);
806 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
807 RT2661_EEPROM_CTL(sc, RT2661_S);
809 /* write start bit (1) */
810 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D);
811 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C);
813 /* write READ opcode (10) */
814 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D);
815 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C);
816 RT2661_EEPROM_CTL(sc, RT2661_S);
817 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
819 /* write address (A5-A0 or A7-A0) */
820 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7;
821 for (; n >= 0; n--) {
822 RT2661_EEPROM_CTL(sc, RT2661_S |
823 (((addr >> n) & 1) << RT2661_SHIFT_D));
824 RT2661_EEPROM_CTL(sc, RT2661_S |
825 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C);
828 RT2661_EEPROM_CTL(sc, RT2661_S);
830 /* read data Q15-Q0 */
832 for (n = 15; n >= 0; n--) {
833 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
834 tmp = RAL_READ(sc, RT2661_E2PROM_CSR);
835 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n;
836 RT2661_EEPROM_CTL(sc, RT2661_S);
839 RT2661_EEPROM_CTL(sc, 0);
841 /* clear Chip Select and clock C */
842 RT2661_EEPROM_CTL(sc, RT2661_S);
843 RT2661_EEPROM_CTL(sc, 0);
844 RT2661_EEPROM_CTL(sc, RT2661_C);
850 rt2661_tx_intr(struct rt2661_softc *sc)
852 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs;
853 struct rt2661_tx_ring *txq;
854 struct rt2661_tx_data *data;
858 txs->flags = IEEE80211_RATECTL_TX_FAIL_LONG;
860 struct ieee80211_node *ni;
863 val = RAL_READ(sc, RT2661_STA_CSR4);
864 if (!(val & RT2661_TX_STAT_VALID))
867 /* retrieve the queue in which this frame was sent */
868 qid = RT2661_TX_QID(val);
869 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq;
871 /* retrieve rate control algorithm context */
872 data = &txq->data[txq->stat];
878 /* if no frame has been sent, ignore */
882 switch (RT2661_TX_RESULT(val)) {
883 case RT2661_TX_SUCCESS:
884 txs->status = IEEE80211_RATECTL_TX_SUCCESS;
885 txs->long_retries = RT2661_TX_RETRYCNT(val);
887 DPRINTFN(sc, 10, "data frame sent successfully after "
888 "%d retries\n", txs->long_retries);
889 if (data->rix != IEEE80211_FIXED_RATE_NONE)
890 ieee80211_ratectl_tx_complete(ni, txs);
894 case RT2661_TX_RETRY_FAIL:
895 txs->status = IEEE80211_RATECTL_TX_FAIL_LONG;
896 txs->long_retries = RT2661_TX_RETRYCNT(val);
898 DPRINTFN(sc, 9, "%s\n",
899 "sending data frame failed (too much retries)");
900 if (data->rix != IEEE80211_FIXED_RATE_NONE)
901 ieee80211_ratectl_tx_complete(ni, txs);
907 device_printf(sc->sc_dev,
908 "sending data frame failed 0x%08x\n", val);
912 DPRINTFN(sc, 15, "tx done q=%d idx=%u\n", qid, txq->stat);
915 if (++txq->stat >= txq->count) /* faster than % count */
918 ieee80211_tx_complete(ni, m, error);
927 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq)
929 struct rt2661_tx_desc *desc;
930 struct rt2661_tx_data *data;
932 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD);
935 desc = &txq->desc[txq->next];
936 data = &txq->data[txq->next];
938 if ((le32toh(desc->flags) & RT2661_TX_BUSY) ||
939 !(le32toh(desc->flags) & RT2661_TX_VALID))
942 bus_dmamap_sync(txq->data_dmat, data->map,
943 BUS_DMASYNC_POSTWRITE);
944 bus_dmamap_unload(txq->data_dmat, data->map);
946 /* descriptor is no longer valid */
947 desc->flags &= ~htole32(RT2661_TX_VALID);
949 DPRINTFN(sc, 15, "tx dma done q=%p idx=%u\n", txq, txq->next);
951 if (++txq->next >= txq->count) /* faster than % count */
955 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
959 rt2661_rx_intr(struct rt2661_softc *sc)
961 struct ieee80211com *ic = &sc->sc_ic;
962 struct rt2661_rx_desc *desc;
963 struct rt2661_rx_data *data;
965 struct ieee80211_frame *wh;
966 struct ieee80211_node *ni;
967 struct mbuf *mnew, *m;
970 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
971 BUS_DMASYNC_POSTREAD);
976 desc = &sc->rxq.desc[sc->rxq.cur];
977 data = &sc->rxq.data[sc->rxq.cur];
979 if (le32toh(desc->flags) & RT2661_RX_BUSY)
982 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) ||
983 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) {
985 * This should not happen since we did not request
986 * to receive those frames when we filled TXRX_CSR0.
988 DPRINTFN(sc, 5, "PHY or CRC error flags 0x%08x\n",
989 le32toh(desc->flags));
990 counter_u64_add(ic->ic_ierrors, 1);
994 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) {
995 counter_u64_add(ic->ic_ierrors, 1);
1000 * Try to allocate a new mbuf for this ring element and load it
1001 * before processing the current mbuf. If the ring element
1002 * cannot be loaded, drop the received packet and reuse the old
1003 * mbuf. In the unlikely case that the old mbuf can't be
1004 * reloaded either, explicitly panic.
1006 mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1008 counter_u64_add(ic->ic_ierrors, 1);
1012 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
1013 BUS_DMASYNC_POSTREAD);
1014 bus_dmamap_unload(sc->rxq.data_dmat, data->map);
1016 error = bus_dmamap_load(sc->rxq.data_dmat, data->map,
1017 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr,
1022 /* try to reload the old mbuf */
1023 error = bus_dmamap_load(sc->rxq.data_dmat, data->map,
1024 mtod(data->m, void *), MCLBYTES,
1025 rt2661_dma_map_addr, &physaddr, 0);
1027 /* very unlikely that it will fail... */
1028 panic("%s: could not load old rx mbuf",
1029 device_get_name(sc->sc_dev));
1031 counter_u64_add(ic->ic_ierrors, 1);
1036 * New mbuf successfully loaded, update Rx ring and continue
1041 desc->physaddr = htole32(physaddr);
1044 m->m_pkthdr.len = m->m_len =
1045 (le32toh(desc->flags) >> 16) & 0xfff;
1047 rssi = rt2661_get_rssi(sc, desc->rssi);
1048 /* Error happened during RSSI conversion. */
1050 rssi = -30; /* XXX ignored by net80211 */
1051 nf = RT2661_NOISE_FLOOR;
1053 if (ieee80211_radiotap_active(ic)) {
1054 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap;
1055 uint32_t tsf_lo, tsf_hi;
1057 /* get timestamp (low and high 32 bits) */
1058 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13);
1059 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12);
1062 htole64(((uint64_t)tsf_hi << 32) | tsf_lo);
1064 tap->wr_rate = ieee80211_plcp2rate(desc->rate,
1065 (desc->flags & htole32(RT2661_RX_OFDM)) ?
1066 IEEE80211_T_OFDM : IEEE80211_T_CCK);
1067 tap->wr_antsignal = nf + rssi;
1068 tap->wr_antnoise = nf;
1070 sc->sc_flags |= RAL_INPUT_RUNNING;
1072 wh = mtod(m, struct ieee80211_frame *);
1074 /* send the frame to the 802.11 layer */
1075 ni = ieee80211_find_rxnode(ic,
1076 (struct ieee80211_frame_min *)wh);
1078 (void) ieee80211_input(ni, m, rssi, nf);
1079 ieee80211_free_node(ni);
1081 (void) ieee80211_input_all(ic, m, rssi, nf);
1084 sc->sc_flags &= ~RAL_INPUT_RUNNING;
1086 skip: desc->flags |= htole32(RT2661_RX_BUSY);
1088 DPRINTFN(sc, 15, "rx intr idx=%u\n", sc->rxq.cur);
1090 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT;
1093 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
1094 BUS_DMASYNC_PREWRITE);
1099 rt2661_mcu_beacon_expire(struct rt2661_softc *sc)
1105 rt2661_mcu_wakeup(struct rt2661_softc *sc)
1107 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16);
1109 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7);
1110 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18);
1111 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20);
1113 /* send wakeup command to MCU */
1114 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0);
1118 rt2661_mcu_cmd_intr(struct rt2661_softc *sc)
1120 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR);
1121 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff);
1125 rt2661_intr(void *arg)
1127 struct rt2661_softc *sc = arg;
1132 /* disable MAC and MCU interrupts */
1133 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f);
1134 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
1136 /* don't re-enable interrupts if we're shutting down */
1137 if (!(sc->sc_flags & RAL_RUNNING)) {
1142 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR);
1143 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1);
1145 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR);
1146 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2);
1148 if (r1 & RT2661_MGT_DONE)
1149 rt2661_tx_dma_intr(sc, &sc->mgtq);
1151 if (r1 & RT2661_RX_DONE)
1154 if (r1 & RT2661_TX0_DMA_DONE)
1155 rt2661_tx_dma_intr(sc, &sc->txq[0]);
1157 if (r1 & RT2661_TX1_DMA_DONE)
1158 rt2661_tx_dma_intr(sc, &sc->txq[1]);
1160 if (r1 & RT2661_TX2_DMA_DONE)
1161 rt2661_tx_dma_intr(sc, &sc->txq[2]);
1163 if (r1 & RT2661_TX3_DMA_DONE)
1164 rt2661_tx_dma_intr(sc, &sc->txq[3]);
1166 if (r1 & RT2661_TX_DONE)
1169 if (r2 & RT2661_MCU_CMD_DONE)
1170 rt2661_mcu_cmd_intr(sc);
1172 if (r2 & RT2661_MCU_BEACON_EXPIRE)
1173 rt2661_mcu_beacon_expire(sc);
1175 if (r2 & RT2661_MCU_WAKEUP)
1176 rt2661_mcu_wakeup(sc);
1178 /* re-enable MAC and MCU interrupts */
1179 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10);
1180 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0);
1186 rt2661_plcp_signal(int rate)
1189 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */
1190 case 12: return 0xb;
1191 case 18: return 0xf;
1192 case 24: return 0xa;
1193 case 36: return 0xe;
1194 case 48: return 0x9;
1195 case 72: return 0xd;
1196 case 96: return 0x8;
1197 case 108: return 0xc;
1199 /* CCK rates (NB: not IEEE std, device-specific) */
1202 case 11: return 0x2;
1203 case 22: return 0x3;
1205 return 0xff; /* XXX unsupported/unknown rate */
1209 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc,
1210 uint32_t flags, uint16_t xflags, int len, int rate,
1211 const bus_dma_segment_t *segs, int nsegs, int ac)
1213 struct ieee80211com *ic = &sc->sc_ic;
1214 uint16_t plcp_length;
1217 desc->flags = htole32(flags);
1218 desc->flags |= htole32(len << 16);
1219 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID);
1221 desc->xflags = htole16(xflags);
1222 desc->xflags |= htole16(nsegs << 13);
1224 desc->wme = htole16(
1227 RT2661_LOGCWMIN(4) |
1228 RT2661_LOGCWMAX(10));
1231 * Remember in which queue this frame was sent. This field is driver
1232 * private data only. It will be made available by the NIC in STA_CSR4
1237 /* setup PLCP fields */
1238 desc->plcp_signal = rt2661_plcp_signal(rate);
1239 desc->plcp_service = 4;
1241 len += IEEE80211_CRC_LEN;
1242 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) {
1243 desc->flags |= htole32(RT2661_TX_OFDM);
1245 plcp_length = len & 0xfff;
1246 desc->plcp_length_hi = plcp_length >> 6;
1247 desc->plcp_length_lo = plcp_length & 0x3f;
1249 plcp_length = howmany(16 * len, rate);
1251 remainder = (16 * len) % 22;
1252 if (remainder != 0 && remainder < 7)
1253 desc->plcp_service |= RT2661_PLCP_LENGEXT;
1255 desc->plcp_length_hi = plcp_length >> 8;
1256 desc->plcp_length_lo = plcp_length & 0xff;
1258 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1259 desc->plcp_signal |= 0x08;
1262 /* RT2x61 supports scatter with up to 5 segments */
1263 for (i = 0; i < nsegs; i++) {
1264 desc->addr[i] = htole32(segs[i].ds_addr);
1265 desc->len [i] = htole16(segs[i].ds_len);
1270 rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0,
1271 struct ieee80211_node *ni)
1273 struct ieee80211vap *vap = ni->ni_vap;
1274 struct ieee80211com *ic = ni->ni_ic;
1275 struct rt2661_tx_desc *desc;
1276 struct rt2661_tx_data *data;
1277 struct ieee80211_frame *wh;
1278 struct ieee80211_key *k;
1279 bus_dma_segment_t segs[RT2661_MAX_SCATTER];
1281 uint32_t flags = 0; /* XXX HWSEQ */
1282 int nsegs, rate, error;
1284 desc = &sc->mgtq.desc[sc->mgtq.cur];
1285 data = &sc->mgtq.data[sc->mgtq.cur];
1287 rate = ni->ni_txparms->mgmtrate;
1289 wh = mtod(m0, struct ieee80211_frame *);
1291 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1292 k = ieee80211_crypto_encap(ni, m0);
1299 error = bus_dmamap_load_mbuf_sg(sc->mgtq.data_dmat, data->map, m0,
1302 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n",
1308 if (ieee80211_radiotap_active_vap(vap)) {
1309 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap;
1312 tap->wt_rate = rate;
1314 ieee80211_radiotap_tx(vap, m0);
1319 /* management frames are not taken into account for amrr */
1320 data->rix = IEEE80211_FIXED_RATE_NONE;
1322 wh = mtod(m0, struct ieee80211_frame *);
1324 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1325 flags |= RT2661_TX_NEED_ACK;
1327 dur = ieee80211_ack_duration(ic->ic_rt,
1328 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE);
1329 *(uint16_t *)wh->i_dur = htole16(dur);
1331 /* tell hardware to add timestamp in probe responses */
1333 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
1334 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP))
1335 flags |= RT2661_TX_TIMESTAMP;
1338 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */,
1339 m0->m_pkthdr.len, rate, segs, nsegs, RT2661_QID_MGT);
1341 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1342 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map,
1343 BUS_DMASYNC_PREWRITE);
1345 DPRINTFN(sc, 10, "sending mgt frame len=%u idx=%u rate=%u\n",
1346 m0->m_pkthdr.len, sc->mgtq.cur, rate);
1350 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT;
1351 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT);
1357 rt2661_sendprot(struct rt2661_softc *sc, int ac,
1358 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate)
1360 struct ieee80211com *ic = ni->ni_ic;
1361 struct rt2661_tx_ring *txq = &sc->txq[ac];
1362 struct rt2661_tx_desc *desc;
1363 struct rt2661_tx_data *data;
1365 int protrate, flags, error;
1366 bus_dma_segment_t segs[RT2661_MAX_SCATTER];
1369 mprot = ieee80211_alloc_prot(ni, m, rate, prot);
1370 if (mprot == NULL) {
1371 if_inc_counter(ni->ni_vap->iv_ifp, IFCOUNTER_OERRORS, 1);
1372 device_printf(sc->sc_dev,
1373 "could not allocate mbuf for protection mode %d\n", prot);
1377 data = &txq->data[txq->cur];
1378 desc = &txq->desc[txq->cur];
1380 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, mprot, segs,
1383 device_printf(sc->sc_dev,
1384 "could not map mbuf (error %d)\n", error);
1390 data->ni = ieee80211_ref_node(ni);
1391 /* ctl frames are not taken into account for amrr */
1392 data->rix = IEEE80211_FIXED_RATE_NONE;
1394 protrate = ieee80211_ctl_rate(ic->ic_rt, rate);
1395 flags = RT2661_TX_MORE_FRAG;
1396 if (prot == IEEE80211_PROT_RTSCTS)
1397 flags |= RT2661_TX_NEED_ACK;
1399 rt2661_setup_tx_desc(sc, desc, flags, 0, mprot->m_pkthdr.len,
1400 protrate, segs, 1, ac);
1402 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1403 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
1406 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT;
1412 rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0,
1413 struct ieee80211_node *ni, int ac)
1415 struct ieee80211vap *vap = ni->ni_vap;
1416 struct ieee80211com *ic = &sc->sc_ic;
1417 struct rt2661_tx_ring *txq = &sc->txq[ac];
1418 struct rt2661_tx_desc *desc;
1419 struct rt2661_tx_data *data;
1420 struct ieee80211_frame *wh;
1421 const struct ieee80211_txparam *tp = ni->ni_txparms;
1422 struct ieee80211_key *k;
1424 bus_dma_segment_t segs[RT2661_MAX_SCATTER];
1427 int error, nsegs, rate, noack = 0;
1429 wh = mtod(m0, struct ieee80211_frame *);
1431 if (m0->m_flags & M_EAPOL) {
1432 rate = tp->mgmtrate;
1433 } else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1434 rate = tp->mcastrate;
1435 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) {
1436 rate = tp->ucastrate;
1438 (void) ieee80211_ratectl_rate(ni, NULL, 0);
1439 rate = ni->ni_txrate;
1441 rate &= IEEE80211_RATE_VAL;
1443 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS)
1444 noack = !! ieee80211_wme_vap_ac_is_noack(vap, ac);
1446 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1447 k = ieee80211_crypto_encap(ni, m0);
1453 /* packet header may have moved, reset our local pointer */
1454 wh = mtod(m0, struct ieee80211_frame *);
1458 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1459 int prot = IEEE80211_PROT_NONE;
1460 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold)
1461 prot = IEEE80211_PROT_RTSCTS;
1462 else if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
1463 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM)
1464 prot = ic->ic_protmode;
1465 if (prot != IEEE80211_PROT_NONE) {
1466 error = rt2661_sendprot(sc, ac, m0, ni, prot, rate);
1471 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS;
1475 data = &txq->data[txq->cur];
1476 desc = &txq->desc[txq->cur];
1478 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, segs,
1480 if (error != 0 && error != EFBIG) {
1481 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n",
1487 mnew = m_defrag(m0, M_NOWAIT);
1489 device_printf(sc->sc_dev,
1490 "could not defragment mbuf\n");
1496 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0,
1499 device_printf(sc->sc_dev,
1500 "could not map mbuf (error %d)\n", error);
1505 /* packet header have moved, reset our local pointer */
1506 wh = mtod(m0, struct ieee80211_frame *);
1509 if (ieee80211_radiotap_active_vap(vap)) {
1510 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap;
1513 tap->wt_rate = rate;
1515 ieee80211_radiotap_tx(vap, m0);
1521 /* remember link conditions for rate adaptation algorithm */
1522 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) {
1523 data->rix = ni->ni_txrate;
1524 /* XXX probably need last rssi value and not avg */
1525 data->rssi = ic->ic_node_getrssi(ni);
1527 data->rix = IEEE80211_FIXED_RATE_NONE;
1529 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1530 flags |= RT2661_TX_NEED_ACK;
1532 dur = ieee80211_ack_duration(ic->ic_rt,
1533 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE);
1534 *(uint16_t *)wh->i_dur = htole16(dur);
1537 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, segs,
1540 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1541 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
1543 DPRINTFN(sc, 10, "sending data frame len=%u idx=%u rate=%u\n",
1544 m0->m_pkthdr.len, txq->cur, rate);
1548 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT;
1549 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac);
1555 rt2661_transmit(struct ieee80211com *ic, struct mbuf *m)
1557 struct rt2661_softc *sc = ic->ic_softc;
1561 if ((sc->sc_flags & RAL_RUNNING) == 0) {
1565 error = mbufq_enqueue(&sc->sc_snd, m);
1577 rt2661_start(struct rt2661_softc *sc)
1580 struct ieee80211_node *ni;
1583 RAL_LOCK_ASSERT(sc);
1585 /* prevent management frames from being sent if we're not ready */
1586 if (!(sc->sc_flags & RAL_RUNNING) || sc->sc_invalid)
1589 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
1590 ac = M_WME_GETAC(m);
1591 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) {
1592 /* there is no place left in this ring */
1593 mbufq_prepend(&sc->sc_snd, m);
1596 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1597 if (rt2661_tx_data(sc, m, ni, ac) != 0) {
1598 if_inc_counter(ni->ni_vap->iv_ifp,
1599 IFCOUNTER_OERRORS, 1);
1600 ieee80211_free_node(ni);
1603 sc->sc_tx_timer = 5;
1608 rt2661_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1609 const struct ieee80211_bpf_params *params)
1611 struct ieee80211com *ic = ni->ni_ic;
1612 struct rt2661_softc *sc = ic->ic_softc;
1616 /* prevent management frames from being sent if we're not ready */
1617 if (!(sc->sc_flags & RAL_RUNNING)) {
1622 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) {
1625 return ENOBUFS; /* XXX */
1629 * Legacy path; interpret frame contents to decide
1630 * precisely how to send the frame.
1633 if (rt2661_tx_mgt(sc, m, ni) != 0)
1635 sc->sc_tx_timer = 5;
1642 return EIO; /* XXX */
1646 rt2661_watchdog(void *arg)
1648 struct rt2661_softc *sc = (struct rt2661_softc *)arg;
1650 RAL_LOCK_ASSERT(sc);
1652 KASSERT(sc->sc_flags & RAL_RUNNING, ("not running"));
1654 if (sc->sc_invalid) /* card ejected */
1657 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) {
1658 device_printf(sc->sc_dev, "device timeout\n");
1659 rt2661_init_locked(sc);
1660 counter_u64_add(sc->sc_ic.ic_oerrors, 1);
1661 /* NB: callout is reset in rt2661_init() */
1664 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc);
1668 rt2661_parent(struct ieee80211com *ic)
1670 struct rt2661_softc *sc = ic->ic_softc;
1674 if (ic->ic_nrunning > 0) {
1675 if ((sc->sc_flags & RAL_RUNNING) == 0) {
1676 rt2661_init_locked(sc);
1679 rt2661_update_promisc(ic);
1680 } else if (sc->sc_flags & RAL_RUNNING)
1681 rt2661_stop_locked(sc);
1684 ieee80211_start_all(ic);
1688 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val)
1693 for (ntries = 0; ntries < 100; ntries++) {
1694 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY))
1698 if (ntries == 100) {
1699 device_printf(sc->sc_dev, "could not write to BBP\n");
1703 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val;
1704 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp);
1706 DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val);
1710 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg)
1715 for (ntries = 0; ntries < 100; ntries++) {
1716 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY))
1720 if (ntries == 100) {
1721 device_printf(sc->sc_dev, "could not read from BBP\n");
1725 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8;
1726 RAL_WRITE(sc, RT2661_PHY_CSR3, val);
1728 for (ntries = 0; ntries < 100; ntries++) {
1729 val = RAL_READ(sc, RT2661_PHY_CSR3);
1730 if (!(val & RT2661_BBP_BUSY))
1735 device_printf(sc->sc_dev, "could not read from BBP\n");
1740 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val)
1745 for (ntries = 0; ntries < 100; ntries++) {
1746 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY))
1750 if (ntries == 100) {
1751 device_printf(sc->sc_dev, "could not write to RF\n");
1755 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 |
1757 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp);
1759 /* remember last written value in sc */
1760 sc->rf_regs[reg] = val;
1762 DPRINTFN(sc, 15, "RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff);
1766 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg)
1768 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY)
1769 return EIO; /* there is already a command pending */
1771 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR,
1772 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg);
1774 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd);
1780 rt2661_select_antenna(struct rt2661_softc *sc)
1782 uint8_t bbp4, bbp77;
1785 bbp4 = rt2661_bbp_read(sc, 4);
1786 bbp77 = rt2661_bbp_read(sc, 77);
1790 /* make sure Rx is disabled before switching antenna */
1791 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
1792 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
1794 rt2661_bbp_write(sc, 4, bbp4);
1795 rt2661_bbp_write(sc, 77, bbp77);
1797 /* restore Rx filter */
1798 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
1802 * Enable multi-rate retries for frames sent at OFDM rates.
1803 * In 802.11b/g mode, allow fallback to CCK rates.
1806 rt2661_enable_mrr(struct rt2661_softc *sc)
1808 struct ieee80211com *ic = &sc->sc_ic;
1811 tmp = RAL_READ(sc, RT2661_TXRX_CSR4);
1813 tmp &= ~RT2661_MRR_CCK_FALLBACK;
1814 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan))
1815 tmp |= RT2661_MRR_CCK_FALLBACK;
1816 tmp |= RT2661_MRR_ENABLED;
1818 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp);
1822 rt2661_set_txpreamble(struct rt2661_softc *sc)
1824 struct ieee80211com *ic = &sc->sc_ic;
1827 tmp = RAL_READ(sc, RT2661_TXRX_CSR4);
1829 tmp &= ~RT2661_SHORT_PREAMBLE;
1830 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
1831 tmp |= RT2661_SHORT_PREAMBLE;
1833 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp);
1837 rt2661_set_basicrates(struct rt2661_softc *sc,
1838 const struct ieee80211_rateset *rs)
1840 struct ieee80211com *ic = &sc->sc_ic;
1845 for (i = 0; i < rs->rs_nrates; i++) {
1846 rate = rs->rs_rates[i];
1848 if (!(rate & IEEE80211_RATE_BASIC))
1851 mask |= 1 << ieee80211_legacy_rate_lookup(ic->ic_rt,
1852 IEEE80211_RV(rate));
1855 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask);
1857 DPRINTF(sc, "Setting basic rate mask to 0x%x\n", mask);
1861 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference
1865 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c)
1867 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104;
1870 /* update all BBP registers that depend on the band */
1871 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c;
1872 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48;
1873 if (IEEE80211_IS_CHAN_5GHZ(c)) {
1874 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c;
1875 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10;
1877 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) ||
1878 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) {
1879 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10;
1882 rt2661_bbp_write(sc, 17, bbp17);
1883 rt2661_bbp_write(sc, 96, bbp96);
1884 rt2661_bbp_write(sc, 104, bbp104);
1886 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) ||
1887 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) {
1888 rt2661_bbp_write(sc, 75, 0x80);
1889 rt2661_bbp_write(sc, 86, 0x80);
1890 rt2661_bbp_write(sc, 88, 0x80);
1893 rt2661_bbp_write(sc, 35, bbp35);
1894 rt2661_bbp_write(sc, 97, bbp97);
1895 rt2661_bbp_write(sc, 98, bbp98);
1897 tmp = RAL_READ(sc, RT2661_PHY_CSR0);
1898 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ);
1899 if (IEEE80211_IS_CHAN_2GHZ(c))
1900 tmp |= RT2661_PA_PE_2GHZ;
1902 tmp |= RT2661_PA_PE_5GHZ;
1903 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp);
1907 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c)
1909 struct ieee80211com *ic = &sc->sc_ic;
1910 const struct rfprog *rfprog;
1911 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT;
1915 chan = ieee80211_chan2ieee(ic, c);
1916 KASSERT(chan != 0 && chan != IEEE80211_CHAN_ANY, ("chan 0x%x", chan));
1918 /* select the appropriate RF settings based on what EEPROM says */
1919 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2;
1921 /* find the settings for this channel (we know it exists) */
1922 for (i = 0; rfprog[i].chan != chan; i++);
1924 power = sc->txpow[i];
1928 } else if (power > 31) {
1929 bbp94 += power - 31;
1934 * If we are switching from the 2GHz band to the 5GHz band or
1935 * vice-versa, BBP registers need to be reprogrammed.
1937 if (c->ic_flags != sc->sc_curchan->ic_flags) {
1938 rt2661_select_band(sc, c);
1939 rt2661_select_antenna(sc);
1943 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1);
1944 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2);
1945 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7);
1946 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10);
1950 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1);
1951 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2);
1952 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1);
1953 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10);
1957 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1);
1958 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2);
1959 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7);
1960 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10);
1962 /* enable smart mode for MIMO-capable RFs */
1963 bbp3 = rt2661_bbp_read(sc, 3);
1965 bbp3 &= ~RT2661_SMART_MODE;
1966 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529)
1967 bbp3 |= RT2661_SMART_MODE;
1969 rt2661_bbp_write(sc, 3, bbp3);
1971 if (bbp94 != RT2661_BBPR94_DEFAULT)
1972 rt2661_bbp_write(sc, 94, bbp94);
1974 /* 5GHz radio needs a 1ms delay here */
1975 if (IEEE80211_IS_CHAN_5GHZ(c))
1980 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid)
1984 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24;
1985 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp);
1987 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16;
1988 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp);
1992 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr)
1996 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24;
1997 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp);
1999 tmp = addr[4] | addr[5] << 8;
2000 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp);
2004 rt2661_update_promisc(struct ieee80211com *ic)
2006 struct rt2661_softc *sc = ic->ic_softc;
2009 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
2011 tmp &= ~RT2661_DROP_NOT_TO_ME;
2012 if (ic->ic_promisc == 0)
2013 tmp |= RT2661_DROP_NOT_TO_ME;
2015 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2017 DPRINTF(sc, "%s promiscuous mode\n",
2018 (ic->ic_promisc > 0) ? "entering" : "leaving");
2022 * Update QoS (802.11e) settings for each h/w Tx ring.
2025 rt2661_wme_update(struct ieee80211com *ic)
2027 struct rt2661_softc *sc = ic->ic_softc;
2028 struct chanAccParams chp;
2029 const struct wmeParams *wmep;
2031 ieee80211_wme_ic_getparams(ic, &chp);
2033 wmep = chp.cap_wmeParams;
2035 /* XXX: not sure about shifts. */
2036 /* XXX: the reference driver plays with AC_VI settings too. */
2039 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0,
2040 wmep[WME_AC_BE].wmep_txopLimit << 16 |
2041 wmep[WME_AC_BK].wmep_txopLimit);
2042 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1,
2043 wmep[WME_AC_VI].wmep_txopLimit << 16 |
2044 wmep[WME_AC_VO].wmep_txopLimit);
2047 RAL_WRITE(sc, RT2661_CWMIN_CSR,
2048 wmep[WME_AC_BE].wmep_logcwmin << 12 |
2049 wmep[WME_AC_BK].wmep_logcwmin << 8 |
2050 wmep[WME_AC_VI].wmep_logcwmin << 4 |
2051 wmep[WME_AC_VO].wmep_logcwmin);
2054 RAL_WRITE(sc, RT2661_CWMAX_CSR,
2055 wmep[WME_AC_BE].wmep_logcwmax << 12 |
2056 wmep[WME_AC_BK].wmep_logcwmax << 8 |
2057 wmep[WME_AC_VI].wmep_logcwmax << 4 |
2058 wmep[WME_AC_VO].wmep_logcwmax);
2061 RAL_WRITE(sc, RT2661_AIFSN_CSR,
2062 wmep[WME_AC_BE].wmep_aifsn << 12 |
2063 wmep[WME_AC_BK].wmep_aifsn << 8 |
2064 wmep[WME_AC_VI].wmep_aifsn << 4 |
2065 wmep[WME_AC_VO].wmep_aifsn);
2071 rt2661_update_slot(struct ieee80211com *ic)
2073 struct rt2661_softc *sc = ic->ic_softc;
2077 slottime = IEEE80211_GET_SLOTTIME(ic);
2079 tmp = RAL_READ(sc, RT2661_MAC_CSR9);
2080 tmp = (tmp & ~0xff) | slottime;
2081 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp);
2085 rt2661_get_rf(int rev)
2088 case RT2661_RF_5225: return "RT5225";
2089 case RT2661_RF_5325: return "RT5325 (MIMO XR)";
2090 case RT2661_RF_2527: return "RT2527";
2091 case RT2661_RF_2529: return "RT2529 (MIMO XR)";
2092 default: return "unknown";
2097 rt2661_read_eeprom(struct rt2661_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN])
2102 /* read MAC address */
2103 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01);
2104 macaddr[0] = val & 0xff;
2105 macaddr[1] = val >> 8;
2107 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23);
2108 macaddr[2] = val & 0xff;
2109 macaddr[3] = val >> 8;
2111 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45);
2112 macaddr[4] = val & 0xff;
2113 macaddr[5] = val >> 8;
2115 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA);
2116 /* XXX: test if different from 0xffff? */
2117 sc->rf_rev = (val >> 11) & 0x1f;
2118 sc->hw_radio = (val >> 10) & 0x1;
2119 sc->rx_ant = (val >> 4) & 0x3;
2120 sc->tx_ant = (val >> 2) & 0x3;
2121 sc->nb_ant = val & 0x3;
2123 DPRINTF(sc, "RF revision=%d\n", sc->rf_rev);
2125 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2);
2126 sc->ext_5ghz_lna = (val >> 6) & 0x1;
2127 sc->ext_2ghz_lna = (val >> 4) & 0x1;
2129 DPRINTF(sc, "External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n",
2130 sc->ext_2ghz_lna, sc->ext_5ghz_lna);
2132 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET);
2133 if ((val & 0xff) != 0xff)
2134 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */
2136 /* Only [-10, 10] is valid */
2137 if (sc->rssi_2ghz_corr < -10 || sc->rssi_2ghz_corr > 10)
2138 sc->rssi_2ghz_corr = 0;
2140 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET);
2141 if ((val & 0xff) != 0xff)
2142 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */
2144 /* Only [-10, 10] is valid */
2145 if (sc->rssi_5ghz_corr < -10 || sc->rssi_5ghz_corr > 10)
2146 sc->rssi_5ghz_corr = 0;
2148 /* adjust RSSI correction for external low-noise amplifier */
2149 if (sc->ext_2ghz_lna)
2150 sc->rssi_2ghz_corr -= 14;
2151 if (sc->ext_5ghz_lna)
2152 sc->rssi_5ghz_corr -= 14;
2154 DPRINTF(sc, "RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n",
2155 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr);
2157 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET);
2158 if ((val >> 8) != 0xff)
2159 sc->rfprog = (val >> 8) & 0x3;
2160 if ((val & 0xff) != 0xff)
2161 sc->rffreq = val & 0xff;
2163 DPRINTF(sc, "RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq);
2165 /* read Tx power for all a/b/g channels */
2166 for (i = 0; i < 19; i++) {
2167 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i);
2168 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */
2169 DPRINTF(sc, "Channel=%d Tx power=%d\n",
2170 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2]);
2171 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */
2172 DPRINTF(sc, "Channel=%d Tx power=%d\n",
2173 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1]);
2176 /* read vendor-specific BBP values */
2177 for (i = 0; i < 16; i++) {
2178 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i);
2179 if (val == 0 || val == 0xffff)
2180 continue; /* skip invalid entries */
2181 sc->bbp_prom[i].reg = val >> 8;
2182 sc->bbp_prom[i].val = val & 0xff;
2183 DPRINTF(sc, "BBP R%d=%02x\n", sc->bbp_prom[i].reg,
2184 sc->bbp_prom[i].val);
2189 rt2661_bbp_init(struct rt2661_softc *sc)
2194 /* wait for BBP to be ready */
2195 for (ntries = 0; ntries < 100; ntries++) {
2196 val = rt2661_bbp_read(sc, 0);
2197 if (val != 0 && val != 0xff)
2201 if (ntries == 100) {
2202 device_printf(sc->sc_dev, "timeout waiting for BBP\n");
2206 /* initialize BBP registers to default values */
2207 for (i = 0; i < nitems(rt2661_def_bbp); i++) {
2208 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg,
2209 rt2661_def_bbp[i].val);
2212 /* write vendor-specific BBP values (from EEPROM) */
2213 for (i = 0; i < 16; i++) {
2214 if (sc->bbp_prom[i].reg == 0)
2216 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
2223 rt2661_init_locked(struct rt2661_softc *sc)
2225 struct ieee80211com *ic = &sc->sc_ic;
2226 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2227 uint32_t tmp, sta[3];
2228 int i, error, ntries;
2230 RAL_LOCK_ASSERT(sc);
2232 if ((sc->sc_flags & RAL_FW_LOADED) == 0) {
2233 error = rt2661_load_microcode(sc);
2235 device_printf(sc->sc_dev,
2236 "%s: could not load 8051 microcode, error %d\n",
2240 sc->sc_flags |= RAL_FW_LOADED;
2243 rt2661_stop_locked(sc);
2245 /* initialize Tx rings */
2246 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr);
2247 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr);
2248 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr);
2249 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr);
2251 /* initialize Mgt ring */
2252 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr);
2254 /* initialize Rx ring */
2255 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr);
2257 /* initialize Tx rings sizes */
2258 RAL_WRITE(sc, RT2661_TX_RING_CSR0,
2259 RT2661_TX_RING_COUNT << 24 |
2260 RT2661_TX_RING_COUNT << 16 |
2261 RT2661_TX_RING_COUNT << 8 |
2262 RT2661_TX_RING_COUNT);
2264 RAL_WRITE(sc, RT2661_TX_RING_CSR1,
2265 RT2661_TX_DESC_WSIZE << 16 |
2266 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */
2267 RT2661_MGT_RING_COUNT);
2269 /* initialize Rx rings */
2270 RAL_WRITE(sc, RT2661_RX_RING_CSR,
2271 RT2661_RX_DESC_BACK << 16 |
2272 RT2661_RX_DESC_WSIZE << 8 |
2273 RT2661_RX_RING_COUNT);
2275 /* XXX: some magic here */
2276 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa);
2278 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */
2279 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f);
2281 /* load base address of Rx ring */
2282 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2);
2284 /* initialize MAC registers to default values */
2285 for (i = 0; i < nitems(rt2661_def_mac); i++)
2286 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val);
2288 rt2661_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr);
2290 /* set host ready */
2291 RAL_WRITE(sc, RT2661_MAC_CSR1, 3);
2292 RAL_WRITE(sc, RT2661_MAC_CSR1, 0);
2294 /* wait for BBP/RF to wakeup */
2295 for (ntries = 0; ntries < 1000; ntries++) {
2296 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8)
2300 if (ntries == 1000) {
2301 printf("timeout waiting for BBP/RF to wakeup\n");
2302 rt2661_stop_locked(sc);
2306 if (rt2661_bbp_init(sc) != 0) {
2307 rt2661_stop_locked(sc);
2311 /* select default channel */
2312 sc->sc_curchan = ic->ic_curchan;
2313 rt2661_select_band(sc, sc->sc_curchan);
2314 rt2661_select_antenna(sc);
2315 rt2661_set_chan(sc, sc->sc_curchan);
2317 /* update Rx filter */
2318 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff;
2320 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR;
2321 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2322 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR |
2324 if (ic->ic_opmode != IEEE80211_M_HOSTAP &&
2325 ic->ic_opmode != IEEE80211_M_MBSS)
2326 tmp |= RT2661_DROP_TODS;
2327 if (ic->ic_promisc == 0)
2328 tmp |= RT2661_DROP_NOT_TO_ME;
2331 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2333 /* clear STA registers */
2334 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, nitems(sta));
2336 /* initialize ASIC */
2337 RAL_WRITE(sc, RT2661_MAC_CSR1, 4);
2339 /* clear any pending interrupt */
2340 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff);
2342 /* enable interrupts */
2343 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10);
2344 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0);
2347 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1);
2349 sc->sc_flags |= RAL_RUNNING;
2351 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc);
2355 rt2661_init(void *priv)
2357 struct rt2661_softc *sc = priv;
2358 struct ieee80211com *ic = &sc->sc_ic;
2361 rt2661_init_locked(sc);
2364 if (sc->sc_flags & RAL_RUNNING)
2365 ieee80211_start_all(ic); /* start all vap's */
2369 rt2661_stop_locked(struct rt2661_softc *sc)
2371 volatile int *flags = &sc->sc_flags;
2374 while (*flags & RAL_INPUT_RUNNING)
2375 msleep(sc, &sc->sc_mtx, 0, "ralrunning", hz/10);
2377 callout_stop(&sc->watchdog_ch);
2378 sc->sc_tx_timer = 0;
2380 if (sc->sc_flags & RAL_RUNNING) {
2381 sc->sc_flags &= ~RAL_RUNNING;
2383 /* abort Tx (for all 5 Tx rings) */
2384 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16);
2386 /* disable Rx (value remains after reset!) */
2387 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
2388 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2391 RAL_WRITE(sc, RT2661_MAC_CSR1, 3);
2392 RAL_WRITE(sc, RT2661_MAC_CSR1, 0);
2394 /* disable interrupts */
2395 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff);
2396 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
2398 /* clear any pending interrupt */
2399 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff);
2400 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff);
2402 /* reset Tx and Rx rings */
2403 rt2661_reset_tx_ring(sc, &sc->txq[0]);
2404 rt2661_reset_tx_ring(sc, &sc->txq[1]);
2405 rt2661_reset_tx_ring(sc, &sc->txq[2]);
2406 rt2661_reset_tx_ring(sc, &sc->txq[3]);
2407 rt2661_reset_tx_ring(sc, &sc->mgtq);
2408 rt2661_reset_rx_ring(sc, &sc->rxq);
2413 rt2661_stop(void *priv)
2415 struct rt2661_softc *sc = priv;
2418 rt2661_stop_locked(sc);
2423 rt2661_load_microcode(struct rt2661_softc *sc)
2425 const struct firmware *fp;
2426 const char *imagename;
2429 RAL_LOCK_ASSERT(sc);
2431 switch (sc->sc_id) {
2432 case 0x0301: imagename = "rt2561sfw"; break;
2433 case 0x0302: imagename = "rt2561fw"; break;
2434 case 0x0401: imagename = "rt2661fw"; break;
2436 device_printf(sc->sc_dev, "%s: unexpected pci device id 0x%x, "
2437 "don't know how to retrieve firmware\n",
2438 __func__, sc->sc_id);
2442 fp = firmware_get(imagename);
2445 device_printf(sc->sc_dev,
2446 "%s: unable to retrieve firmware image %s\n",
2447 __func__, imagename);
2452 * Load 8051 microcode into NIC.
2455 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET);
2457 /* cancel any pending Host to MCU command */
2458 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0);
2459 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff);
2460 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0);
2462 /* write 8051's microcode */
2463 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL);
2464 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, fp->data, fp->datasize);
2465 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET);
2467 /* kick 8051's ass */
2468 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0);
2470 /* wait for 8051 to initialize */
2471 for (ntries = 0; ntries < 500; ntries++) {
2472 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY)
2476 if (ntries == 500) {
2477 device_printf(sc->sc_dev,
2478 "%s: timeout waiting for MCU to initialize\n", __func__);
2483 firmware_put(fp, FIRMWARE_UNLOAD);
2489 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and
2490 * false CCA count. This function is called periodically (every seconds) when
2491 * in the RUN state. Values taken from the reference driver.
2494 rt2661_rx_tune(struct rt2661_softc *sc)
2501 * Tuning range depends on operating band and on the presence of an
2502 * external low-noise amplifier.
2505 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan))
2507 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) ||
2508 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna))
2512 /* retrieve false CCA count since last call (clear on read) */
2513 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff;
2517 } else if (dbm >= -58) {
2519 } else if (dbm >= -66) {
2521 } else if (dbm >= -74) {
2524 /* RSSI < -74dBm, tune using false CCA count */
2526 bbp17 = sc->bbp17; /* current value */
2528 hi -= 2 * (-74 - dbm);
2535 } else if (cca > 512) {
2538 } else if (cca < 100) {
2544 if (bbp17 != sc->bbp17) {
2545 rt2661_bbp_write(sc, 17, bbp17);
2551 * Enter/Leave radar detection mode.
2552 * This is for 802.11h additional regulatory domains.
2555 rt2661_radar_start(struct rt2661_softc *sc)
2560 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
2561 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2563 rt2661_bbp_write(sc, 82, 0x20);
2564 rt2661_bbp_write(sc, 83, 0x00);
2565 rt2661_bbp_write(sc, 84, 0x40);
2567 /* save current BBP registers values */
2568 sc->bbp18 = rt2661_bbp_read(sc, 18);
2569 sc->bbp21 = rt2661_bbp_read(sc, 21);
2570 sc->bbp22 = rt2661_bbp_read(sc, 22);
2571 sc->bbp16 = rt2661_bbp_read(sc, 16);
2572 sc->bbp17 = rt2661_bbp_read(sc, 17);
2573 sc->bbp64 = rt2661_bbp_read(sc, 64);
2575 rt2661_bbp_write(sc, 18, 0xff);
2576 rt2661_bbp_write(sc, 21, 0x3f);
2577 rt2661_bbp_write(sc, 22, 0x3f);
2578 rt2661_bbp_write(sc, 16, 0xbd);
2579 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34);
2580 rt2661_bbp_write(sc, 64, 0x21);
2582 /* restore Rx filter */
2583 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2587 rt2661_radar_stop(struct rt2661_softc *sc)
2591 /* read radar detection result */
2592 bbp66 = rt2661_bbp_read(sc, 66);
2594 /* restore BBP registers values */
2595 rt2661_bbp_write(sc, 16, sc->bbp16);
2596 rt2661_bbp_write(sc, 17, sc->bbp17);
2597 rt2661_bbp_write(sc, 18, sc->bbp18);
2598 rt2661_bbp_write(sc, 21, sc->bbp21);
2599 rt2661_bbp_write(sc, 22, sc->bbp22);
2600 rt2661_bbp_write(sc, 64, sc->bbp64);
2607 rt2661_prepare_beacon(struct rt2661_softc *sc, struct ieee80211vap *vap)
2609 struct ieee80211com *ic = vap->iv_ic;
2610 struct rt2661_tx_desc desc;
2614 if ((m0 = ieee80211_beacon_alloc(vap->iv_bss))== NULL) {
2615 device_printf(sc->sc_dev, "could not allocate beacon frame\n");
2619 /* send beacons at the lowest available rate */
2620 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 12 : 2;
2622 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ,
2623 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT);
2625 /* copy the first 24 bytes of Tx descriptor into NIC memory */
2626 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24);
2628 /* copy beacon header and payload into NIC memory */
2629 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24,
2630 mtod(m0, uint8_t *), m0->m_pkthdr.len);
2638 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS
2639 * and HostAP operating modes.
2642 rt2661_enable_tsf_sync(struct rt2661_softc *sc)
2644 struct ieee80211com *ic = &sc->sc_ic;
2645 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2648 if (vap->iv_opmode != IEEE80211_M_STA) {
2650 * Change default 16ms TBTT adjustment to 8ms.
2651 * Must be done before enabling beacon generation.
2653 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8);
2656 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000;
2658 /* set beacon interval (in 1/16ms unit) */
2659 tmp |= vap->iv_bss->ni_intval * 16;
2661 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT;
2662 if (vap->iv_opmode == IEEE80211_M_STA)
2663 tmp |= RT2661_TSF_MODE(1);
2665 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON;
2667 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp);
2671 rt2661_enable_tsf(struct rt2661_softc *sc)
2673 RAL_WRITE(sc, RT2661_TXRX_CSR9,
2674 (RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000)
2675 | RT2661_TSF_TICKING | RT2661_TSF_MODE(2));
2679 * Retrieve the "Received Signal Strength Indicator" from the raw values
2680 * contained in Rx descriptors. The computation depends on which band the
2681 * frame was received. Correction values taken from the reference driver.
2684 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw)
2688 lna = (raw >> 5) & 0x3;
2693 * No mapping available.
2695 * NB: Since RSSI is relative to noise floor, -1 is
2696 * adequate for caller to know error happened.
2701 rssi = (2 * agc) - RT2661_NOISE_FLOOR;
2703 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) {
2704 rssi += sc->rssi_2ghz_corr;
2713 rssi += sc->rssi_5ghz_corr;
2726 rt2661_scan_start(struct ieee80211com *ic)
2728 struct rt2661_softc *sc = ic->ic_softc;
2731 /* abort TSF synchronization */
2732 tmp = RAL_READ(sc, RT2661_TXRX_CSR9);
2733 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0xffffff);
2734 rt2661_set_bssid(sc, ieee80211broadcastaddr);
2738 rt2661_scan_end(struct ieee80211com *ic)
2740 struct rt2661_softc *sc = ic->ic_softc;
2741 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2743 rt2661_enable_tsf_sync(sc);
2744 /* XXX keep local copy */
2745 rt2661_set_bssid(sc, vap->iv_bss->ni_bssid);
2749 rt2661_getradiocaps(struct ieee80211com *ic,
2750 int maxchans, int *nchans, struct ieee80211_channel chans[])
2752 struct rt2661_softc *sc = ic->ic_softc;
2753 uint8_t bands[IEEE80211_MODE_BYTES];
2755 memset(bands, 0, sizeof(bands));
2756 setbit(bands, IEEE80211_MODE_11B);
2757 setbit(bands, IEEE80211_MODE_11G);
2758 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0);
2760 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) {
2761 setbit(bands, IEEE80211_MODE_11A);
2762 ieee80211_add_channel_list_5ghz(chans, maxchans, nchans,
2763 rt2661_chan_5ghz, nitems(rt2661_chan_5ghz), bands, 0);
2768 rt2661_set_channel(struct ieee80211com *ic)
2770 struct rt2661_softc *sc = ic->ic_softc;
2773 rt2661_set_chan(sc, ic->ic_curchan);