5 * Damien Bergamini <damien.bergamini@free.fr>
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <sys/cdefs.h>
21 __FBSDID("$FreeBSD$");
24 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver
25 * http://www.ralinktech.com/
28 #include <sys/param.h>
29 #include <sys/sysctl.h>
30 #include <sys/sockio.h>
32 #include <sys/kernel.h>
33 #include <sys/socket.h>
34 #include <sys/systm.h>
35 #include <sys/malloc.h>
37 #include <sys/mutex.h>
38 #include <sys/module.h>
40 #include <sys/endian.h>
41 #include <sys/firmware.h>
43 #include <machine/bus.h>
44 #include <machine/resource.h>
49 #include <net/if_arp.h>
50 #include <net/ethernet.h>
51 #include <net/if_dl.h>
52 #include <net/if_media.h>
53 #include <net/if_types.h>
55 #include <net80211/ieee80211_var.h>
56 #include <net80211/ieee80211_phy.h>
57 #include <net80211/ieee80211_radiotap.h>
58 #include <net80211/ieee80211_regdomain.h>
59 #include <net80211/ieee80211_amrr.h>
61 #include <netinet/in.h>
62 #include <netinet/in_systm.h>
63 #include <netinet/in_var.h>
64 #include <netinet/ip.h>
65 #include <netinet/if_ether.h>
67 #include <dev/ral/rt2661reg.h>
68 #include <dev/ral/rt2661var.h>
72 #define DPRINTF(sc, fmt, ...) do { \
73 if (sc->sc_debug > 0) \
74 printf(fmt, __VA_ARGS__); \
76 #define DPRINTFN(sc, n, fmt, ...) do { \
77 if (sc->sc_debug >= (n)) \
78 printf(fmt, __VA_ARGS__); \
81 #define DPRINTF(sc, fmt, ...)
82 #define DPRINTFN(sc, n, fmt, ...)
85 static struct ieee80211vap *rt2661_vap_create(struct ieee80211com *,
86 const char name[IFNAMSIZ], int unit, int opmode,
87 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
88 const uint8_t mac[IEEE80211_ADDR_LEN]);
89 static void rt2661_vap_delete(struct ieee80211vap *);
90 static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int,
92 static int rt2661_alloc_tx_ring(struct rt2661_softc *,
93 struct rt2661_tx_ring *, int);
94 static void rt2661_reset_tx_ring(struct rt2661_softc *,
95 struct rt2661_tx_ring *);
96 static void rt2661_free_tx_ring(struct rt2661_softc *,
97 struct rt2661_tx_ring *);
98 static int rt2661_alloc_rx_ring(struct rt2661_softc *,
99 struct rt2661_rx_ring *, int);
100 static void rt2661_reset_rx_ring(struct rt2661_softc *,
101 struct rt2661_rx_ring *);
102 static void rt2661_free_rx_ring(struct rt2661_softc *,
103 struct rt2661_rx_ring *);
104 static struct ieee80211_node *rt2661_node_alloc(
105 struct ieee80211_node_table *);
106 static void rt2661_newassoc(struct ieee80211_node *, int);
107 static int rt2661_newstate(struct ieee80211vap *,
108 enum ieee80211_state, int);
109 static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t);
110 static void rt2661_rx_intr(struct rt2661_softc *);
111 static void rt2661_tx_intr(struct rt2661_softc *);
112 static void rt2661_tx_dma_intr(struct rt2661_softc *,
113 struct rt2661_tx_ring *);
114 static void rt2661_mcu_beacon_expire(struct rt2661_softc *);
115 static void rt2661_mcu_wakeup(struct rt2661_softc *);
116 static void rt2661_mcu_cmd_intr(struct rt2661_softc *);
117 static void rt2661_scan_start(struct ieee80211com *);
118 static void rt2661_scan_end(struct ieee80211com *);
119 static void rt2661_set_channel(struct ieee80211com *);
120 static void rt2661_setup_tx_desc(struct rt2661_softc *,
121 struct rt2661_tx_desc *, uint32_t, uint16_t, int,
122 int, const bus_dma_segment_t *, int, int);
123 static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *,
124 struct ieee80211_node *, int);
125 static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *,
126 struct ieee80211_node *);
127 static void rt2661_start_locked(struct ifnet *);
128 static void rt2661_start(struct ifnet *);
129 static int rt2661_raw_xmit(struct ieee80211_node *, struct mbuf *,
130 const struct ieee80211_bpf_params *);
131 static void rt2661_watchdog(void *);
132 static int rt2661_ioctl(struct ifnet *, u_long, caddr_t);
133 static void rt2661_bbp_write(struct rt2661_softc *, uint8_t,
135 static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t);
136 static void rt2661_rf_write(struct rt2661_softc *, uint8_t,
138 static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t,
140 static void rt2661_select_antenna(struct rt2661_softc *);
141 static void rt2661_enable_mrr(struct rt2661_softc *);
142 static void rt2661_set_txpreamble(struct rt2661_softc *);
143 static void rt2661_set_basicrates(struct rt2661_softc *,
144 const struct ieee80211_rateset *);
145 static void rt2661_select_band(struct rt2661_softc *,
146 struct ieee80211_channel *);
147 static void rt2661_set_chan(struct rt2661_softc *,
148 struct ieee80211_channel *);
149 static void rt2661_set_bssid(struct rt2661_softc *,
151 static void rt2661_set_macaddr(struct rt2661_softc *,
153 static void rt2661_update_promisc(struct ifnet *);
154 static int rt2661_wme_update(struct ieee80211com *) __unused;
155 static void rt2661_update_slot(struct ifnet *);
156 static const char *rt2661_get_rf(int);
157 static void rt2661_read_eeprom(struct rt2661_softc *,
158 struct ieee80211com *);
159 static int rt2661_bbp_init(struct rt2661_softc *);
160 static void rt2661_init_locked(struct rt2661_softc *);
161 static void rt2661_init(void *);
162 static void rt2661_stop_locked(struct rt2661_softc *);
163 static void rt2661_stop(void *);
164 static int rt2661_load_microcode(struct rt2661_softc *);
166 static void rt2661_rx_tune(struct rt2661_softc *);
167 static void rt2661_radar_start(struct rt2661_softc *);
168 static int rt2661_radar_stop(struct rt2661_softc *);
170 static int rt2661_prepare_beacon(struct rt2661_softc *,
171 struct ieee80211vap *);
172 static void rt2661_enable_tsf_sync(struct rt2661_softc *);
173 static int rt2661_get_rssi(struct rt2661_softc *, uint8_t);
175 static const struct {
178 } rt2661_def_mac[] = {
182 static const struct {
185 } rt2661_def_bbp[] = {
189 static const struct rfprog {
191 uint32_t r1, r2, r3, r4;
192 } rt2661_rf5225_1[] = {
194 }, rt2661_rf5225_2[] = {
199 rt2661_attach(device_t dev, int id)
201 struct rt2661_softc *sc = device_get_softc(dev);
202 struct ieee80211com *ic;
205 int error, ac, ntries;
211 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
213 device_printf(sc->sc_dev, "can not if_alloc()\n");
218 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
219 MTX_DEF | MTX_RECURSE);
221 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0);
223 /* wait for NIC to initialize */
224 for (ntries = 0; ntries < 1000; ntries++) {
225 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0)
229 if (ntries == 1000) {
230 device_printf(sc->sc_dev,
231 "timeout waiting for NIC to initialize\n");
236 /* retrieve RF rev. no and various other things from EEPROM */
237 rt2661_read_eeprom(sc, ic);
239 device_printf(dev, "MAC/BBP RT%X, RF %s\n", val,
240 rt2661_get_rf(sc->rf_rev));
243 * Allocate Tx and Rx rings.
245 for (ac = 0; ac < 4; ac++) {
246 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac],
247 RT2661_TX_RING_COUNT);
249 device_printf(sc->sc_dev,
250 "could not allocate Tx ring %d\n", ac);
255 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT);
257 device_printf(sc->sc_dev, "could not allocate Mgt ring\n");
261 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT);
263 device_printf(sc->sc_dev, "could not allocate Rx ring\n");
268 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
269 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
270 ifp->if_init = rt2661_init;
271 ifp->if_ioctl = rt2661_ioctl;
272 ifp->if_start = rt2661_start;
273 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
274 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
275 IFQ_SET_READY(&ifp->if_snd);
278 ic->ic_opmode = IEEE80211_M_STA;
279 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
281 /* set device capabilities */
283 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
284 | IEEE80211_C_HOSTAP /* hostap mode */
285 | IEEE80211_C_MONITOR /* monitor mode */
286 | IEEE80211_C_AHDEMO /* adhoc demo mode */
287 | IEEE80211_C_WDS /* 4-address traffic works */
288 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
289 | IEEE80211_C_SHSLOT /* short slot time supported */
290 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
291 | IEEE80211_C_BGSCAN /* capable of bg scanning */
293 | IEEE80211_C_TXFRAG /* handle tx frags */
294 | IEEE80211_C_WME /* 802.11e */
299 setbit(&bands, IEEE80211_MODE_11B);
300 setbit(&bands, IEEE80211_MODE_11G);
301 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325)
302 setbit(&bands, IEEE80211_MODE_11A);
303 ieee80211_init_channels(ic, NULL, &bands);
305 ieee80211_ifattach(ic);
306 ic->ic_newassoc = rt2661_newassoc;
307 ic->ic_node_alloc = rt2661_node_alloc;
309 ic->ic_wme.wme_update = rt2661_wme_update;
311 ic->ic_scan_start = rt2661_scan_start;
312 ic->ic_scan_end = rt2661_scan_end;
313 ic->ic_set_channel = rt2661_set_channel;
314 ic->ic_updateslot = rt2661_update_slot;
315 ic->ic_update_promisc = rt2661_update_promisc;
316 ic->ic_raw_xmit = rt2661_raw_xmit;
318 ic->ic_vap_create = rt2661_vap_create;
319 ic->ic_vap_delete = rt2661_vap_delete;
321 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan);
323 bpfattach(ifp, DLT_IEEE802_11_RADIO,
324 sizeof (struct ieee80211_frame) + sizeof (sc->sc_txtap));
326 sc->sc_rxtap_len = sizeof sc->sc_rxtap;
327 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len);
328 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2661_RX_RADIOTAP_PRESENT);
330 sc->sc_txtap_len = sizeof sc->sc_txtap;
331 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len);
332 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2661_TX_RADIOTAP_PRESENT);
335 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
336 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
337 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs");
340 ieee80211_announce(ic);
344 fail3: rt2661_free_tx_ring(sc, &sc->mgtq);
345 fail2: while (--ac >= 0)
346 rt2661_free_tx_ring(sc, &sc->txq[ac]);
347 fail1: mtx_destroy(&sc->sc_mtx);
353 rt2661_detach(void *xsc)
355 struct rt2661_softc *sc = xsc;
356 struct ifnet *ifp = sc->sc_ifp;
357 struct ieee80211com *ic = ifp->if_l2com;
360 rt2661_stop_locked(sc);
364 ieee80211_ifdetach(ic);
366 rt2661_free_tx_ring(sc, &sc->txq[0]);
367 rt2661_free_tx_ring(sc, &sc->txq[1]);
368 rt2661_free_tx_ring(sc, &sc->txq[2]);
369 rt2661_free_tx_ring(sc, &sc->txq[3]);
370 rt2661_free_tx_ring(sc, &sc->mgtq);
371 rt2661_free_rx_ring(sc, &sc->rxq);
375 mtx_destroy(&sc->sc_mtx);
380 static struct ieee80211vap *
381 rt2661_vap_create(struct ieee80211com *ic,
382 const char name[IFNAMSIZ], int unit, int opmode, int flags,
383 const uint8_t bssid[IEEE80211_ADDR_LEN],
384 const uint8_t mac[IEEE80211_ADDR_LEN])
386 struct ifnet *ifp = ic->ic_ifp;
387 struct rt2661_vap *rvp;
388 struct ieee80211vap *vap;
391 case IEEE80211_M_STA:
392 case IEEE80211_M_IBSS:
393 case IEEE80211_M_AHDEMO:
394 case IEEE80211_M_MONITOR:
395 case IEEE80211_M_HOSTAP:
396 if (!TAILQ_EMPTY(&ic->ic_vaps)) {
397 if_printf(ifp, "only 1 vap supported\n");
400 if (opmode == IEEE80211_M_STA)
401 flags |= IEEE80211_CLONE_NOBEACONS;
403 case IEEE80211_M_WDS:
404 if (TAILQ_EMPTY(&ic->ic_vaps) ||
405 ic->ic_opmode != IEEE80211_M_HOSTAP) {
406 if_printf(ifp, "wds only supported in ap mode\n");
410 * Silently remove any request for a unique
411 * bssid; WDS vap's always share the local
414 flags &= ~IEEE80211_CLONE_BSSID;
417 if_printf(ifp, "unknown opmode %d\n", opmode);
420 rvp = (struct rt2661_vap *) malloc(sizeof(struct rt2661_vap),
421 M_80211_VAP, M_NOWAIT | M_ZERO);
425 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac);
427 /* override state transition machine */
428 rvp->ral_newstate = vap->iv_newstate;
429 vap->iv_newstate = rt2661_newstate;
431 vap->iv_update_beacon = rt2661_beacon_update;
434 ieee80211_amrr_init(&rvp->amrr, vap,
435 IEEE80211_AMRR_MIN_SUCCESS_THRESHOLD,
436 IEEE80211_AMRR_MAX_SUCCESS_THRESHOLD,
440 ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status);
441 if (TAILQ_FIRST(&ic->ic_vaps) == vap)
442 ic->ic_opmode = opmode;
447 rt2661_vap_delete(struct ieee80211vap *vap)
449 struct rt2661_vap *rvp = RT2661_VAP(vap);
451 ieee80211_amrr_cleanup(&rvp->amrr);
452 ieee80211_vap_detach(vap);
453 free(rvp, M_80211_VAP);
457 rt2661_shutdown(void *xsc)
459 struct rt2661_softc *sc = xsc;
465 rt2661_suspend(void *xsc)
467 struct rt2661_softc *sc = xsc;
473 rt2661_resume(void *xsc)
475 struct rt2661_softc *sc = xsc;
476 struct ifnet *ifp = sc->sc_ifp;
478 if (ifp->if_flags & IFF_UP)
483 rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
488 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
490 *(bus_addr_t *)arg = segs[0].ds_addr;
494 rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring,
501 ring->cur = ring->next = ring->stat = 0;
503 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0,
504 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
505 count * RT2661_TX_DESC_SIZE, 1, count * RT2661_TX_DESC_SIZE,
506 0, NULL, NULL, &ring->desc_dmat);
508 device_printf(sc->sc_dev, "could not create desc DMA tag\n");
512 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc,
513 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map);
515 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
519 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc,
520 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr,
523 device_printf(sc->sc_dev, "could not load desc DMA map\n");
527 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF,
529 if (ring->data == NULL) {
530 device_printf(sc->sc_dev, "could not allocate soft data\n");
535 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
536 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
537 RT2661_MAX_SCATTER, MCLBYTES, 0, NULL, NULL, &ring->data_dmat);
539 device_printf(sc->sc_dev, "could not create data DMA tag\n");
543 for (i = 0; i < count; i++) {
544 error = bus_dmamap_create(ring->data_dmat, 0,
547 device_printf(sc->sc_dev, "could not create DMA map\n");
554 fail: rt2661_free_tx_ring(sc, ring);
559 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring)
561 struct rt2661_tx_desc *desc;
562 struct rt2661_tx_data *data;
565 for (i = 0; i < ring->count; i++) {
566 desc = &ring->desc[i];
567 data = &ring->data[i];
569 if (data->m != NULL) {
570 bus_dmamap_sync(ring->data_dmat, data->map,
571 BUS_DMASYNC_POSTWRITE);
572 bus_dmamap_unload(ring->data_dmat, data->map);
577 if (data->ni != NULL) {
578 ieee80211_free_node(data->ni);
585 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
588 ring->cur = ring->next = ring->stat = 0;
592 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring)
594 struct rt2661_tx_data *data;
597 if (ring->desc != NULL) {
598 bus_dmamap_sync(ring->desc_dmat, ring->desc_map,
599 BUS_DMASYNC_POSTWRITE);
600 bus_dmamap_unload(ring->desc_dmat, ring->desc_map);
601 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map);
604 if (ring->desc_dmat != NULL)
605 bus_dma_tag_destroy(ring->desc_dmat);
607 if (ring->data != NULL) {
608 for (i = 0; i < ring->count; i++) {
609 data = &ring->data[i];
611 if (data->m != NULL) {
612 bus_dmamap_sync(ring->data_dmat, data->map,
613 BUS_DMASYNC_POSTWRITE);
614 bus_dmamap_unload(ring->data_dmat, data->map);
618 if (data->ni != NULL)
619 ieee80211_free_node(data->ni);
621 if (data->map != NULL)
622 bus_dmamap_destroy(ring->data_dmat, data->map);
625 free(ring->data, M_DEVBUF);
628 if (ring->data_dmat != NULL)
629 bus_dma_tag_destroy(ring->data_dmat);
633 rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring,
636 struct rt2661_rx_desc *desc;
637 struct rt2661_rx_data *data;
642 ring->cur = ring->next = 0;
644 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0,
645 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
646 count * RT2661_RX_DESC_SIZE, 1, count * RT2661_RX_DESC_SIZE,
647 0, NULL, NULL, &ring->desc_dmat);
649 device_printf(sc->sc_dev, "could not create desc DMA tag\n");
653 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc,
654 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map);
656 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
660 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc,
661 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr,
664 device_printf(sc->sc_dev, "could not load desc DMA map\n");
668 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF,
670 if (ring->data == NULL) {
671 device_printf(sc->sc_dev, "could not allocate soft data\n");
677 * Pre-allocate Rx buffers and populate Rx ring.
679 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
680 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
681 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat);
683 device_printf(sc->sc_dev, "could not create data DMA tag\n");
687 for (i = 0; i < count; i++) {
688 desc = &sc->rxq.desc[i];
689 data = &sc->rxq.data[i];
691 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
693 device_printf(sc->sc_dev, "could not create DMA map\n");
697 data->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
698 if (data->m == NULL) {
699 device_printf(sc->sc_dev,
700 "could not allocate rx mbuf\n");
705 error = bus_dmamap_load(ring->data_dmat, data->map,
706 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr,
709 device_printf(sc->sc_dev,
710 "could not load rx buf DMA map");
714 desc->flags = htole32(RT2661_RX_BUSY);
715 desc->physaddr = htole32(physaddr);
718 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
722 fail: rt2661_free_rx_ring(sc, ring);
727 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring)
731 for (i = 0; i < ring->count; i++)
732 ring->desc[i].flags = htole32(RT2661_RX_BUSY);
734 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
736 ring->cur = ring->next = 0;
740 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring)
742 struct rt2661_rx_data *data;
745 if (ring->desc != NULL) {
746 bus_dmamap_sync(ring->desc_dmat, ring->desc_map,
747 BUS_DMASYNC_POSTWRITE);
748 bus_dmamap_unload(ring->desc_dmat, ring->desc_map);
749 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map);
752 if (ring->desc_dmat != NULL)
753 bus_dma_tag_destroy(ring->desc_dmat);
755 if (ring->data != NULL) {
756 for (i = 0; i < ring->count; i++) {
757 data = &ring->data[i];
759 if (data->m != NULL) {
760 bus_dmamap_sync(ring->data_dmat, data->map,
761 BUS_DMASYNC_POSTREAD);
762 bus_dmamap_unload(ring->data_dmat, data->map);
766 if (data->map != NULL)
767 bus_dmamap_destroy(ring->data_dmat, data->map);
770 free(ring->data, M_DEVBUF);
773 if (ring->data_dmat != NULL)
774 bus_dma_tag_destroy(ring->data_dmat);
777 static struct ieee80211_node *
778 rt2661_node_alloc(struct ieee80211_node_table *nt)
780 struct rt2661_node *rn;
782 rn = malloc(sizeof (struct rt2661_node), M_80211_NODE,
785 return (rn != NULL) ? &rn->ni : NULL;
789 rt2661_newassoc(struct ieee80211_node *ni, int isnew)
791 struct ieee80211vap *vap = ni->ni_vap;
793 ieee80211_amrr_node_init(&RT2661_VAP(vap)->amrr,
794 &RT2661_NODE(ni)->amrr, ni);
798 rt2661_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
800 struct rt2661_vap *rvp = RT2661_VAP(vap);
801 struct ieee80211com *ic = vap->iv_ic;
802 struct rt2661_softc *sc = ic->ic_ifp->if_softc;
805 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) {
808 /* abort TSF synchronization */
809 tmp = RAL_READ(sc, RT2661_TXRX_CSR9);
810 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff);
813 error = rvp->ral_newstate(vap, nstate, arg);
815 if (error == 0 && nstate == IEEE80211_S_RUN) {
816 struct ieee80211_node *ni = vap->iv_bss;
818 if (vap->iv_opmode != IEEE80211_M_MONITOR) {
819 rt2661_enable_mrr(sc);
820 rt2661_set_txpreamble(sc);
821 rt2661_set_basicrates(sc, &ni->ni_rates);
822 rt2661_set_bssid(sc, ni->ni_bssid);
825 if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
826 vap->iv_opmode == IEEE80211_M_IBSS) {
827 error = rt2661_prepare_beacon(sc, vap);
831 if (vap->iv_opmode != IEEE80211_M_MONITOR) {
832 if (vap->iv_opmode == IEEE80211_M_STA) {
833 /* fake a join to init the tx rate */
834 rt2661_newassoc(ni, 1);
836 rt2661_enable_tsf_sync(sc);
843 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or
847 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr)
853 /* clock C once before the first command */
854 RT2661_EEPROM_CTL(sc, 0);
856 RT2661_EEPROM_CTL(sc, RT2661_S);
857 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
858 RT2661_EEPROM_CTL(sc, RT2661_S);
860 /* write start bit (1) */
861 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D);
862 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C);
864 /* write READ opcode (10) */
865 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D);
866 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C);
867 RT2661_EEPROM_CTL(sc, RT2661_S);
868 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
870 /* write address (A5-A0 or A7-A0) */
871 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7;
872 for (; n >= 0; n--) {
873 RT2661_EEPROM_CTL(sc, RT2661_S |
874 (((addr >> n) & 1) << RT2661_SHIFT_D));
875 RT2661_EEPROM_CTL(sc, RT2661_S |
876 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C);
879 RT2661_EEPROM_CTL(sc, RT2661_S);
881 /* read data Q15-Q0 */
883 for (n = 15; n >= 0; n--) {
884 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
885 tmp = RAL_READ(sc, RT2661_E2PROM_CSR);
886 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n;
887 RT2661_EEPROM_CTL(sc, RT2661_S);
890 RT2661_EEPROM_CTL(sc, 0);
892 /* clear Chip Select and clock C */
893 RT2661_EEPROM_CTL(sc, RT2661_S);
894 RT2661_EEPROM_CTL(sc, 0);
895 RT2661_EEPROM_CTL(sc, RT2661_C);
901 rt2661_tx_intr(struct rt2661_softc *sc)
903 struct ifnet *ifp = sc->sc_ifp;
904 struct rt2661_tx_ring *txq;
905 struct rt2661_tx_data *data;
906 struct rt2661_node *rn;
911 struct ieee80211_node *ni;
914 val = RAL_READ(sc, RT2661_STA_CSR4);
915 if (!(val & RT2661_TX_STAT_VALID))
918 /* retrieve the queue in which this frame was sent */
919 qid = RT2661_TX_QID(val);
920 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq;
922 /* retrieve rate control algorithm context */
923 data = &txq->data[txq->stat];
929 /* if no frame has been sent, ignore */
933 rn = RT2661_NODE(ni);
935 switch (RT2661_TX_RESULT(val)) {
936 case RT2661_TX_SUCCESS:
937 retrycnt = RT2661_TX_RETRYCNT(val);
939 DPRINTFN(sc, 10, "data frame sent successfully after "
940 "%d retries\n", retrycnt);
941 if (data->rix != IEEE80211_FIXED_RATE_NONE)
942 ieee80211_amrr_tx_complete(&rn->amrr,
943 IEEE80211_AMRR_SUCCESS, retrycnt);
947 case RT2661_TX_RETRY_FAIL:
948 retrycnt = RT2661_TX_RETRYCNT(val);
950 DPRINTFN(sc, 9, "%s\n",
951 "sending data frame failed (too much retries)");
952 if (data->rix != IEEE80211_FIXED_RATE_NONE)
953 ieee80211_amrr_tx_complete(&rn->amrr,
954 IEEE80211_AMRR_FAILURE, retrycnt);
960 device_printf(sc->sc_dev,
961 "sending data frame failed 0x%08x\n", val);
965 DPRINTFN(sc, 15, "tx done q=%d idx=%u\n", qid, txq->stat);
968 if (++txq->stat >= txq->count) /* faster than % count */
971 if (m->m_flags & M_TXCB)
972 ieee80211_process_callback(ni, m,
973 RT2661_TX_RESULT(val) != RT2661_TX_SUCCESS);
975 ieee80211_free_node(ni);
979 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
981 rt2661_start_locked(ifp);
985 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq)
987 struct rt2661_tx_desc *desc;
988 struct rt2661_tx_data *data;
990 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD);
993 desc = &txq->desc[txq->next];
994 data = &txq->data[txq->next];
996 if ((le32toh(desc->flags) & RT2661_TX_BUSY) ||
997 !(le32toh(desc->flags) & RT2661_TX_VALID))
1000 bus_dmamap_sync(txq->data_dmat, data->map,
1001 BUS_DMASYNC_POSTWRITE);
1002 bus_dmamap_unload(txq->data_dmat, data->map);
1004 /* descriptor is no longer valid */
1005 desc->flags &= ~htole32(RT2661_TX_VALID);
1007 DPRINTFN(sc, 15, "tx dma done q=%p idx=%u\n", txq, txq->next);
1009 if (++txq->next >= txq->count) /* faster than % count */
1013 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
1017 rt2661_rx_intr(struct rt2661_softc *sc)
1019 struct ifnet *ifp = sc->sc_ifp;
1020 struct ieee80211com *ic = ifp->if_l2com;
1021 struct rt2661_rx_desc *desc;
1022 struct rt2661_rx_data *data;
1023 bus_addr_t physaddr;
1024 struct ieee80211_frame *wh;
1025 struct ieee80211_node *ni;
1026 struct mbuf *mnew, *m;
1029 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
1030 BUS_DMASYNC_POSTREAD);
1035 desc = &sc->rxq.desc[sc->rxq.cur];
1036 data = &sc->rxq.data[sc->rxq.cur];
1038 if (le32toh(desc->flags) & RT2661_RX_BUSY)
1041 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) ||
1042 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) {
1044 * This should not happen since we did not request
1045 * to receive those frames when we filled TXRX_CSR0.
1047 DPRINTFN(sc, 5, "PHY or CRC error flags 0x%08x\n",
1048 le32toh(desc->flags));
1053 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) {
1059 * Try to allocate a new mbuf for this ring element and load it
1060 * before processing the current mbuf. If the ring element
1061 * cannot be loaded, drop the received packet and reuse the old
1062 * mbuf. In the unlikely case that the old mbuf can't be
1063 * reloaded either, explicitly panic.
1065 mnew = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1071 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
1072 BUS_DMASYNC_POSTREAD);
1073 bus_dmamap_unload(sc->rxq.data_dmat, data->map);
1075 error = bus_dmamap_load(sc->rxq.data_dmat, data->map,
1076 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr,
1081 /* try to reload the old mbuf */
1082 error = bus_dmamap_load(sc->rxq.data_dmat, data->map,
1083 mtod(data->m, void *), MCLBYTES,
1084 rt2661_dma_map_addr, &physaddr, 0);
1086 /* very unlikely that it will fail... */
1087 panic("%s: could not load old rx mbuf",
1088 device_get_name(sc->sc_dev));
1095 * New mbuf successfully loaded, update Rx ring and continue
1100 desc->physaddr = htole32(physaddr);
1103 m->m_pkthdr.rcvif = ifp;
1104 m->m_pkthdr.len = m->m_len =
1105 (le32toh(desc->flags) >> 16) & 0xfff;
1107 rssi = rt2661_get_rssi(sc, desc->rssi);
1109 if (bpf_peers_present(ifp->if_bpf)) {
1110 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap;
1111 uint32_t tsf_lo, tsf_hi;
1113 /* get timestamp (low and high 32 bits) */
1114 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13);
1115 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12);
1118 htole64(((uint64_t)tsf_hi << 32) | tsf_lo);
1120 tap->wr_rate = ieee80211_plcp2rate(desc->rate,
1121 le32toh(desc->flags) & RT2661_RX_OFDM);
1122 tap->wr_antsignal = rssi < 0 ? 0 : rssi;
1124 bpf_mtap2(ifp->if_bpf, tap, sc->sc_rxtap_len, m);
1126 sc->sc_flags |= RAL_INPUT_RUNNING;
1128 wh = mtod(m, struct ieee80211_frame *);
1130 /* send the frame to the 802.11 layer */
1131 ni = ieee80211_find_rxnode(ic,
1132 (struct ieee80211_frame_min *)wh);
1134 /* Error happened during RSSI conversion. */
1136 rssi = -30; /* XXX ignored by net80211 */
1138 (void) ieee80211_input(ni, m, rssi,
1139 RT2661_NOISE_FLOOR, 0);
1140 ieee80211_free_node(ni);
1142 (void) ieee80211_input_all(ic, m, rssi,
1143 RT2661_NOISE_FLOOR, 0);
1146 sc->sc_flags &= ~RAL_INPUT_RUNNING;
1148 skip: desc->flags |= htole32(RT2661_RX_BUSY);
1150 DPRINTFN(sc, 15, "rx intr idx=%u\n", sc->rxq.cur);
1152 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT;
1155 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
1156 BUS_DMASYNC_PREWRITE);
1161 rt2661_mcu_beacon_expire(struct rt2661_softc *sc)
1167 rt2661_mcu_wakeup(struct rt2661_softc *sc)
1169 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16);
1171 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7);
1172 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18);
1173 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20);
1175 /* send wakeup command to MCU */
1176 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0);
1180 rt2661_mcu_cmd_intr(struct rt2661_softc *sc)
1182 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR);
1183 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff);
1187 rt2661_intr(void *arg)
1189 struct rt2661_softc *sc = arg;
1190 struct ifnet *ifp = sc->sc_ifp;
1195 /* disable MAC and MCU interrupts */
1196 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f);
1197 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
1199 /* don't re-enable interrupts if we're shutting down */
1200 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1205 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR);
1206 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1);
1208 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR);
1209 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2);
1211 if (r1 & RT2661_MGT_DONE)
1212 rt2661_tx_dma_intr(sc, &sc->mgtq);
1214 if (r1 & RT2661_RX_DONE)
1217 if (r1 & RT2661_TX0_DMA_DONE)
1218 rt2661_tx_dma_intr(sc, &sc->txq[0]);
1220 if (r1 & RT2661_TX1_DMA_DONE)
1221 rt2661_tx_dma_intr(sc, &sc->txq[1]);
1223 if (r1 & RT2661_TX2_DMA_DONE)
1224 rt2661_tx_dma_intr(sc, &sc->txq[2]);
1226 if (r1 & RT2661_TX3_DMA_DONE)
1227 rt2661_tx_dma_intr(sc, &sc->txq[3]);
1229 if (r1 & RT2661_TX_DONE)
1232 if (r2 & RT2661_MCU_CMD_DONE)
1233 rt2661_mcu_cmd_intr(sc);
1235 if (r2 & RT2661_MCU_BEACON_EXPIRE)
1236 rt2661_mcu_beacon_expire(sc);
1238 if (r2 & RT2661_MCU_WAKEUP)
1239 rt2661_mcu_wakeup(sc);
1241 /* re-enable MAC and MCU interrupts */
1242 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10);
1243 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0);
1249 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc,
1250 uint32_t flags, uint16_t xflags, int len, int rate,
1251 const bus_dma_segment_t *segs, int nsegs, int ac)
1253 struct ifnet *ifp = sc->sc_ifp;
1254 struct ieee80211com *ic = ifp->if_l2com;
1255 uint16_t plcp_length;
1258 desc->flags = htole32(flags);
1259 desc->flags |= htole32(len << 16);
1260 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID);
1262 desc->xflags = htole16(xflags);
1263 desc->xflags |= htole16(nsegs << 13);
1265 desc->wme = htole16(
1268 RT2661_LOGCWMIN(4) |
1269 RT2661_LOGCWMAX(10));
1272 * Remember in which queue this frame was sent. This field is driver
1273 * private data only. It will be made available by the NIC in STA_CSR4
1278 /* setup PLCP fields */
1279 desc->plcp_signal = ieee80211_rate2plcp(rate);
1280 desc->plcp_service = 4;
1282 len += IEEE80211_CRC_LEN;
1283 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) {
1284 desc->flags |= htole32(RT2661_TX_OFDM);
1286 plcp_length = len & 0xfff;
1287 desc->plcp_length_hi = plcp_length >> 6;
1288 desc->plcp_length_lo = plcp_length & 0x3f;
1290 plcp_length = (16 * len + rate - 1) / rate;
1292 remainder = (16 * len) % 22;
1293 if (remainder != 0 && remainder < 7)
1294 desc->plcp_service |= RT2661_PLCP_LENGEXT;
1296 desc->plcp_length_hi = plcp_length >> 8;
1297 desc->plcp_length_lo = plcp_length & 0xff;
1299 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1300 desc->plcp_signal |= 0x08;
1303 /* RT2x61 supports scatter with up to 5 segments */
1304 for (i = 0; i < nsegs; i++) {
1305 desc->addr[i] = htole32(segs[i].ds_addr);
1306 desc->len [i] = htole16(segs[i].ds_len);
1311 rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0,
1312 struct ieee80211_node *ni)
1314 struct ieee80211vap *vap = ni->ni_vap;
1315 struct ieee80211com *ic = ni->ni_ic;
1316 struct ifnet *ifp = sc->sc_ifp;
1317 struct rt2661_tx_desc *desc;
1318 struct rt2661_tx_data *data;
1319 struct ieee80211_frame *wh;
1320 struct ieee80211_key *k;
1321 bus_dma_segment_t segs[RT2661_MAX_SCATTER];
1323 uint32_t flags = 0; /* XXX HWSEQ */
1324 int nsegs, rate, error;
1326 desc = &sc->mgtq.desc[sc->mgtq.cur];
1327 data = &sc->mgtq.data[sc->mgtq.cur];
1329 rate = vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)].mgmtrate;
1331 wh = mtod(m0, struct ieee80211_frame *);
1333 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1334 k = ieee80211_crypto_encap(ni, m0);
1341 error = bus_dmamap_load_mbuf_sg(sc->mgtq.data_dmat, data->map, m0,
1344 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n",
1350 if (bpf_peers_present(ifp->if_bpf)) {
1351 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap;
1354 tap->wt_rate = rate;
1356 bpf_mtap2(ifp->if_bpf, tap, sc->sc_txtap_len, m0);
1361 /* management frames are not taken into account for amrr */
1362 data->rix = IEEE80211_FIXED_RATE_NONE;
1364 wh = mtod(m0, struct ieee80211_frame *);
1366 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1367 flags |= RT2661_TX_NEED_ACK;
1369 dur = ieee80211_ack_duration(sc->sc_rates,
1370 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE);
1371 *(uint16_t *)wh->i_dur = htole16(dur);
1373 /* tell hardware to add timestamp in probe responses */
1375 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
1376 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP))
1377 flags |= RT2661_TX_TIMESTAMP;
1380 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */,
1381 m0->m_pkthdr.len, rate, segs, nsegs, RT2661_QID_MGT);
1383 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1384 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map,
1385 BUS_DMASYNC_PREWRITE);
1387 DPRINTFN(sc, 10, "sending mgt frame len=%u idx=%u rate=%u\n",
1388 m0->m_pkthdr.len, sc->mgtq.cur, rate);
1392 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT;
1393 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT);
1399 rt2661_sendprot(struct rt2661_softc *sc, int ac,
1400 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate)
1402 struct ieee80211com *ic = ni->ni_ic;
1403 struct rt2661_tx_ring *txq = &sc->txq[ac];
1404 const struct ieee80211_frame *wh;
1405 struct rt2661_tx_desc *desc;
1406 struct rt2661_tx_data *data;
1408 int protrate, ackrate, pktlen, flags, isshort, error;
1410 bus_dma_segment_t segs[RT2661_MAX_SCATTER];
1413 KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY,
1414 ("protection %d", prot));
1416 wh = mtod(m, const struct ieee80211_frame *);
1417 pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN;
1419 protrate = ieee80211_ctl_rate(sc->sc_rates, rate);
1420 ackrate = ieee80211_ack_rate(sc->sc_rates, rate);
1422 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0;
1423 dur = ieee80211_compute_duration(sc->sc_rates, pktlen, rate, isshort);
1424 + ieee80211_ack_duration(sc->sc_rates, rate, isshort);
1425 flags = RT2661_TX_MORE_FRAG;
1426 if (prot == IEEE80211_PROT_RTSCTS) {
1427 /* NB: CTS is the same size as an ACK */
1428 dur += ieee80211_ack_duration(sc->sc_rates, rate, isshort);
1429 flags |= RT2661_TX_NEED_ACK;
1430 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur);
1432 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur);
1434 if (mprot == NULL) {
1435 /* XXX stat + msg */
1439 data = &txq->data[txq->cur];
1440 desc = &txq->desc[txq->cur];
1442 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, mprot, segs,
1445 device_printf(sc->sc_dev,
1446 "could not map mbuf (error %d)\n", error);
1452 data->ni = ieee80211_ref_node(ni);
1453 /* ctl frames are not taken into account for amrr */
1454 data->rix = IEEE80211_FIXED_RATE_NONE;
1456 rt2661_setup_tx_desc(sc, desc, flags, 0, mprot->m_pkthdr.len,
1457 protrate, segs, 1, ac);
1459 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1460 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
1463 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT;
1469 rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0,
1470 struct ieee80211_node *ni, int ac)
1472 struct ieee80211vap *vap = ni->ni_vap;
1473 struct ifnet *ifp = sc->sc_ifp;
1474 struct ieee80211com *ic = ifp->if_l2com;
1475 struct rt2661_tx_ring *txq = &sc->txq[ac];
1476 struct rt2661_tx_desc *desc;
1477 struct rt2661_tx_data *data;
1478 struct ieee80211_frame *wh;
1479 const struct ieee80211_txparam *tp;
1480 struct ieee80211_key *k;
1481 const struct chanAccParams *cap;
1483 bus_dma_segment_t segs[RT2661_MAX_SCATTER];
1486 int error, nsegs, rate, noack = 0;
1488 wh = mtod(m0, struct ieee80211_frame *);
1490 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)];
1491 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1492 rate = tp->mcastrate;
1493 } else if (m0->m_flags & M_EAPOL) {
1494 rate = tp->mgmtrate;
1495 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) {
1496 rate = tp->ucastrate;
1498 (void) ieee80211_amrr_choose(ni, &RT2661_NODE(ni)->amrr);
1499 rate = ni->ni_txrate;
1501 rate &= IEEE80211_RATE_VAL;
1503 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) {
1504 cap = &ic->ic_wme.wme_chanParams;
1505 noack = cap->cap_wmeParams[ac].wmep_noackPolicy;
1508 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1509 k = ieee80211_crypto_encap(ni, m0);
1515 /* packet header may have moved, reset our local pointer */
1516 wh = mtod(m0, struct ieee80211_frame *);
1520 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1521 int prot = IEEE80211_PROT_NONE;
1522 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold)
1523 prot = IEEE80211_PROT_RTSCTS;
1524 else if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
1525 ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM)
1526 prot = ic->ic_protmode;
1527 if (prot != IEEE80211_PROT_NONE) {
1528 error = rt2661_sendprot(sc, ac, m0, ni, prot, rate);
1533 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS;
1537 data = &txq->data[txq->cur];
1538 desc = &txq->desc[txq->cur];
1540 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, segs,
1542 if (error != 0 && error != EFBIG) {
1543 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n",
1549 mnew = m_defrag(m0, M_DONTWAIT);
1551 device_printf(sc->sc_dev,
1552 "could not defragment mbuf\n");
1558 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0,
1561 device_printf(sc->sc_dev,
1562 "could not map mbuf (error %d)\n", error);
1567 /* packet header have moved, reset our local pointer */
1568 wh = mtod(m0, struct ieee80211_frame *);
1571 if (bpf_peers_present(ifp->if_bpf)) {
1572 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap;
1575 tap->wt_rate = rate;
1576 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
1577 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
1579 bpf_mtap2(ifp->if_bpf, tap, sc->sc_txtap_len, m0);
1585 /* remember link conditions for rate adaptation algorithm */
1586 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) {
1587 data->rix = ni->ni_txrate;
1588 /* XXX probably need last rssi value and not avg */
1589 data->rssi = ic->ic_node_getrssi(ni);
1591 data->rix = IEEE80211_FIXED_RATE_NONE;
1593 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1594 flags |= RT2661_TX_NEED_ACK;
1596 dur = ieee80211_ack_duration(sc->sc_rates,
1597 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE);
1598 *(uint16_t *)wh->i_dur = htole16(dur);
1601 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, segs,
1604 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1605 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
1607 DPRINTFN(sc, 10, "sending data frame len=%u idx=%u rate=%u\n",
1608 m0->m_pkthdr.len, txq->cur, rate);
1612 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT;
1613 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac);
1619 rt2661_start_locked(struct ifnet *ifp)
1621 struct rt2661_softc *sc = ifp->if_softc;
1623 struct ieee80211_node *ni;
1626 RAL_LOCK_ASSERT(sc);
1628 /* prevent management frames from being sent if we're not ready */
1629 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING) || sc->sc_invalid)
1633 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1637 ac = M_WME_GETAC(m);
1638 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) {
1639 /* there is no place left in this ring */
1640 IFQ_DRV_PREPEND(&ifp->if_snd, m);
1641 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1645 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1646 m = ieee80211_encap(ni, m);
1648 ieee80211_free_node(ni);
1653 if (rt2661_tx_data(sc, m, ni, ac) != 0) {
1654 ieee80211_free_node(ni);
1659 sc->sc_tx_timer = 5;
1664 rt2661_start(struct ifnet *ifp)
1666 struct rt2661_softc *sc = ifp->if_softc;
1669 rt2661_start_locked(ifp);
1674 rt2661_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1675 const struct ieee80211_bpf_params *params)
1677 struct ieee80211com *ic = ni->ni_ic;
1678 struct ifnet *ifp = ic->ic_ifp;
1679 struct rt2661_softc *sc = ifp->if_softc;
1683 /* prevent management frames from being sent if we're not ready */
1684 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1687 ieee80211_free_node(ni);
1690 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) {
1691 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1694 ieee80211_free_node(ni);
1695 return ENOBUFS; /* XXX */
1701 * Legacy path; interpret frame contents to decide
1702 * precisely how to send the frame.
1705 if (rt2661_tx_mgt(sc, m, ni) != 0)
1707 sc->sc_tx_timer = 5;
1714 ieee80211_free_node(ni);
1716 return EIO; /* XXX */
1720 rt2661_watchdog(void *arg)
1722 struct rt2661_softc *sc = (struct rt2661_softc *)arg;
1723 struct ifnet *ifp = sc->sc_ifp;
1725 RAL_LOCK_ASSERT(sc);
1727 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("not running"));
1729 if (sc->sc_invalid) /* card ejected */
1732 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) {
1733 if_printf(ifp, "device timeout\n");
1734 rt2661_init_locked(sc);
1736 /* NB: callout is reset in rt2661_init() */
1739 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc);
1743 rt2661_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1745 struct rt2661_softc *sc = ifp->if_softc;
1746 struct ieee80211com *ic = ifp->if_l2com;
1747 struct ifreq *ifr = (struct ifreq *) data;
1748 int error = 0, startall = 0;
1753 if (ifp->if_flags & IFF_UP) {
1754 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1755 rt2661_init_locked(sc);
1758 rt2661_update_promisc(ifp);
1760 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1761 rt2661_stop_locked(sc);
1765 ieee80211_start_all(ic);
1768 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
1771 error = ether_ioctl(ifp, cmd, data);
1781 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val)
1786 for (ntries = 0; ntries < 100; ntries++) {
1787 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY))
1791 if (ntries == 100) {
1792 device_printf(sc->sc_dev, "could not write to BBP\n");
1796 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val;
1797 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp);
1799 DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val);
1803 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg)
1808 for (ntries = 0; ntries < 100; ntries++) {
1809 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY))
1813 if (ntries == 100) {
1814 device_printf(sc->sc_dev, "could not read from BBP\n");
1818 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8;
1819 RAL_WRITE(sc, RT2661_PHY_CSR3, val);
1821 for (ntries = 0; ntries < 100; ntries++) {
1822 val = RAL_READ(sc, RT2661_PHY_CSR3);
1823 if (!(val & RT2661_BBP_BUSY))
1828 device_printf(sc->sc_dev, "could not read from BBP\n");
1833 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val)
1838 for (ntries = 0; ntries < 100; ntries++) {
1839 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY))
1843 if (ntries == 100) {
1844 device_printf(sc->sc_dev, "could not write to RF\n");
1848 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 |
1850 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp);
1852 /* remember last written value in sc */
1853 sc->rf_regs[reg] = val;
1855 DPRINTFN(sc, 15, "RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff);
1859 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg)
1861 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY)
1862 return EIO; /* there is already a command pending */
1864 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR,
1865 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg);
1867 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd);
1873 rt2661_select_antenna(struct rt2661_softc *sc)
1875 uint8_t bbp4, bbp77;
1878 bbp4 = rt2661_bbp_read(sc, 4);
1879 bbp77 = rt2661_bbp_read(sc, 77);
1883 /* make sure Rx is disabled before switching antenna */
1884 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
1885 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
1887 rt2661_bbp_write(sc, 4, bbp4);
1888 rt2661_bbp_write(sc, 77, bbp77);
1890 /* restore Rx filter */
1891 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
1895 * Enable multi-rate retries for frames sent at OFDM rates.
1896 * In 802.11b/g mode, allow fallback to CCK rates.
1899 rt2661_enable_mrr(struct rt2661_softc *sc)
1901 struct ifnet *ifp = sc->sc_ifp;
1902 struct ieee80211com *ic = ifp->if_l2com;
1905 tmp = RAL_READ(sc, RT2661_TXRX_CSR4);
1907 tmp &= ~RT2661_MRR_CCK_FALLBACK;
1908 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan))
1909 tmp |= RT2661_MRR_CCK_FALLBACK;
1910 tmp |= RT2661_MRR_ENABLED;
1912 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp);
1916 rt2661_set_txpreamble(struct rt2661_softc *sc)
1918 struct ifnet *ifp = sc->sc_ifp;
1919 struct ieee80211com *ic = ifp->if_l2com;
1922 tmp = RAL_READ(sc, RT2661_TXRX_CSR4);
1924 tmp &= ~RT2661_SHORT_PREAMBLE;
1925 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
1926 tmp |= RT2661_SHORT_PREAMBLE;
1928 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp);
1932 rt2661_set_basicrates(struct rt2661_softc *sc,
1933 const struct ieee80211_rateset *rs)
1935 #define RV(r) ((r) & IEEE80211_RATE_VAL)
1936 struct ifnet *ifp = sc->sc_ifp;
1937 struct ieee80211com *ic = ifp->if_l2com;
1942 for (i = 0; i < rs->rs_nrates; i++) {
1943 rate = rs->rs_rates[i];
1945 if (!(rate & IEEE80211_RATE_BASIC))
1949 * Find h/w rate index. We know it exists because the rate
1950 * set has already been negotiated.
1952 for (j = 0; ic->ic_sup_rates[IEEE80211_MODE_11G].rs_rates[j] != RV(rate); j++);
1957 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask);
1959 DPRINTF(sc, "Setting basic rate mask to 0x%x\n", mask);
1964 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference
1968 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c)
1970 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104;
1973 /* update all BBP registers that depend on the band */
1974 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c;
1975 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48;
1976 if (IEEE80211_IS_CHAN_5GHZ(c)) {
1977 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c;
1978 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10;
1980 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) ||
1981 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) {
1982 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10;
1985 rt2661_bbp_write(sc, 17, bbp17);
1986 rt2661_bbp_write(sc, 96, bbp96);
1987 rt2661_bbp_write(sc, 104, bbp104);
1989 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) ||
1990 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) {
1991 rt2661_bbp_write(sc, 75, 0x80);
1992 rt2661_bbp_write(sc, 86, 0x80);
1993 rt2661_bbp_write(sc, 88, 0x80);
1996 rt2661_bbp_write(sc, 35, bbp35);
1997 rt2661_bbp_write(sc, 97, bbp97);
1998 rt2661_bbp_write(sc, 98, bbp98);
2000 tmp = RAL_READ(sc, RT2661_PHY_CSR0);
2001 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ);
2002 if (IEEE80211_IS_CHAN_2GHZ(c))
2003 tmp |= RT2661_PA_PE_2GHZ;
2005 tmp |= RT2661_PA_PE_5GHZ;
2006 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp);
2010 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c)
2012 struct ifnet *ifp = sc->sc_ifp;
2013 struct ieee80211com *ic = ifp->if_l2com;
2014 const struct rfprog *rfprog;
2015 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT;
2019 chan = ieee80211_chan2ieee(ic, c);
2020 KASSERT(chan != 0 && chan != IEEE80211_CHAN_ANY, ("chan 0x%x", chan));
2022 sc->sc_rates = ieee80211_get_ratetable(c);
2024 /* select the appropriate RF settings based on what EEPROM says */
2025 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2;
2027 /* find the settings for this channel (we know it exists) */
2028 for (i = 0; rfprog[i].chan != chan; i++);
2030 power = sc->txpow[i];
2034 } else if (power > 31) {
2035 bbp94 += power - 31;
2040 * If we are switching from the 2GHz band to the 5GHz band or
2041 * vice-versa, BBP registers need to be reprogrammed.
2043 if (c->ic_flags != sc->sc_curchan->ic_flags) {
2044 rt2661_select_band(sc, c);
2045 rt2661_select_antenna(sc);
2049 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1);
2050 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2);
2051 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7);
2052 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10);
2056 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1);
2057 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2);
2058 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1);
2059 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10);
2063 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1);
2064 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2);
2065 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7);
2066 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10);
2068 /* enable smart mode for MIMO-capable RFs */
2069 bbp3 = rt2661_bbp_read(sc, 3);
2071 bbp3 &= ~RT2661_SMART_MODE;
2072 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529)
2073 bbp3 |= RT2661_SMART_MODE;
2075 rt2661_bbp_write(sc, 3, bbp3);
2077 if (bbp94 != RT2661_BBPR94_DEFAULT)
2078 rt2661_bbp_write(sc, 94, bbp94);
2080 /* 5GHz radio needs a 1ms delay here */
2081 if (IEEE80211_IS_CHAN_5GHZ(c))
2086 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid)
2090 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24;
2091 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp);
2093 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16;
2094 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp);
2098 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr)
2102 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24;
2103 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp);
2105 tmp = addr[4] | addr[5] << 8;
2106 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp);
2110 rt2661_update_promisc(struct ifnet *ifp)
2112 struct rt2661_softc *sc = ifp->if_softc;
2115 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
2117 tmp &= ~RT2661_DROP_NOT_TO_ME;
2118 if (!(ifp->if_flags & IFF_PROMISC))
2119 tmp |= RT2661_DROP_NOT_TO_ME;
2121 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2123 DPRINTF(sc, "%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ?
2124 "entering" : "leaving");
2128 * Update QoS (802.11e) settings for each h/w Tx ring.
2131 rt2661_wme_update(struct ieee80211com *ic)
2133 struct rt2661_softc *sc = ic->ic_ifp->if_softc;
2134 const struct wmeParams *wmep;
2136 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams;
2138 /* XXX: not sure about shifts. */
2139 /* XXX: the reference driver plays with AC_VI settings too. */
2142 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0,
2143 wmep[WME_AC_BE].wmep_txopLimit << 16 |
2144 wmep[WME_AC_BK].wmep_txopLimit);
2145 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1,
2146 wmep[WME_AC_VI].wmep_txopLimit << 16 |
2147 wmep[WME_AC_VO].wmep_txopLimit);
2150 RAL_WRITE(sc, RT2661_CWMIN_CSR,
2151 wmep[WME_AC_BE].wmep_logcwmin << 12 |
2152 wmep[WME_AC_BK].wmep_logcwmin << 8 |
2153 wmep[WME_AC_VI].wmep_logcwmin << 4 |
2154 wmep[WME_AC_VO].wmep_logcwmin);
2157 RAL_WRITE(sc, RT2661_CWMAX_CSR,
2158 wmep[WME_AC_BE].wmep_logcwmax << 12 |
2159 wmep[WME_AC_BK].wmep_logcwmax << 8 |
2160 wmep[WME_AC_VI].wmep_logcwmax << 4 |
2161 wmep[WME_AC_VO].wmep_logcwmax);
2164 RAL_WRITE(sc, RT2661_AIFSN_CSR,
2165 wmep[WME_AC_BE].wmep_aifsn << 12 |
2166 wmep[WME_AC_BK].wmep_aifsn << 8 |
2167 wmep[WME_AC_VI].wmep_aifsn << 4 |
2168 wmep[WME_AC_VO].wmep_aifsn);
2174 rt2661_update_slot(struct ifnet *ifp)
2176 struct rt2661_softc *sc = ifp->if_softc;
2177 struct ieee80211com *ic = ifp->if_l2com;
2181 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20;
2183 tmp = RAL_READ(sc, RT2661_MAC_CSR9);
2184 tmp = (tmp & ~0xff) | slottime;
2185 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp);
2189 rt2661_get_rf(int rev)
2192 case RT2661_RF_5225: return "RT5225";
2193 case RT2661_RF_5325: return "RT5325 (MIMO XR)";
2194 case RT2661_RF_2527: return "RT2527";
2195 case RT2661_RF_2529: return "RT2529 (MIMO XR)";
2196 default: return "unknown";
2201 rt2661_read_eeprom(struct rt2661_softc *sc, struct ieee80211com *ic)
2206 /* read MAC address */
2207 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01);
2208 ic->ic_myaddr[0] = val & 0xff;
2209 ic->ic_myaddr[1] = val >> 8;
2211 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23);
2212 ic->ic_myaddr[2] = val & 0xff;
2213 ic->ic_myaddr[3] = val >> 8;
2215 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45);
2216 ic->ic_myaddr[4] = val & 0xff;
2217 ic->ic_myaddr[5] = val >> 8;
2219 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA);
2220 /* XXX: test if different from 0xffff? */
2221 sc->rf_rev = (val >> 11) & 0x1f;
2222 sc->hw_radio = (val >> 10) & 0x1;
2223 sc->rx_ant = (val >> 4) & 0x3;
2224 sc->tx_ant = (val >> 2) & 0x3;
2225 sc->nb_ant = val & 0x3;
2227 DPRINTF(sc, "RF revision=%d\n", sc->rf_rev);
2229 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2);
2230 sc->ext_5ghz_lna = (val >> 6) & 0x1;
2231 sc->ext_2ghz_lna = (val >> 4) & 0x1;
2233 DPRINTF(sc, "External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n",
2234 sc->ext_2ghz_lna, sc->ext_5ghz_lna);
2236 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET);
2237 if ((val & 0xff) != 0xff)
2238 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */
2240 /* Only [-10, 10] is valid */
2241 if (sc->rssi_2ghz_corr < -10 || sc->rssi_2ghz_corr > 10)
2242 sc->rssi_2ghz_corr = 0;
2244 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET);
2245 if ((val & 0xff) != 0xff)
2246 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */
2248 /* Only [-10, 10] is valid */
2249 if (sc->rssi_5ghz_corr < -10 || sc->rssi_5ghz_corr > 10)
2250 sc->rssi_5ghz_corr = 0;
2252 /* adjust RSSI correction for external low-noise amplifier */
2253 if (sc->ext_2ghz_lna)
2254 sc->rssi_2ghz_corr -= 14;
2255 if (sc->ext_5ghz_lna)
2256 sc->rssi_5ghz_corr -= 14;
2258 DPRINTF(sc, "RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n",
2259 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr);
2261 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET);
2262 if ((val >> 8) != 0xff)
2263 sc->rfprog = (val >> 8) & 0x3;
2264 if ((val & 0xff) != 0xff)
2265 sc->rffreq = val & 0xff;
2267 DPRINTF(sc, "RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq);
2269 /* read Tx power for all a/b/g channels */
2270 for (i = 0; i < 19; i++) {
2271 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i);
2272 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */
2273 DPRINTF(sc, "Channel=%d Tx power=%d\n",
2274 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2]);
2275 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */
2276 DPRINTF(sc, "Channel=%d Tx power=%d\n",
2277 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1]);
2280 /* read vendor-specific BBP values */
2281 for (i = 0; i < 16; i++) {
2282 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i);
2283 if (val == 0 || val == 0xffff)
2284 continue; /* skip invalid entries */
2285 sc->bbp_prom[i].reg = val >> 8;
2286 sc->bbp_prom[i].val = val & 0xff;
2287 DPRINTF(sc, "BBP R%d=%02x\n", sc->bbp_prom[i].reg,
2288 sc->bbp_prom[i].val);
2293 rt2661_bbp_init(struct rt2661_softc *sc)
2295 #define N(a) (sizeof (a) / sizeof ((a)[0]))
2299 /* wait for BBP to be ready */
2300 for (ntries = 0; ntries < 100; ntries++) {
2301 val = rt2661_bbp_read(sc, 0);
2302 if (val != 0 && val != 0xff)
2306 if (ntries == 100) {
2307 device_printf(sc->sc_dev, "timeout waiting for BBP\n");
2311 /* initialize BBP registers to default values */
2312 for (i = 0; i < N(rt2661_def_bbp); i++) {
2313 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg,
2314 rt2661_def_bbp[i].val);
2317 /* write vendor-specific BBP values (from EEPROM) */
2318 for (i = 0; i < 16; i++) {
2319 if (sc->bbp_prom[i].reg == 0)
2321 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
2329 rt2661_init_locked(struct rt2661_softc *sc)
2331 #define N(a) (sizeof (a) / sizeof ((a)[0]))
2332 struct ifnet *ifp = sc->sc_ifp;
2333 struct ieee80211com *ic = ifp->if_l2com;
2334 uint32_t tmp, sta[3];
2335 int i, error, ntries;
2337 RAL_LOCK_ASSERT(sc);
2339 if ((sc->sc_flags & RAL_FW_LOADED) == 0) {
2340 error = rt2661_load_microcode(sc);
2343 "%s: could not load 8051 microcode, error %d\n",
2347 sc->sc_flags |= RAL_FW_LOADED;
2350 rt2661_stop_locked(sc);
2352 /* initialize Tx rings */
2353 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr);
2354 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr);
2355 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr);
2356 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr);
2358 /* initialize Mgt ring */
2359 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr);
2361 /* initialize Rx ring */
2362 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr);
2364 /* initialize Tx rings sizes */
2365 RAL_WRITE(sc, RT2661_TX_RING_CSR0,
2366 RT2661_TX_RING_COUNT << 24 |
2367 RT2661_TX_RING_COUNT << 16 |
2368 RT2661_TX_RING_COUNT << 8 |
2369 RT2661_TX_RING_COUNT);
2371 RAL_WRITE(sc, RT2661_TX_RING_CSR1,
2372 RT2661_TX_DESC_WSIZE << 16 |
2373 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */
2374 RT2661_MGT_RING_COUNT);
2376 /* initialize Rx rings */
2377 RAL_WRITE(sc, RT2661_RX_RING_CSR,
2378 RT2661_RX_DESC_BACK << 16 |
2379 RT2661_RX_DESC_WSIZE << 8 |
2380 RT2661_RX_RING_COUNT);
2382 /* XXX: some magic here */
2383 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa);
2385 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */
2386 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f);
2388 /* load base address of Rx ring */
2389 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2);
2391 /* initialize MAC registers to default values */
2392 for (i = 0; i < N(rt2661_def_mac); i++)
2393 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val);
2395 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp));
2396 rt2661_set_macaddr(sc, ic->ic_myaddr);
2398 /* set host ready */
2399 RAL_WRITE(sc, RT2661_MAC_CSR1, 3);
2400 RAL_WRITE(sc, RT2661_MAC_CSR1, 0);
2402 /* wait for BBP/RF to wakeup */
2403 for (ntries = 0; ntries < 1000; ntries++) {
2404 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8)
2408 if (ntries == 1000) {
2409 printf("timeout waiting for BBP/RF to wakeup\n");
2410 rt2661_stop_locked(sc);
2414 if (rt2661_bbp_init(sc) != 0) {
2415 rt2661_stop_locked(sc);
2419 /* select default channel */
2420 sc->sc_curchan = ic->ic_curchan;
2421 rt2661_select_band(sc, sc->sc_curchan);
2422 rt2661_select_antenna(sc);
2423 rt2661_set_chan(sc, sc->sc_curchan);
2425 /* update Rx filter */
2426 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff;
2428 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR;
2429 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2430 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR |
2432 if (ic->ic_opmode != IEEE80211_M_HOSTAP)
2433 tmp |= RT2661_DROP_TODS;
2434 if (!(ifp->if_flags & IFF_PROMISC))
2435 tmp |= RT2661_DROP_NOT_TO_ME;
2438 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2440 /* clear STA registers */
2441 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, N(sta));
2443 /* initialize ASIC */
2444 RAL_WRITE(sc, RT2661_MAC_CSR1, 4);
2446 /* clear any pending interrupt */
2447 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff);
2449 /* enable interrupts */
2450 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10);
2451 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0);
2454 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1);
2456 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2457 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2459 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc);
2464 rt2661_init(void *priv)
2466 struct rt2661_softc *sc = priv;
2467 struct ifnet *ifp = sc->sc_ifp;
2468 struct ieee80211com *ic = ifp->if_l2com;
2471 rt2661_init_locked(sc);
2474 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2475 ieee80211_start_all(ic); /* start all vap's */
2479 rt2661_stop_locked(struct rt2661_softc *sc)
2481 struct ifnet *ifp = sc->sc_ifp;
2483 volatile int *flags = &sc->sc_flags;
2485 while (*flags & RAL_INPUT_RUNNING)
2486 msleep(sc, &sc->sc_mtx, 0, "ralrunning", hz/10);
2488 callout_stop(&sc->watchdog_ch);
2489 sc->sc_tx_timer = 0;
2491 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2492 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2494 /* abort Tx (for all 5 Tx rings) */
2495 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16);
2497 /* disable Rx (value remains after reset!) */
2498 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
2499 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2502 RAL_WRITE(sc, RT2661_MAC_CSR1, 3);
2503 RAL_WRITE(sc, RT2661_MAC_CSR1, 0);
2505 /* disable interrupts */
2506 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff);
2507 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
2509 /* clear any pending interrupt */
2510 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff);
2511 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff);
2513 /* reset Tx and Rx rings */
2514 rt2661_reset_tx_ring(sc, &sc->txq[0]);
2515 rt2661_reset_tx_ring(sc, &sc->txq[1]);
2516 rt2661_reset_tx_ring(sc, &sc->txq[2]);
2517 rt2661_reset_tx_ring(sc, &sc->txq[3]);
2518 rt2661_reset_tx_ring(sc, &sc->mgtq);
2519 rt2661_reset_rx_ring(sc, &sc->rxq);
2524 rt2661_stop(void *priv)
2526 struct rt2661_softc *sc = priv;
2529 rt2661_stop_locked(sc);
2534 rt2661_load_microcode(struct rt2661_softc *sc)
2536 struct ifnet *ifp = sc->sc_ifp;
2537 const struct firmware *fp;
2538 const char *imagename;
2541 RAL_LOCK_ASSERT(sc);
2543 switch (sc->sc_id) {
2544 case 0x0301: imagename = "rt2561sfw"; break;
2545 case 0x0302: imagename = "rt2561fw"; break;
2546 case 0x0401: imagename = "rt2661fw"; break;
2548 if_printf(ifp, "%s: unexpected pci device id 0x%x, "
2549 "don't know how to retrieve firmware\n",
2550 __func__, sc->sc_id);
2554 fp = firmware_get(imagename);
2557 if_printf(ifp, "%s: unable to retrieve firmware image %s\n",
2558 __func__, imagename);
2563 * Load 8051 microcode into NIC.
2566 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET);
2568 /* cancel any pending Host to MCU command */
2569 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0);
2570 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff);
2571 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0);
2573 /* write 8051's microcode */
2574 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL);
2575 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, fp->data, fp->datasize);
2576 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET);
2578 /* kick 8051's ass */
2579 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0);
2581 /* wait for 8051 to initialize */
2582 for (ntries = 0; ntries < 500; ntries++) {
2583 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY)
2587 if (ntries == 500) {
2588 if_printf(ifp, "%s: timeout waiting for MCU to initialize\n",
2594 firmware_put(fp, FIRMWARE_UNLOAD);
2600 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and
2601 * false CCA count. This function is called periodically (every seconds) when
2602 * in the RUN state. Values taken from the reference driver.
2605 rt2661_rx_tune(struct rt2661_softc *sc)
2612 * Tuning range depends on operating band and on the presence of an
2613 * external low-noise amplifier.
2616 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan))
2618 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) ||
2619 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna))
2623 /* retrieve false CCA count since last call (clear on read) */
2624 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff;
2628 } else if (dbm >= -58) {
2630 } else if (dbm >= -66) {
2632 } else if (dbm >= -74) {
2635 /* RSSI < -74dBm, tune using false CCA count */
2637 bbp17 = sc->bbp17; /* current value */
2639 hi -= 2 * (-74 - dbm);
2646 } else if (cca > 512) {
2649 } else if (cca < 100) {
2655 if (bbp17 != sc->bbp17) {
2656 rt2661_bbp_write(sc, 17, bbp17);
2662 * Enter/Leave radar detection mode.
2663 * This is for 802.11h additional regulatory domains.
2666 rt2661_radar_start(struct rt2661_softc *sc)
2671 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
2672 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2674 rt2661_bbp_write(sc, 82, 0x20);
2675 rt2661_bbp_write(sc, 83, 0x00);
2676 rt2661_bbp_write(sc, 84, 0x40);
2678 /* save current BBP registers values */
2679 sc->bbp18 = rt2661_bbp_read(sc, 18);
2680 sc->bbp21 = rt2661_bbp_read(sc, 21);
2681 sc->bbp22 = rt2661_bbp_read(sc, 22);
2682 sc->bbp16 = rt2661_bbp_read(sc, 16);
2683 sc->bbp17 = rt2661_bbp_read(sc, 17);
2684 sc->bbp64 = rt2661_bbp_read(sc, 64);
2686 rt2661_bbp_write(sc, 18, 0xff);
2687 rt2661_bbp_write(sc, 21, 0x3f);
2688 rt2661_bbp_write(sc, 22, 0x3f);
2689 rt2661_bbp_write(sc, 16, 0xbd);
2690 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34);
2691 rt2661_bbp_write(sc, 64, 0x21);
2693 /* restore Rx filter */
2694 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2698 rt2661_radar_stop(struct rt2661_softc *sc)
2702 /* read radar detection result */
2703 bbp66 = rt2661_bbp_read(sc, 66);
2705 /* restore BBP registers values */
2706 rt2661_bbp_write(sc, 16, sc->bbp16);
2707 rt2661_bbp_write(sc, 17, sc->bbp17);
2708 rt2661_bbp_write(sc, 18, sc->bbp18);
2709 rt2661_bbp_write(sc, 21, sc->bbp21);
2710 rt2661_bbp_write(sc, 22, sc->bbp22);
2711 rt2661_bbp_write(sc, 64, sc->bbp64);
2718 rt2661_prepare_beacon(struct rt2661_softc *sc, struct ieee80211vap *vap)
2720 struct ieee80211com *ic = vap->iv_ic;
2721 struct ieee80211_beacon_offsets bo;
2722 struct rt2661_tx_desc desc;
2726 m0 = ieee80211_beacon_alloc(vap->iv_bss, &bo);
2728 device_printf(sc->sc_dev, "could not allocate beacon frame\n");
2732 /* send beacons at the lowest available rate */
2733 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 12 : 2;
2735 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ,
2736 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT);
2738 /* copy the first 24 bytes of Tx descriptor into NIC memory */
2739 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24);
2741 /* copy beacon header and payload into NIC memory */
2742 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24,
2743 mtod(m0, uint8_t *), m0->m_pkthdr.len);
2751 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS
2752 * and HostAP operating modes.
2755 rt2661_enable_tsf_sync(struct rt2661_softc *sc)
2757 struct ifnet *ifp = sc->sc_ifp;
2758 struct ieee80211com *ic = ifp->if_l2com;
2759 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2762 if (vap->iv_opmode != IEEE80211_M_STA) {
2764 * Change default 16ms TBTT adjustment to 8ms.
2765 * Must be done before enabling beacon generation.
2767 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8);
2770 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000;
2772 /* set beacon interval (in 1/16ms unit) */
2773 tmp |= vap->iv_bss->ni_intval * 16;
2775 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT;
2776 if (vap->iv_opmode == IEEE80211_M_STA)
2777 tmp |= RT2661_TSF_MODE(1);
2779 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON;
2781 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp);
2785 * Retrieve the "Received Signal Strength Indicator" from the raw values
2786 * contained in Rx descriptors. The computation depends on which band the
2787 * frame was received. Correction values taken from the reference driver.
2790 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw)
2794 lna = (raw >> 5) & 0x3;
2799 * No mapping available.
2801 * NB: Since RSSI is relative to noise floor, -1 is
2802 * adequate for caller to know error happened.
2807 rssi = (2 * agc) - RT2661_NOISE_FLOOR;
2809 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) {
2810 rssi += sc->rssi_2ghz_corr;
2819 rssi += sc->rssi_5ghz_corr;
2832 rt2661_scan_start(struct ieee80211com *ic)
2834 struct ifnet *ifp = ic->ic_ifp;
2835 struct rt2661_softc *sc = ifp->if_softc;
2838 /* abort TSF synchronization */
2839 tmp = RAL_READ(sc, RT2661_TXRX_CSR9);
2840 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0xffffff);
2841 rt2661_set_bssid(sc, ifp->if_broadcastaddr);
2845 rt2661_scan_end(struct ieee80211com *ic)
2847 struct ifnet *ifp = ic->ic_ifp;
2848 struct rt2661_softc *sc = ifp->if_softc;
2849 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2851 rt2661_enable_tsf_sync(sc);
2852 /* XXX keep local copy */
2853 rt2661_set_bssid(sc, vap->iv_bss->ni_bssid);
2857 rt2661_set_channel(struct ieee80211com *ic)
2859 struct ifnet *ifp = ic->ic_ifp;
2860 struct rt2661_softc *sc = ifp->if_softc;
2863 rt2661_set_chan(sc, ic->ic_curchan);
2865 sc->sc_txtap.wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
2866 sc->sc_txtap.wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
2867 sc->sc_rxtap.wr_chan_freq = htole16(ic->ic_curchan->ic_freq);
2868 sc->sc_rxtap.wr_chan_flags = htole16(ic->ic_curchan->ic_flags);