2 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr>
3 * Copyright (c) 2012 Bernhard Schmidt <bschmidt@FreeBSD.org>
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $OpenBSD: rt2860.c,v 1.65 2010/10/23 14:24:54 damien Exp $
20 #include <sys/cdefs.h>
21 __FBSDID("$FreeBSD$");
24 * Ralink Technology RT2860/RT3090/RT3390/RT3562/RT5390/RT5392 chipset driver
25 * http://www.ralinktech.com/
28 #include <sys/param.h>
29 #include <sys/sysctl.h>
30 #include <sys/sockio.h>
32 #include <sys/kernel.h>
33 #include <sys/socket.h>
34 #include <sys/systm.h>
35 #include <sys/malloc.h>
37 #include <sys/mutex.h>
38 #include <sys/module.h>
40 #include <sys/endian.h>
41 #include <sys/firmware.h>
43 #include <machine/bus.h>
44 #include <machine/resource.h>
49 #include <net/if_var.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_dl.h>
53 #include <net/if_media.h>
54 #include <net/if_types.h>
56 #include <net80211/ieee80211_var.h>
57 #include <net80211/ieee80211_radiotap.h>
58 #include <net80211/ieee80211_regdomain.h>
59 #include <net80211/ieee80211_ratectl.h>
61 #include <netinet/in.h>
62 #include <netinet/in_systm.h>
63 #include <netinet/in_var.h>
64 #include <netinet/ip.h>
65 #include <netinet/if_ether.h>
67 #include <dev/ral/rt2860reg.h>
68 #include <dev/ral/rt2860var.h>
72 #define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0)
73 #define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0)
76 #define DPRINTFN(n, x)
79 static struct ieee80211vap *rt2860_vap_create(struct ieee80211com *,
80 const char [IFNAMSIZ], int, enum ieee80211_opmode,
81 int, const uint8_t [IEEE80211_ADDR_LEN],
82 const uint8_t [IEEE80211_ADDR_LEN]);
83 static void rt2860_vap_delete(struct ieee80211vap *);
84 static void rt2860_dma_map_addr(void *, bus_dma_segment_t *, int, int);
85 static int rt2860_alloc_tx_ring(struct rt2860_softc *,
86 struct rt2860_tx_ring *);
87 static void rt2860_reset_tx_ring(struct rt2860_softc *,
88 struct rt2860_tx_ring *);
89 static void rt2860_free_tx_ring(struct rt2860_softc *,
90 struct rt2860_tx_ring *);
91 static int rt2860_alloc_tx_pool(struct rt2860_softc *);
92 static void rt2860_free_tx_pool(struct rt2860_softc *);
93 static int rt2860_alloc_rx_ring(struct rt2860_softc *,
94 struct rt2860_rx_ring *);
95 static void rt2860_reset_rx_ring(struct rt2860_softc *,
96 struct rt2860_rx_ring *);
97 static void rt2860_free_rx_ring(struct rt2860_softc *,
98 struct rt2860_rx_ring *);
99 static void rt2860_updatestats(struct rt2860_softc *);
100 static void rt2860_newassoc(struct ieee80211_node *, int);
101 static void rt2860_node_free(struct ieee80211_node *);
103 static int rt2860_ampdu_rx_start(struct ieee80211com *,
104 struct ieee80211_node *, uint8_t);
105 static void rt2860_ampdu_rx_stop(struct ieee80211com *,
106 struct ieee80211_node *, uint8_t);
108 static int rt2860_newstate(struct ieee80211vap *, enum ieee80211_state,
110 static uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t);
111 static uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t);
112 static void rt2860_intr_coherent(struct rt2860_softc *);
113 static void rt2860_drain_stats_fifo(struct rt2860_softc *);
114 static void rt2860_tx_intr(struct rt2860_softc *, int);
115 static void rt2860_rx_intr(struct rt2860_softc *);
116 static void rt2860_tbtt_intr(struct rt2860_softc *);
117 static void rt2860_gp_intr(struct rt2860_softc *);
118 static int rt2860_tx(struct rt2860_softc *, struct mbuf *,
119 struct ieee80211_node *);
120 static int rt2860_raw_xmit(struct ieee80211_node *, struct mbuf *,
121 const struct ieee80211_bpf_params *);
122 static int rt2860_tx_raw(struct rt2860_softc *, struct mbuf *,
123 struct ieee80211_node *,
124 const struct ieee80211_bpf_params *params);
125 static int rt2860_transmit(struct ieee80211com *, struct mbuf *);
126 static void rt2860_start(struct rt2860_softc *);
127 static void rt2860_watchdog(void *);
128 static void rt2860_parent(struct ieee80211com *);
129 static void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t);
130 static uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t);
131 static void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t);
132 static uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t);
133 static void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t);
134 static int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int);
135 static void rt2860_enable_mrr(struct rt2860_softc *);
136 static void rt2860_set_txpreamble(struct rt2860_softc *);
137 static void rt2860_set_basicrates(struct rt2860_softc *,
138 const struct ieee80211_rateset *);
139 static void rt2860_scan_start(struct ieee80211com *);
140 static void rt2860_scan_end(struct ieee80211com *);
141 static void rt2860_set_channel(struct ieee80211com *);
142 static void rt2860_select_chan_group(struct rt2860_softc *, int);
143 static void rt2860_set_chan(struct rt2860_softc *, u_int);
144 static void rt3090_set_chan(struct rt2860_softc *, u_int);
145 static void rt5390_set_chan(struct rt2860_softc *, u_int);
146 static int rt3090_rf_init(struct rt2860_softc *);
147 static void rt5390_rf_init(struct rt2860_softc *);
148 static void rt3090_rf_wakeup(struct rt2860_softc *);
149 static void rt5390_rf_wakeup(struct rt2860_softc *);
150 static int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t,
152 static void rt3090_rf_setup(struct rt2860_softc *);
153 static void rt2860_set_leds(struct rt2860_softc *, uint16_t);
154 static void rt2860_set_gp_timer(struct rt2860_softc *, int);
155 static void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *);
156 static void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *);
157 static void rt2860_update_promisc(struct ieee80211com *);
158 static void rt2860_updateslot(struct ieee80211com *);
159 static void rt2860_updateprot(struct rt2860_softc *);
160 static int rt2860_updateedca(struct ieee80211com *);
162 static int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *,
163 struct ieee80211_key *);
164 static void rt2860_delete_key(struct ieee80211com *,
165 struct ieee80211_node *, struct ieee80211_key *);
167 static int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t);
168 static const char *rt2860_get_rf(uint8_t);
169 static int rt2860_read_eeprom(struct rt2860_softc *,
170 uint8_t macaddr[IEEE80211_ADDR_LEN]);
171 static int rt2860_bbp_init(struct rt2860_softc *);
172 static void rt5390_bbp_init(struct rt2860_softc *);
173 static int rt2860_txrx_enable(struct rt2860_softc *);
174 static void rt2860_init(void *);
175 static void rt2860_init_locked(struct rt2860_softc *);
176 static void rt2860_stop(void *);
177 static void rt2860_stop_locked(struct rt2860_softc *);
178 static int rt2860_load_microcode(struct rt2860_softc *);
180 static void rt2860_calib(struct rt2860_softc *);
182 static void rt3090_set_rx_antenna(struct rt2860_softc *, int);
183 static void rt2860_switch_chan(struct rt2860_softc *,
184 struct ieee80211_channel *);
185 static int rt2860_setup_beacon(struct rt2860_softc *,
186 struct ieee80211vap *);
187 static void rt2860_enable_tsf_sync(struct rt2860_softc *);
189 static const struct {
192 } rt2860_def_mac[] = {
196 static const struct {
199 } rt2860_def_bbp[] = {
201 }, rt5390_def_bbp[] = {
205 static const struct rfprog {
207 uint32_t r1, r2, r3, r4;
208 } rt2860_rf2850[] = {
218 static const struct {
221 } rt3090_def_rf[] = {
223 }, rt5390_def_rf[] = {
225 }, rt5392_def_rf[] = {
230 rt2860_attach(device_t dev, int id)
232 struct rt2860_softc *sc = device_get_softc(dev);
233 struct ieee80211com *ic = &sc->sc_ic;
235 int error, ntries, qid;
241 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
242 MTX_DEF | MTX_RECURSE);
244 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0);
245 mbufq_init(&sc->sc_snd, ifqmaxlen);
247 /* wait for NIC to initialize */
248 for (ntries = 0; ntries < 100; ntries++) {
249 tmp = RAL_READ(sc, RT2860_ASIC_VER_ID);
250 if (tmp != 0 && tmp != 0xffffffff)
255 device_printf(sc->sc_dev,
256 "timeout waiting for NIC to initialize\n");
260 sc->mac_ver = tmp >> 16;
261 sc->mac_rev = tmp & 0xffff;
263 if (sc->mac_ver != 0x2860 &&
264 (id == 0x0681 || id == 0x0781 || id == 0x1059))
265 sc->sc_flags |= RT2860_ADVANCED_PS;
267 /* retrieve RF rev. no and various other things from EEPROM */
268 rt2860_read_eeprom(sc, ic->ic_macaddr);
269 device_printf(sc->sc_dev, "MAC/BBP RT%X (rev 0x%04X), "
270 "RF %s (MIMO %dT%dR), address %6D\n",
271 sc->mac_ver, sc->mac_rev, rt2860_get_rf(sc->rf_rev),
272 sc->ntxchains, sc->nrxchains, ic->ic_macaddr, ":");
275 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings.
277 for (qid = 0; qid < 6; qid++) {
278 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) {
279 device_printf(sc->sc_dev,
280 "could not allocate Tx ring %d\n", qid);
285 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) {
286 device_printf(sc->sc_dev, "could not allocate Rx ring\n");
290 if ((error = rt2860_alloc_tx_pool(sc)) != 0) {
291 device_printf(sc->sc_dev, "could not allocate Tx pool\n");
295 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */
296 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ?
300 ic->ic_name = device_get_nameunit(dev);
301 ic->ic_opmode = IEEE80211_M_STA;
302 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
304 /* set device capabilities */
306 IEEE80211_C_STA /* station mode */
307 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
308 | IEEE80211_C_HOSTAP /* hostap mode */
309 | IEEE80211_C_MONITOR /* monitor mode */
310 | IEEE80211_C_AHDEMO /* adhoc demo mode */
311 | IEEE80211_C_WDS /* 4-address traffic works */
312 | IEEE80211_C_MBSS /* mesh point link mode */
313 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
314 | IEEE80211_C_SHSLOT /* short slot time supported */
315 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
317 | IEEE80211_C_BGSCAN /* capable of bg scanning */
319 | IEEE80211_C_WME /* 802.11e */
323 setbit(&bands, IEEE80211_MODE_11B);
324 setbit(&bands, IEEE80211_MODE_11G);
325 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850)
326 setbit(&bands, IEEE80211_MODE_11A);
327 ieee80211_init_channels(ic, NULL, &bands);
329 ieee80211_ifattach(ic);
331 ic->ic_wme.wme_update = rt2860_updateedca;
332 ic->ic_scan_start = rt2860_scan_start;
333 ic->ic_scan_end = rt2860_scan_end;
334 ic->ic_set_channel = rt2860_set_channel;
335 ic->ic_updateslot = rt2860_updateslot;
336 ic->ic_update_promisc = rt2860_update_promisc;
337 ic->ic_raw_xmit = rt2860_raw_xmit;
338 sc->sc_node_free = ic->ic_node_free;
339 ic->ic_node_free = rt2860_node_free;
340 ic->ic_newassoc = rt2860_newassoc;
341 ic->ic_transmit = rt2860_transmit;
342 ic->ic_parent = rt2860_parent;
343 ic->ic_vap_create = rt2860_vap_create;
344 ic->ic_vap_delete = rt2860_vap_delete;
346 ieee80211_radiotap_attach(ic,
347 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
348 RT2860_TX_RADIOTAP_PRESENT,
349 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
350 RT2860_RX_RADIOTAP_PRESENT);
353 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
354 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
355 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs");
358 ieee80211_announce(ic);
362 fail3: rt2860_free_rx_ring(sc, &sc->rxq);
363 fail2: while (--qid >= 0)
364 rt2860_free_tx_ring(sc, &sc->txq[qid]);
365 fail1: mtx_destroy(&sc->sc_mtx);
370 rt2860_detach(void *xsc)
372 struct rt2860_softc *sc = xsc;
373 struct ieee80211com *ic = &sc->sc_ic;
377 rt2860_stop_locked(sc);
380 ieee80211_ifdetach(ic);
381 mbufq_drain(&sc->sc_snd);
382 for (qid = 0; qid < 6; qid++)
383 rt2860_free_tx_ring(sc, &sc->txq[qid]);
384 rt2860_free_rx_ring(sc, &sc->rxq);
385 rt2860_free_tx_pool(sc);
387 mtx_destroy(&sc->sc_mtx);
393 rt2860_shutdown(void *xsc)
395 struct rt2860_softc *sc = xsc;
401 rt2860_suspend(void *xsc)
403 struct rt2860_softc *sc = xsc;
409 rt2860_resume(void *xsc)
411 struct rt2860_softc *sc = xsc;
413 if (sc->sc_ic.ic_nrunning > 0)
417 static struct ieee80211vap *
418 rt2860_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
419 enum ieee80211_opmode opmode, int flags,
420 const uint8_t bssid[IEEE80211_ADDR_LEN],
421 const uint8_t mac[IEEE80211_ADDR_LEN])
423 struct rt2860_softc *sc = ic->ic_softc;
424 struct rt2860_vap *rvp;
425 struct ieee80211vap *vap;
428 case IEEE80211_M_STA:
429 case IEEE80211_M_IBSS:
430 case IEEE80211_M_AHDEMO:
431 case IEEE80211_M_MONITOR:
432 case IEEE80211_M_HOSTAP:
433 case IEEE80211_M_MBSS:
435 if (!TAILQ_EMPTY(&ic->ic_vaps)) {
436 device_printf(sc->sc_dev, "only 1 vap supported\n");
439 if (opmode == IEEE80211_M_STA)
440 flags |= IEEE80211_CLONE_NOBEACONS;
442 case IEEE80211_M_WDS:
443 if (TAILQ_EMPTY(&ic->ic_vaps) ||
444 ic->ic_opmode != IEEE80211_M_HOSTAP) {
445 device_printf(sc->sc_dev,
446 "wds only supported in ap mode\n");
450 * Silently remove any request for a unique
451 * bssid; WDS vap's always share the local
454 flags &= ~IEEE80211_CLONE_BSSID;
457 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode);
460 rvp = malloc(sizeof(struct rt2860_vap), M_80211_VAP, M_WAITOK | M_ZERO);
462 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid);
464 /* override state transition machine */
465 rvp->ral_newstate = vap->iv_newstate;
466 vap->iv_newstate = rt2860_newstate;
468 vap->iv_update_beacon = rt2860_beacon_update;
471 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */
472 vap->iv_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX);
474 ieee80211_ratectl_init(vap);
476 ieee80211_vap_attach(vap, ieee80211_media_change,
477 ieee80211_media_status, mac);
478 if (TAILQ_FIRST(&ic->ic_vaps) == vap)
479 ic->ic_opmode = opmode;
484 rt2860_vap_delete(struct ieee80211vap *vap)
486 struct rt2860_vap *rvp = RT2860_VAP(vap);
488 ieee80211_ratectl_deinit(vap);
489 ieee80211_vap_detach(vap);
490 free(rvp, M_80211_VAP);
494 rt2860_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
499 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
501 *(bus_addr_t *)arg = segs[0].ds_addr;
506 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
510 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd);
512 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0,
513 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
514 size, 1, size, 0, NULL, NULL, &ring->desc_dmat);
516 device_printf(sc->sc_dev, "could not create desc DMA map\n");
520 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->txd,
521 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map);
523 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
527 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->txd,
528 size, rt2860_dma_map_addr, &ring->paddr, 0);
530 device_printf(sc->sc_dev, "could not load desc DMA map\n");
534 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
538 fail: rt2860_free_tx_ring(sc, ring);
543 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
545 struct rt2860_tx_data *data;
548 for (i = 0; i < RT2860_TX_RING_COUNT; i++) {
549 if ((data = ring->data[i]) == NULL)
550 continue; /* nothing mapped in this slot */
552 if (data->m != NULL) {
553 bus_dmamap_sync(sc->txwi_dmat, data->map,
554 BUS_DMASYNC_POSTWRITE);
555 bus_dmamap_unload(sc->txwi_dmat, data->map);
559 if (data->ni != NULL) {
560 ieee80211_free_node(data->ni);
564 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
565 ring->data[i] = NULL;
569 ring->cur = ring->next = 0;
573 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring)
575 struct rt2860_tx_data *data;
578 if (ring->txd != NULL) {
579 bus_dmamap_sync(ring->desc_dmat, ring->desc_map,
580 BUS_DMASYNC_POSTWRITE);
581 bus_dmamap_unload(ring->desc_dmat, ring->desc_map);
582 bus_dmamem_free(ring->desc_dmat, ring->txd, ring->desc_map);
584 if (ring->desc_dmat != NULL)
585 bus_dma_tag_destroy(ring->desc_dmat);
587 for (i = 0; i < RT2860_TX_RING_COUNT; i++) {
588 if ((data = ring->data[i]) == NULL)
589 continue; /* nothing mapped in this slot */
591 if (data->m != NULL) {
592 bus_dmamap_sync(sc->txwi_dmat, data->map,
593 BUS_DMASYNC_POSTWRITE);
594 bus_dmamap_unload(sc->txwi_dmat, data->map);
597 if (data->ni != NULL)
598 ieee80211_free_node(data->ni);
600 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
605 * Allocate a pool of TX Wireless Information blocks.
608 rt2860_alloc_tx_pool(struct rt2860_softc *sc)
614 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ;
616 /* init data_pool early in case of failure.. */
617 SLIST_INIT(&sc->data_pool);
619 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
620 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
621 size, 1, size, 0, NULL, NULL, &sc->txwi_dmat);
623 device_printf(sc->sc_dev, "could not create txwi DMA tag\n");
627 error = bus_dmamem_alloc(sc->txwi_dmat, (void **)&sc->txwi_vaddr,
628 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->txwi_map);
630 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
634 error = bus_dmamap_load(sc->txwi_dmat, sc->txwi_map,
635 sc->txwi_vaddr, size, rt2860_dma_map_addr, &paddr, 0);
637 device_printf(sc->sc_dev, "could not load txwi DMA map\n");
641 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE);
643 vaddr = sc->txwi_vaddr;
644 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) {
645 struct rt2860_tx_data *data = &sc->data[i];
647 error = bus_dmamap_create(sc->txwi_dmat, 0, &data->map);
649 device_printf(sc->sc_dev, "could not create DMA map\n");
652 data->txwi = (struct rt2860_txwi *)vaddr;
654 vaddr += RT2860_TXWI_DMASZ;
655 paddr += RT2860_TXWI_DMASZ;
657 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
662 fail: rt2860_free_tx_pool(sc);
667 rt2860_free_tx_pool(struct rt2860_softc *sc)
669 if (sc->txwi_vaddr != NULL) {
670 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map,
671 BUS_DMASYNC_POSTWRITE);
672 bus_dmamap_unload(sc->txwi_dmat, sc->txwi_map);
673 bus_dmamem_free(sc->txwi_dmat, sc->txwi_vaddr, sc->txwi_map);
675 if (sc->txwi_dmat != NULL)
676 bus_dma_tag_destroy(sc->txwi_dmat);
678 while (!SLIST_EMPTY(&sc->data_pool)) {
679 struct rt2860_tx_data *data;
680 data = SLIST_FIRST(&sc->data_pool);
681 bus_dmamap_destroy(sc->txwi_dmat, data->map);
682 SLIST_REMOVE_HEAD(&sc->data_pool, next);
687 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
692 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd);
694 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0,
695 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
696 size, 1, size, 0, NULL, NULL, &ring->desc_dmat);
698 device_printf(sc->sc_dev, "could not create desc DMA tag\n");
702 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->rxd,
703 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map);
705 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
709 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->rxd,
710 size, rt2860_dma_map_addr, &ring->paddr, 0);
712 device_printf(sc->sc_dev, "could not load desc DMA map\n");
716 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
717 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
718 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat);
720 device_printf(sc->sc_dev, "could not create data DMA tag\n");
724 for (i = 0; i < RT2860_RX_RING_COUNT; i++) {
725 struct rt2860_rx_data *data = &ring->data[i];
726 struct rt2860_rxd *rxd = &ring->rxd[i];
728 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
730 device_printf(sc->sc_dev, "could not create DMA map\n");
734 data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
735 if (data->m == NULL) {
736 device_printf(sc->sc_dev,
737 "could not allocate rx mbuf\n");
742 error = bus_dmamap_load(ring->data_dmat, data->map,
743 mtod(data->m, void *), MCLBYTES, rt2860_dma_map_addr,
746 device_printf(sc->sc_dev,
747 "could not load rx buf DMA map");
751 rxd->sdp0 = htole32(physaddr);
752 rxd->sdl0 = htole16(MCLBYTES);
755 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
759 fail: rt2860_free_rx_ring(sc, ring);
764 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
768 for (i = 0; i < RT2860_RX_RING_COUNT; i++)
769 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE);
771 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
777 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring)
781 if (ring->rxd != NULL) {
782 bus_dmamap_sync(ring->desc_dmat, ring->desc_map,
783 BUS_DMASYNC_POSTWRITE);
784 bus_dmamap_unload(ring->desc_dmat, ring->desc_map);
785 bus_dmamem_free(ring->desc_dmat, ring->rxd, ring->desc_map);
787 if (ring->desc_dmat != NULL)
788 bus_dma_tag_destroy(ring->desc_dmat);
790 for (i = 0; i < RT2860_RX_RING_COUNT; i++) {
791 struct rt2860_rx_data *data = &ring->data[i];
793 if (data->m != NULL) {
794 bus_dmamap_sync(ring->data_dmat, data->map,
795 BUS_DMASYNC_POSTREAD);
796 bus_dmamap_unload(ring->data_dmat, data->map);
799 if (data->map != NULL)
800 bus_dmamap_destroy(ring->data_dmat, data->map);
802 if (ring->data_dmat != NULL)
803 bus_dma_tag_destroy(ring->data_dmat);
807 rt2860_updatestats(struct rt2860_softc *sc)
809 struct ieee80211com *ic = &sc->sc_ic;
812 * In IBSS or HostAP modes (when the hardware sends beacons), the
813 * MAC can run into a livelock and start sending CTS-to-self frames
814 * like crazy if protection is enabled. Fortunately, we can detect
815 * when such a situation occurs and reset the MAC.
817 if (ic->ic_curmode != IEEE80211_M_STA) {
818 /* check if we're in a livelock situation.. */
819 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG);
820 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) {
821 /* ..and reset MAC/BBP for a while.. */
822 DPRINTF(("CTS-to-self livelock detected\n"));
823 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST);
824 RAL_BARRIER_WRITE(sc);
826 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL,
827 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
833 rt2860_newassoc(struct ieee80211_node *ni, int isnew)
835 struct ieee80211com *ic = ni->ni_ic;
836 struct rt2860_softc *sc = ic->ic_softc;
839 wcid = IEEE80211_AID(ni->ni_associd);
840 if (isnew && ni->ni_associd != 0) {
841 sc->wcid2ni[wcid] = ni;
843 /* init WCID table entry */
844 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid),
845 ni->ni_macaddr, IEEE80211_ADDR_LEN);
847 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n",
848 isnew, ether_sprintf(ni->ni_macaddr), wcid));
852 rt2860_node_free(struct ieee80211_node *ni)
854 struct ieee80211com *ic = ni->ni_ic;
855 struct rt2860_softc *sc = ic->ic_softc;
858 if (ni->ni_associd != 0) {
859 wcid = IEEE80211_AID(ni->ni_associd);
861 /* clear Rx WCID search table entry */
862 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(wcid), 0, 2);
864 sc->sc_node_free(ni);
869 rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni,
872 struct rt2860_softc *sc = ic->ic_softc;
873 uint8_t wcid = ((struct rt2860_node *)ni)->wcid;
876 /* update BA session mask */
877 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4);
878 tmp |= (1 << tid) << 16;
879 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp);
884 rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni,
887 struct rt2860_softc *sc = ic->ic_softc;
888 uint8_t wcid = ((struct rt2860_node *)ni)->wcid;
891 /* update BA session mask */
892 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4);
893 tmp &= ~((1 << tid) << 16);
894 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp);
899 rt2860_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
901 struct rt2860_vap *rvp = RT2860_VAP(vap);
902 struct ieee80211com *ic = vap->iv_ic;
903 struct rt2860_softc *sc = ic->ic_softc;
907 if (vap->iv_state == IEEE80211_S_RUN) {
908 /* turn link LED off */
909 rt2860_set_leds(sc, RT2860_LED_RADIO);
912 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) {
913 /* abort TSF synchronization */
914 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG);
915 RAL_WRITE(sc, RT2860_BCN_TIME_CFG,
916 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN |
917 RT2860_TBTT_TIMER_EN));
920 rt2860_set_gp_timer(sc, 0);
922 error = rvp->ral_newstate(vap, nstate, arg);
926 if (nstate == IEEE80211_S_RUN) {
927 struct ieee80211_node *ni = vap->iv_bss;
929 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
930 rt2860_enable_mrr(sc);
931 rt2860_set_txpreamble(sc);
932 rt2860_set_basicrates(sc, &ni->ni_rates);
933 rt2860_set_bssid(sc, ni->ni_bssid);
936 if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
937 vap->iv_opmode == IEEE80211_M_IBSS ||
938 vap->iv_opmode == IEEE80211_M_MBSS) {
939 error = rt2860_setup_beacon(sc, vap);
944 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
945 rt2860_enable_tsf_sync(sc);
946 rt2860_set_gp_timer(sc, 500);
949 /* turn link LED on */
950 rt2860_set_leds(sc, RT2860_LED_RADIO |
951 (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan) ?
952 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ));
957 /* Read 16-bit from eFUSE ROM (>=RT3071 only.) */
959 rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr)
967 * Read one 16-byte block into registers EFUSE_DATA[0-3]:
973 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL);
974 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK);
975 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK;
976 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp);
977 for (ntries = 0; ntries < 500; ntries++) {
978 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL);
979 if (!(tmp & RT3070_EFSROM_KICK))
986 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK)
987 return 0xffff; /* address not found */
989 /* determine to which 32-bit register our 16-bit word belongs */
990 reg = RT3070_EFUSE_DATA3 - (addr & 0xc);
991 tmp = RAL_READ(sc, reg);
993 return (addr & 2) ? tmp >> 16 : tmp & 0xffff;
997 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46,
1001 rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr)
1007 /* clock C once before the first command */
1008 RT2860_EEPROM_CTL(sc, 0);
1010 RT2860_EEPROM_CTL(sc, RT2860_S);
1011 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
1012 RT2860_EEPROM_CTL(sc, RT2860_S);
1014 /* write start bit (1) */
1015 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D);
1016 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C);
1018 /* write READ opcode (10) */
1019 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D);
1020 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C);
1021 RT2860_EEPROM_CTL(sc, RT2860_S);
1022 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
1024 /* write address (A5-A0 or A7-A0) */
1025 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7;
1026 for (; n >= 0; n--) {
1027 RT2860_EEPROM_CTL(sc, RT2860_S |
1028 (((addr >> n) & 1) << RT2860_SHIFT_D));
1029 RT2860_EEPROM_CTL(sc, RT2860_S |
1030 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C);
1033 RT2860_EEPROM_CTL(sc, RT2860_S);
1035 /* read data Q15-Q0 */
1037 for (n = 15; n >= 0; n--) {
1038 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C);
1039 tmp = RAL_READ(sc, RT2860_PCI_EECTRL);
1040 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n;
1041 RT2860_EEPROM_CTL(sc, RT2860_S);
1044 RT2860_EEPROM_CTL(sc, 0);
1046 /* clear Chip Select and clock C */
1047 RT2860_EEPROM_CTL(sc, RT2860_S);
1048 RT2860_EEPROM_CTL(sc, 0);
1049 RT2860_EEPROM_CTL(sc, RT2860_C);
1054 static __inline uint16_t
1055 rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr)
1057 /* either eFUSE ROM or EEPROM */
1058 return sc->sc_srom_read(sc, addr);
1062 rt2860_intr_coherent(struct rt2860_softc *sc)
1066 /* DMA finds data coherent event when checking the DDONE bit */
1068 DPRINTF(("Tx/Rx Coherent interrupt\n"));
1070 /* restart DMA engine */
1071 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
1072 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN);
1073 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
1075 (void)rt2860_txrx_enable(sc);
1079 rt2860_drain_stats_fifo(struct rt2860_softc *sc)
1081 struct ieee80211_node *ni;
1084 uint8_t wcid, mcs, pid;
1086 /* drain Tx status FIFO (maxsize = 16) */
1087 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) {
1088 DPRINTFN(4, ("tx stat 0x%08x\n", stat));
1090 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff;
1091 ni = sc->wcid2ni[wcid];
1093 /* if no ACK was requested, no feedback is available */
1094 if (!(stat & RT2860_TXQ_ACKREQ) || wcid == 0xff || ni == NULL)
1097 /* update per-STA AMRR stats */
1098 if (stat & RT2860_TXQ_OK) {
1100 * Check if there were retries, ie if the Tx success
1101 * rate is different from the requested rate. Note
1102 * that it works only because we do not allow rate
1103 * fallback from OFDM to CCK.
1105 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f;
1106 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf;
1111 ieee80211_ratectl_tx_complete(ni->ni_vap, ni,
1112 IEEE80211_RATECTL_TX_SUCCESS, &retrycnt, NULL);
1114 ieee80211_ratectl_tx_complete(ni->ni_vap, ni,
1115 IEEE80211_RATECTL_TX_FAILURE, &retrycnt, NULL);
1116 if_inc_counter(ni->ni_vap->iv_ifp,
1117 IFCOUNTER_OERRORS, 1);
1123 rt2860_tx_intr(struct rt2860_softc *sc, int qid)
1125 struct rt2860_tx_ring *ring = &sc->txq[qid];
1128 rt2860_drain_stats_fifo(sc);
1130 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid));
1131 while (ring->next != hw) {
1132 struct rt2860_tx_data *data = ring->data[ring->next];
1135 bus_dmamap_sync(sc->txwi_dmat, data->map,
1136 BUS_DMASYNC_POSTWRITE);
1137 bus_dmamap_unload(sc->txwi_dmat, data->map);
1138 if (data->m->m_flags & M_TXCB) {
1139 ieee80211_process_callback(data->ni, data->m,
1142 ieee80211_tx_complete(data->ni, data->m, 0);
1145 SLIST_INSERT_HEAD(&sc->data_pool, data, next);
1146 ring->data[ring->next] = NULL;
1149 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT;
1152 sc->sc_tx_timer = 0;
1153 if (ring->queued < RT2860_TX_RING_COUNT)
1154 sc->qfullmsk &= ~(1 << qid);
1159 * Return the Rx chain with the highest RSSI for a given frame.
1161 static __inline uint8_t
1162 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi)
1164 uint8_t rxchain = 0;
1166 if (sc->nrxchains > 1) {
1167 if (rxwi->rssi[1] > rxwi->rssi[rxchain])
1169 if (sc->nrxchains > 2)
1170 if (rxwi->rssi[2] > rxwi->rssi[rxchain])
1177 rt2860_rx_intr(struct rt2860_softc *sc)
1179 struct rt2860_rx_radiotap_header *tap;
1180 struct ieee80211com *ic = &sc->sc_ic;
1181 struct ieee80211_frame *wh;
1182 struct ieee80211_node *ni;
1183 struct mbuf *m, *m1;
1184 bus_addr_t physaddr;
1191 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff;
1192 while (sc->rxq.cur != hw) {
1193 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur];
1194 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur];
1195 struct rt2860_rxwi *rxwi;
1197 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
1198 BUS_DMASYNC_POSTREAD);
1200 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) {
1201 DPRINTF(("RXD DDONE bit not set!\n"));
1202 break; /* should not happen */
1205 if (__predict_false(rxd->flags &
1206 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) {
1207 counter_u64_add(ic->ic_ierrors, 1);
1212 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) {
1213 /* report MIC failures to net80211 for TKIP */
1214 ic->ic_stats.is_rx_locmicfail++;
1215 ieee80211_michael_mic_failure(ic, 0/* XXX */);
1216 counter_u64_add(ic->ic_ierrors, 1);
1221 m1 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1222 if (__predict_false(m1 == NULL)) {
1223 counter_u64_add(ic->ic_ierrors, 1);
1227 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
1228 BUS_DMASYNC_POSTREAD);
1229 bus_dmamap_unload(sc->rxq.data_dmat, data->map);
1231 error = bus_dmamap_load(sc->rxq.data_dmat, data->map,
1232 mtod(m1, void *), MCLBYTES, rt2860_dma_map_addr,
1234 if (__predict_false(error != 0)) {
1237 /* try to reload the old mbuf */
1238 error = bus_dmamap_load(sc->rxq.data_dmat, data->map,
1239 mtod(data->m, void *), MCLBYTES,
1240 rt2860_dma_map_addr, &physaddr, 0);
1241 if (__predict_false(error != 0)) {
1242 panic("%s: could not load old rx mbuf",
1243 device_get_name(sc->sc_dev));
1245 /* physical address may have changed */
1246 rxd->sdp0 = htole32(physaddr);
1247 counter_u64_add(ic->ic_ierrors, 1);
1252 * New mbuf successfully loaded, update Rx ring and continue
1257 rxd->sdp0 = htole32(physaddr);
1259 rxwi = mtod(m, struct rt2860_rxwi *);
1262 m->m_data = (caddr_t)(rxwi + 1);
1263 m->m_pkthdr.len = m->m_len = le16toh(rxwi->len) & 0xfff;
1265 wh = mtod(m, struct ieee80211_frame *);
1267 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1268 /* frame is decrypted by hardware */
1269 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED;
1273 /* HW may insert 2 padding bytes after 802.11 header */
1274 if (rxd->flags & htole32(RT2860_RX_L2PAD)) {
1275 u_int hdrlen = ieee80211_hdrsize(wh);
1276 ovbcopy(wh, (caddr_t)wh + 2, hdrlen);
1278 wh = mtod(m, struct ieee80211_frame *);
1281 ant = rt2860_maxrssi_chain(sc, rxwi);
1282 rssi = rt2860_rssi2dbm(sc, rxwi->rssi[ant], ant);
1283 nf = RT2860_NOISE_FLOOR;
1285 if (ieee80211_radiotap_active(ic)) {
1286 tap = &sc->sc_rxtap;
1288 tap->wr_antenna = ant;
1289 tap->wr_antsignal = nf + rssi;
1290 tap->wr_antnoise = nf;
1291 /* in case it can't be found below */
1293 phy = le16toh(rxwi->phy);
1294 switch (phy & RT2860_PHY_MODE) {
1295 case RT2860_PHY_CCK:
1296 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) {
1297 case 0: tap->wr_rate = 2; break;
1298 case 1: tap->wr_rate = 4; break;
1299 case 2: tap->wr_rate = 11; break;
1300 case 3: tap->wr_rate = 22; break;
1302 if (phy & RT2860_PHY_SHPRE)
1303 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
1305 case RT2860_PHY_OFDM:
1306 switch (phy & RT2860_PHY_MCS) {
1307 case 0: tap->wr_rate = 12; break;
1308 case 1: tap->wr_rate = 18; break;
1309 case 2: tap->wr_rate = 24; break;
1310 case 3: tap->wr_rate = 36; break;
1311 case 4: tap->wr_rate = 48; break;
1312 case 5: tap->wr_rate = 72; break;
1313 case 6: tap->wr_rate = 96; break;
1314 case 7: tap->wr_rate = 108; break;
1321 wh = mtod(m, struct ieee80211_frame *);
1323 /* send the frame to the 802.11 layer */
1324 ni = ieee80211_find_rxnode(ic,
1325 (struct ieee80211_frame_min *)wh);
1327 (void)ieee80211_input(ni, m, rssi - nf, nf);
1328 ieee80211_free_node(ni);
1330 (void)ieee80211_input_all(ic, m, rssi - nf, nf);
1334 skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE);
1336 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
1337 BUS_DMASYNC_PREWRITE);
1339 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT;
1342 /* tell HW what we have processed */
1343 RAL_WRITE(sc, RT2860_RX_CALC_IDX,
1344 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT);
1348 rt2860_tbtt_intr(struct rt2860_softc *sc)
1351 struct ieee80211com *ic = &sc->sc_ic;
1353 #ifndef IEEE80211_STA_ONLY
1354 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
1355 /* one less beacon until next DTIM */
1356 if (ic->ic_dtim_count == 0)
1357 ic->ic_dtim_count = ic->ic_dtim_period - 1;
1359 ic->ic_dtim_count--;
1361 /* update dynamic parts of beacon */
1362 rt2860_setup_beacon(sc);
1364 /* flush buffered multicast frames */
1365 if (ic->ic_dtim_count == 0)
1366 ieee80211_notify_dtim(ic);
1369 /* check if protection mode has changed */
1370 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) {
1371 rt2860_updateprot(sc);
1372 sc->sc_ic_flags = ic->ic_flags;
1378 rt2860_gp_intr(struct rt2860_softc *sc)
1380 struct ieee80211com *ic = &sc->sc_ic;
1381 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
1383 DPRINTFN(2, ("GP timeout state=%d\n", vap->iv_state));
1385 if (vap->iv_state == IEEE80211_S_RUN)
1386 rt2860_updatestats(sc);
1390 rt2860_intr(void *arg)
1392 struct rt2860_softc *sc = arg;
1397 r = RAL_READ(sc, RT2860_INT_STATUS);
1398 if (__predict_false(r == 0xffffffff)) {
1400 return; /* device likely went away */
1404 return; /* not for us */
1407 /* acknowledge interrupts */
1408 RAL_WRITE(sc, RT2860_INT_STATUS, r);
1410 if (r & RT2860_TX_RX_COHERENT)
1411 rt2860_intr_coherent(sc);
1413 if (r & RT2860_MAC_INT_2) /* TX status */
1414 rt2860_drain_stats_fifo(sc);
1416 if (r & RT2860_TX_DONE_INT5)
1417 rt2860_tx_intr(sc, 5);
1419 if (r & RT2860_RX_DONE_INT)
1422 if (r & RT2860_TX_DONE_INT4)
1423 rt2860_tx_intr(sc, 4);
1425 if (r & RT2860_TX_DONE_INT3)
1426 rt2860_tx_intr(sc, 3);
1428 if (r & RT2860_TX_DONE_INT2)
1429 rt2860_tx_intr(sc, 2);
1431 if (r & RT2860_TX_DONE_INT1)
1432 rt2860_tx_intr(sc, 1);
1434 if (r & RT2860_TX_DONE_INT0)
1435 rt2860_tx_intr(sc, 0);
1437 if (r & RT2860_MAC_INT_0) /* TBTT */
1438 rt2860_tbtt_intr(sc);
1440 if (r & RT2860_MAC_INT_3) /* Auto wakeup */
1443 if (r & RT2860_MAC_INT_4) /* GP timer */
1450 rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
1452 struct ieee80211com *ic = &sc->sc_ic;
1453 struct ieee80211vap *vap = ni->ni_vap;
1454 struct rt2860_tx_ring *ring;
1455 struct rt2860_tx_data *data;
1456 struct rt2860_txd *txd;
1457 struct rt2860_txwi *txwi;
1458 struct ieee80211_frame *wh;
1459 const struct ieee80211_txparam *tp;
1460 struct ieee80211_key *k;
1462 bus_dma_segment_t segs[RT2860_MAX_SCATTER];
1463 bus_dma_segment_t *seg;
1466 uint8_t type, qsel, mcs, pid, tid, qid;
1467 int i, nsegs, ntxds, pad, rate, ridx, error;
1469 /* the data pool contains at least one element, pick the first */
1470 data = SLIST_FIRST(&sc->data_pool);
1472 wh = mtod(m, struct ieee80211_frame *);
1474 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1475 k = ieee80211_crypto_encap(ni, m);
1481 /* packet header may have moved, reset our local pointer */
1482 wh = mtod(m, struct ieee80211_frame *);
1485 hdrlen = ieee80211_anyhdrsize(wh);
1486 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1488 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)];
1489 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1490 rate = tp->mcastrate;
1491 } else if (m->m_flags & M_EAPOL) {
1492 rate = tp->mgmtrate;
1493 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) {
1494 rate = tp->ucastrate;
1496 (void) ieee80211_ratectl_rate(ni, NULL, 0);
1497 rate = ni->ni_txrate;
1499 rate &= IEEE80211_RATE_VAL;
1501 qid = M_WME_GETAC(m);
1502 if (IEEE80211_QOS_HAS_SEQ(wh)) {
1503 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0];
1504 tid = qos & IEEE80211_QOS_TID;
1509 ring = &sc->txq[qid];
1510 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, rate);
1512 /* get MCS code from rate index */
1513 mcs = rt2860_rates[ridx].mcs;
1515 /* setup TX Wireless Information */
1518 /* let HW generate seq numbers for non-QoS frames */
1519 txwi->xflags = qos ? 0 : RT2860_TX_NSEQ;
1520 if (type == IEEE80211_FC0_TYPE_DATA)
1521 txwi->wcid = IEEE80211_AID(ni->ni_associd);
1524 txwi->len = htole16(m->m_pkthdr.len);
1525 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) {
1526 txwi->phy = htole16(RT2860_PHY_CCK);
1527 if (ridx != RT2860_RIDX_CCK1 &&
1528 (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1529 mcs |= RT2860_PHY_SHPRE;
1531 txwi->phy = htole16(RT2860_PHY_OFDM);
1532 txwi->phy |= htole16(mcs);
1535 * We store the MCS code into the driver-private PacketID field.
1536 * The PacketID is latched into TX_STAT_FIFO when Tx completes so
1537 * that we know at which initial rate the frame was transmitted.
1538 * We add 1 to the MCS code because setting the PacketID field to
1539 * 0 means that we don't want feedback in TX_STAT_FIFO.
1541 pid = (mcs + 1) & 0xf;
1542 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT);
1544 /* check if RTS/CTS or CTS-to-self protection is required */
1545 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1546 (m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold ||
1547 ((ic->ic_flags & IEEE80211_F_USEPROT) &&
1548 rt2860_rates[ridx].phy == IEEE80211_T_OFDM)))
1549 txwi->txop = RT2860_TX_TXOP_HT;
1551 txwi->txop = RT2860_TX_TXOP_BACKOFF;
1553 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1554 (!qos || (qos & IEEE80211_QOS_ACKPOLICY) !=
1555 IEEE80211_QOS_ACKPOLICY_NOACK)) {
1556 txwi->xflags |= RT2860_TX_ACK;
1558 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
1559 dur = rt2860_rates[ridx].sp_ack_dur;
1561 dur = rt2860_rates[ridx].lp_ack_dur;
1562 *(uint16_t *)wh->i_dur = htole16(dur);
1564 /* ask MAC to insert timestamp into probe responses */
1566 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
1567 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP))
1568 /* NOTE: beacons do not pass through tx_data() */
1569 txwi->flags |= RT2860_TX_TS;
1571 if (ieee80211_radiotap_active_vap(vap)) {
1572 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap;
1575 tap->wt_rate = rate;
1576 if (mcs & RT2860_PHY_SHPRE)
1577 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
1579 ieee80211_radiotap_tx(vap, m);
1582 pad = (hdrlen + 3) & ~3;
1584 /* copy and trim 802.11 header */
1585 memcpy(txwi + 1, wh, hdrlen);
1588 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs,
1590 if (__predict_false(error != 0 && error != EFBIG)) {
1591 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n",
1596 if (__predict_true(error == 0)) {
1597 /* determine how many TXDs are required */
1598 ntxds = 1 + (nsegs / 2);
1600 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) {
1601 /* not enough free TXDs, force mbuf defrag */
1602 bus_dmamap_unload(sc->txwi_dmat, data->map);
1606 if (__predict_false(error != 0)) {
1607 m1 = m_defrag(m, M_NOWAIT);
1609 device_printf(sc->sc_dev,
1610 "could not defragment mbuf\n");
1616 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m,
1618 if (__predict_false(error != 0)) {
1619 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n",
1625 /* determine how many TXDs are now required */
1626 ntxds = 1 + (nsegs / 2);
1628 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) {
1629 /* this is a hopeless case, drop the mbuf! */
1630 bus_dmamap_unload(sc->txwi_dmat, data->map);
1636 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT;
1638 /* first segment is TXWI + 802.11 header */
1639 txd = &ring->txd[ring->cur];
1640 txd->sdp0 = htole32(data->paddr);
1641 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad);
1644 /* setup payload segments */
1646 for (i = nsegs; i >= 2; i -= 2) {
1647 txd->sdp1 = htole32(seg->ds_addr);
1648 txd->sdl1 = htole16(seg->ds_len);
1650 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT;
1651 /* grab a new Tx descriptor */
1652 txd = &ring->txd[ring->cur];
1653 txd->sdp0 = htole32(seg->ds_addr);
1654 txd->sdl0 = htole16(seg->ds_len);
1658 /* finalize last segment */
1660 txd->sdp1 = htole32(seg->ds_addr);
1661 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1);
1663 txd->sdl0 |= htole16(RT2860_TX_LS0);
1667 /* remove from the free pool and link it into the SW Tx slot */
1668 SLIST_REMOVE_HEAD(&sc->data_pool, next);
1671 ring->data[ring->cur] = data;
1673 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE);
1674 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE);
1675 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
1677 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n",
1678 qid, txwi->wcid, nsegs, ridx));
1680 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT;
1681 ring->queued += ntxds;
1682 if (ring->queued >= RT2860_TX_RING_COUNT)
1683 sc->qfullmsk |= 1 << qid;
1686 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur);
1692 rt2860_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1693 const struct ieee80211_bpf_params *params)
1695 struct ieee80211com *ic = ni->ni_ic;
1696 struct rt2860_softc *sc = ic->ic_softc;
1701 /* prevent management frames from being sent if we're not ready */
1702 if (!(sc->sc_flags & RT2860_RUNNNING)) {
1705 ieee80211_free_node(ni);
1708 if (params == NULL) {
1710 * Legacy path; interpret frame contents to decide
1711 * precisely how to send the frame.
1713 error = rt2860_tx(sc, m, ni);
1716 * Caller supplied explicit parameters to use in
1717 * sending the frame.
1719 error = rt2860_tx_raw(sc, m, ni, params);
1722 /* NB: m is reclaimed on tx failure */
1723 ieee80211_free_node(ni);
1725 sc->sc_tx_timer = 5;
1731 rt2860_tx_raw(struct rt2860_softc *sc, struct mbuf *m,
1732 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params)
1734 struct ieee80211com *ic = &sc->sc_ic;
1735 struct ieee80211vap *vap = ni->ni_vap;
1736 struct rt2860_tx_ring *ring;
1737 struct rt2860_tx_data *data;
1738 struct rt2860_txd *txd;
1739 struct rt2860_txwi *txwi;
1740 struct ieee80211_frame *wh;
1742 bus_dma_segment_t segs[RT2860_MAX_SCATTER];
1743 bus_dma_segment_t *seg;
1746 uint8_t type, qsel, mcs, pid, tid, qid;
1747 int i, nsegs, ntxds, pad, rate, ridx, error;
1749 /* the data pool contains at least one element, pick the first */
1750 data = SLIST_FIRST(&sc->data_pool);
1752 wh = mtod(m, struct ieee80211_frame *);
1753 hdrlen = ieee80211_hdrsize(wh);
1754 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1756 /* Choose a TX rate index. */
1757 rate = params->ibp_rate0;
1758 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt,
1759 rate & IEEE80211_RATE_VAL);
1760 if (ridx == (uint8_t)-1) {
1761 /* XXX fall back to mcast/mgmt rate? */
1766 qid = params->ibp_pri & 3;
1768 ring = &sc->txq[qid];
1770 /* get MCS code from rate index */
1771 mcs = rt2860_rates[ridx].mcs;
1773 /* setup TX Wireless Information */
1776 /* let HW generate seq numbers for non-QoS frames */
1777 txwi->xflags = params->ibp_pri & 3 ? 0 : RT2860_TX_NSEQ;
1779 txwi->len = htole16(m->m_pkthdr.len);
1780 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) {
1781 txwi->phy = htole16(RT2860_PHY_CCK);
1782 if (ridx != RT2860_RIDX_CCK1 &&
1783 (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1784 mcs |= RT2860_PHY_SHPRE;
1786 txwi->phy = htole16(RT2860_PHY_OFDM);
1787 txwi->phy |= htole16(mcs);
1790 * We store the MCS code into the driver-private PacketID field.
1791 * The PacketID is latched into TX_STAT_FIFO when Tx completes so
1792 * that we know at which initial rate the frame was transmitted.
1793 * We add 1 to the MCS code because setting the PacketID field to
1794 * 0 means that we don't want feedback in TX_STAT_FIFO.
1796 pid = (mcs + 1) & 0xf;
1797 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT);
1799 /* check if RTS/CTS or CTS-to-self protection is required */
1800 if (params->ibp_flags & IEEE80211_BPF_RTS ||
1801 params->ibp_flags & IEEE80211_BPF_CTS)
1802 txwi->txop = RT2860_TX_TXOP_HT;
1804 txwi->txop = RT2860_TX_TXOP_BACKOFF;
1805 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) {
1806 txwi->xflags |= RT2860_TX_ACK;
1808 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
1809 dur = rt2860_rates[ridx].sp_ack_dur;
1811 dur = rt2860_rates[ridx].lp_ack_dur;
1812 *(uint16_t *)wh->i_dur = htole16(dur);
1814 /* ask MAC to insert timestamp into probe responses */
1816 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
1817 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP))
1818 /* NOTE: beacons do not pass through tx_data() */
1819 txwi->flags |= RT2860_TX_TS;
1821 if (ieee80211_radiotap_active_vap(vap)) {
1822 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap;
1825 tap->wt_rate = rate;
1826 if (mcs & RT2860_PHY_SHPRE)
1827 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
1829 ieee80211_radiotap_tx(vap, m);
1832 pad = (hdrlen + 3) & ~3;
1834 /* copy and trim 802.11 header */
1835 memcpy(txwi + 1, wh, hdrlen);
1838 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs,
1840 if (__predict_false(error != 0 && error != EFBIG)) {
1841 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n",
1846 if (__predict_true(error == 0)) {
1847 /* determine how many TXDs are required */
1848 ntxds = 1 + (nsegs / 2);
1850 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) {
1851 /* not enough free TXDs, force mbuf defrag */
1852 bus_dmamap_unload(sc->txwi_dmat, data->map);
1856 if (__predict_false(error != 0)) {
1857 m1 = m_defrag(m, M_NOWAIT);
1859 device_printf(sc->sc_dev,
1860 "could not defragment mbuf\n");
1866 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m,
1868 if (__predict_false(error != 0)) {
1869 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n",
1875 /* determine how many TXDs are now required */
1876 ntxds = 1 + (nsegs / 2);
1878 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) {
1879 /* this is a hopeless case, drop the mbuf! */
1880 bus_dmamap_unload(sc->txwi_dmat, data->map);
1886 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT;
1888 /* first segment is TXWI + 802.11 header */
1889 txd = &ring->txd[ring->cur];
1890 txd->sdp0 = htole32(data->paddr);
1891 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad);
1894 /* setup payload segments */
1896 for (i = nsegs; i >= 2; i -= 2) {
1897 txd->sdp1 = htole32(seg->ds_addr);
1898 txd->sdl1 = htole16(seg->ds_len);
1900 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT;
1901 /* grab a new Tx descriptor */
1902 txd = &ring->txd[ring->cur];
1903 txd->sdp0 = htole32(seg->ds_addr);
1904 txd->sdl0 = htole16(seg->ds_len);
1908 /* finalize last segment */
1910 txd->sdp1 = htole32(seg->ds_addr);
1911 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1);
1913 txd->sdl0 |= htole16(RT2860_TX_LS0);
1917 /* remove from the free pool and link it into the SW Tx slot */
1918 SLIST_REMOVE_HEAD(&sc->data_pool, next);
1921 ring->data[ring->cur] = data;
1923 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE);
1924 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE);
1925 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
1927 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n",
1928 qid, txwi->wcid, nsegs, ridx));
1930 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT;
1931 ring->queued += ntxds;
1932 if (ring->queued >= RT2860_TX_RING_COUNT)
1933 sc->qfullmsk |= 1 << qid;
1936 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur);
1942 rt2860_transmit(struct ieee80211com *ic, struct mbuf *m)
1944 struct rt2860_softc *sc = ic->ic_softc;
1948 if ((sc->sc_flags & RT2860_RUNNNING) == 0) {
1952 error = mbufq_enqueue(&sc->sc_snd, m);
1964 rt2860_start(struct rt2860_softc *sc)
1966 struct ieee80211_node *ni;
1969 RAL_LOCK_ASSERT(sc);
1971 if ((sc->sc_flags & RT2860_RUNNNING) == 0)
1974 while (!SLIST_EMPTY(&sc->data_pool) && sc->qfullmsk == 0 &&
1975 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
1976 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1977 if (rt2860_tx(sc, m, ni) != 0) {
1978 if_inc_counter(ni->ni_vap->iv_ifp,
1979 IFCOUNTER_OERRORS, 1);
1980 ieee80211_free_node(ni);
1983 sc->sc_tx_timer = 5;
1988 rt2860_watchdog(void *arg)
1990 struct rt2860_softc *sc = arg;
1992 RAL_LOCK_ASSERT(sc);
1994 KASSERT(sc->sc_flags & RT2860_RUNNNING, ("not running"));
1996 if (sc->sc_invalid) /* card ejected */
1999 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) {
2000 device_printf(sc->sc_dev, "device timeout\n");
2001 rt2860_stop_locked(sc);
2002 rt2860_init_locked(sc);
2003 counter_u64_add(sc->sc_ic.ic_oerrors, 1);
2006 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc);
2010 rt2860_parent(struct ieee80211com *ic)
2012 struct rt2860_softc *sc = ic->ic_softc;
2016 if (ic->ic_nrunning> 0) {
2017 if (!(sc->sc_flags & RT2860_RUNNNING)) {
2018 rt2860_init_locked(sc);
2021 rt2860_update_promisc(ic);
2022 } else if (sc->sc_flags & RT2860_RUNNNING)
2023 rt2860_stop_locked(sc);
2026 ieee80211_start_all(ic);
2030 * Reading and writing from/to the BBP is different from RT2560 and RT2661.
2031 * We access the BBP through the 8051 microcontroller unit which means that
2032 * the microcode must be loaded first.
2035 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)
2039 for (ntries = 0; ntries < 100; ntries++) {
2040 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK))
2044 if (ntries == 100) {
2045 device_printf(sc->sc_dev,
2046 "could not write to BBP through MCU\n");
2050 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL |
2051 RT2860_BBP_CSR_KICK | reg << 8 | val);
2052 RAL_BARRIER_WRITE(sc);
2054 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0);
2059 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg)
2064 for (ntries = 0; ntries < 100; ntries++) {
2065 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK))
2069 if (ntries == 100) {
2070 device_printf(sc->sc_dev,
2071 "could not read from BBP through MCU\n");
2075 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL |
2076 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8);
2077 RAL_BARRIER_WRITE(sc);
2079 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0);
2082 for (ntries = 0; ntries < 100; ntries++) {
2083 val = RAL_READ(sc, RT2860_H2M_BBPAGENT);
2084 if (!(val & RT2860_BBP_CSR_KICK))
2088 device_printf(sc->sc_dev, "could not read from BBP through MCU\n");
2094 * Write to one of the 4 programmable 24-bit RF registers.
2097 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val)
2102 for (ntries = 0; ntries < 100; ntries++) {
2103 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL))
2107 if (ntries == 100) {
2108 device_printf(sc->sc_dev, "could not write to RF\n");
2112 /* RF registers are 24-bit on the RT2860 */
2113 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT |
2114 (val & 0x3fffff) << 2 | (reg & 3);
2115 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp);
2119 rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg)
2124 for (ntries = 0; ntries < 100; ntries++) {
2125 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK))
2129 if (ntries == 100) {
2130 device_printf(sc->sc_dev, "could not read RF register\n");
2133 tmp = RT3070_RF_KICK | reg << 8;
2134 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp);
2136 for (ntries = 0; ntries < 100; ntries++) {
2137 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG);
2138 if (!(tmp & RT3070_RF_KICK))
2142 if (ntries == 100) {
2143 device_printf(sc->sc_dev, "could not read RF register\n");
2150 rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val)
2155 for (ntries = 0; ntries < 10; ntries++) {
2156 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK))
2161 device_printf(sc->sc_dev, "could not write to RF\n");
2165 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val;
2166 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp);
2170 * Send a command to the 8051 microcontroller unit.
2173 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait)
2179 for (ntries = 0; ntries < 100; ntries++) {
2180 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY))
2187 cid = wait ? cmd : RT2860_TOKEN_NO_INTR;
2188 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg);
2189 RAL_BARRIER_WRITE(sc);
2190 RAL_WRITE(sc, RT2860_HOST_CMD, cmd);
2194 /* wait for the command to complete */
2195 for (ntries = 0; ntries < 200; ntries++) {
2196 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID);
2197 /* find the command slot */
2198 for (slot = 0; slot < 4; slot++, tmp >>= 8)
2199 if ((tmp & 0xff) == cid)
2205 if (ntries == 200) {
2206 /* clear command and status */
2207 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff);
2208 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff);
2211 /* get command status (1 means success) */
2212 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS);
2213 tmp = (tmp >> (slot * 8)) & 0xff;
2214 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n",
2216 /* clear command and status */
2217 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff);
2218 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff);
2219 return (tmp == 1) ? 0 : EIO;
2223 rt2860_enable_mrr(struct rt2860_softc *sc)
2225 #define CCK(mcs) (mcs)
2226 #define OFDM(mcs) (1 << 3 | (mcs))
2227 RAL_WRITE(sc, RT2860_LG_FBK_CFG0,
2228 OFDM(6) << 28 | /* 54->48 */
2229 OFDM(5) << 24 | /* 48->36 */
2230 OFDM(4) << 20 | /* 36->24 */
2231 OFDM(3) << 16 | /* 24->18 */
2232 OFDM(2) << 12 | /* 18->12 */
2233 OFDM(1) << 8 | /* 12-> 9 */
2234 OFDM(0) << 4 | /* 9-> 6 */
2235 OFDM(0)); /* 6-> 6 */
2237 RAL_WRITE(sc, RT2860_LG_FBK_CFG1,
2238 CCK(2) << 12 | /* 11->5.5 */
2239 CCK(1) << 8 | /* 5.5-> 2 */
2240 CCK(0) << 4 | /* 2-> 1 */
2241 CCK(0)); /* 1-> 1 */
2247 rt2860_set_txpreamble(struct rt2860_softc *sc)
2249 struct ieee80211com *ic = &sc->sc_ic;
2252 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG);
2253 tmp &= ~RT2860_CCK_SHORT_EN;
2254 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
2255 tmp |= RT2860_CCK_SHORT_EN;
2256 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp);
2260 rt2860_set_basicrates(struct rt2860_softc *sc,
2261 const struct ieee80211_rateset *rs)
2263 #define RV(r) ((r) & IEEE80211_RATE_VAL)
2264 struct ieee80211com *ic = &sc->sc_ic;
2269 for (i = 0; i < rs->rs_nrates; i++) {
2270 rate = rs->rs_rates[i];
2272 if (!(rate & IEEE80211_RATE_BASIC))
2275 mask |= 1 << ieee80211_legacy_rate_lookup(ic->ic_rt, RV(rate));
2278 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, mask);
2283 rt2860_scan_start(struct ieee80211com *ic)
2285 struct rt2860_softc *sc = ic->ic_softc;
2288 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG);
2289 RAL_WRITE(sc, RT2860_BCN_TIME_CFG,
2290 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN |
2291 RT2860_TBTT_TIMER_EN));
2292 rt2860_set_gp_timer(sc, 0);
2296 rt2860_scan_end(struct ieee80211com *ic)
2298 struct rt2860_softc *sc = ic->ic_softc;
2299 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2301 if (vap->iv_state == IEEE80211_S_RUN) {
2302 rt2860_enable_tsf_sync(sc);
2303 rt2860_set_gp_timer(sc, 500);
2308 rt2860_set_channel(struct ieee80211com *ic)
2310 struct rt2860_softc *sc = ic->ic_softc;
2313 rt2860_switch_chan(sc, ic->ic_curchan);
2318 rt2860_select_chan_group(struct rt2860_softc *sc, int group)
2323 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]);
2324 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]);
2325 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]);
2326 rt2860_mcu_bbp_write(sc, 86, 0x00);
2329 if (sc->ext_2ghz_lna) {
2330 rt2860_mcu_bbp_write(sc, 82, 0x62);
2331 rt2860_mcu_bbp_write(sc, 75, 0x46);
2333 rt2860_mcu_bbp_write(sc, 82, 0x84);
2334 rt2860_mcu_bbp_write(sc, 75, 0x50);
2337 if (sc->ext_5ghz_lna) {
2338 rt2860_mcu_bbp_write(sc, 82, 0xf2);
2339 rt2860_mcu_bbp_write(sc, 75, 0x46);
2341 rt2860_mcu_bbp_write(sc, 82, 0xf2);
2342 rt2860_mcu_bbp_write(sc, 75, 0x50);
2346 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG);
2347 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P);
2348 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P;
2349 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp);
2351 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */
2352 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN;
2353 if (sc->nrxchains > 1)
2354 tmp |= RT2860_LNA_PE1_EN;
2355 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2)
2356 tmp |= RT3593_LNA_PE2_EN;
2357 if (group == 0) { /* 2GHz */
2358 tmp |= RT2860_PA_PE_G0_EN;
2359 if (sc->ntxchains > 1)
2360 tmp |= RT2860_PA_PE_G1_EN;
2361 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2)
2362 tmp |= RT3593_PA_PE_G2_EN;
2364 tmp |= RT2860_PA_PE_A0_EN;
2365 if (sc->ntxchains > 1)
2366 tmp |= RT2860_PA_PE_A1_EN;
2367 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2)
2368 tmp |= RT3593_PA_PE_A2_EN;
2370 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp);
2372 if (sc->mac_ver == 0x3593) {
2373 tmp = RAL_READ(sc, RT2860_GPIO_CTRL);
2374 if (sc->sc_flags & RT2860_PCIE) {
2383 tmp = (tmp & ~0x00001000) | 0x00000010;
2384 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp);
2387 /* set initial AGC value */
2388 if (group == 0) { /* 2GHz band */
2389 if (sc->mac_ver >= 0x3071)
2390 agc = 0x1c + sc->lna[0] * 2;
2392 agc = 0x2e + sc->lna[0];
2393 } else { /* 5GHz band */
2394 agc = 0x32 + (sc->lna[group] * 5) / 3;
2396 rt2860_mcu_bbp_write(sc, 66, agc);
2402 rt2860_set_chan(struct rt2860_softc *sc, u_int chan)
2404 const struct rfprog *rfprog = rt2860_rf2850;
2405 uint32_t r2, r3, r4;
2406 int8_t txpow1, txpow2;
2409 /* find the settings for this channel (we know it exists) */
2410 for (i = 0; rfprog[i].chan != chan; i++);
2413 if (sc->ntxchains == 1)
2414 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */
2415 if (sc->nrxchains == 1)
2416 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */
2417 else if (sc->nrxchains == 2)
2418 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */
2420 /* use Tx power values from EEPROM */
2421 txpow1 = sc->txpow1[i];
2422 txpow2 = sc->txpow2[i];
2425 txpow1 = txpow1 << 1 | 1;
2427 txpow1 = (7 + txpow1) << 1;
2429 txpow2 = txpow2 << 1 | 1;
2431 txpow2 = (7 + txpow2) << 1;
2433 r3 = rfprog[i].r3 | txpow1 << 7;
2434 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4;
2436 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1);
2437 rt2860_rf_write(sc, RT2860_RF2, r2);
2438 rt2860_rf_write(sc, RT2860_RF3, r3);
2439 rt2860_rf_write(sc, RT2860_RF4, r4);
2443 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1);
2444 rt2860_rf_write(sc, RT2860_RF2, r2);
2445 rt2860_rf_write(sc, RT2860_RF3, r3 | 1);
2446 rt2860_rf_write(sc, RT2860_RF4, r4);
2450 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1);
2451 rt2860_rf_write(sc, RT2860_RF2, r2);
2452 rt2860_rf_write(sc, RT2860_RF3, r3);
2453 rt2860_rf_write(sc, RT2860_RF4, r4);
2457 rt3090_set_chan(struct rt2860_softc *sc, u_int chan)
2459 int8_t txpow1, txpow2;
2463 /* RT3090 is 2GHz only */
2464 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan));
2466 /* find the settings for this channel (we know it exists) */
2467 for (i = 0; rt2860_rf2850[i].chan != chan; i++);
2469 /* use Tx power values from EEPROM */
2470 txpow1 = sc->txpow1[i];
2471 txpow2 = sc->txpow2[i];
2473 rt3090_rf_write(sc, 2, rt3090_freqs[i].n);
2474 rf = rt3090_rf_read(sc, 3);
2475 rf = (rf & ~0x0f) | rt3090_freqs[i].k;
2476 rt3090_rf_write(sc, 3, rf);
2477 rf = rt3090_rf_read(sc, 6);
2478 rf = (rf & ~0x03) | rt3090_freqs[i].r;
2479 rt3090_rf_write(sc, 6, rf);
2482 rf = rt3090_rf_read(sc, 12);
2483 rf = (rf & ~0x1f) | txpow1;
2484 rt3090_rf_write(sc, 12, rf);
2487 rf = rt3090_rf_read(sc, 13);
2488 rf = (rf & ~0x1f) | txpow2;
2489 rt3090_rf_write(sc, 13, rf);
2491 rf = rt3090_rf_read(sc, 1);
2493 if (sc->ntxchains == 1)
2494 rf |= RT3070_TX1_PD | RT3070_TX2_PD;
2495 else if (sc->ntxchains == 2)
2496 rf |= RT3070_TX2_PD;
2497 if (sc->nrxchains == 1)
2498 rf |= RT3070_RX1_PD | RT3070_RX2_PD;
2499 else if (sc->nrxchains == 2)
2500 rf |= RT3070_RX2_PD;
2501 rt3090_rf_write(sc, 1, rf);
2504 rf = rt3090_rf_read(sc, 23);
2505 rf = (rf & ~0x7f) | sc->freq;
2506 rt3090_rf_write(sc, 23, rf);
2508 /* program RF filter */
2509 rf = rt3090_rf_read(sc, 24); /* Tx */
2510 rf = (rf & ~0x3f) | sc->rf24_20mhz;
2511 rt3090_rf_write(sc, 24, rf);
2512 rf = rt3090_rf_read(sc, 31); /* Rx */
2513 rf = (rf & ~0x3f) | sc->rf24_20mhz;
2514 rt3090_rf_write(sc, 31, rf);
2516 /* enable RF tuning */
2517 rf = rt3090_rf_read(sc, 7);
2518 rt3090_rf_write(sc, 7, rf | RT3070_TUNE);
2522 rt5390_set_chan(struct rt2860_softc *sc, u_int chan)
2524 uint8_t h20mhz, rf, tmp;
2525 int8_t txpow1, txpow2;
2528 /* RT5390 is 2GHz only */
2529 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan));
2531 /* find the settings for this channel (we know it exists) */
2532 for (i = 0; rt2860_rf2850[i].chan != chan; i++);
2534 /* use Tx power values from EEPROM */
2535 txpow1 = sc->txpow1[i];
2536 txpow2 = sc->txpow2[i];
2538 rt3090_rf_write(sc, 8, rt3090_freqs[i].n);
2539 rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f);
2540 rf = rt3090_rf_read(sc, 11);
2541 rf = (rf & ~0x03) | (rt3090_freqs[i].r & 0x03);
2542 rt3090_rf_write(sc, 11, rf);
2544 rf = rt3090_rf_read(sc, 49);
2545 rf = (rf & ~0x3f) | (txpow1 & 0x3f);
2546 /* the valid range of the RF R49 is 0x00~0x27 */
2547 if ((rf & 0x3f) > 0x27)
2548 rf = (rf & ~0x3f) | 0x27;
2549 rt3090_rf_write(sc, 49, rf);
2550 if (sc->mac_ver == 0x5392) {
2551 rf = rt3090_rf_read(sc, 50);
2552 rf = (rf & ~0x3f) | (txpow2 & 0x3f);
2553 /* the valid range of the RF R50 is 0x00~0x27 */
2554 if ((rf & 0x3f) > 0x27)
2555 rf = (rf & ~0x3f) | 0x27;
2556 rt3090_rf_write(sc, 50, rf);
2559 rf = rt3090_rf_read(sc, 1);
2560 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD;
2561 if (sc->mac_ver == 0x5392)
2562 rf |= RT3070_RX1_PD | RT3070_TX1_PD;
2563 rt3090_rf_write(sc, 1, rf);
2565 rf = rt3090_rf_read(sc, 2);
2566 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL);
2568 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL);
2570 rf = rt3090_rf_read(sc, 17);
2572 rf = (rf & ~0x7f) | (sc->freq & 0x7f);
2575 rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0);
2577 if (sc->mac_ver == 0x5390) {
2580 else if (chan >= 5 && chan <= 6)
2582 else if (chan >= 7 && chan <= 10)
2586 rt3090_rf_write(sc, 55, rf);
2594 else if (chan >= 4 && chan <= 6)
2596 else if (chan >= 7 && chan <= 12)
2598 else if (chan == 13)
2602 rt3090_rf_write(sc, 59, rf);
2606 h20mhz = (sc->rf24_20mhz & 0x20) >> 5;
2607 rf = rt3090_rf_read(sc, 30);
2608 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2);
2609 rt3090_rf_write(sc, 30, rf);
2611 /* Rx BB filter VCM */
2612 rf = rt3090_rf_read(sc, 30);
2613 rf = (rf & ~0x18) | 0x10;
2614 rt3090_rf_write(sc, 30, rf);
2616 /* Initiate VCO calibration. */
2617 rf = rt3090_rf_read(sc, 3);
2618 rf |= RT3593_VCOCAL;
2619 rt3090_rf_write(sc, 3, rf);
2623 rt3090_rf_init(struct rt2860_softc *sc)
2629 rf = rt3090_rf_read(sc, 30);
2630 /* toggle RF R30 bit 7 */
2631 rt3090_rf_write(sc, 30, rf | 0x80);
2633 rt3090_rf_write(sc, 30, rf & ~0x80);
2635 tmp = RAL_READ(sc, RT3070_LDO_CFG0);
2637 if (sc->patch_dac && sc->mac_rev < 0x0211)
2638 tmp |= 0x0d000000; /* 1.35V */
2640 tmp |= 0x01000000; /* 1.2V */
2641 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp);
2643 /* patch LNA_PE_G1 */
2644 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH);
2645 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20);
2647 /* initialize RF registers to default value */
2648 for (i = 0; i < nitems(rt3090_def_rf); i++) {
2649 rt3090_rf_write(sc, rt3090_def_rf[i].reg,
2650 rt3090_def_rf[i].val);
2653 /* select 20MHz bandwidth */
2654 rt3090_rf_write(sc, 31, 0x14);
2656 rf = rt3090_rf_read(sc, 6);
2657 rt3090_rf_write(sc, 6, rf | 0x40);
2659 if (sc->mac_ver != 0x3593) {
2660 /* calibrate filter for 20MHz bandwidth */
2661 sc->rf24_20mhz = 0x1f; /* default value */
2662 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz);
2664 /* select 40MHz bandwidth */
2665 bbp = rt2860_mcu_bbp_read(sc, 4);
2666 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10);
2667 rf = rt3090_rf_read(sc, 31);
2668 rt3090_rf_write(sc, 31, rf | 0x20);
2670 /* calibrate filter for 40MHz bandwidth */
2671 sc->rf24_40mhz = 0x2f; /* default value */
2672 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz);
2674 /* go back to 20MHz bandwidth */
2675 bbp = rt2860_mcu_bbp_read(sc, 4);
2676 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18);
2678 if (sc->mac_rev < 0x0211)
2679 rt3090_rf_write(sc, 27, 0x03);
2681 tmp = RAL_READ(sc, RT3070_OPT_14);
2682 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1);
2684 if (sc->rf_rev == RT3070_RF_3020)
2685 rt3090_set_rx_antenna(sc, 0);
2687 bbp = rt2860_mcu_bbp_read(sc, 138);
2688 if (sc->mac_ver == 0x3593) {
2689 if (sc->ntxchains == 1)
2690 bbp |= 0x60; /* turn off DAC1 and DAC2 */
2691 else if (sc->ntxchains == 2)
2692 bbp |= 0x40; /* turn off DAC2 */
2693 if (sc->nrxchains == 1)
2694 bbp &= ~0x06; /* turn off ADC1 and ADC2 */
2695 else if (sc->nrxchains == 2)
2696 bbp &= ~0x04; /* turn off ADC2 */
2698 if (sc->ntxchains == 1)
2699 bbp |= 0x20; /* turn off DAC1 */
2700 if (sc->nrxchains == 1)
2701 bbp &= ~0x02; /* turn off ADC1 */
2703 rt2860_mcu_bbp_write(sc, 138, bbp);
2705 rf = rt3090_rf_read(sc, 1);
2706 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD);
2707 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD;
2708 rt3090_rf_write(sc, 1, rf);
2710 rf = rt3090_rf_read(sc, 15);
2711 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2);
2713 rf = rt3090_rf_read(sc, 17);
2714 rf &= ~RT3070_TX_LO1;
2715 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna)
2716 rf |= 0x20; /* fix for long range Rx issue */
2717 if (sc->txmixgain_2ghz >= 2)
2718 rf = (rf & ~0x7) | sc->txmixgain_2ghz;
2719 rt3090_rf_write(sc, 17, rf);
2721 rf = rt3090_rf_read(sc, 20);
2722 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1);
2724 rf = rt3090_rf_read(sc, 21);
2725 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2);
2731 rt5390_rf_init(struct rt2860_softc *sc)
2736 rf = rt3090_rf_read(sc, 2);
2737 /* Toggle RF R2 bit 7. */
2738 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL);
2740 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL);
2742 /* Initialize RF registers to default value. */
2743 if (sc->mac_ver == 0x5392) {
2744 for (i = 0; i < nitems(rt5392_def_rf); i++) {
2745 rt3090_rf_write(sc, rt5392_def_rf[i].reg,
2746 rt5392_def_rf[i].val);
2749 for (i = 0; i < nitems(rt5390_def_rf); i++) {
2750 rt3090_rf_write(sc, rt5390_def_rf[i].reg,
2751 rt5390_def_rf[i].val);
2755 sc->rf24_20mhz = 0x1f;
2756 sc->rf24_40mhz = 0x2f;
2758 if (sc->mac_rev < 0x0211)
2759 rt3090_rf_write(sc, 27, 0x03);
2761 /* Set led open drain enable. */
2762 RAL_WRITE(sc, RT3070_OPT_14, RAL_READ(sc, RT3070_OPT_14) | 1);
2764 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0);
2765 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0);
2767 if (sc->mac_ver == 0x5390)
2768 rt3090_set_rx_antenna(sc, 0);
2770 /* Patch RSSI inaccurate issue. */
2771 rt2860_mcu_bbp_write(sc, 79, 0x13);
2772 rt2860_mcu_bbp_write(sc, 80, 0x05);
2773 rt2860_mcu_bbp_write(sc, 81, 0x33);
2775 /* Enable DC filter. */
2776 if (sc->mac_rev >= 0x0211)
2777 rt2860_mcu_bbp_write(sc, 103, 0xc0);
2779 bbp = rt2860_mcu_bbp_read(sc, 138);
2780 if (sc->ntxchains == 1)
2781 bbp |= 0x20; /* Turn off DAC1. */
2782 if (sc->nrxchains == 1)
2783 bbp &= ~0x02; /* Turn off ADC1. */
2784 rt2860_mcu_bbp_write(sc, 138, bbp);
2786 /* Enable RX LO1 and LO2. */
2787 rt3090_rf_write(sc, 38, rt3090_rf_read(sc, 38) & ~RT5390_RX_LO1);
2788 rt3090_rf_write(sc, 39, rt3090_rf_read(sc, 39) & ~RT5390_RX_LO2);
2790 /* Avoid data lost and CRC error. */
2791 rt2860_mcu_bbp_write(sc, 4,
2792 rt2860_mcu_bbp_read(sc, 4) | RT5390_MAC_IF_CTRL);
2794 rf = rt3090_rf_read(sc, 30);
2795 rf = (rf & ~0x18) | 0x10;
2796 rt3090_rf_write(sc, 30, rf);
2800 rt3090_rf_wakeup(struct rt2860_softc *sc)
2805 if (sc->mac_ver == 0x3593) {
2807 rf = rt3090_rf_read(sc, 1);
2808 rt3090_rf_write(sc, 1, rf | RT3593_VCO);
2810 /* initiate VCO calibration */
2811 rf = rt3090_rf_read(sc, 3);
2812 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL);
2814 /* enable VCO bias current control */
2815 rf = rt3090_rf_read(sc, 6);
2816 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC);
2818 /* initiate res calibration */
2819 rf = rt3090_rf_read(sc, 2);
2820 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL);
2822 /* set reference current control to 0.33 mA */
2823 rf = rt3090_rf_read(sc, 22);
2824 rf &= ~RT3593_CP_IC_MASK;
2825 rf |= 1 << RT3593_CP_IC_SHIFT;
2826 rt3090_rf_write(sc, 22, rf);
2829 rf = rt3090_rf_read(sc, 46);
2830 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB);
2832 rf = rt3090_rf_read(sc, 20);
2833 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK);
2834 rt3090_rf_write(sc, 20, rf);
2836 /* enable RF block */
2837 rf = rt3090_rf_read(sc, 1);
2838 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK);
2840 /* enable VCO bias current control */
2841 rf = rt3090_rf_read(sc, 7);
2842 rt3090_rf_write(sc, 7, rf | 0x30);
2844 rf = rt3090_rf_read(sc, 9);
2845 rt3090_rf_write(sc, 9, rf | 0x0e);
2848 rf = rt3090_rf_read(sc, 21);
2849 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB);
2851 /* fix Tx to Rx IQ glitch by raising RF voltage */
2852 rf = rt3090_rf_read(sc, 27);
2854 if (sc->mac_rev < 0x0211)
2856 rt3090_rf_write(sc, 27, rf);
2858 if (sc->patch_dac && sc->mac_rev < 0x0211) {
2859 tmp = RAL_READ(sc, RT3070_LDO_CFG0);
2860 tmp = (tmp & ~0x1f000000) | 0x0d000000;
2861 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp);
2866 rt5390_rf_wakeup(struct rt2860_softc *sc)
2871 rf = rt3090_rf_read(sc, 1);
2872 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD |
2874 if (sc->mac_ver == 0x5392)
2875 rf |= RT3070_RX1_PD | RT3070_TX1_PD;
2876 rt3090_rf_write(sc, 1, rf);
2878 rf = rt3090_rf_read(sc, 6);
2879 rf |= RT3593_VCO_IC | RT3593_VCOCAL;
2880 if (sc->mac_ver == 0x5390)
2881 rf &= ~RT3593_VCO_IC;
2882 rt3090_rf_write(sc, 6, rf);
2884 rt3090_rf_write(sc, 2, rt3090_rf_read(sc, 2) | RT3593_RESCAL);
2886 rf = rt3090_rf_read(sc, 22);
2887 rf = (rf & ~0xe0) | 0x20;
2888 rt3090_rf_write(sc, 22, rf);
2890 rt3090_rf_write(sc, 42, rt3090_rf_read(sc, 42) | RT5390_RX_CTB);
2891 rt3090_rf_write(sc, 20, rt3090_rf_read(sc, 20) & ~0x77);
2892 rt3090_rf_write(sc, 3, rt3090_rf_read(sc, 3) | RT3593_VCOCAL);
2894 if (sc->patch_dac && sc->mac_rev < 0x0211) {
2895 tmp = RAL_READ(sc, RT3070_LDO_CFG0);
2896 tmp = (tmp & ~0x1f000000) | 0x0d000000;
2897 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp);
2902 rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target,
2906 uint8_t bbp55_pb, bbp55_sb, delta;
2909 /* program filter */
2910 rf24 = rt3090_rf_read(sc, 24);
2911 rf24 = (rf24 & 0xc0) | init; /* initial filter value */
2912 rt3090_rf_write(sc, 24, rf24);
2914 /* enable baseband loopback mode */
2915 rf22 = rt3090_rf_read(sc, 22);
2916 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK);
2918 /* set power and frequency of passband test tone */
2919 rt2860_mcu_bbp_write(sc, 24, 0x00);
2920 for (ntries = 0; ntries < 100; ntries++) {
2921 /* transmit test tone */
2922 rt2860_mcu_bbp_write(sc, 25, 0x90);
2924 /* read received power */
2925 bbp55_pb = rt2860_mcu_bbp_read(sc, 55);
2932 /* set power and frequency of stopband test tone */
2933 rt2860_mcu_bbp_write(sc, 24, 0x06);
2934 for (ntries = 0; ntries < 100; ntries++) {
2935 /* transmit test tone */
2936 rt2860_mcu_bbp_write(sc, 25, 0x90);
2938 /* read received power */
2939 bbp55_sb = rt2860_mcu_bbp_read(sc, 55);
2941 delta = bbp55_pb - bbp55_sb;
2945 /* reprogram filter */
2947 rt3090_rf_write(sc, 24, rf24);
2951 rf24--; /* backtrack */
2953 rt3090_rf_write(sc, 24, rf24);
2956 /* restore initial state */
2957 rt2860_mcu_bbp_write(sc, 24, 0x00);
2959 /* disable baseband loopback mode */
2960 rf22 = rt3090_rf_read(sc, 22);
2961 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK);
2967 rt3090_rf_setup(struct rt2860_softc *sc)
2972 if (sc->mac_rev >= 0x0211) {
2973 /* enable DC filter */
2974 rt2860_mcu_bbp_write(sc, 103, 0xc0);
2976 /* improve power consumption */
2977 bbp = rt2860_mcu_bbp_read(sc, 31);
2978 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03);
2981 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0);
2982 if (sc->mac_rev < 0x0211) {
2983 RAL_WRITE(sc, RT2860_TX_SW_CFG2,
2984 sc->patch_dac ? 0x2c : 0x0f);
2986 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0);
2988 /* initialize RF registers from ROM */
2989 if (sc->mac_ver < 0x5390) {
2990 for (i = 0; i < 10; i++) {
2991 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff)
2993 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val);
2999 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which)
3001 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS,
3002 which | (sc->leds & 0x7f), 0);
3006 * Hardware has a general-purpose programmable timer interrupt that can
3007 * periodically raise MAC_INT_4.
3010 rt2860_set_gp_timer(struct rt2860_softc *sc, int ms)
3014 /* disable GP timer before reprogramming it */
3015 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN);
3016 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN);
3021 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG);
3022 ms *= 16; /* Unit: 64us */
3023 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT;
3024 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp);
3026 /* enable GP timer */
3027 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN);
3028 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN);
3032 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid)
3034 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0,
3035 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24);
3036 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1,
3037 bssid[4] | bssid[5] << 8);
3041 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr)
3043 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0,
3044 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3045 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1,
3046 addr[4] | addr[5] << 8 | 0xff << 16);
3050 rt2860_updateslot(struct ieee80211com *ic)
3052 struct rt2860_softc *sc = ic->ic_softc;
3055 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG);
3057 tmp |= (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20;
3058 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp);
3062 rt2860_updateprot(struct rt2860_softc *sc)
3064 struct ieee80211com *ic = &sc->sc_ic;
3067 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL;
3068 /* setup protection frame rate (MCS code) */
3069 tmp |= IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ?
3070 rt2860_rates[RT2860_RIDX_OFDM6].mcs :
3071 rt2860_rates[RT2860_RIDX_CCK11].mcs;
3073 /* CCK frames don't require protection */
3074 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp);
3076 if (ic->ic_flags & IEEE80211_F_USEPROT) {
3077 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
3078 tmp |= RT2860_PROT_CTRL_RTS_CTS;
3079 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
3080 tmp |= RT2860_PROT_CTRL_CTS;
3082 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp);
3086 rt2860_update_promisc(struct ieee80211com *ic)
3088 struct rt2860_softc *sc = ic->ic_softc;
3091 tmp = RAL_READ(sc, RT2860_RX_FILTR_CFG);
3092 tmp &= ~RT2860_DROP_NOT_MYBSS;
3093 if (ic->ic_promisc == 0)
3094 tmp |= RT2860_DROP_NOT_MYBSS;
3095 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp);
3099 rt2860_updateedca(struct ieee80211com *ic)
3101 struct rt2860_softc *sc = ic->ic_softc;
3102 const struct wmeParams *wmep;
3105 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams;
3107 /* update MAC TX configuration registers */
3108 for (aci = 0; aci < WME_NUM_AC; aci++) {
3109 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci),
3110 wmep[aci].wmep_logcwmax << 16 |
3111 wmep[aci].wmep_logcwmin << 12 |
3112 wmep[aci].wmep_aifsn << 8 |
3113 wmep[aci].wmep_txopLimit);
3116 /* update SCH/DMA registers too */
3117 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG,
3118 wmep[WME_AC_VO].wmep_aifsn << 12 |
3119 wmep[WME_AC_VI].wmep_aifsn << 8 |
3120 wmep[WME_AC_BK].wmep_aifsn << 4 |
3121 wmep[WME_AC_BE].wmep_aifsn);
3122 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG,
3123 wmep[WME_AC_VO].wmep_logcwmin << 12 |
3124 wmep[WME_AC_VI].wmep_logcwmin << 8 |
3125 wmep[WME_AC_BK].wmep_logcwmin << 4 |
3126 wmep[WME_AC_BE].wmep_logcwmin);
3127 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG,
3128 wmep[WME_AC_VO].wmep_logcwmax << 12 |
3129 wmep[WME_AC_VI].wmep_logcwmax << 8 |
3130 wmep[WME_AC_BK].wmep_logcwmax << 4 |
3131 wmep[WME_AC_BE].wmep_logcwmax);
3132 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG,
3133 wmep[WME_AC_BK].wmep_txopLimit << 16 |
3134 wmep[WME_AC_BE].wmep_txopLimit);
3135 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG,
3136 wmep[WME_AC_VO].wmep_txopLimit << 16 |
3137 wmep[WME_AC_VI].wmep_txopLimit);
3144 rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni,
3145 struct ieee80211_key *k)
3147 struct rt2860_softc *sc = ic->ic_softc;
3150 uint8_t mode, wcid, iv[8];
3152 /* defer setting of WEP keys until interface is brought up */
3153 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) !=
3154 (IFF_UP | IFF_RUNNING))
3157 /* map net80211 cipher to RT2860 security mode */
3158 switch (k->k_cipher) {
3159 case IEEE80211_CIPHER_WEP40:
3160 mode = RT2860_MODE_WEP40;
3162 case IEEE80211_CIPHER_WEP104:
3163 mode = RT2860_MODE_WEP104;
3165 case IEEE80211_CIPHER_TKIP:
3166 mode = RT2860_MODE_TKIP;
3168 case IEEE80211_CIPHER_CCMP:
3169 mode = RT2860_MODE_AES_CCMP;
3175 if (k->k_flags & IEEE80211_KEY_GROUP) {
3176 wcid = 0; /* NB: update WCID0 for group keys */
3177 base = RT2860_SKEY(0, k->k_id);
3179 wcid = ((struct rt2860_node *)ni)->wcid;
3180 base = RT2860_PKEY(wcid);
3183 if (k->k_cipher == IEEE80211_CIPHER_TKIP) {
3184 RAL_WRITE_REGION_1(sc, base, k->k_key, 16);
3185 #ifndef IEEE80211_STA_ONLY
3186 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
3187 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8);
3188 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8);
3192 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8);
3193 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8);
3196 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len);
3198 if (!(k->k_flags & IEEE80211_KEY_GROUP) ||
3199 (k->k_flags & IEEE80211_KEY_TX)) {
3200 /* set initial packet number in IV+EIV */
3201 if (k->k_cipher == IEEE80211_CIPHER_WEP40 ||
3202 k->k_cipher == IEEE80211_CIPHER_WEP104) {
3203 uint32_t val = arc4random();
3204 /* skip weak IVs from Fluhrer/Mantin/Shamir */
3205 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00)
3210 iv[3] = k->k_id << 6;
3211 iv[4] = iv[5] = iv[6] = iv[7] = 0;
3213 if (k->k_cipher == IEEE80211_CIPHER_TKIP) {
3214 iv[0] = k->k_tsc >> 8;
3215 iv[1] = (iv[0] | 0x20) & 0x7f;
3219 iv[1] = k->k_tsc >> 8;
3222 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV;
3223 iv[4] = k->k_tsc >> 16;
3224 iv[5] = k->k_tsc >> 24;
3225 iv[6] = k->k_tsc >> 32;
3226 iv[7] = k->k_tsc >> 40;
3228 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8);
3231 if (k->k_flags & IEEE80211_KEY_GROUP) {
3232 /* install group key */
3233 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7);
3234 attr &= ~(0xf << (k->k_id * 4));
3235 attr |= mode << (k->k_id * 4);
3236 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr);
3238 /* install pairwise key */
3239 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid));
3240 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN;
3241 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr);
3247 rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni,
3248 struct ieee80211_key *k)
3250 struct rt2860_softc *sc = ic->ic_softc;
3254 if (k->k_flags & IEEE80211_KEY_GROUP) {
3255 /* remove group key */
3256 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7);
3257 attr &= ~(0xf << (k->k_id * 4));
3258 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr);
3261 /* remove pairwise key */
3262 wcid = ((struct rt2860_node *)ni)->wcid;
3263 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid));
3265 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr);
3271 rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain)
3273 struct ieee80211com *ic = &sc->sc_ic;
3274 struct ieee80211_channel *c = ic->ic_curchan;
3277 if (IEEE80211_IS_CHAN_5GHZ(c)) {
3278 u_int chan = ieee80211_chan2ieee(ic, c);
3279 delta = sc->rssi_5ghz[rxchain];
3281 /* determine channel group */
3283 delta -= sc->lna[1];
3284 else if (chan <= 128)
3285 delta -= sc->lna[2];
3287 delta -= sc->lna[3];
3289 delta = sc->rssi_2ghz[rxchain] - sc->lna[0];
3291 return -12 - delta - rssi;
3295 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word.
3296 * Used to adjust per-rate Tx power registers.
3298 static __inline uint32_t
3299 b4inc(uint32_t b32, int8_t delta)
3303 for (i = 0; i < 8; i++) {
3310 b32 = b32 >> 4 | b4 << 28;
3316 rt2860_get_rf(uint8_t rev)
3319 case RT2860_RF_2820: return "RT2820";
3320 case RT2860_RF_2850: return "RT2850";
3321 case RT2860_RF_2720: return "RT2720";
3322 case RT2860_RF_2750: return "RT2750";
3323 case RT3070_RF_3020: return "RT3020";
3324 case RT3070_RF_2020: return "RT2020";
3325 case RT3070_RF_3021: return "RT3021";
3326 case RT3070_RF_3022: return "RT3022";
3327 case RT3070_RF_3052: return "RT3052";
3328 case RT3070_RF_3320: return "RT3320";
3329 case RT3070_RF_3053: return "RT3053";
3330 case RT5390_RF_5390: return "RT5390";
3331 default: return "unknown";
3336 rt2860_read_eeprom(struct rt2860_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN])
3338 int8_t delta_2ghz, delta_5ghz;
3343 /* check whether the ROM is eFUSE ROM or EEPROM */
3344 sc->sc_srom_read = rt2860_eeprom_read_2;
3345 if (sc->mac_ver >= 0x3071) {
3346 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL);
3347 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp));
3348 if (tmp & RT3070_SEL_EFUSE)
3349 sc->sc_srom_read = rt3090_efuse_read_2;
3352 /* read EEPROM version */
3353 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION);
3354 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8));
3356 /* read MAC address */
3357 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01);
3358 macaddr[0] = val & 0xff;
3359 macaddr[1] = val >> 8;
3360 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23);
3361 macaddr[2] = val & 0xff;
3362 macaddr[3] = val >> 8;
3363 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45);
3364 macaddr[4] = val & 0xff;
3365 macaddr[5] = val >> 8;
3367 /* read country code */
3368 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY);
3369 DPRINTF(("EEPROM region code=0x%04x\n", val));
3371 /* read vendor BBP settings */
3372 for (i = 0; i < 8; i++) {
3373 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i);
3374 sc->bbp[i].val = val & 0xff;
3375 sc->bbp[i].reg = val >> 8;
3376 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val));
3378 if (sc->mac_ver >= 0x3071) {
3379 /* read vendor RF settings */
3380 for (i = 0; i < 10; i++) {
3381 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i);
3382 sc->rf[i].val = val & 0xff;
3383 sc->rf[i].reg = val >> 8;
3384 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg,
3389 /* read RF frequency offset from EEPROM */
3390 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS);
3391 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0;
3392 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff));
3393 if ((val >> 8) != 0xff) {
3394 /* read LEDs operating mode */
3395 sc->leds = val >> 8;
3396 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1);
3397 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2);
3398 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3);
3400 /* broken EEPROM, use default settings */
3402 sc->led[0] = 0x5555;
3403 sc->led[1] = 0x2221;
3404 sc->led[2] = 0xa9f8;
3406 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n",
3407 sc->leds, sc->led[0], sc->led[1], sc->led[2]));
3409 /* read RF information */
3410 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA);
3411 if (val == 0xffff) {
3412 DPRINTF(("invalid EEPROM antenna info, using default\n"));
3413 if (sc->mac_ver >= 0x5390) {
3414 /* default to RF5390 */
3415 sc->rf_rev = RT5390_RF_5390;
3416 sc->ntxchains = (sc->mac_ver == 0x5392) ? 2 : 1;
3417 sc->nrxchains = (sc->mac_ver == 0x5392) ? 2 : 1;
3418 } else if (sc->mac_ver == 0x3593) {
3419 /* default to RF3053 3T3R */
3420 sc->rf_rev = RT3070_RF_3053;
3423 } else if (sc->mac_ver >= 0x3071) {
3424 /* default to RF3020 1T1R */
3425 sc->rf_rev = RT3070_RF_3020;
3429 /* default to RF2820 1T2R */
3430 sc->rf_rev = RT2860_RF_2820;
3435 sc->rf_rev = (val >> 8) & 0xf;
3436 if (sc->mac_ver >= 0x5390) {
3437 sc->ntxchains = (sc->mac_ver == 0x5392) ? 2 : 1;
3438 sc->nrxchains = (sc->mac_ver == 0x5392) ? 2 : 1;
3440 sc->ntxchains = (val >> 4) & 0xf;
3441 sc->nrxchains = val & 0xf;
3444 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n",
3445 sc->rf_rev, sc->ntxchains, sc->nrxchains));
3447 /* check if RF supports automatic Tx access gain control */
3448 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG);
3449 DPRINTF(("EEPROM CFG 0x%04x\n", val));
3450 /* check if driver should patch the DAC issue */
3451 if ((val >> 8) != 0xff)
3452 sc->patch_dac = (val >> 15) & 1;
3453 if ((val & 0xff) != 0xff) {
3454 sc->ext_5ghz_lna = (val >> 3) & 1;
3455 sc->ext_2ghz_lna = (val >> 2) & 1;
3456 /* check if RF supports automatic Tx access gain control */
3457 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */;
3458 /* check if we have a hardware radio switch */
3459 sc->rfswitch = val & 1;
3461 if (sc->sc_flags & RT2860_ADVANCED_PS) {
3462 /* read PCIe power save level */
3463 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL);
3464 if ((val & 0xff) != 0xff) {
3465 sc->pslevel = val & 0x3;
3466 val = rt2860_srom_read(sc, RT2860_EEPROM_REV);
3467 if ((val & 0xff80) != 0x9280)
3468 sc->pslevel = MIN(sc->pslevel, 1);
3469 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel));
3473 /* read power settings for 2GHz channels */
3474 for (i = 0; i < 14; i += 2) {
3475 val = rt2860_srom_read(sc,
3476 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2);
3477 sc->txpow1[i + 0] = (int8_t)(val & 0xff);
3478 sc->txpow1[i + 1] = (int8_t)(val >> 8);
3480 if (sc->mac_ver != 0x5390) {
3481 val = rt2860_srom_read(sc,
3482 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2);
3483 sc->txpow2[i + 0] = (int8_t)(val & 0xff);
3484 sc->txpow2[i + 1] = (int8_t)(val >> 8);
3487 /* fix broken Tx power entries */
3488 for (i = 0; i < 14; i++) {
3489 if (sc->txpow1[i] < 0 ||
3490 sc->txpow1[i] > ((sc->mac_ver >= 0x5390) ? 39 : 31))
3492 if (sc->mac_ver != 0x5390) {
3493 if (sc->txpow2[i] < 0 ||
3494 sc->txpow2[i] > ((sc->mac_ver == 0x5392) ? 39 : 31))
3497 DPRINTF(("chan %d: power1=%d, power2=%d\n",
3498 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i]));
3500 /* read power settings for 5GHz channels */
3501 for (i = 0; i < 40; i += 2) {
3502 val = rt2860_srom_read(sc,
3503 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2);
3504 sc->txpow1[i + 14] = (int8_t)(val & 0xff);
3505 sc->txpow1[i + 15] = (int8_t)(val >> 8);
3507 val = rt2860_srom_read(sc,
3508 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2);
3509 sc->txpow2[i + 14] = (int8_t)(val & 0xff);
3510 sc->txpow2[i + 15] = (int8_t)(val >> 8);
3512 /* fix broken Tx power entries */
3513 for (i = 0; i < 40; i++) {
3514 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15)
3515 sc->txpow1[14 + i] = 5;
3516 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15)
3517 sc->txpow2[14 + i] = 5;
3518 DPRINTF(("chan %d: power1=%d, power2=%d\n",
3519 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i],
3520 sc->txpow2[14 + i]));
3523 /* read Tx power compensation for each Tx rate */
3524 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR);
3525 delta_2ghz = delta_5ghz = 0;
3526 if ((val & 0xff) != 0xff && (val & 0x80)) {
3527 delta_2ghz = val & 0xf;
3528 if (!(val & 0x40)) /* negative number */
3529 delta_2ghz = -delta_2ghz;
3532 if ((val & 0xff) != 0xff && (val & 0x80)) {
3533 delta_5ghz = val & 0xf;
3534 if (!(val & 0x40)) /* negative number */
3535 delta_5ghz = -delta_5ghz;
3537 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n",
3538 delta_2ghz, delta_5ghz));
3540 for (ridx = 0; ridx < 5; ridx++) {
3543 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2);
3545 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1);
3546 reg |= (uint32_t)val << 16;
3548 sc->txpow20mhz[ridx] = reg;
3549 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz);
3550 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz);
3552 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, "
3553 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx],
3554 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx]));
3557 /* read factory-calibrated samples for temperature compensation */
3558 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ);
3559 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */
3560 sc->tssi_2ghz[1] = val >> 8; /* [-3] */
3561 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ);
3562 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */
3563 sc->tssi_2ghz[3] = val >> 8; /* [-1] */
3564 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ);
3565 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */
3566 sc->tssi_2ghz[5] = val >> 8; /* [+1] */
3567 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ);
3568 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */
3569 sc->tssi_2ghz[7] = val >> 8; /* [+3] */
3570 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ);
3571 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */
3572 sc->step_2ghz = val >> 8;
3573 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x "
3574 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1],
3575 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4],
3576 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7],
3577 sc->tssi_2ghz[8], sc->step_2ghz));
3578 /* check that ref value is correct, otherwise disable calibration */
3579 if (sc->tssi_2ghz[4] == 0xff)
3582 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ);
3583 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */
3584 sc->tssi_5ghz[1] = val >> 8; /* [-3] */
3585 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ);
3586 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */
3587 sc->tssi_5ghz[3] = val >> 8; /* [-1] */
3588 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ);
3589 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */
3590 sc->tssi_5ghz[5] = val >> 8; /* [+1] */
3591 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ);
3592 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */
3593 sc->tssi_5ghz[7] = val >> 8; /* [+3] */
3594 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ);
3595 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */
3596 sc->step_5ghz = val >> 8;
3597 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x "
3598 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1],
3599 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4],
3600 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7],
3601 sc->tssi_5ghz[8], sc->step_5ghz));
3602 /* check that ref value is correct, otherwise disable calibration */
3603 if (sc->tssi_5ghz[4] == 0xff)
3606 /* read RSSI offsets and LNA gains from EEPROM */
3607 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ);
3608 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */
3609 sc->rssi_2ghz[1] = val >> 8; /* Ant B */
3610 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ);
3611 if (sc->mac_ver >= 0x3071) {
3613 * On RT3090 chips (limited to 2 Rx chains), this ROM
3614 * field contains the Tx mixer gain for the 2GHz band.
3616 if ((val & 0xff) != 0xff)
3617 sc->txmixgain_2ghz = val & 0x7;
3618 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz));
3620 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */
3621 sc->lna[2] = val >> 8; /* channel group 2 */
3623 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ);
3624 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */
3625 sc->rssi_5ghz[1] = val >> 8; /* Ant B */
3626 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ);
3627 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */
3628 sc->lna[3] = val >> 8; /* channel group 3 */
3630 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA);
3631 if (sc->mac_ver >= 0x3071)
3632 sc->lna[0] = RT3090_DEF_LNA;
3633 else /* channel group 0 */
3634 sc->lna[0] = val & 0xff;
3635 sc->lna[1] = val >> 8; /* channel group 1 */
3637 /* fix broken 5GHz LNA entries */
3638 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) {
3639 DPRINTF(("invalid LNA for channel group %d\n", 2));
3640 sc->lna[2] = sc->lna[1];
3642 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) {
3643 DPRINTF(("invalid LNA for channel group %d\n", 3));
3644 sc->lna[3] = sc->lna[1];
3647 /* fix broken RSSI offset entries */
3648 for (ant = 0; ant < 3; ant++) {
3649 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) {
3650 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n",
3651 ant + 1, sc->rssi_2ghz[ant]));
3652 sc->rssi_2ghz[ant] = 0;
3654 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) {
3655 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n",
3656 ant + 1, sc->rssi_5ghz[ant]));
3657 sc->rssi_5ghz[ant] = 0;
3665 rt2860_bbp_init(struct rt2860_softc *sc)
3669 /* wait for BBP to wake up */
3670 for (ntries = 0; ntries < 20; ntries++) {
3671 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0);
3672 if (bbp0 != 0 && bbp0 != 0xff)
3676 device_printf(sc->sc_dev,
3677 "timeout waiting for BBP to wake up\n");
3681 /* initialize BBP registers to default values */
3682 if (sc->mac_ver >= 0x5390)
3683 rt5390_bbp_init(sc);
3685 for (i = 0; i < nitems(rt2860_def_bbp); i++) {
3686 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg,
3687 rt2860_def_bbp[i].val);
3691 /* fix BBP84 for RT2860E */
3692 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101)
3693 rt2860_mcu_bbp_write(sc, 84, 0x19);
3695 if (sc->mac_ver >= 0x3071) {
3696 rt2860_mcu_bbp_write(sc, 79, 0x13);
3697 rt2860_mcu_bbp_write(sc, 80, 0x05);
3698 rt2860_mcu_bbp_write(sc, 81, 0x33);
3699 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) {
3700 rt2860_mcu_bbp_write(sc, 69, 0x16);
3701 rt2860_mcu_bbp_write(sc, 73, 0x12);
3708 rt5390_bbp_init(struct rt2860_softc *sc)
3713 /* Apply maximum likelihood detection for 2 stream case. */
3714 if (sc->nrxchains > 1) {
3715 bbp = rt2860_mcu_bbp_read(sc, 105);
3716 rt2860_mcu_bbp_write(sc, 105, bbp | RT5390_MLD);
3719 /* Avoid data lost and CRC error. */
3720 bbp = rt2860_mcu_bbp_read(sc, 4);
3721 rt2860_mcu_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL);
3723 for (i = 0; i < nitems(rt5390_def_bbp); i++) {
3724 rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg,
3725 rt5390_def_bbp[i].val);
3728 if (sc->mac_ver == 0x5392) {
3729 rt2860_mcu_bbp_write(sc, 84, 0x9a);
3730 rt2860_mcu_bbp_write(sc, 95, 0x9a);
3731 rt2860_mcu_bbp_write(sc, 98, 0x12);
3732 rt2860_mcu_bbp_write(sc, 106, 0x05);
3733 rt2860_mcu_bbp_write(sc, 134, 0xd0);
3734 rt2860_mcu_bbp_write(sc, 135, 0xf6);
3737 bbp = rt2860_mcu_bbp_read(sc, 152);
3738 rt2860_mcu_bbp_write(sc, 152, bbp | 0x80);
3740 /* Disable hardware antenna diversity. */
3741 if (sc->mac_ver == 0x5390)
3742 rt2860_mcu_bbp_write(sc, 154, 0);
3746 rt2860_txrx_enable(struct rt2860_softc *sc)
3748 struct ieee80211com *ic = &sc->sc_ic;
3752 /* enable Tx/Rx DMA engine */
3753 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN);
3754 RAL_BARRIER_READ_WRITE(sc);
3755 for (ntries = 0; ntries < 200; ntries++) {
3756 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
3757 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
3761 if (ntries == 200) {
3762 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n");
3768 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN |
3769 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT;
3770 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
3773 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR;
3774 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
3775 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL |
3776 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK |
3777 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV |
3778 RT2860_DROP_CFACK | RT2860_DROP_CFEND;
3779 if (ic->ic_opmode == IEEE80211_M_STA)
3780 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL;
3782 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp);
3784 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL,
3785 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
3791 rt2860_init(void *arg)
3793 struct rt2860_softc *sc = arg;
3794 struct ieee80211com *ic = &sc->sc_ic;
3797 rt2860_init_locked(sc);
3800 if (sc->sc_flags & RT2860_RUNNNING)
3801 ieee80211_start_all(ic);
3805 rt2860_init_locked(struct rt2860_softc *sc)
3807 struct ieee80211com *ic = &sc->sc_ic;
3808 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
3811 int i, qid, ridx, ntries, error;
3813 RAL_LOCK_ASSERT(sc);
3816 /* hardware has a radio switch on GPIO pin 2 */
3817 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) {
3818 device_printf(sc->sc_dev,
3819 "radio is disabled by hardware switch\n");
3821 rt2860_stop_locked(sc);
3826 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE);
3829 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
3831 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
3833 /* PBF hardware reset */
3834 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f);
3835 RAL_BARRIER_WRITE(sc);
3836 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00);
3838 if ((error = rt2860_load_microcode(sc)) != 0) {
3839 device_printf(sc->sc_dev, "could not load 8051 microcode\n");
3840 rt2860_stop_locked(sc);
3844 rt2860_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr);
3846 /* init Tx power for all Tx rates (from EEPROM) */
3847 for (ridx = 0; ridx < 5; ridx++) {
3848 if (sc->txpow20mhz[ridx] == 0xffffffff)
3850 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]);
3853 for (ntries = 0; ntries < 100; ntries++) {
3854 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
3855 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
3859 if (ntries == 100) {
3860 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n");
3861 rt2860_stop_locked(sc);
3865 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
3867 /* reset Rx ring and all 6 Tx rings */
3868 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f);
3870 /* PBF hardware reset */
3871 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f);
3872 RAL_BARRIER_WRITE(sc);
3873 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00);
3875 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE);
3877 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST);
3878 RAL_BARRIER_WRITE(sc);
3879 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0);
3881 for (i = 0; i < nitems(rt2860_def_mac); i++)
3882 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val);
3883 if (sc->mac_ver >= 0x5390)
3884 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 0x00000404);
3885 else if (sc->mac_ver >= 0x3071) {
3886 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */
3887 RAL_WRITE(sc, RT2860_TX_SW_CFG0,
3888 4 << RT2860_DLY_PAPE_EN_SHIFT);
3891 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) {
3892 sc->sc_flags |= RT2860_PCIE;
3893 /* PCIe has different clock cycle count than PCI */
3894 tmp = RAL_READ(sc, RT2860_US_CYC_CNT);
3895 tmp = (tmp & ~0xff) | 0x7d;
3896 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp);
3899 /* wait while MAC is busy */
3900 for (ntries = 0; ntries < 100; ntries++) {
3901 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) &
3902 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY)))
3906 if (ntries == 100) {
3907 device_printf(sc->sc_dev, "timeout waiting for MAC\n");
3908 rt2860_stop_locked(sc);
3912 /* clear Host to MCU mailbox */
3913 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0);
3914 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0);
3916 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0);
3919 if ((error = rt2860_bbp_init(sc)) != 0) {
3920 rt2860_stop_locked(sc);
3924 /* clear RX WCID search table */
3925 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512);
3926 /* clear pairwise key table */
3927 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048);
3928 /* clear IV/EIV table */
3929 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512);
3930 /* clear WCID attribute table */
3931 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256);
3932 /* clear shared key table */
3933 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32);
3934 /* clear shared key mode */
3935 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4);
3937 /* init Tx rings (4 EDCAs + HCCA + Mgt) */
3938 for (qid = 0; qid < 6; qid++) {
3939 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr);
3940 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT);
3941 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0);
3945 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr);
3946 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT);
3947 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1);
3949 /* setup maximum buffer sizes */
3950 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 |
3951 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2));
3953 for (ntries = 0; ntries < 100; ntries++) {
3954 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG);
3955 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0)
3959 if (ntries == 100) {
3960 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n");
3961 rt2860_stop_locked(sc);
3965 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp);
3967 /* disable interrupts mitigation */
3968 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0);
3970 /* write vendor-specific BBP values (from EEPROM) */
3971 for (i = 0; i < 8; i++) {
3972 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff)
3974 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val);
3977 /* select Main antenna for 1T1R devices */
3978 if (sc->rf_rev == RT3070_RF_2020 ||
3979 sc->rf_rev == RT3070_RF_3020 ||
3980 sc->rf_rev == RT3070_RF_3320 ||
3981 sc->mac_ver == 0x5390)
3982 rt3090_set_rx_antenna(sc, 0);
3984 /* send LEDs operating mode to microcontroller */
3985 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0);
3986 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0);
3987 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0);
3989 if (sc->mac_ver >= 0x5390)
3991 else if (sc->mac_ver >= 0x3071) {
3992 if ((error = rt3090_rf_init(sc)) != 0) {
3993 rt2860_stop_locked(sc);
3998 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1);
3999 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1);
4001 if (sc->mac_ver >= 0x5390)
4002 rt5390_rf_wakeup(sc);
4003 else if (sc->mac_ver >= 0x3071)
4004 rt3090_rf_wakeup(sc);
4006 /* disable non-existing Rx chains */
4007 bbp3 = rt2860_mcu_bbp_read(sc, 3);
4008 bbp3 &= ~(1 << 3 | 1 << 4);
4009 if (sc->nrxchains == 2)
4011 else if (sc->nrxchains == 3)
4013 rt2860_mcu_bbp_write(sc, 3, bbp3);
4015 /* disable non-existing Tx chains */
4016 bbp1 = rt2860_mcu_bbp_read(sc, 1);
4017 if (sc->ntxchains == 1)
4018 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4));
4019 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2)
4020 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3;
4021 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3)
4022 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4;
4023 rt2860_mcu_bbp_write(sc, 1, bbp1);
4025 if (sc->mac_ver >= 0x3071)
4026 rt3090_rf_setup(sc);
4028 /* select default channel */
4029 rt2860_switch_chan(sc, ic->ic_curchan);
4031 /* reset RF from MCU */
4032 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0);
4034 /* set RTS threshold */
4035 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG);
4037 tmp |= IEEE80211_RTS_DEFAULT << 8;
4038 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp);
4040 /* setup initial protection mode */
4041 rt2860_updateprot(sc);
4043 /* turn radio LED on */
4044 rt2860_set_leds(sc, RT2860_LED_RADIO);
4046 /* enable Tx/Rx DMA engine */
4047 if ((error = rt2860_txrx_enable(sc)) != 0) {
4048 rt2860_stop_locked(sc);
4052 /* clear pending interrupts */
4053 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff);
4054 /* enable interrupts */
4055 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc);
4057 if (sc->sc_flags & RT2860_ADVANCED_PS)
4058 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0);
4060 sc->sc_flags |= RT2860_RUNNNING;
4062 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc);
4066 rt2860_stop(void *arg)
4068 struct rt2860_softc *sc = arg;
4071 rt2860_stop_locked(sc);
4076 rt2860_stop_locked(struct rt2860_softc *sc)
4081 if (sc->sc_flags & RT2860_RUNNNING)
4082 rt2860_set_leds(sc, 0); /* turn all LEDs off */
4084 callout_stop(&sc->watchdog_ch);
4085 sc->sc_tx_timer = 0;
4086 sc->sc_flags &= ~RT2860_RUNNNING;
4088 /* disable interrupts */
4089 RAL_WRITE(sc, RT2860_INT_MASK, 0);
4091 /* disable GP timer */
4092 rt2860_set_gp_timer(sc, 0);
4095 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL);
4096 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN);
4097 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp);
4100 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST);
4101 RAL_BARRIER_WRITE(sc);
4102 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0);
4104 /* reset Tx and Rx rings (and reclaim TXWIs) */
4106 for (qid = 0; qid < 6; qid++)
4107 rt2860_reset_tx_ring(sc, &sc->txq[qid]);
4108 rt2860_reset_rx_ring(sc, &sc->rxq);
4112 rt2860_load_microcode(struct rt2860_softc *sc)
4114 const struct firmware *fp;
4117 RAL_LOCK_ASSERT(sc);
4120 fp = firmware_get("rt2860fw");
4123 device_printf(sc->sc_dev,
4124 "unable to receive rt2860fw firmware image\n");
4128 /* set "host program ram write selection" bit */
4129 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL);
4130 /* write microcode image */
4131 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, fp->data, fp->datasize);
4132 /* kick microcontroller unit */
4133 RAL_WRITE(sc, RT2860_SYS_CTRL, 0);
4134 RAL_BARRIER_WRITE(sc);
4135 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET);
4137 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0);
4138 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0);
4140 /* wait until microcontroller is ready */
4141 RAL_BARRIER_READ_WRITE(sc);
4142 for (ntries = 0; ntries < 1000; ntries++) {
4143 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY)
4147 if (ntries == 1000) {
4148 device_printf(sc->sc_dev,
4149 "timeout waiting for MCU to initialize\n");
4154 firmware_put(fp, FIRMWARE_UNLOAD);
4159 * This function is called periodically to adjust Tx power based on
4160 * temperature variation.
4164 rt2860_calib(struct rt2860_softc *sc)
4166 struct ieee80211com *ic = &sc->sc_ic;
4167 const uint8_t *tssi;
4168 uint8_t step, bbp49;
4171 /* read current temperature */
4172 bbp49 = rt2860_mcu_bbp_read(sc, 49);
4174 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) {
4175 tssi = &sc->tssi_2ghz[4];
4176 step = sc->step_2ghz;
4178 tssi = &sc->tssi_5ghz[4];
4179 step = sc->step_5ghz;
4182 if (bbp49 < tssi[0]) { /* lower than reference */
4183 /* use higher Tx power than default */
4184 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--);
4185 } else if (bbp49 > tssi[0]) { /* greater than reference */
4186 /* use lower Tx power than default */
4187 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++);
4189 /* use default Tx power */
4194 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d));
4196 /* write adjusted Tx power values for each Tx rate */
4197 for (ridx = 0; ridx < 5; ridx++) {
4198 if (sc->txpow20mhz[ridx] == 0xffffffff)
4200 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx),
4201 b4inc(sc->txpow20mhz[ridx], d));
4207 rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux)
4212 if (sc->mac_ver == 0x5390) {
4213 rt2860_mcu_bbp_write(sc, 152,
4214 rt2860_mcu_bbp_read(sc, 152) & ~0x80);
4216 tmp = RAL_READ(sc, RT2860_PCI_EECTRL);
4217 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp & ~RT2860_C);
4218 tmp = RAL_READ(sc, RT2860_GPIO_CTRL);
4219 RAL_WRITE(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08);
4222 if (sc->mac_ver == 0x5390) {
4223 rt2860_mcu_bbp_write(sc, 152,
4224 rt2860_mcu_bbp_read(sc, 152) | 0x80);
4226 tmp = RAL_READ(sc, RT2860_PCI_EECTRL);
4227 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp | RT2860_C);
4228 tmp = RAL_READ(sc, RT2860_GPIO_CTRL);
4229 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp & ~0x0808);
4235 rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c)
4237 struct ieee80211com *ic = &sc->sc_ic;
4240 chan = ieee80211_chan2ieee(ic, c);
4241 if (chan == 0 || chan == IEEE80211_CHAN_ANY)
4244 if (sc->mac_ver >= 0x5390)
4245 rt5390_set_chan(sc, chan);
4246 else if (sc->mac_ver >= 0x3071)
4247 rt3090_set_chan(sc, chan);
4249 rt2860_set_chan(sc, chan);
4251 /* determine channel group */
4254 else if (chan <= 64)
4256 else if (chan <= 128)
4261 /* XXX necessary only when group has changed! */
4262 if (sc->mac_ver < 0x5390)
4263 rt2860_select_chan_group(sc, group);
4269 rt2860_setup_beacon(struct rt2860_softc *sc, struct ieee80211vap *vap)
4271 struct ieee80211com *ic = vap->iv_ic;
4272 struct ieee80211_beacon_offsets bo;
4273 struct rt2860_txwi txwi;
4277 if ((m = ieee80211_beacon_alloc(vap->iv_bss, &bo)) == NULL)
4280 memset(&txwi, 0, sizeof txwi);
4282 txwi.len = htole16(m->m_pkthdr.len);
4283 /* send beacons at the lowest available rate */
4284 ridx = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ?
4285 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1;
4286 txwi.phy = htole16(rt2860_rates[ridx].mcs);
4287 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM)
4288 txwi.phy |= htole16(RT2860_PHY_OFDM);
4289 txwi.txop = RT2860_TX_TXOP_HT;
4290 txwi.flags = RT2860_TX_TS;
4291 txwi.xflags = RT2860_TX_NSEQ;
4293 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0),
4294 (uint8_t *)&txwi, sizeof txwi);
4295 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi,
4296 mtod(m, uint8_t *), m->m_pkthdr.len);
4304 rt2860_enable_tsf_sync(struct rt2860_softc *sc)
4306 struct ieee80211com *ic = &sc->sc_ic;
4307 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
4310 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG);
4313 tmp |= vap->iv_bss->ni_intval * 16;
4314 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN;
4315 if (vap->iv_opmode == IEEE80211_M_STA) {
4317 * Local TSF is always updated with remote TSF on beacon
4320 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT;
4322 else if (vap->iv_opmode == IEEE80211_M_IBSS ||
4323 vap->iv_opmode == IEEE80211_M_MBSS) {
4324 tmp |= RT2860_BCN_TX_EN;
4326 * Local TSF is updated with remote TSF on beacon reception
4327 * only if the remote TSF is greater than local TSF.
4329 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT;
4330 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP) {
4331 tmp |= RT2860_BCN_TX_EN;
4332 /* SYNC with nobody */
4333 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT;
4336 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp);