2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (C) 1995 by Pavel Antonov, Moscow, Russia.
5 * Copyright (C) 1995 by Andrey A. Chernov, Moscow, Russia.
7 * Copyright (C) 2002 by John Baldwin <jhb@FreeBSD.org>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SDL Communications Riscom/8 (based on Cirrus Logic CL-CD180) driver
42 #include <sys/param.h>
43 #include <sys/systm.h>
46 #include <sys/fcntl.h>
47 #include <sys/interrupt.h>
48 #include <sys/kernel.h>
49 #include <sys/malloc.h>
50 #include <sys/module.h>
51 #include <sys/serial.h>
53 #include <machine/bus.h>
54 #include <machine/resource.h>
57 #include <dev/ic/cd180.h>
58 #include <dev/rc/rcreg.h>
59 #include <isa/isavar.h>
61 #define IOBASE_ADDRS 14
63 #define rcin(sc, port) RC_IN(sc, port)
64 #define rcout(sc, port, v) RC_OUT(sc, port, v)
66 #define WAITFORCCR(sc, chan) rc_wait0((sc), (chan), __LINE__)
68 #define CCRCMD(sc, chan, cmd) do { \
69 WAITFORCCR((sc), (chan)); \
70 rcout((sc), CD180_CCR, (cmd)); \
73 #define RC_IBUFSIZE 256
74 #define RB_I_HIGH_WATER (TTYHOG - 2 * RC_IBUFSIZE)
75 #define RC_OBUFSIZE 512
76 #define RC_IHIGHWATER (3 * RC_IBUFSIZE / 4)
77 #define INPUT_FLAGS_SHIFT (2 * RC_IBUFSIZE)
78 #define LOTS_OF_EVENTS 64
80 #define RC_FAKEID 0x10
82 /* Per-channel structure */
84 struct rc_softc *rc_rcb; /* back ptr */
85 u_short rc_flags; /* Misc. flags */
86 int rc_chan; /* Channel # */
87 u_char rc_ier; /* intr. enable reg */
88 u_char rc_msvr; /* modem sig. status */
89 u_char rc_cor2; /* options reg */
90 u_char rc_pendcmd; /* special cmd pending */
91 u_int rc_dcdwaits; /* how many waits DCD in open */
92 struct tty *rc_tp; /* tty struct */
93 u_char *rc_iptr; /* Chars input buffer */
94 u_char *rc_hiwat; /* hi-water mark */
95 u_char *rc_bufend; /* end of buffer */
96 u_char *rc_optr; /* ptr in output buf */
97 u_char *rc_obufend; /* end of output buf */
98 u_char rc_ibuf[4 * RC_IBUFSIZE]; /* input buffer */
99 u_char rc_obuf[RC_OBUFSIZE]; /* output buffer */
100 struct callout rc_dtrcallout;
103 /* Per-board structure */
106 struct resource *sc_irq;
107 struct resource *sc_port[IOBASE_ADDRS];
110 bus_space_tag_t sc_bt;
111 bus_space_handle_t sc_bh;
112 u_int sc_unit; /* unit # */
113 u_char sc_dtr; /* DTR status */
114 int sc_scheduled_event;
116 struct rc_chans sc_channels[CD180_NCHAN]; /* channels */
119 /* Static prototypes */
120 static t_close_t rc_close;
121 static void rc_break(struct tty *, int);
122 static void rc_release_resources(device_t dev);
123 static void rc_intr(void *);
124 static void rc_hwreset(struct rc_softc *, unsigned int);
125 static int rc_test(struct rc_softc *);
126 static void rc_discard_output(struct rc_chans *);
127 static int rc_modem(struct tty *, int, int);
128 static void rc_start(struct tty *);
129 static void rc_stop(struct tty *, int rw);
130 static int rc_param(struct tty *, struct termios *);
131 static void rc_pollcard(void *);
132 static void rc_reinit(struct rc_softc *);
134 static void printrcflags();
136 static void rc_wait0(struct rc_softc *sc, int chan, int line);
138 static devclass_t rc_devclass;
141 #define RC_DTR_OFF 0x0001 /* DTR wait, for close/open */
142 #define RC_ACTOUT 0x0002 /* Dial-out port active */
143 #define RC_RTSFLOW 0x0004 /* RTS flow ctl enabled */
144 #define RC_CTSFLOW 0x0008 /* CTS flow ctl enabled */
145 #define RC_DORXFER 0x0010 /* RXFER event planned */
146 #define RC_DOXXFER 0x0020 /* XXFER event planned */
147 #define RC_MODCHG 0x0040 /* Modem status changed */
148 #define RC_OSUSP 0x0080 /* Output suspended */
149 #define RC_OSBUSY 0x0100 /* start() routine in progress */
150 #define RC_WAS_BUFOVFL 0x0200 /* low-level buffer ovferflow */
151 #define RC_WAS_SILOVFL 0x0400 /* silo buffer overflow */
152 #define RC_SEND_RDY 0x0800 /* ready to send */
154 /* Table for translation of RCSR status bits to internal form */
155 static int rc_rcsrt[16] = {
157 TTY_FE|TTY_OE, TTY_PE, TTY_PE|TTY_OE,
158 TTY_PE|TTY_FE, TTY_PE|TTY_FE|TTY_OE, TTY_BI,
159 TTY_BI|TTY_OE, TTY_BI|TTY_FE, TTY_BI|TTY_FE|TTY_OE,
160 TTY_BI|TTY_PE, TTY_BI|TTY_PE|TTY_OE, TTY_BI|TTY_PE|TTY_FE,
161 TTY_BI|TTY_PE|TTY_FE|TTY_OE
164 static int rc_ports[] =
165 { 0x220, 0x240, 0x250, 0x260, 0x2a0, 0x2b0, 0x300, 0x320 };
166 static int iobase_addrs[IOBASE_ADDRS] =
167 { 0, 0x400, 0x800, 0xc00, 0x1400, 0x1800, 0x1c00, 0x2000,
168 0x3000, 0x3400, 0x3800, 0x3c00, 0x4000, 0x8000 };
170 /**********************************************/
173 rc_probe(device_t dev)
179 * We don't know of any PnP ID's for these cards.
181 if (isa_get_logicalid(dev) != 0)
185 * We have to have an IO port hint that is valid.
187 port = isa_get_port(dev);
191 for (i = 0; i < nitems(rc_ports); i++)
192 if (rc_ports[i] == port) {
200 * We have to have an IRQ hint.
202 if (isa_get_irq(dev) == -1)
205 device_set_desc(dev, "SDL Riscom/8");
210 rc_attach(device_t dev)
216 int base, chan, error, i, x;
218 sc = device_get_softc(dev);
222 * We need to have IO ports. Lots of them. We need
223 * the following ranges relative to the base port:
239 port = isa_get_port(dev);
240 for (i = 0; i < IOBASE_ADDRS; i++)
241 if (bus_set_resource(dev, SYS_RES_IOPORT, i,
242 port + iobase_addrs[i], 0x10) != 0)
245 for (i = 0; i < IOBASE_ADDRS; i++) {
247 sc->sc_port[i] = bus_alloc_resource_anywhere(dev,
248 SYS_RES_IOPORT, &x, 0x10, RF_ACTIVE);
250 device_printf(dev, "ioport %d was rid %d\n", i, x);
253 if (sc->sc_port[i] == NULL) {
254 device_printf(dev, "failed to alloc ioports %x-%x\n",
255 port + iobase_addrs[i],
256 port + iobase_addrs[i] + 0x10);
260 sc->sc_bt = rman_get_bustag(sc->sc_port[0]);
261 sc->sc_bh = rman_get_bushandle(sc->sc_port[0]);
263 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irqrid,
265 if (sc->sc_irq == NULL) {
266 device_printf(dev, "failed to alloc IRQ\n");
271 * Now do some actual tests to make sure it works.
274 rcout(sc, CD180_PPRL, 0x22); /* Random values to Prescale reg. */
275 rcout(sc, CD180_PPRH, 0x11);
276 if (rcin(sc, CD180_PPRL) != 0x22 || rcin(sc, CD180_PPRH) != 0x11)
282 * Ok, start actually hooking things up.
284 sc->sc_unit = device_get_unit(dev);
285 /*sc->sc_chipid = 0x10 + device_get_unit(dev);*/
286 device_printf(dev, "%d chans, firmware rev. %c\n",
287 CD180_NCHAN, (rcin(sc, CD180_GFRCR) & 0xF) + 'A');
288 rc = sc->sc_channels;
289 base = CD180_NCHAN * sc->sc_unit;
290 for (chan = 0; chan < CD180_NCHAN; chan++, rc++) {
293 rc->rc_iptr = rc->rc_ibuf;
294 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
295 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER];
296 rc->rc_optr = rc->rc_obufend = rc->rc_obuf;
297 callout_init(&rc->rc_dtrcallout, 0);
298 tp = rc->rc_tp = ttyalloc();
300 tp->t_oproc = rc_start;
301 tp->t_param = rc_param;
302 tp->t_modem = rc_modem;
303 tp->t_break = rc_break;
304 tp->t_close = rc_close;
305 tp->t_stop = rc_stop;
306 ttycreate(tp, TS_CALLOUT, "m%d", chan + base);
309 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_TTY, NULL, rc_intr,
310 sc, &sc->sc_hwicookie);
312 device_printf(dev, "failed to register interrupt handler\n");
316 swi_add(&tty_intr_event, "rc", rc_pollcard, sc, SWI_TTY, 0,
321 rc_release_resources(dev);
326 rc_detach(device_t dev)
332 sc = device_get_softc(dev);
334 rc = sc->sc_channels;
335 for (i = 0; i < CD180_NCHAN; i++, rc++)
338 error = bus_teardown_intr(dev, sc->sc_irq, sc->sc_hwicookie);
340 device_printf(dev, "failed to deregister interrupt handler\n");
341 swi_remove(sc->sc_swicookie);
342 rc_release_resources(dev);
348 rc_release_resources(device_t dev)
353 sc = device_get_softc(dev);
354 if (sc->sc_irq != NULL) {
355 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irqrid,
359 for (i = 0; i < IOBASE_ADDRS; i++) {
360 if (sc->sc_port[i] == NULL)
362 bus_release_resource(dev, SYS_RES_IOPORT, i, sc->sc_port[i]);
363 sc->sc_port[i] = NULL;
367 /* RC interrupt handling */
374 u_char val, iack, bsr, ucnt, *optr;
375 int good_data, t_state;
377 sc = (struct rc_softc *)arg;
378 bsr = ~(rcin(sc, RC_BSR));
379 if (!(bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT))) {
380 device_printf(sc->sc_dev, "extra interrupt\n");
381 rcout(sc, CD180_EOIR, 0);
385 while (bsr & (RC_BSR_TOUT|RC_BSR_RXINT|RC_BSR_TXINT|RC_BSR_MOINT)) {
386 #ifdef RCDEBUG_DETAILED
387 device_printf(sc->sc_dev, "intr (%p) %s%s%s%s\n", arg, bsr,
388 (bsr & RC_BSR_TOUT)?"TOUT ":"",
389 (bsr & RC_BSR_RXINT)?"RXINT ":"",
390 (bsr & RC_BSR_TXINT)?"TXINT ":"",
391 (bsr & RC_BSR_MOINT)?"MOINT":"");
393 if (bsr & RC_BSR_TOUT) {
394 device_printf(sc->sc_dev,
395 "hardware failure, reset board\n");
396 rcout(sc, RC_CTOUT, 0);
400 if (bsr & RC_BSR_RXINT) {
401 iack = rcin(sc, RC_PILR_RX);
402 good_data = (iack == (GIVR_IT_RGDI | RC_FAKEID));
403 if (!good_data && iack != (GIVR_IT_REI | RC_FAKEID)) {
404 device_printf(sc->sc_dev,
405 "fake rxint: %02x\n", iack);
408 chan = ((rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH);
409 rc = &sc->sc_channels[chan];
410 t_state = rc->rc_tp->t_state;
411 /* Do RTS flow control stuff */
412 if ( (rc->rc_flags & RC_RTSFLOW)
413 || !(t_state & TS_ISOPEN)
415 if ( ( !(t_state & TS_ISOPEN)
416 || (t_state & TS_TBLOCK)
418 && (rc->rc_msvr & MSVR_RTS)
420 rcout(sc, CD180_MSVR,
421 rc->rc_msvr &= ~MSVR_RTS);
422 else if (!(rc->rc_msvr & MSVR_RTS))
423 rcout(sc, CD180_MSVR,
424 rc->rc_msvr |= MSVR_RTS);
426 ucnt = rcin(sc, CD180_RDCR) & 0xF;
429 if (t_state & TS_ISOPEN) {
430 /* check for input buffer overflow */
431 if ((rc->rc_iptr + ucnt) >= rc->rc_bufend) {
433 ucnt = rc->rc_bufend - rc->rc_iptr;
435 if (!(rc->rc_flags & RC_WAS_BUFOVFL)) {
436 rc->rc_flags |= RC_WAS_BUFOVFL;
437 sc->sc_scheduled_event++;
441 /* check foor good data */
444 val = rcin(sc, CD180_RDR);
446 optr[INPUT_FLAGS_SHIFT] = 0;
448 sc->sc_scheduled_event++;
449 if (val != 0 && val == rc->rc_tp->t_hotchar)
450 swi_sched(sc->sc_swicookie, 0);
453 /* Store also status data */
455 iack = rcin(sc, CD180_RCSR);
456 if (iack & RCSR_Timeout)
458 if ( (iack & RCSR_OE)
459 && !(rc->rc_flags & RC_WAS_SILOVFL)) {
460 rc->rc_flags |= RC_WAS_SILOVFL;
461 sc->sc_scheduled_event++;
463 val = rcin(sc, CD180_RDR);
465 Don't store PE if IGNPAR and BREAK if IGNBRK,
466 this hack allows "raw" tty optimization
467 works even if IGN* is set.
469 if ( !(iack & (RCSR_PE|RCSR_FE|RCSR_Break))
470 || ((!(iack & (RCSR_PE|RCSR_FE))
471 || !(rc->rc_tp->t_iflag & IGNPAR))
472 && (!(iack & RCSR_Break)
473 || !(rc->rc_tp->t_iflag & IGNBRK)))) {
474 if ( (iack & (RCSR_PE|RCSR_FE))
475 && (t_state & TS_CAN_BYPASS_L_RINT)
478 && (rc->rc_tp->t_iflag & INPCK))))
480 else if (val != 0 && val == rc->rc_tp->t_hotchar)
481 swi_sched(sc->sc_swicookie, 0);
483 optr[INPUT_FLAGS_SHIFT] = iack;
485 sc->sc_scheduled_event++;
490 rc->rc_flags |= RC_DORXFER;
493 /* Clear FIFO if necessary */
494 while (resid-- > 0) {
496 iack = rcin(sc, CD180_RCSR);
499 if (iack & RCSR_Timeout)
501 (void) rcin(sc, CD180_RDR);
505 if (bsr & RC_BSR_MOINT) {
506 iack = rcin(sc, RC_PILR_MODEM);
507 if (iack != (GIVR_IT_MSCI | RC_FAKEID)) {
508 device_printf(sc->sc_dev, "fake moint: %02x\n",
512 chan = ((rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH);
513 rc = &sc->sc_channels[chan];
514 iack = rcin(sc, CD180_MCR);
515 rc->rc_msvr = rcin(sc, CD180_MSVR);
516 rcout(sc, CD180_MCR, 0);
518 printrcflags(rc, "moint");
520 if (rc->rc_flags & RC_CTSFLOW) {
521 if (rc->rc_msvr & MSVR_CTS)
522 rc->rc_flags |= RC_SEND_RDY;
524 rc->rc_flags &= ~RC_SEND_RDY;
526 rc->rc_flags |= RC_SEND_RDY;
527 if ((iack & MCR_CDchg) && !(rc->rc_flags & RC_MODCHG)) {
528 sc->sc_scheduled_event += LOTS_OF_EVENTS;
529 rc->rc_flags |= RC_MODCHG;
530 swi_sched(sc->sc_swicookie, 0);
534 if (bsr & RC_BSR_TXINT) {
535 iack = rcin(sc, RC_PILR_TX);
536 if (iack != (GIVR_IT_TDI | RC_FAKEID)) {
537 device_printf(sc->sc_dev, "fake txint: %02x\n",
541 chan = ((rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH);
542 rc = &sc->sc_channels[chan];
543 if ( (rc->rc_flags & RC_OSUSP)
544 || !(rc->rc_flags & RC_SEND_RDY)
547 /* Handle breaks and other stuff */
548 if (rc->rc_pendcmd) {
549 rcout(sc, CD180_COR2, rc->rc_cor2 |= COR2_ETC);
550 rcout(sc, CD180_TDR, CD180_C_ESC);
551 rcout(sc, CD180_TDR, rc->rc_pendcmd);
552 rcout(sc, CD180_COR2, rc->rc_cor2 &= ~COR2_ETC);
557 resid = rc->rc_obufend - optr;
558 if (resid > CD180_NFIFO)
561 rcout(sc, CD180_TDR, *optr++);
564 /* output completed? */
565 if (optr >= rc->rc_obufend) {
566 rcout(sc, CD180_IER, rc->rc_ier &= ~IER_TxRdy);
568 device_printf(sc->sc_dev,
569 "channel %d: output completed\n",
572 if (!(rc->rc_flags & RC_DOXXFER)) {
573 sc->sc_scheduled_event += LOTS_OF_EVENTS;
574 rc->rc_flags |= RC_DOXXFER;
575 swi_sched(sc->sc_swicookie, 0);
580 rcout(sc, CD180_EOIR, 0); /* end of interrupt */
581 rcout(sc, RC_CTOUT, 0);
582 bsr = ~(rcin(sc, RC_BSR));
586 /* Feed characters to output buffer */
588 rc_start(struct tty *tp)
595 if (rc->rc_flags & RC_OSBUSY)
599 rc->rc_flags |= RC_OSBUSY;
601 if (tp->t_state & TS_TTSTOP)
602 rc->rc_flags |= RC_OSUSP;
604 rc->rc_flags &= ~RC_OSUSP;
605 /* Do RTS flow control stuff */
606 if ( (rc->rc_flags & RC_RTSFLOW)
607 && (tp->t_state & TS_TBLOCK)
608 && (rc->rc_msvr & MSVR_RTS)
610 rcout(sc, CD180_CAR, rc->rc_chan);
611 rcout(sc, CD180_MSVR, rc->rc_msvr &= ~MSVR_RTS);
612 } else if (!(rc->rc_msvr & MSVR_RTS)) {
613 rcout(sc, CD180_CAR, rc->rc_chan);
614 rcout(sc, CD180_MSVR, rc->rc_msvr |= MSVR_RTS);
617 if (tp->t_state & (TS_TIMEOUT|TS_TTSTOP))
620 printrcflags(rc, "rcstart");
624 printf("rcstart: outq = %d obuf = %d\n",
625 tp->t_outq.c_cc, rc->rc_obufend - rc->rc_optr);
627 if (tp->t_state & TS_BUSY)
628 goto out; /* output still in progress ... */
630 if (tp->t_outq.c_cc > 0) {
633 tp->t_state |= TS_BUSY;
634 ocnt = q_to_b(&tp->t_outq, rc->rc_obuf, sizeof rc->rc_obuf);
636 rc->rc_optr = rc->rc_obuf;
637 rc->rc_obufend = rc->rc_optr + ocnt;
639 if (!(rc->rc_ier & IER_TxRdy)) {
641 device_printf(sc->sc_dev,
642 "channel %d: rcstart enable txint\n", rc->rc_chan);
644 rcout(sc, CD180_CAR, rc->rc_chan);
645 rcout(sc, CD180_IER, rc->rc_ier |= IER_TxRdy);
649 rc->rc_flags &= ~RC_OSBUSY;
653 /* Handle delayed events. */
655 rc_pollcard(void *arg)
663 sc = (struct rc_softc *)arg;
664 if (sc->sc_scheduled_event == 0)
667 rc = sc->sc_channels;
668 for (chan = 0; chan < CD180_NCHAN; rc++, chan++) {
671 if (rc->rc_flags & (RC_DORXFER|RC_DOXXFER|RC_MODCHG|
672 RC_WAS_BUFOVFL|RC_WAS_SILOVFL))
673 printrcflags(rc, "rcevent");
675 if (rc->rc_flags & RC_WAS_BUFOVFL) {
677 rc->rc_flags &= ~RC_WAS_BUFOVFL;
678 sc->sc_scheduled_event--;
680 device_printf(sc->sc_dev,
681 "channel %d: interrupt-level buffer overflow\n",
684 if (rc->rc_flags & RC_WAS_SILOVFL) {
686 rc->rc_flags &= ~RC_WAS_SILOVFL;
687 sc->sc_scheduled_event--;
689 device_printf(sc->sc_dev,
690 "channel %d: silo overflow\n", chan);
692 if (rc->rc_flags & RC_MODCHG) {
694 rc->rc_flags &= ~RC_MODCHG;
695 sc->sc_scheduled_event -= LOTS_OF_EVENTS;
697 ttyld_modem(tp, !!(rc->rc_msvr & MSVR_CD));
699 if (rc->rc_flags & RC_DORXFER) {
701 rc->rc_flags &= ~RC_DORXFER;
703 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE])
704 tptr = &rc->rc_ibuf[RC_IBUFSIZE];
709 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
710 rc->rc_iptr = rc->rc_ibuf;
711 rc->rc_bufend = &rc->rc_ibuf[RC_IBUFSIZE];
712 rc->rc_hiwat = &rc->rc_ibuf[RC_IHIGHWATER];
714 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
715 rc->rc_bufend = &rc->rc_ibuf[2 * RC_IBUFSIZE];
717 &rc->rc_ibuf[RC_IBUFSIZE + RC_IHIGHWATER];
719 if ( (rc->rc_flags & RC_RTSFLOW)
720 && (tp->t_state & TS_ISOPEN)
721 && !(tp->t_state & TS_TBLOCK)
722 && !(rc->rc_msvr & MSVR_RTS)
724 rcout(sc, CD180_CAR, chan);
725 rcout(sc, CD180_MSVR,
726 rc->rc_msvr |= MSVR_RTS);
728 sc->sc_scheduled_event -= icnt;
732 if (icnt <= 0 || !(tp->t_state & TS_ISOPEN))
735 if ( (tp->t_state & TS_CAN_BYPASS_L_RINT)
736 && !(tp->t_state & TS_LOCAL)) {
737 if ((tp->t_rawq.c_cc + icnt) >= RB_I_HIGH_WATER
738 && ((rc->rc_flags & RC_RTSFLOW) || (tp->t_iflag & IXOFF))
739 && !(tp->t_state & TS_TBLOCK))
744 if (b_to_q(tptr, icnt, &tp->t_rawq))
745 device_printf(sc->sc_dev,
746 "channel %d: tty-level buffer overflow\n",
749 if ((tp->t_state & TS_TTSTOP) && ((tp->t_iflag & IXANY)
750 || (tp->t_cc[VSTART] == tp->t_cc[VSTOP]))) {
751 tp->t_state &= ~TS_TTSTOP;
752 tp->t_lflag &= ~FLUSHO;
756 for (; tptr < eptr; tptr++)
759 rc_rcsrt[tptr[INPUT_FLAGS_SHIFT] & 0xF]));
763 if (rc->rc_flags & RC_DOXXFER) {
765 sc->sc_scheduled_event -= LOTS_OF_EVENTS;
766 rc->rc_flags &= ~RC_DOXXFER;
767 rc->rc_tp->t_state &= ~TS_BUSY;
771 if (sc->sc_scheduled_event == 0)
774 } while (sc->sc_scheduled_event >= LOTS_OF_EVENTS);
778 rc_stop(struct tty *tp, int rw)
787 device_printf(sc->sc_dev, "channel %d: rc_stop %s%s\n",
788 rc->rc_chan, (rw & FWRITE)?"FWRITE ":"", (rw & FREAD)?"FREAD":"");
791 rc_discard_output(rc);
794 rc->rc_flags &= ~RC_DORXFER;
796 if (rc->rc_bufend == &rc->rc_ibuf[2 * RC_IBUFSIZE]) {
797 tptr = &rc->rc_ibuf[RC_IBUFSIZE];
798 rc->rc_iptr = &rc->rc_ibuf[RC_IBUFSIZE];
801 rc->rc_iptr = rc->rc_ibuf;
803 sc->sc_scheduled_event -= eptr - tptr;
805 if (tp->t_state & TS_TTSTOP)
806 rc->rc_flags |= RC_OSUSP;
808 rc->rc_flags &= ~RC_OSUSP;
813 rc_close(struct tty *tp)
822 rcout(sc, CD180_CAR, rc->rc_chan);
824 /* Disable rx/tx intrs */
825 rcout(sc, CD180_IER, rc->rc_ier = 0);
826 if ( (tp->t_cflag & HUPCL)
827 || (!(rc->rc_flags & RC_ACTOUT)
828 && !(rc->rc_msvr & MSVR_CD)
829 && !(tp->t_cflag & CLOCAL))
830 || !(tp->t_state & TS_ISOPEN)
832 CCRCMD(sc, rc->rc_chan, CCR_ResetChan);
833 WAITFORCCR(sc, rc->rc_chan);
834 (void) rc_modem(tp, SER_RTS, 0);
837 rc->rc_flags &= ~RC_ACTOUT;
838 wakeup( &rc->rc_rcb); /* wake bi */
839 wakeup(TSA_CARR_ON(tp));
843 /* Reset the bastard */
845 rc_hwreset(struct rc_softc *sc, u_int chipid)
847 CCRCMD(sc, -1, CCR_HWRESET); /* Hardware reset */
851 rcout(sc, RC_CTOUT, 0); /* Clear timeout */
852 rcout(sc, CD180_GIVR, chipid);
853 rcout(sc, CD180_GICR, 0);
855 /* Set Prescaler Registers (1 msec) */
856 rcout(sc, CD180_PPRL, ((RC_OSCFREQ + 999) / 1000) & 0xFF);
857 rcout(sc, CD180_PPRH, ((RC_OSCFREQ + 999) / 1000) >> 8);
859 /* Initialize Priority Interrupt Level Registers */
860 rcout(sc, CD180_PILR1, RC_PILR_MODEM);
861 rcout(sc, CD180_PILR2, RC_PILR_TX);
862 rcout(sc, CD180_PILR3, RC_PILR_RX);
865 rcout(sc, RC_DTREG, ~0);
868 /* Set channel parameters */
870 rc_param(struct tty *tp, struct termios *ts)
874 int idivs, odivs, s, val, cflag, iflag, lflag, inpflow;
876 if ( ts->c_ospeed < 0 || ts->c_ospeed > 76800
877 || ts->c_ispeed < 0 || ts->c_ispeed > 76800
880 if (ts->c_ispeed == 0)
881 ts->c_ispeed = ts->c_ospeed;
882 odivs = RC_BRD(ts->c_ospeed);
883 idivs = RC_BRD(ts->c_ispeed);
890 rcout(sc, CD180_CAR, rc->rc_chan);
892 /* If speed == 0, hangup line */
893 if (ts->c_ospeed == 0) {
894 CCRCMD(sc, rc->rc_chan, CCR_ResetChan);
895 WAITFORCCR(sc, rc->rc_chan);
896 (void) rc_modem(tp, 0, SER_DTR);
899 tp->t_state &= ~TS_CAN_BYPASS_L_RINT;
905 rcout(sc, CD180_RBPRL, idivs & 0xFF);
906 rcout(sc, CD180_RBPRH, idivs >> 8);
909 rcout(sc, CD180_TBPRL, odivs & 0xFF);
910 rcout(sc, CD180_TBPRH, odivs >> 8);
913 /* set timeout value */
914 if (ts->c_ispeed > 0) {
915 int itm = ts->c_ispeed > 2400 ? 5 : 10000 / ts->c_ispeed + 1;
917 if ( !(lflag & ICANON)
918 && ts->c_cc[VMIN] != 0 && ts->c_cc[VTIME] != 0
919 && ts->c_cc[VTIME] * 10 > itm)
920 itm = ts->c_cc[VTIME] * 10;
922 rcout(sc, CD180_RTPR, itm <= 255 ? itm : 255);
925 switch (cflag & CSIZE) {
926 case CS5: val = COR1_5BITS; break;
927 case CS6: val = COR1_6BITS; break;
928 case CS7: val = COR1_7BITS; break;
930 case CS8: val = COR1_8BITS; break;
932 if (cflag & PARENB) {
936 if (!(cflag & INPCK))
942 rcout(sc, CD180_COR1, val);
944 /* Set FIFO threshold */
945 val = ts->c_ospeed <= 4800 ? 1 : CD180_NFIFO / 2;
948 && ( ts->c_cc[VSTOP] != _POSIX_VDISABLE
949 && ( ts->c_cc[VSTART] != _POSIX_VDISABLE
955 val |= COR3_SCDE|COR3_FCT;
957 rcout(sc, CD180_COR3, val);
959 /* Initialize on-chip automatic flow control */
961 rc->rc_flags &= ~(RC_CTSFLOW|RC_SEND_RDY);
962 if (cflag & CCTS_OFLOW) {
963 rc->rc_flags |= RC_CTSFLOW;
966 rc->rc_flags |= RC_SEND_RDY;
967 if (tp->t_state & TS_TTSTOP)
968 rc->rc_flags |= RC_OSUSP;
970 rc->rc_flags &= ~RC_OSUSP;
971 if (cflag & CRTS_IFLOW)
972 rc->rc_flags |= RC_RTSFLOW;
974 rc->rc_flags &= ~RC_RTSFLOW;
977 if (ts->c_cc[VSTART] != _POSIX_VDISABLE)
978 rcout(sc, CD180_SCHR1, ts->c_cc[VSTART]);
979 rcout(sc, CD180_SCHR2, ts->c_cc[VSTOP]);
985 rcout(sc, CD180_COR2, rc->rc_cor2 = val);
987 CCRCMD(sc, rc->rc_chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
992 val = cflag & CLOCAL ? 0 : MCOR1_CDzd;
993 if (cflag & CCTS_OFLOW)
995 rcout(sc, CD180_MCOR1, val);
997 val = cflag & CLOCAL ? 0 : MCOR2_CDod;
998 if (cflag & CCTS_OFLOW)
1000 rcout(sc, CD180_MCOR2, val);
1002 /* enable i/o and interrupts */
1003 CCRCMD(sc, rc->rc_chan,
1004 CCR_XMTREN | ((cflag & CREAD) ? CCR_RCVREN : CCR_RCVRDIS));
1005 WAITFORCCR(sc, rc->rc_chan);
1007 rc->rc_ier = cflag & CLOCAL ? 0 : IER_CD;
1008 if (cflag & CCTS_OFLOW)
1009 rc->rc_ier |= IER_CTS;
1011 rc->rc_ier |= IER_RxData;
1012 if (tp->t_state & TS_BUSY)
1013 rc->rc_ier |= IER_TxRdy;
1014 if (ts->c_ospeed != 0)
1015 rc_modem(tp, SER_DTR, 0);
1016 if ((cflag & CCTS_OFLOW) && (rc->rc_msvr & MSVR_CTS))
1017 rc->rc_flags |= RC_SEND_RDY;
1018 rcout(sc, CD180_IER, rc->rc_ier);
1023 /* Re-initialize board after bogus interrupts */
1025 rc_reinit(struct rc_softc *sc)
1027 struct rc_chans *rc;
1030 rc_hwreset(sc, RC_FAKEID);
1031 rc = sc->sc_channels;
1032 for (i = 0; i < CD180_NCHAN; i++, rc++)
1033 (void) rc_param(rc->rc_tp, &rc->rc_tp->t_termios);
1036 /* Modem control routines */
1039 rc_modem(struct tty *tp, int biton, int bitoff)
1041 struct rc_chans *rc;
1042 struct rc_softc *sc;
1049 rcout(sc, CD180_CAR, rc->rc_chan);
1051 if (biton == 0 && bitoff == 0) {
1052 msvr = rc->rc_msvr = rcin(sc, CD180_MSVR);
1054 if (msvr & MSVR_RTS)
1056 if (msvr & MSVR_CTS)
1058 if (msvr & MSVR_DSR)
1060 if (msvr & MSVR_DTR)
1064 if (~rcin(sc, RC_RIREG) & (1 << rc->rc_chan))
1068 if (biton & SER_DTR)
1069 rcout(sc, RC_DTREG, ~(*dtr |= 1 << rc->rc_chan));
1070 if (bitoff & SER_DTR)
1071 rcout(sc, RC_DTREG, ~(*dtr &= ~(1 << rc->rc_chan)));
1072 msvr = rcin(sc, CD180_MSVR);
1073 if (biton & SER_DTR)
1075 if (bitoff & SER_DTR)
1077 if (biton & SER_RTS)
1079 if (bitoff & SER_RTS)
1081 rcout(sc, CD180_MSVR, msvr);
1086 rc_break(struct tty *tp, int brk)
1088 struct rc_chans *rc;
1093 rc->rc_pendcmd = CD180_C_SBRK;
1095 rc->rc_pendcmd = CD180_C_EBRK;
1098 #define ERR(s) do { \
1099 device_printf(sc->sc_dev, "%s", ""); \
1102 (void) splx(old_level); \
1106 /* Test the board. */
1108 rc_test(struct rc_softc *sc)
1111 int i = 0, rcnt, old_level;
1112 unsigned int iack, chipid;
1113 unsigned short divs;
1114 static u_char ctest[] = "\377\125\252\045\244\0\377";
1118 u_char txbuf[CD180_NFIFO]; /* TX buffer */
1119 u_char rxbuf[CD180_NFIFO]; /* RX buffer */
1120 int rxptr; /* RX pointer */
1121 int txptr; /* TX pointer */
1122 } tchans[CD180_NCHAN];
1124 old_level = spltty();
1128 /* First, reset board to initial state */
1129 rc_hwreset(sc, chipid);
1131 divs = RC_BRD(19200);
1133 /* Initialize channels */
1134 for (chan = 0; chan < CD180_NCHAN; chan++) {
1136 /* Select and reset channel */
1137 rcout(sc, CD180_CAR, chan);
1138 CCRCMD(sc, chan, CCR_ResetChan);
1139 WAITFORCCR(sc, chan);
1142 rcout(sc, CD180_RBPRL, divs & 0xFF);
1143 rcout(sc, CD180_RBPRH, divs >> 8);
1144 rcout(sc, CD180_TBPRL, divs & 0xFF);
1145 rcout(sc, CD180_TBPRH, divs >> 8);
1147 /* set timeout value */
1148 rcout(sc, CD180_RTPR, 0);
1150 /* Establish local loopback */
1151 rcout(sc, CD180_COR1, COR1_NOPAR | COR1_8BITS | COR1_1SB);
1152 rcout(sc, CD180_COR2, COR2_LLM);
1153 rcout(sc, CD180_COR3, CD180_NFIFO);
1154 CCRCMD(sc, chan, CCR_CORCHG1 | CCR_CORCHG2 | CCR_CORCHG3);
1155 CCRCMD(sc, chan, CCR_RCVREN | CCR_XMTREN);
1156 WAITFORCCR(sc, chan);
1157 rcout(sc, CD180_MSVR, MSVR_RTS);
1159 /* Fill TXBUF with test data */
1160 for (i = 0; i < CD180_NFIFO; i++) {
1161 tchans[chan].txbuf[i] = ctest[i];
1162 tchans[chan].rxbuf[i] = 0;
1164 tchans[chan].txptr = tchans[chan].rxptr = 0;
1166 /* Now, start transmit */
1167 rcout(sc, CD180_IER, IER_TxMpty|IER_RxData);
1169 /* Pseudo-interrupt poll stuff */
1170 for (rcnt = 10000; rcnt-- > 0; rcnt--) {
1171 i = ~(rcin(sc, RC_BSR));
1172 if (i & RC_BSR_TOUT)
1173 ERR(("BSR timeout bit set\n"));
1174 else if (i & RC_BSR_TXINT) {
1175 iack = rcin(sc, RC_PILR_TX);
1176 if (iack != (GIVR_IT_TDI | chipid))
1177 ERR(("Bad TX intr ack (%02x != %02x)\n",
1178 iack, GIVR_IT_TDI | chipid));
1179 chan = (rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1180 /* If no more data to transmit, disable TX intr */
1181 if (tchans[chan].txptr >= CD180_NFIFO) {
1182 iack = rcin(sc, CD180_IER);
1183 rcout(sc, CD180_IER, iack & ~IER_TxMpty);
1185 for (iack = tchans[chan].txptr;
1186 iack < CD180_NFIFO; iack++)
1187 rcout(sc, CD180_TDR,
1188 tchans[chan].txbuf[iack]);
1189 tchans[chan].txptr = iack;
1191 rcout(sc, CD180_EOIR, 0);
1192 } else if (i & RC_BSR_RXINT) {
1195 iack = rcin(sc, RC_PILR_RX);
1196 if (iack != (GIVR_IT_RGDI | chipid) &&
1197 iack != (GIVR_IT_REI | chipid))
1198 ERR(("Bad RX intr ack (%02x != %02x)\n",
1199 iack, GIVR_IT_RGDI | chipid));
1200 chan = (rcin(sc, CD180_GICR) & GICR_CHAN) >> GICR_LSH;
1201 ucnt = rcin(sc, CD180_RDCR) & 0xF;
1202 while (ucnt-- > 0) {
1203 iack = rcin(sc, CD180_RCSR);
1204 if (iack & RCSR_Timeout)
1207 ERR(("Bad char chan %d (RCSR = %02X)\n",
1209 if (tchans[chan].rxptr > CD180_NFIFO)
1210 ERR(("Got extra chars chan %d\n",
1212 tchans[chan].rxbuf[tchans[chan].rxptr++] =
1213 rcin(sc, CD180_RDR);
1215 rcout(sc, CD180_EOIR, 0);
1217 rcout(sc, RC_CTOUT, 0);
1218 for (iack = chan = 0; chan < CD180_NCHAN; chan++)
1219 if (tchans[chan].rxptr >= CD180_NFIFO)
1221 if (iack == CD180_NCHAN)
1224 for (chan = 0; chan < CD180_NCHAN; chan++) {
1225 /* Select and reset channel */
1226 rcout(sc, CD180_CAR, chan);
1227 CCRCMD(sc, chan, CCR_ResetChan);
1231 ERR(("looses characters during local loopback\n"));
1232 /* Now, check data */
1233 for (chan = 0; chan < CD180_NCHAN; chan++)
1234 for (i = 0; i < CD180_NFIFO; i++)
1235 if (ctest[i] != tchans[chan].rxbuf[i])
1236 ERR(("data mismatch chan %d ptr %d (%d != %d)\n",
1237 chan, i, ctest[i], tchans[chan].rxbuf[i]));
1238 (void) splx(old_level);
1244 printrcflags(struct rc_chans *rc, char *comment)
1246 struct rc_softc *sc;
1247 u_short f = rc->rc_flags;
1250 printf("rc%d/%d: %s flags: %s%s%s%s%s%s%s%s%s%s%s%s\n",
1251 rc->rc_rcb->rcb_unit, rc->rc_chan, comment,
1252 (f & RC_DTR_OFF)?"DTR_OFF " :"",
1253 (f & RC_ACTOUT) ?"ACTOUT " :"",
1254 (f & RC_RTSFLOW)?"RTSFLOW " :"",
1255 (f & RC_CTSFLOW)?"CTSFLOW " :"",
1256 (f & RC_DORXFER)?"DORXFER " :"",
1257 (f & RC_DOXXFER)?"DOXXFER " :"",
1258 (f & RC_MODCHG) ?"MODCHG " :"",
1259 (f & RC_OSUSP) ?"OSUSP " :"",
1260 (f & RC_OSBUSY) ?"OSBUSY " :"",
1261 (f & RC_WAS_BUFOVFL) ?"BUFOVFL " :"",
1262 (f & RC_WAS_SILOVFL) ?"SILOVFL " :"",
1263 (f & RC_SEND_RDY) ?"SEND_RDY":"");
1265 rcout(sc, CD180_CAR, rc->rc_chan);
1267 printf("rc%d/%d: msvr %02x ier %02x ccsr %02x\n",
1268 rc->rc_rcb->rcb_unit, rc->rc_chan,
1269 rcin(sc, CD180_MSVR),
1270 rcin(sc, CD180_IER),
1271 rcin(sc, CD180_CCSR));
1273 #endif /* RCDEBUG */
1276 rc_discard_output(struct rc_chans *rc)
1279 if (rc->rc_flags & RC_DOXXFER) {
1280 rc->rc_rcb->sc_scheduled_event -= LOTS_OF_EVENTS;
1281 rc->rc_flags &= ~RC_DOXXFER;
1283 rc->rc_optr = rc->rc_obufend;
1284 rc->rc_tp->t_state &= ~TS_BUSY;
1286 ttwwakeup(rc->rc_tp);
1290 rc_wait0(struct rc_softc *sc, int chan, int line)
1294 for (rcnt = 50; rcnt && rcin(sc, CD180_CCR); rcnt--)
1297 device_printf(sc->sc_dev,
1298 "channel %d command timeout, rc.c line: %d\n", chan, line);
1301 static device_method_t rc_methods[] = {
1302 /* Device interface */
1303 DEVMETHOD(device_probe, rc_probe),
1304 DEVMETHOD(device_attach, rc_attach),
1305 DEVMETHOD(device_detach, rc_detach),
1309 static driver_t rc_driver = {
1311 rc_methods, sizeof(struct rc_softc),
1314 DRIVER_MODULE(rc, isa, rc_driver, rc_devclass, 0, 0);