2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
45 * This driver is designed to support RealTek's next generation of
46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
51 * with the older 8139 family, however it also supports a special
52 * C+ mode of operation that provides several new performance enhancing
53 * features. These include:
55 * o Descriptor based DMA mechanism. Each descriptor represents
56 * a single packet fragment. Data buffers may be aligned on
61 * o TCP/IP checksum offload for both RX and TX
63 * o High and normal priority transmit DMA rings
65 * o VLAN tag insertion and extraction
67 * o TCP large send (segmentation offload)
69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
70 * programming API is fairly straightforward. The RX filtering, EEPROM
71 * access and PHY access is the same as it is on the older 8139 series
74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
75 * same programming API and feature set as the 8139C+ with the following
76 * differences and additions:
82 * o GMII and TBI ports/registers for interfacing with copper
85 * o RX and TX DMA rings can have up to 1024 descriptors
86 * (the 8139C+ allows a maximum of 64)
88 * o Slight differences in register layout from the 8139C+
90 * The TX start and timer interrupt registers are at different locations
91 * on the 8169 than they are on the 8139C+. Also, the status word in the
92 * RX descriptor has a slightly different bit layout. The 8169 does not
93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
97 * (the 'S' stands for 'single-chip'). These devices have the same
98 * programming API as the older 8169, but also have some vendor-specific
99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
102 * This driver takes advantage of the RX and TX checksum offload and
103 * VLAN tag insertion/extraction features. It also implements TX
104 * interrupt moderation using the timer interrupt registers, which
105 * significantly reduces TX interrupt load. There is also support
106 * for jumbo frames, however the 8169/8169S/8110S can not transmit
107 * jumbo frames larger than 7440, so the max MTU possible with this
108 * driver is 7422 bytes.
111 #ifdef HAVE_KERNEL_OPTION_HEADERS
112 #include "opt_device_polling.h"
115 #include <sys/param.h>
116 #include <sys/endian.h>
117 #include <sys/systm.h>
118 #include <sys/sockio.h>
119 #include <sys/mbuf.h>
120 #include <sys/malloc.h>
121 #include <sys/module.h>
122 #include <sys/kernel.h>
123 #include <sys/socket.h>
124 #include <sys/lock.h>
125 #include <sys/mutex.h>
126 #include <sys/sysctl.h>
127 #include <sys/taskqueue.h>
130 #include <net/if_var.h>
131 #include <net/if_arp.h>
132 #include <net/ethernet.h>
133 #include <net/if_dl.h>
134 #include <net/if_media.h>
135 #include <net/if_types.h>
136 #include <net/if_vlan_var.h>
140 #include <machine/bus.h>
141 #include <machine/resource.h>
143 #include <sys/rman.h>
145 #include <dev/mii/mii.h>
146 #include <dev/mii/miivar.h>
148 #include <dev/pci/pcireg.h>
149 #include <dev/pci/pcivar.h>
151 #include <dev/rl/if_rlreg.h>
153 MODULE_DEPEND(re, pci, 1, 1, 1);
154 MODULE_DEPEND(re, ether, 1, 1, 1);
155 MODULE_DEPEND(re, miibus, 1, 1, 1);
157 /* "device miibus" required. See GENERIC if you get errors here. */
158 #include "miibus_if.h"
161 static int intr_filter = 0;
162 TUNABLE_INT("hw.re.intr_filter", &intr_filter);
163 static int msi_disable = 0;
164 TUNABLE_INT("hw.re.msi_disable", &msi_disable);
165 static int msix_disable = 0;
166 TUNABLE_INT("hw.re.msix_disable", &msix_disable);
167 static int prefer_iomap = 0;
168 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap);
170 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
173 * Various supported device vendors/types and their names.
175 static const struct rl_type re_devs[] = {
176 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0,
177 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
178 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0,
179 "D-Link DGE-530(T) Gigabit Ethernet Adapter" },
180 { RT_VENDORID, RT_DEVICEID_8139, 0,
181 "RealTek 8139C+ 10/100BaseTX" },
182 { RT_VENDORID, RT_DEVICEID_8101E, 0,
183 "RealTek 810xE PCIe 10/100baseTX" },
184 { RT_VENDORID, RT_DEVICEID_8168, 0,
185 "RealTek 8168/8111 B/C/CP/D/DP/E/F/G PCIe Gigabit Ethernet" },
186 { RT_VENDORID, RT_DEVICEID_8169, 0,
187 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" },
188 { RT_VENDORID, RT_DEVICEID_8169SC, 0,
189 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
190 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0,
191 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
192 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0,
193 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" },
194 { USR_VENDORID, USR_DEVICEID_997902, 0,
195 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" }
198 static const struct rl_hwrev re_hwrevs[] = {
199 { RL_HWREV_8139, RL_8139, "", RL_MTU },
200 { RL_HWREV_8139A, RL_8139, "A", RL_MTU },
201 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU },
202 { RL_HWREV_8139B, RL_8139, "B", RL_MTU },
203 { RL_HWREV_8130, RL_8139, "8130", RL_MTU },
204 { RL_HWREV_8139C, RL_8139, "C", RL_MTU },
205 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU },
206 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU },
207 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU },
208 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU },
209 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU },
210 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU },
211 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU },
212 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU },
213 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU },
214 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU },
215 { RL_HWREV_8100, RL_8139, "8100", RL_MTU },
216 { RL_HWREV_8101, RL_8139, "8101", RL_MTU },
217 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU },
218 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU },
219 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU },
220 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU },
221 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU },
222 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU },
223 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU },
224 { RL_HWREV_8402, RL_8169, "8402", RL_MTU },
225 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU },
226 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU },
227 { RL_HWREV_8106E, RL_8169, "8106E", RL_MTU },
228 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU },
229 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU },
230 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K },
231 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K },
232 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K },
233 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K },
234 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K },
235 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K},
236 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K},
237 { RL_HWREV_8168EP, RL_8169, "8168EP/8111EP", RL_JUMBO_MTU_9K},
238 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K},
239 { RL_HWREV_8168G, RL_8169, "8168G/8111G", RL_JUMBO_MTU_9K},
240 { RL_HWREV_8168GU, RL_8169, "8168GU/8111GU", RL_JUMBO_MTU_9K},
241 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K},
242 { RL_HWREV_8411B, RL_8169, "8411B", RL_JUMBO_MTU_9K},
246 static int re_probe (device_t);
247 static int re_attach (device_t);
248 static int re_detach (device_t);
250 static int re_encap (struct rl_softc *, struct mbuf **);
252 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int);
253 static int re_allocmem (device_t, struct rl_softc *);
254 static __inline void re_discard_rxbuf
255 (struct rl_softc *, int);
256 static int re_newbuf (struct rl_softc *, int);
257 static int re_jumbo_newbuf (struct rl_softc *, int);
258 static int re_rx_list_init (struct rl_softc *);
259 static int re_jrx_list_init (struct rl_softc *);
260 static int re_tx_list_init (struct rl_softc *);
262 static __inline void re_fixup_rx
265 static int re_rxeof (struct rl_softc *, int *);
266 static void re_txeof (struct rl_softc *);
267 #ifdef DEVICE_POLLING
268 static int re_poll (struct ifnet *, enum poll_cmd, int);
269 static int re_poll_locked (struct ifnet *, enum poll_cmd, int);
271 static int re_intr (void *);
272 static void re_intr_msi (void *);
273 static void re_tick (void *);
274 static void re_int_task (void *, int);
275 static void re_start (struct ifnet *);
276 static void re_start_locked (struct ifnet *);
277 static int re_ioctl (struct ifnet *, u_long, caddr_t);
278 static void re_init (void *);
279 static void re_init_locked (struct rl_softc *);
280 static void re_stop (struct rl_softc *);
281 static void re_watchdog (struct rl_softc *);
282 static int re_suspend (device_t);
283 static int re_resume (device_t);
284 static int re_shutdown (device_t);
285 static int re_ifmedia_upd (struct ifnet *);
286 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *);
288 static void re_eeprom_putbyte (struct rl_softc *, int);
289 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *);
290 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int);
291 static int re_gmii_readreg (device_t, int, int);
292 static int re_gmii_writereg (device_t, int, int, int);
294 static int re_miibus_readreg (device_t, int, int);
295 static int re_miibus_writereg (device_t, int, int, int);
296 static void re_miibus_statchg (device_t);
298 static void re_set_jumbo (struct rl_softc *, int);
299 static void re_set_rxmode (struct rl_softc *);
300 static void re_reset (struct rl_softc *);
301 static void re_setwol (struct rl_softc *);
302 static void re_clrwol (struct rl_softc *);
303 static void re_set_linkspeed (struct rl_softc *);
305 #ifdef DEV_NETMAP /* see ixgbe.c for details */
306 #include <dev/netmap/if_re_netmap.h>
307 #endif /* !DEV_NETMAP */
310 static int re_diag (struct rl_softc *);
313 static void re_add_sysctls (struct rl_softc *);
314 static int re_sysctl_stats (SYSCTL_HANDLER_ARGS);
315 static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int);
316 static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS);
318 static device_method_t re_methods[] = {
319 /* Device interface */
320 DEVMETHOD(device_probe, re_probe),
321 DEVMETHOD(device_attach, re_attach),
322 DEVMETHOD(device_detach, re_detach),
323 DEVMETHOD(device_suspend, re_suspend),
324 DEVMETHOD(device_resume, re_resume),
325 DEVMETHOD(device_shutdown, re_shutdown),
328 DEVMETHOD(miibus_readreg, re_miibus_readreg),
329 DEVMETHOD(miibus_writereg, re_miibus_writereg),
330 DEVMETHOD(miibus_statchg, re_miibus_statchg),
335 static driver_t re_driver = {
338 sizeof(struct rl_softc)
341 static devclass_t re_devclass;
343 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0);
344 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
347 CSR_WRITE_1(sc, RL_EECMD, \
348 CSR_READ_1(sc, RL_EECMD) | x)
351 CSR_WRITE_1(sc, RL_EECMD, \
352 CSR_READ_1(sc, RL_EECMD) & ~x)
355 * Send a read command and address to the EEPROM, check for ACK.
358 re_eeprom_putbyte(struct rl_softc *sc, int addr)
362 d = addr | (RL_9346_READ << sc->rl_eewidth);
365 * Feed in each bit and strobe the clock.
368 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) {
370 EE_SET(RL_EE_DATAIN);
372 EE_CLR(RL_EE_DATAIN);
383 * Read a word of data stored in the EEPROM at address 'addr.'
386 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest)
392 * Send address of word we want to read.
394 re_eeprom_putbyte(sc, addr);
397 * Start reading bits from EEPROM.
399 for (i = 0x8000; i; i >>= 1) {
402 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
412 * Read a sequence of words from the EEPROM.
415 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt)
418 u_int16_t word = 0, *ptr;
420 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
424 for (i = 0; i < cnt; i++) {
425 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL);
426 re_eeprom_getword(sc, off + i, &word);
427 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL);
428 ptr = (u_int16_t *)(dest + (i * 2));
432 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
436 re_gmii_readreg(device_t dev, int phy, int reg)
442 sc = device_get_softc(dev);
444 /* Let the rgephy driver read the GMEDIASTAT register */
446 if (reg == RL_GMEDIASTAT) {
447 rval = CSR_READ_1(sc, RL_GMEDIASTAT);
451 CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
453 for (i = 0; i < RL_PHY_TIMEOUT; i++) {
454 rval = CSR_READ_4(sc, RL_PHYAR);
455 if (rval & RL_PHYAR_BUSY)
460 if (i == RL_PHY_TIMEOUT) {
461 device_printf(sc->rl_dev, "PHY read failed\n");
466 * Controller requires a 20us delay to process next MDIO request.
470 return (rval & RL_PHYAR_PHYDATA);
474 re_gmii_writereg(device_t dev, int phy, int reg, int data)
480 sc = device_get_softc(dev);
482 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
483 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
485 for (i = 0; i < RL_PHY_TIMEOUT; i++) {
486 rval = CSR_READ_4(sc, RL_PHYAR);
487 if (!(rval & RL_PHYAR_BUSY))
492 if (i == RL_PHY_TIMEOUT) {
493 device_printf(sc->rl_dev, "PHY write failed\n");
498 * Controller requires a 20us delay to process next MDIO request.
506 re_miibus_readreg(device_t dev, int phy, int reg)
510 u_int16_t re8139_reg = 0;
512 sc = device_get_softc(dev);
514 if (sc->rl_type == RL_8169) {
515 rval = re_gmii_readreg(dev, phy, reg);
521 re8139_reg = RL_BMCR;
524 re8139_reg = RL_BMSR;
527 re8139_reg = RL_ANAR;
530 re8139_reg = RL_ANER;
533 re8139_reg = RL_LPAR;
539 * Allow the rlphy driver to read the media status
540 * register. If we have a link partner which does not
541 * support NWAY, this is the register which will tell
542 * us the results of parallel detection.
545 rval = CSR_READ_1(sc, RL_MEDIASTAT);
548 device_printf(sc->rl_dev, "bad phy register\n");
551 rval = CSR_READ_2(sc, re8139_reg);
552 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) {
553 /* 8139C+ has different bit layout. */
554 rval &= ~(BMCR_LOOP | BMCR_ISO);
560 re_miibus_writereg(device_t dev, int phy, int reg, int data)
563 u_int16_t re8139_reg = 0;
566 sc = device_get_softc(dev);
568 if (sc->rl_type == RL_8169) {
569 rval = re_gmii_writereg(dev, phy, reg, data);
575 re8139_reg = RL_BMCR;
576 if (sc->rl_type == RL_8139CPLUS) {
577 /* 8139C+ has different bit layout. */
578 data &= ~(BMCR_LOOP | BMCR_ISO);
582 re8139_reg = RL_BMSR;
585 re8139_reg = RL_ANAR;
588 re8139_reg = RL_ANER;
591 re8139_reg = RL_LPAR;
598 device_printf(sc->rl_dev, "bad phy register\n");
601 CSR_WRITE_2(sc, re8139_reg, data);
606 re_miibus_statchg(device_t dev)
610 struct mii_data *mii;
612 sc = device_get_softc(dev);
613 mii = device_get_softc(sc->rl_miibus);
615 if (mii == NULL || ifp == NULL ||
616 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
619 sc->rl_flags &= ~RL_FLAG_LINK;
620 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
621 (IFM_ACTIVE | IFM_AVALID)) {
622 switch (IFM_SUBTYPE(mii->mii_media_active)) {
625 sc->rl_flags |= RL_FLAG_LINK;
628 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0)
630 sc->rl_flags |= RL_FLAG_LINK;
637 * RealTek controllers does not provide any interface to
638 * Tx/Rx MACs for resolved speed, duplex and flow-control
644 * Set the RX configuration and 64-bit multicast hash filter.
647 re_set_rxmode(struct rl_softc *sc)
650 struct ifmultiaddr *ifma;
651 uint32_t hashes[2] = { 0, 0 };
658 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD;
659 if ((sc->rl_flags & RL_FLAG_EARLYOFF) != 0)
660 rxfilt |= RL_RXCFG_EARLYOFF;
661 else if ((sc->rl_flags & RL_FLAG_EARLYOFFV2) != 0)
662 rxfilt |= RL_RXCFG_EARLYOFFV2;
664 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
665 if (ifp->if_flags & IFF_PROMISC)
666 rxfilt |= RL_RXCFG_RX_ALLPHYS;
668 * Unlike other hardwares, we have to explicitly set
669 * RL_RXCFG_RX_MULTI to receive multicast frames in
672 rxfilt |= RL_RXCFG_RX_MULTI;
673 hashes[0] = hashes[1] = 0xffffffff;
678 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
679 if (ifma->ifma_addr->sa_family != AF_LINK)
681 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
682 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
684 hashes[0] |= (1 << h);
686 hashes[1] |= (1 << (h - 32));
688 if_maddr_runlock(ifp);
690 if (hashes[0] != 0 || hashes[1] != 0) {
692 * For some unfathomable reason, RealTek decided to
693 * reverse the order of the multicast hash registers
694 * in the PCI Express parts. This means we have to
695 * write the hash pattern in reverse order for those
698 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) {
699 h = bswap32(hashes[0]);
700 hashes[0] = bswap32(hashes[1]);
703 rxfilt |= RL_RXCFG_RX_MULTI;
706 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168F) {
707 /* Disable multicast filtering due to silicon bug. */
708 hashes[0] = 0xffffffff;
709 hashes[1] = 0xffffffff;
713 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
714 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
715 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
719 re_reset(struct rl_softc *sc)
725 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
727 for (i = 0; i < RL_TIMEOUT; i++) {
729 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
733 device_printf(sc->rl_dev, "reset never completed!\n");
735 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0)
736 CSR_WRITE_1(sc, 0x82, 1);
737 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S)
738 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0);
744 * The following routine is designed to test for a defect on some
745 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
746 * lines connected to the bus, however for a 32-bit only card, they
747 * should be pulled high. The result of this defect is that the
748 * NIC will not work right if you plug it into a 64-bit slot: DMA
749 * operations will be done with 64-bit transfers, which will fail
750 * because the 64-bit data lines aren't connected.
752 * There's no way to work around this (short of talking a soldering
753 * iron to the board), however we can detect it. The method we use
754 * here is to put the NIC into digital loopback mode, set the receiver
755 * to promiscuous mode, and then try to send a frame. We then compare
756 * the frame data we sent to what was received. If the data matches,
757 * then the NIC is working correctly, otherwise we know the user has
758 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
759 * slot. In the latter case, there's no way the NIC can work correctly,
760 * so we print out a message on the console and abort the device attach.
764 re_diag(struct rl_softc *sc)
766 struct ifnet *ifp = sc->rl_ifp;
768 struct ether_header *eh;
769 struct rl_desc *cur_rx;
772 int total_len, i, error = 0, phyaddr;
773 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
774 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
776 /* Allocate a single mbuf */
777 MGETHDR(m0, M_NOWAIT, MT_DATA);
784 * Initialize the NIC in test mode. This sets the chip up
785 * so that it can send and receive frames, but performs the
786 * following special functions:
787 * - Puts receiver in promiscuous mode
788 * - Enables digital loopback mode
789 * - Leaves interrupts turned off
792 ifp->if_flags |= IFF_PROMISC;
794 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
796 sc->rl_flags |= RL_FLAG_LINK;
797 if (sc->rl_type == RL_8169)
802 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET);
803 for (i = 0; i < RL_TIMEOUT; i++) {
804 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR);
805 if (!(status & BMCR_RESET))
809 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP);
810 CSR_WRITE_2(sc, RL_ISR, RL_INTRS);
814 /* Put some data in the mbuf */
816 eh = mtod(m0, struct ether_header *);
817 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
818 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
819 eh->ether_type = htons(ETHERTYPE_IP);
820 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
823 * Queue the packet, start transmission.
824 * Note: IF_HANDOFF() ultimately calls re_start() for us.
827 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
829 /* XXX: re_diag must not be called when in ALTQ mode */
830 IF_HANDOFF(&ifp->if_snd, m0, ifp);
834 /* Wait for it to propagate through the chip */
837 for (i = 0; i < RL_TIMEOUT; i++) {
838 status = CSR_READ_2(sc, RL_ISR);
839 CSR_WRITE_2(sc, RL_ISR, status);
840 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
841 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
846 if (i == RL_TIMEOUT) {
847 device_printf(sc->rl_dev,
848 "diagnostic failed, failed to receive packet in"
855 * The packet should have been dumped into the first
856 * entry in the RX DMA ring. Grab it from there.
859 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
860 sc->rl_ldata.rl_rx_list_map,
861 BUS_DMASYNC_POSTREAD);
862 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
863 sc->rl_ldata.rl_rx_desc[0].rx_dmamap,
864 BUS_DMASYNC_POSTREAD);
865 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
866 sc->rl_ldata.rl_rx_desc[0].rx_dmamap);
868 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m;
869 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL;
870 eh = mtod(m0, struct ether_header *);
872 cur_rx = &sc->rl_ldata.rl_rx_list[0];
873 total_len = RL_RXBYTES(cur_rx);
874 rxstat = le32toh(cur_rx->rl_cmdstat);
876 if (total_len != ETHER_MIN_LEN) {
877 device_printf(sc->rl_dev,
878 "diagnostic failed, received short packet\n");
883 /* Test that the received packet data matches what we sent. */
885 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
886 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
887 ntohs(eh->ether_type) != ETHERTYPE_IP) {
888 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n");
889 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n",
890 dst, ":", src, ":", ETHERTYPE_IP);
891 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n",
892 eh->ether_dhost, ":", eh->ether_shost, ":",
893 ntohs(eh->ether_type));
894 device_printf(sc->rl_dev, "You may have a defective 32-bit "
895 "NIC plugged into a 64-bit PCI slot.\n");
896 device_printf(sc->rl_dev, "Please re-install the NIC in a "
897 "32-bit slot for proper operation.\n");
898 device_printf(sc->rl_dev, "Read the re(4) man page for more "
904 /* Turn interface off, release resources */
907 sc->rl_flags &= ~RL_FLAG_LINK;
908 ifp->if_flags &= ~IFF_PROMISC;
921 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
922 * IDs against our list and return a device name if we find a match.
925 re_probe(device_t dev)
927 const struct rl_type *t;
928 uint16_t devid, vendor;
929 uint16_t revid, sdevid;
932 vendor = pci_get_vendor(dev);
933 devid = pci_get_device(dev);
934 revid = pci_get_revid(dev);
935 sdevid = pci_get_subdevice(dev);
937 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) {
938 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) {
940 * Only attach to rev. 3 of the Linksys EG1032 adapter.
941 * Rev. 2 is supported by sk(4).
947 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
949 /* 8139, let rl(4) take care of this device. */
955 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) {
956 if (vendor == t->rl_vid && devid == t->rl_did) {
957 device_set_desc(dev, t->rl_name);
958 return (BUS_PROBE_DEFAULT);
966 * Map a single buffer address.
970 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
977 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
979 *addr = segs->ds_addr;
983 re_allocmem(device_t dev, struct rl_softc *sc)
986 bus_size_t rx_list_size, tx_list_size;
990 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc);
991 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc);
994 * Allocate the parent bus DMA tag appropriate for PCI.
995 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD
996 * register should be set. However some RealTek chips are known
997 * to be buggy on DAC handling, therefore disable DAC by limiting
998 * DMA address space to 32bit. PCIe variants of RealTek chips
999 * may not have the limitation.
1001 lowaddr = BUS_SPACE_MAXADDR;
1002 if ((sc->rl_flags & RL_FLAG_PCIE) == 0)
1003 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1004 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
1005 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL,
1006 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1007 NULL, NULL, &sc->rl_parent_tag);
1009 device_printf(dev, "could not allocate parent DMA tag\n");
1014 * Allocate map for TX mbufs.
1016 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0,
1017 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
1018 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0,
1019 NULL, NULL, &sc->rl_ldata.rl_tx_mtag);
1021 device_printf(dev, "could not allocate TX DMA tag\n");
1026 * Allocate map for RX mbufs.
1029 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
1030 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t),
1031 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1032 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL,
1033 &sc->rl_ldata.rl_jrx_mtag);
1036 "could not allocate jumbo RX DMA tag\n");
1040 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0,
1041 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1042 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag);
1044 device_printf(dev, "could not allocate RX DMA tag\n");
1049 * Allocate map for TX descriptor list.
1051 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1052 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1053 NULL, tx_list_size, 1, tx_list_size, 0,
1054 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag);
1056 device_printf(dev, "could not allocate TX DMA ring tag\n");
1060 /* Allocate DMA'able memory for the TX ring */
1062 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
1063 (void **)&sc->rl_ldata.rl_tx_list,
1064 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1065 &sc->rl_ldata.rl_tx_list_map);
1067 device_printf(dev, "could not allocate TX DMA ring\n");
1071 /* Load the map for the TX ring. */
1073 sc->rl_ldata.rl_tx_list_addr = 0;
1074 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
1075 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
1076 tx_list_size, re_dma_map_addr,
1077 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT);
1078 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) {
1079 device_printf(dev, "could not load TX DMA ring\n");
1083 /* Create DMA maps for TX buffers */
1085 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
1086 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0,
1087 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
1089 device_printf(dev, "could not create DMA map for TX\n");
1095 * Allocate map for RX descriptor list.
1097 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1098 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1099 NULL, rx_list_size, 1, rx_list_size, 0,
1100 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag);
1102 device_printf(dev, "could not create RX DMA ring tag\n");
1106 /* Allocate DMA'able memory for the RX ring */
1108 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag,
1109 (void **)&sc->rl_ldata.rl_rx_list,
1110 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1111 &sc->rl_ldata.rl_rx_list_map);
1113 device_printf(dev, "could not allocate RX DMA ring\n");
1117 /* Load the map for the RX ring. */
1119 sc->rl_ldata.rl_rx_list_addr = 0;
1120 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag,
1121 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
1122 rx_list_size, re_dma_map_addr,
1123 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT);
1124 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) {
1125 device_printf(dev, "could not load RX DMA ring\n");
1129 /* Create DMA maps for RX buffers */
1131 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
1132 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0,
1133 &sc->rl_ldata.rl_jrx_sparemap);
1136 "could not create spare DMA map for jumbo RX\n");
1139 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1140 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0,
1141 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap);
1144 "could not create DMA map for jumbo RX\n");
1149 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
1150 &sc->rl_ldata.rl_rx_sparemap);
1152 device_printf(dev, "could not create spare DMA map for RX\n");
1155 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1156 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
1157 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
1159 device_printf(dev, "could not create DMA map for RX\n");
1164 /* Create DMA map for statistics. */
1165 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0,
1166 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1167 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL,
1168 &sc->rl_ldata.rl_stag);
1170 device_printf(dev, "could not create statistics DMA tag\n");
1173 /* Allocate DMA'able memory for statistics. */
1174 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag,
1175 (void **)&sc->rl_ldata.rl_stats,
1176 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1177 &sc->rl_ldata.rl_smap);
1180 "could not allocate statistics DMA memory\n");
1183 /* Load the map for statistics. */
1184 sc->rl_ldata.rl_stats_addr = 0;
1185 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap,
1186 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr,
1187 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT);
1188 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) {
1189 device_printf(dev, "could not load statistics DMA memory\n");
1197 * Attach the interface. Allocate softc structures, do ifmedia
1198 * setup and ethernet/BPF attach.
1201 re_attach(device_t dev)
1203 u_char eaddr[ETHER_ADDR_LEN];
1204 u_int16_t as[ETHER_ADDR_LEN / 2];
1205 struct rl_softc *sc;
1207 const struct rl_hwrev *hw_rev;
1210 u_int16_t devid, re_did = 0;
1211 int error = 0, i, phy, rid;
1212 int msic, msixc, reg;
1215 sc = device_get_softc(dev);
1218 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1220 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
1223 * Map control/status registers.
1225 pci_enable_busmaster(dev);
1227 devid = pci_get_device(dev);
1229 * Prefer memory space register mapping over IO space.
1230 * Because RTL8169SC does not seem to work when memory mapping
1231 * is used always activate io mapping.
1233 if (devid == RT_DEVICEID_8169SC)
1235 if (prefer_iomap == 0) {
1236 sc->rl_res_id = PCIR_BAR(1);
1237 sc->rl_res_type = SYS_RES_MEMORY;
1238 /* RTL8168/8101E seems to use different BARs. */
1239 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E)
1240 sc->rl_res_id = PCIR_BAR(2);
1242 sc->rl_res_id = PCIR_BAR(0);
1243 sc->rl_res_type = SYS_RES_IOPORT;
1245 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
1246 &sc->rl_res_id, RF_ACTIVE);
1247 if (sc->rl_res == NULL && prefer_iomap == 0) {
1248 sc->rl_res_id = PCIR_BAR(0);
1249 sc->rl_res_type = SYS_RES_IOPORT;
1250 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
1251 &sc->rl_res_id, RF_ACTIVE);
1253 if (sc->rl_res == NULL) {
1254 device_printf(dev, "couldn't map ports/memory\n");
1259 sc->rl_btag = rman_get_bustag(sc->rl_res);
1260 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
1262 msic = pci_msi_count(dev);
1263 msixc = pci_msix_count(dev);
1264 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
1265 sc->rl_flags |= RL_FLAG_PCIE;
1266 sc->rl_expcap = reg;
1269 device_printf(dev, "MSI count : %d\n", msic);
1270 device_printf(dev, "MSI-X count : %d\n", msixc);
1272 if (msix_disable > 0)
1274 if (msi_disable > 0)
1276 /* Prefer MSI-X to MSI. */
1278 msixc = RL_MSI_MESSAGES;
1280 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1282 if (sc->rl_res_pba == NULL) {
1283 device_printf(sc->rl_dev,
1284 "could not allocate MSI-X PBA resource\n");
1286 if (sc->rl_res_pba != NULL &&
1287 pci_alloc_msix(dev, &msixc) == 0) {
1288 if (msixc == RL_MSI_MESSAGES) {
1289 device_printf(dev, "Using %d MSI-X message\n",
1291 sc->rl_flags |= RL_FLAG_MSIX;
1293 pci_release_msi(dev);
1295 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) {
1296 if (sc->rl_res_pba != NULL)
1297 bus_release_resource(dev, SYS_RES_MEMORY, rid,
1299 sc->rl_res_pba = NULL;
1303 /* Prefer MSI to INTx. */
1304 if (msixc == 0 && msic > 0) {
1305 msic = RL_MSI_MESSAGES;
1306 if (pci_alloc_msi(dev, &msic) == 0) {
1307 if (msic == RL_MSI_MESSAGES) {
1308 device_printf(dev, "Using %d MSI message\n",
1310 sc->rl_flags |= RL_FLAG_MSI;
1311 /* Explicitly set MSI enable bit. */
1312 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1313 cfg = CSR_READ_1(sc, RL_CFG2);
1315 CSR_WRITE_1(sc, RL_CFG2, cfg);
1316 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1318 pci_release_msi(dev);
1320 if ((sc->rl_flags & RL_FLAG_MSI) == 0)
1324 /* Allocate interrupt */
1325 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) {
1327 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1328 RF_SHAREABLE | RF_ACTIVE);
1329 if (sc->rl_irq[0] == NULL) {
1330 device_printf(dev, "couldn't allocate IRQ resources\n");
1335 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) {
1336 sc->rl_irq[i] = bus_alloc_resource_any(dev,
1337 SYS_RES_IRQ, &rid, RF_ACTIVE);
1338 if (sc->rl_irq[i] == NULL) {
1340 "couldn't allocate IRQ resources for "
1341 "message %d\n", rid);
1348 if ((sc->rl_flags & RL_FLAG_MSI) == 0) {
1349 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1350 cfg = CSR_READ_1(sc, RL_CFG2);
1351 if ((cfg & RL_CFG2_MSI) != 0) {
1352 device_printf(dev, "turning off MSI enable bit.\n");
1353 cfg &= ~RL_CFG2_MSI;
1354 CSR_WRITE_1(sc, RL_CFG2, cfg);
1356 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1359 /* Disable ASPM L0S/L1. */
1360 if (sc->rl_expcap != 0) {
1361 cap = pci_read_config(dev, sc->rl_expcap +
1363 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) {
1364 ctl = pci_read_config(dev, sc->rl_expcap +
1366 if ((ctl & PCIEM_LINK_CTL_ASPMC) != 0) {
1367 ctl &= ~PCIEM_LINK_CTL_ASPMC;
1368 pci_write_config(dev, sc->rl_expcap +
1369 PCIER_LINK_CTL, ctl, 2);
1370 device_printf(dev, "ASPM disabled\n");
1373 device_printf(dev, "no ASPM capability\n");
1377 hwrev = CSR_READ_4(sc, RL_TXCFG);
1378 switch (hwrev & 0x70000000) {
1381 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000);
1382 hwrev &= (RL_TXCFG_HWREV | 0x80000000);
1385 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000);
1386 sc->rl_macrev = hwrev & 0x00700000;
1387 hwrev &= RL_TXCFG_HWREV;
1390 device_printf(dev, "MAC rev. 0x%08x\n", sc->rl_macrev);
1391 while (hw_rev->rl_desc != NULL) {
1392 if (hw_rev->rl_rev == hwrev) {
1393 sc->rl_type = hw_rev->rl_type;
1394 sc->rl_hwrev = hw_rev;
1399 if (hw_rev->rl_desc == NULL) {
1400 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev);
1405 switch (hw_rev->rl_rev) {
1406 case RL_HWREV_8139CPLUS:
1407 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD;
1409 case RL_HWREV_8100E:
1410 case RL_HWREV_8101E:
1411 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER;
1413 case RL_HWREV_8102E:
1414 case RL_HWREV_8102EL:
1415 case RL_HWREV_8102EL_SPIN1:
1416 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
1417 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP |
1420 case RL_HWREV_8103E:
1421 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
1422 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP |
1423 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP;
1425 case RL_HWREV_8401E:
1426 case RL_HWREV_8105E:
1427 case RL_HWREV_8105E_SPIN1:
1428 case RL_HWREV_8106E:
1429 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1430 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1431 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD;
1434 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1435 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1436 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD |
1437 RL_FLAG_CMDSTOP_WAIT_TXQ;
1439 case RL_HWREV_8168B_SPIN1:
1440 case RL_HWREV_8168B_SPIN2:
1441 sc->rl_flags |= RL_FLAG_WOLRXENB;
1443 case RL_HWREV_8168B_SPIN3:
1444 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT;
1446 case RL_HWREV_8168C_SPIN2:
1447 sc->rl_flags |= RL_FLAG_MACSLEEP;
1449 case RL_HWREV_8168C:
1450 if (sc->rl_macrev == 0x00200000)
1451 sc->rl_flags |= RL_FLAG_MACSLEEP;
1453 case RL_HWREV_8168CP:
1454 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1455 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1456 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK;
1458 case RL_HWREV_8168D:
1459 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1460 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1461 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1462 RL_FLAG_WOL_MANLINK;
1464 case RL_HWREV_8168DP:
1465 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1466 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD |
1467 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK;
1469 case RL_HWREV_8168E:
1470 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1471 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1472 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1473 RL_FLAG_WOL_MANLINK;
1475 case RL_HWREV_8168E_VL:
1476 case RL_HWREV_8168F:
1477 sc->rl_flags |= RL_FLAG_EARLYOFF;
1480 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1481 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1482 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1483 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK;
1485 case RL_HWREV_8168EP:
1486 case RL_HWREV_8168G:
1487 case RL_HWREV_8411B:
1488 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1489 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1490 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1491 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK |
1492 RL_FLAG_EARLYOFFV2 | RL_FLAG_RXDV_GATED;
1494 case RL_HWREV_8168GU:
1495 if (pci_get_device(dev) == RT_DEVICEID_8101E) {
1497 sc->rl_flags |= RL_FLAG_FASTETHER;
1499 sc->rl_flags |= RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK;
1501 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1502 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1503 RL_FLAG_AUTOPAD | RL_FLAG_CMDSTOP_WAIT_TXQ |
1504 RL_FLAG_EARLYOFFV2 | RL_FLAG_RXDV_GATED;
1506 case RL_HWREV_8169_8110SB:
1507 case RL_HWREV_8169_8110SBL:
1508 case RL_HWREV_8169_8110SC:
1509 case RL_HWREV_8169_8110SCE:
1510 sc->rl_flags |= RL_FLAG_PHYWAKE;
1513 case RL_HWREV_8169S:
1514 case RL_HWREV_8110S:
1515 sc->rl_flags |= RL_FLAG_MACRESET;
1521 if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) {
1522 sc->rl_cfg0 = RL_8139_CFG0;
1523 sc->rl_cfg1 = RL_8139_CFG1;
1525 sc->rl_cfg3 = RL_8139_CFG3;
1526 sc->rl_cfg4 = RL_8139_CFG4;
1527 sc->rl_cfg5 = RL_8139_CFG5;
1529 sc->rl_cfg0 = RL_CFG0;
1530 sc->rl_cfg1 = RL_CFG1;
1531 sc->rl_cfg2 = RL_CFG2;
1532 sc->rl_cfg3 = RL_CFG3;
1533 sc->rl_cfg4 = RL_CFG4;
1534 sc->rl_cfg5 = RL_CFG5;
1537 /* Reset the adapter. */
1543 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1544 cfg = CSR_READ_1(sc, sc->rl_cfg1);
1546 CSR_WRITE_1(sc, sc->rl_cfg1, cfg);
1547 cfg = CSR_READ_1(sc, sc->rl_cfg5);
1548 cfg &= RL_CFG5_PME_STS;
1549 CSR_WRITE_1(sc, sc->rl_cfg5, cfg);
1550 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1552 if ((sc->rl_flags & RL_FLAG_PAR) != 0) {
1554 * XXX Should have a better way to extract station
1555 * address from EEPROM.
1557 for (i = 0; i < ETHER_ADDR_LEN; i++)
1558 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
1560 sc->rl_eewidth = RL_9356_ADDR_LEN;
1561 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
1562 if (re_did != 0x8129)
1563 sc->rl_eewidth = RL_9346_ADDR_LEN;
1566 * Get station address from the EEPROM.
1568 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3);
1569 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
1570 as[i] = le16toh(as[i]);
1571 bcopy(as, eaddr, ETHER_ADDR_LEN);
1574 if (sc->rl_type == RL_8169) {
1575 /* Set RX length mask and number of descriptors. */
1576 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
1577 sc->rl_txstart = RL_GTXSTART;
1578 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT;
1579 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT;
1581 /* Set RX length mask and number of descriptors. */
1582 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
1583 sc->rl_txstart = RL_TXSTART;
1584 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT;
1585 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT;
1588 error = re_allocmem(dev, sc);
1593 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
1595 device_printf(dev, "can not if_alloc()\n");
1600 /* Take controller out of deep sleep mode. */
1601 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
1602 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
1603 CSR_WRITE_1(sc, RL_GPIO,
1604 CSR_READ_1(sc, RL_GPIO) | 0x01);
1606 CSR_WRITE_1(sc, RL_GPIO,
1607 CSR_READ_1(sc, RL_GPIO) & ~0x01);
1610 /* Take PHY out of power down mode. */
1611 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) {
1612 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80);
1613 if (hw_rev->rl_rev == RL_HWREV_8401E)
1614 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08);
1616 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) {
1617 re_gmii_writereg(dev, 1, 0x1f, 0);
1618 re_gmii_writereg(dev, 1, 0x0e, 0);
1622 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1623 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1624 ifp->if_ioctl = re_ioctl;
1625 ifp->if_start = re_start;
1627 * RTL8168/8111C generates wrong IP checksummed frame if the
1628 * packet has IP options so disable TX checksum offloading.
1630 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C ||
1631 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2 ||
1632 sc->rl_hwrev->rl_rev == RL_HWREV_8168CP) {
1633 ifp->if_hwassist = 0;
1634 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TSO4;
1636 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP;
1637 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
1639 ifp->if_hwassist |= CSUM_TSO;
1640 ifp->if_capenable = ifp->if_capabilities;
1641 ifp->if_init = re_init;
1642 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
1643 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN;
1644 IFQ_SET_READY(&ifp->if_snd);
1646 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc);
1648 #define RE_PHYAD_INTERNAL 0
1651 phy = RE_PHYAD_INTERNAL;
1652 if (sc->rl_type == RL_8169)
1654 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd,
1655 re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE);
1657 device_printf(dev, "attaching PHYs failed\n");
1662 * Call MI attach routine.
1664 ether_ifattach(ifp, eaddr);
1666 /* VLAN capability setup */
1667 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1668 if (ifp->if_capabilities & IFCAP_HWCSUM)
1669 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
1670 /* Enable WOL if PM is supported. */
1671 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0)
1672 ifp->if_capabilities |= IFCAP_WOL;
1673 ifp->if_capenable = ifp->if_capabilities;
1674 ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST);
1676 * Don't enable TSO by default. It is known to generate
1677 * corrupted TCP segments(bad TCP options) under certain
1680 ifp->if_hwassist &= ~CSUM_TSO;
1681 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
1682 #ifdef DEVICE_POLLING
1683 ifp->if_capabilities |= IFCAP_POLLING;
1686 * Tell the upper layer(s) we support long frames.
1687 * Must appear after the call to ether_ifattach() because
1688 * ether_ifattach() sets ifi_hdrlen to the default value.
1690 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
1693 re_netmap_attach(sc);
1694 #endif /* DEV_NETMAP */
1697 * Perform hardware diagnostic on the original RTL8169.
1698 * Some 32-bit cards were incorrectly wired and would
1699 * malfunction if plugged into a 64-bit slot.
1702 if (hwrev == RL_HWREV_8169) {
1703 error = re_diag(sc);
1706 "attach aborted due to hardware diag failure\n");
1707 ether_ifdetach(ifp);
1713 #ifdef RE_TX_MODERATION
1716 /* Hook interrupt last to avoid having to lock softc */
1717 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 &&
1719 error = bus_setup_intr(dev, sc->rl_irq[0],
1720 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc,
1721 &sc->rl_intrhand[0]);
1723 error = bus_setup_intr(dev, sc->rl_irq[0],
1724 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc,
1725 &sc->rl_intrhand[0]);
1728 device_printf(dev, "couldn't set up irq\n");
1729 ether_ifdetach(ifp);
1741 * Shutdown hardware and free up resources. This can be called any
1742 * time after the mutex has been initialized. It is called in both
1743 * the error case in attach and the normal detach case so it needs
1744 * to be careful about only freeing resources that have actually been
1748 re_detach(device_t dev)
1750 struct rl_softc *sc;
1754 sc = device_get_softc(dev);
1756 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized"));
1758 /* These should only be active if attach succeeded */
1759 if (device_is_attached(dev)) {
1760 #ifdef DEVICE_POLLING
1761 if (ifp->if_capenable & IFCAP_POLLING)
1762 ether_poll_deregister(ifp);
1770 callout_drain(&sc->rl_stat_callout);
1771 taskqueue_drain(taskqueue_fast, &sc->rl_inttask);
1773 * Force off the IFF_UP flag here, in case someone
1774 * still had a BPF descriptor attached to this
1775 * interface. If they do, ether_ifdetach() will cause
1776 * the BPF code to try and clear the promisc mode
1777 * flag, which will bubble down to re_ioctl(),
1778 * which will try to call re_init() again. This will
1779 * turn the NIC back on and restart the MII ticker,
1780 * which will panic the system when the kernel tries
1781 * to invoke the re_tick() function that isn't there
1784 ifp->if_flags &= ~IFF_UP;
1785 ether_ifdetach(ifp);
1788 device_delete_child(dev, sc->rl_miibus);
1789 bus_generic_detach(dev);
1792 * The rest is resource deallocation, so we should already be
1796 if (sc->rl_intrhand[0] != NULL) {
1797 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
1798 sc->rl_intrhand[0] = NULL;
1803 #endif /* DEV_NETMAP */
1806 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0)
1810 if (sc->rl_irq[0] != NULL) {
1811 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]);
1812 sc->rl_irq[0] = NULL;
1814 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0)
1815 pci_release_msi(dev);
1816 if (sc->rl_res_pba) {
1818 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba);
1821 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id,
1824 /* Unload and free the RX DMA ring memory and map */
1826 if (sc->rl_ldata.rl_rx_list_tag) {
1827 if (sc->rl_ldata.rl_rx_list_addr)
1828 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag,
1829 sc->rl_ldata.rl_rx_list_map);
1830 if (sc->rl_ldata.rl_rx_list)
1831 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag,
1832 sc->rl_ldata.rl_rx_list,
1833 sc->rl_ldata.rl_rx_list_map);
1834 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag);
1837 /* Unload and free the TX DMA ring memory and map */
1839 if (sc->rl_ldata.rl_tx_list_tag) {
1840 if (sc->rl_ldata.rl_tx_list_addr)
1841 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag,
1842 sc->rl_ldata.rl_tx_list_map);
1843 if (sc->rl_ldata.rl_tx_list)
1844 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag,
1845 sc->rl_ldata.rl_tx_list,
1846 sc->rl_ldata.rl_tx_list_map);
1847 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag);
1850 /* Destroy all the RX and TX buffer maps */
1852 if (sc->rl_ldata.rl_tx_mtag) {
1853 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
1854 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap)
1855 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag,
1856 sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
1858 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag);
1860 if (sc->rl_ldata.rl_rx_mtag) {
1861 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1862 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap)
1863 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
1864 sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
1866 if (sc->rl_ldata.rl_rx_sparemap)
1867 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
1868 sc->rl_ldata.rl_rx_sparemap);
1869 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag);
1871 if (sc->rl_ldata.rl_jrx_mtag) {
1872 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1873 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap)
1874 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag,
1875 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap);
1877 if (sc->rl_ldata.rl_jrx_sparemap)
1878 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag,
1879 sc->rl_ldata.rl_jrx_sparemap);
1880 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag);
1882 /* Unload and free the stats buffer and map */
1884 if (sc->rl_ldata.rl_stag) {
1885 if (sc->rl_ldata.rl_stats_addr)
1886 bus_dmamap_unload(sc->rl_ldata.rl_stag,
1887 sc->rl_ldata.rl_smap);
1888 if (sc->rl_ldata.rl_stats)
1889 bus_dmamem_free(sc->rl_ldata.rl_stag,
1890 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap);
1891 bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1894 if (sc->rl_parent_tag)
1895 bus_dma_tag_destroy(sc->rl_parent_tag);
1897 mtx_destroy(&sc->rl_mtx);
1902 static __inline void
1903 re_discard_rxbuf(struct rl_softc *sc, int idx)
1905 struct rl_desc *desc;
1906 struct rl_rxdesc *rxd;
1909 if (sc->rl_ifp->if_mtu > RL_MTU &&
1910 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0)
1911 rxd = &sc->rl_ldata.rl_jrx_desc[idx];
1913 rxd = &sc->rl_ldata.rl_rx_desc[idx];
1914 desc = &sc->rl_ldata.rl_rx_list[idx];
1915 desc->rl_vlanctl = 0;
1916 cmdstat = rxd->rx_size;
1917 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1918 cmdstat |= RL_RDESC_CMD_EOR;
1919 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1923 re_newbuf(struct rl_softc *sc, int idx)
1926 struct rl_rxdesc *rxd;
1927 bus_dma_segment_t segs[1];
1929 struct rl_desc *desc;
1933 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1937 m->m_len = m->m_pkthdr.len = MCLBYTES;
1940 * This is part of an evil trick to deal with non-x86 platforms.
1941 * The RealTek chip requires RX buffers to be aligned on 64-bit
1942 * boundaries, but that will hose non-x86 machines. To get around
1943 * this, we leave some empty space at the start of each buffer
1944 * and for non-x86 hosts, we copy the buffer back six bytes
1945 * to achieve word alignment. This is slightly more efficient
1946 * than allocating a new buffer, copying the contents, and
1947 * discarding the old buffer.
1949 m_adj(m, RE_ETHER_ALIGN);
1951 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag,
1952 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
1957 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs));
1959 rxd = &sc->rl_ldata.rl_rx_desc[idx];
1960 if (rxd->rx_m != NULL) {
1961 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
1962 BUS_DMASYNC_POSTREAD);
1963 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap);
1967 map = rxd->rx_dmamap;
1968 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap;
1969 rxd->rx_size = segs[0].ds_len;
1970 sc->rl_ldata.rl_rx_sparemap = map;
1971 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
1972 BUS_DMASYNC_PREREAD);
1974 desc = &sc->rl_ldata.rl_rx_list[idx];
1975 desc->rl_vlanctl = 0;
1976 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
1977 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
1978 cmdstat = segs[0].ds_len;
1979 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1980 cmdstat |= RL_RDESC_CMD_EOR;
1981 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1987 re_jumbo_newbuf(struct rl_softc *sc, int idx)
1990 struct rl_rxdesc *rxd;
1991 bus_dma_segment_t segs[1];
1993 struct rl_desc *desc;
1997 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
2000 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
2002 m_adj(m, RE_ETHER_ALIGN);
2004 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag,
2005 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
2010 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs));
2012 rxd = &sc->rl_ldata.rl_jrx_desc[idx];
2013 if (rxd->rx_m != NULL) {
2014 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap,
2015 BUS_DMASYNC_POSTREAD);
2016 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap);
2020 map = rxd->rx_dmamap;
2021 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap;
2022 rxd->rx_size = segs[0].ds_len;
2023 sc->rl_ldata.rl_jrx_sparemap = map;
2024 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap,
2025 BUS_DMASYNC_PREREAD);
2027 desc = &sc->rl_ldata.rl_rx_list[idx];
2028 desc->rl_vlanctl = 0;
2029 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
2030 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
2031 cmdstat = segs[0].ds_len;
2032 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
2033 cmdstat |= RL_RDESC_CMD_EOR;
2034 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
2040 static __inline void
2041 re_fixup_rx(struct mbuf *m)
2044 uint16_t *src, *dst;
2046 src = mtod(m, uint16_t *);
2047 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src;
2049 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
2052 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN;
2057 re_tx_list_init(struct rl_softc *sc)
2059 struct rl_desc *desc;
2064 bzero(sc->rl_ldata.rl_tx_list,
2065 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc));
2066 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++)
2067 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL;
2069 re_netmap_tx_init(sc);
2070 #endif /* DEV_NETMAP */
2072 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1];
2073 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR);
2075 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2076 sc->rl_ldata.rl_tx_list_map,
2077 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2079 sc->rl_ldata.rl_tx_prodidx = 0;
2080 sc->rl_ldata.rl_tx_considx = 0;
2081 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt;
2087 re_rx_list_init(struct rl_softc *sc)
2091 bzero(sc->rl_ldata.rl_rx_list,
2092 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
2093 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
2094 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL;
2095 if ((error = re_newbuf(sc, i)) != 0)
2099 re_netmap_rx_init(sc);
2100 #endif /* DEV_NETMAP */
2102 /* Flush the RX descriptors */
2104 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2105 sc->rl_ldata.rl_rx_list_map,
2106 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2108 sc->rl_ldata.rl_rx_prodidx = 0;
2109 sc->rl_head = sc->rl_tail = NULL;
2110 sc->rl_int_rx_act = 0;
2116 re_jrx_list_init(struct rl_softc *sc)
2120 bzero(sc->rl_ldata.rl_rx_list,
2121 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
2122 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
2123 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL;
2124 if ((error = re_jumbo_newbuf(sc, i)) != 0)
2128 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2129 sc->rl_ldata.rl_rx_list_map,
2130 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2132 sc->rl_ldata.rl_rx_prodidx = 0;
2133 sc->rl_head = sc->rl_tail = NULL;
2134 sc->rl_int_rx_act = 0;
2140 * RX handler for C+ and 8169. For the gigE chips, we support
2141 * the reception of jumbo frames that have been fragmented
2142 * across multiple 2K mbuf cluster buffers.
2145 re_rxeof(struct rl_softc *sc, int *rx_npktsp)
2149 int i, rxerr, total_len;
2150 struct rl_desc *cur_rx;
2151 u_int32_t rxstat, rxvlan;
2152 int jumbo, maxpkt = 16, rx_npkts = 0;
2158 if (netmap_rx_irq(ifp, 0, &rx_npkts))
2160 #endif /* DEV_NETMAP */
2161 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0)
2166 /* Invalidate the descriptor memory */
2168 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2169 sc->rl_ldata.rl_rx_list_map,
2170 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2172 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0;
2173 i = RL_RX_DESC_NXT(sc, i)) {
2174 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2176 cur_rx = &sc->rl_ldata.rl_rx_list[i];
2177 rxstat = le32toh(cur_rx->rl_cmdstat);
2178 if ((rxstat & RL_RDESC_STAT_OWN) != 0)
2180 total_len = rxstat & sc->rl_rxlenmask;
2181 rxvlan = le32toh(cur_rx->rl_vlanctl);
2183 m = sc->rl_ldata.rl_jrx_desc[i].rx_m;
2185 m = sc->rl_ldata.rl_rx_desc[i].rx_m;
2187 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
2188 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) !=
2189 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) {
2191 * RTL8168C or later controllers do not
2192 * support multi-fragment packet.
2194 re_discard_rxbuf(sc, i);
2196 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) {
2197 if (re_newbuf(sc, i) != 0) {
2199 * If this is part of a multi-fragment packet,
2200 * discard all the pieces.
2202 if (sc->rl_head != NULL) {
2203 m_freem(sc->rl_head);
2204 sc->rl_head = sc->rl_tail = NULL;
2206 re_discard_rxbuf(sc, i);
2209 m->m_len = RE_RX_DESC_BUFLEN;
2210 if (sc->rl_head == NULL)
2211 sc->rl_head = sc->rl_tail = m;
2213 m->m_flags &= ~M_PKTHDR;
2214 sc->rl_tail->m_next = m;
2221 * NOTE: for the 8139C+, the frame length field
2222 * is always 12 bits in size, but for the gigE chips,
2223 * it is 13 bits (since the max RX frame length is 16K).
2224 * Unfortunately, all 32 bits in the status word
2225 * were already used, so to make room for the extra
2226 * length bit, RealTek took out the 'frame alignment
2227 * error' bit and shifted the other status bits
2228 * over one slot. The OWN, EOR, FS and LS bits are
2229 * still in the same places. We have already extracted
2230 * the frame length and checked the OWN bit, so rather
2231 * than using an alternate bit mapping, we shift the
2232 * status bits one space to the right so we can evaluate
2233 * them using the 8169 status as though it was in the
2234 * same format as that of the 8139C+.
2236 if (sc->rl_type == RL_8169)
2240 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be
2241 * set, but if CRC is clear, it will still be a valid frame.
2243 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) {
2245 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 &&
2247 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)
2250 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2252 * If this is part of a multi-fragment packet,
2253 * discard all the pieces.
2255 if (sc->rl_head != NULL) {
2256 m_freem(sc->rl_head);
2257 sc->rl_head = sc->rl_tail = NULL;
2259 re_discard_rxbuf(sc, i);
2265 * If allocating a replacement mbuf fails,
2266 * reload the current one.
2269 rxerr = re_jumbo_newbuf(sc, i);
2271 rxerr = re_newbuf(sc, i);
2273 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2274 if (sc->rl_head != NULL) {
2275 m_freem(sc->rl_head);
2276 sc->rl_head = sc->rl_tail = NULL;
2278 re_discard_rxbuf(sc, i);
2282 if (sc->rl_head != NULL) {
2284 m->m_len = total_len;
2286 m->m_len = total_len % RE_RX_DESC_BUFLEN;
2288 m->m_len = RE_RX_DESC_BUFLEN;
2291 * Special case: if there's 4 bytes or less
2292 * in this buffer, the mbuf can be discarded:
2293 * the last 4 bytes is the CRC, which we don't
2294 * care about anyway.
2296 if (m->m_len <= ETHER_CRC_LEN) {
2297 sc->rl_tail->m_len -=
2298 (ETHER_CRC_LEN - m->m_len);
2301 m->m_len -= ETHER_CRC_LEN;
2302 m->m_flags &= ~M_PKTHDR;
2303 sc->rl_tail->m_next = m;
2306 sc->rl_head = sc->rl_tail = NULL;
2307 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
2309 m->m_pkthdr.len = m->m_len =
2310 (total_len - ETHER_CRC_LEN);
2315 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2316 m->m_pkthdr.rcvif = ifp;
2318 /* Do RX checksumming if enabled */
2320 if (ifp->if_capenable & IFCAP_RXCSUM) {
2321 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
2322 /* Check IP header checksum */
2323 if (rxstat & RL_RDESC_STAT_PROTOID)
2324 m->m_pkthdr.csum_flags |=
2326 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
2327 m->m_pkthdr.csum_flags |=
2330 /* Check TCP/UDP checksum */
2331 if ((RL_TCPPKT(rxstat) &&
2332 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
2333 (RL_UDPPKT(rxstat) &&
2334 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
2335 m->m_pkthdr.csum_flags |=
2336 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2337 m->m_pkthdr.csum_data = 0xffff;
2341 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP
2343 if ((rxstat & RL_RDESC_STAT_PROTOID) &&
2344 (rxvlan & RL_RDESC_IPV4))
2345 m->m_pkthdr.csum_flags |=
2347 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) &&
2348 (rxvlan & RL_RDESC_IPV4))
2349 m->m_pkthdr.csum_flags |=
2351 if (((rxstat & RL_RDESC_STAT_TCP) &&
2352 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
2353 ((rxstat & RL_RDESC_STAT_UDP) &&
2354 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
2355 m->m_pkthdr.csum_flags |=
2356 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2357 m->m_pkthdr.csum_data = 0xffff;
2362 if (rxvlan & RL_RDESC_VLANCTL_TAG) {
2363 m->m_pkthdr.ether_vtag =
2364 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA));
2365 m->m_flags |= M_VLANTAG;
2368 (*ifp->if_input)(ifp, m);
2373 /* Flush the RX DMA ring */
2375 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2376 sc->rl_ldata.rl_rx_list_map,
2377 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2379 sc->rl_ldata.rl_rx_prodidx = i;
2381 if (rx_npktsp != NULL)
2382 *rx_npktsp = rx_npkts;
2390 re_txeof(struct rl_softc *sc)
2393 struct rl_txdesc *txd;
2397 cons = sc->rl_ldata.rl_tx_considx;
2398 if (cons == sc->rl_ldata.rl_tx_prodidx)
2403 if (netmap_tx_irq(ifp, 0))
2405 #endif /* DEV_NETMAP */
2406 /* Invalidate the TX descriptor list */
2407 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2408 sc->rl_ldata.rl_tx_list_map,
2409 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2411 for (; cons != sc->rl_ldata.rl_tx_prodidx;
2412 cons = RL_TX_DESC_NXT(sc, cons)) {
2413 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat);
2414 if (txstat & RL_TDESC_STAT_OWN)
2417 * We only stash mbufs in the last descriptor
2418 * in a fragment chain, which also happens to
2419 * be the only place where the TX status bits
2422 if (txstat & RL_TDESC_CMD_EOF) {
2423 txd = &sc->rl_ldata.rl_tx_desc[cons];
2424 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
2425 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2426 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
2428 KASSERT(txd->tx_m != NULL,
2429 ("%s: freeing NULL mbufs!", __func__));
2432 if (txstat & (RL_TDESC_STAT_EXCESSCOL|
2433 RL_TDESC_STAT_COLCNT))
2434 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
2435 if (txstat & RL_TDESC_STAT_TXERRSUM)
2436 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2438 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2440 sc->rl_ldata.rl_tx_free++;
2441 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2443 sc->rl_ldata.rl_tx_considx = cons;
2445 /* No changes made to the TX ring, so no flush needed */
2447 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) {
2448 #ifdef RE_TX_MODERATION
2450 * If not all descriptors have been reaped yet, reload
2451 * the timer so that we will eventually get another
2452 * interrupt that will cause us to re-enter this routine.
2453 * This is done in case the transmitter has gone idle.
2455 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2458 sc->rl_watchdog_timer = 0;
2464 struct rl_softc *sc;
2465 struct mii_data *mii;
2471 mii = device_get_softc(sc->rl_miibus);
2473 if ((sc->rl_flags & RL_FLAG_LINK) == 0)
2474 re_miibus_statchg(sc->rl_dev);
2476 * Reclaim transmitted frames here. Technically it is not
2477 * necessary to do here but it ensures periodic reclamation
2478 * regardless of Tx completion interrupt which seems to be
2479 * lost on PCIe based controllers under certain situations.
2483 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
2486 #ifdef DEVICE_POLLING
2488 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2490 struct rl_softc *sc = ifp->if_softc;
2494 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2495 rx_npkts = re_poll_locked(ifp, cmd, count);
2501 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
2503 struct rl_softc *sc = ifp->if_softc;
2508 sc->rxcycles = count;
2509 re_rxeof(sc, &rx_npkts);
2512 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2513 re_start_locked(ifp);
2515 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
2518 status = CSR_READ_2(sc, RL_ISR);
2519 if (status == 0xffff)
2522 CSR_WRITE_2(sc, RL_ISR, status);
2523 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2524 (sc->rl_flags & RL_FLAG_PCIE))
2525 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2528 * XXX check behaviour on receiver stalls.
2531 if (status & RL_ISR_SYSTEM_ERR) {
2532 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2538 #endif /* DEVICE_POLLING */
2543 struct rl_softc *sc;
2548 status = CSR_READ_2(sc, RL_ISR);
2549 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0)
2550 return (FILTER_STRAY);
2551 CSR_WRITE_2(sc, RL_IMR, 0);
2553 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
2555 return (FILTER_HANDLED);
2559 re_int_task(void *arg, int npending)
2561 struct rl_softc *sc;
2571 status = CSR_READ_2(sc, RL_ISR);
2572 CSR_WRITE_2(sc, RL_ISR, status);
2574 if (sc->suspended ||
2575 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2580 #ifdef DEVICE_POLLING
2581 if (ifp->if_capenable & IFCAP_POLLING) {
2587 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW))
2588 rval = re_rxeof(sc, NULL);
2591 * Some chips will ignore a second TX request issued
2592 * while an existing transmission is in progress. If
2593 * the transmitter goes idle but there are still
2594 * packets waiting to be sent, we need to restart the
2595 * channel here to flush them out. This only seems to
2596 * be required with the PCIe devices.
2598 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2599 (sc->rl_flags & RL_FLAG_PCIE))
2600 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2602 #ifdef RE_TX_MODERATION
2603 RL_ISR_TIMEOUT_EXPIRED|
2607 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL))
2610 if (status & RL_ISR_SYSTEM_ERR) {
2611 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2615 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2616 re_start_locked(ifp);
2620 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) {
2621 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
2625 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2629 re_intr_msi(void *xsc)
2631 struct rl_softc *sc;
2633 uint16_t intrs, status;
2639 #ifdef DEVICE_POLLING
2640 if (ifp->if_capenable & IFCAP_POLLING) {
2645 /* Disable interrupts. */
2646 CSR_WRITE_2(sc, RL_IMR, 0);
2647 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2652 intrs = RL_INTRS_CPLUS;
2653 status = CSR_READ_2(sc, RL_ISR);
2654 CSR_WRITE_2(sc, RL_ISR, status);
2655 if (sc->rl_int_rx_act > 0) {
2656 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW |
2658 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW |
2662 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR |
2663 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) {
2665 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2666 if (sc->rl_int_rx_mod != 0 &&
2667 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR |
2668 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) {
2669 /* Rearm one-shot timer. */
2670 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2671 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR |
2672 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN);
2673 sc->rl_int_rx_act = 1;
2675 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR |
2676 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN;
2677 sc->rl_int_rx_act = 0;
2683 * Some chips will ignore a second TX request issued
2684 * while an existing transmission is in progress. If
2685 * the transmitter goes idle but there are still
2686 * packets waiting to be sent, we need to restart the
2687 * channel here to flush them out. This only seems to
2688 * be required with the PCIe devices.
2690 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2691 (sc->rl_flags & RL_FLAG_PCIE))
2692 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2693 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL))
2696 if (status & RL_ISR_SYSTEM_ERR) {
2697 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2701 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2702 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2703 re_start_locked(ifp);
2704 CSR_WRITE_2(sc, RL_IMR, intrs);
2710 re_encap(struct rl_softc *sc, struct mbuf **m_head)
2712 struct rl_txdesc *txd, *txd_last;
2713 bus_dma_segment_t segs[RL_NTXSEGS];
2716 struct rl_desc *desc;
2718 int i, error, ei, si;
2720 uint32_t cmdstat, csum_flags, vlanctl;
2723 M_ASSERTPKTHDR((*m_head));
2726 * With some of the RealTek chips, using the checksum offload
2727 * support in conjunction with the autopadding feature results
2728 * in the transmission of corrupt frames. For example, if we
2729 * need to send a really small IP fragment that's less than 60
2730 * bytes in size, and IP header checksumming is enabled, the
2731 * resulting ethernet frame that appears on the wire will
2732 * have garbled payload. To work around this, if TX IP checksum
2733 * offload is enabled, we always manually pad short frames out
2734 * to the minimum ethernet frame size.
2736 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 &&
2737 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN &&
2738 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) {
2739 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len;
2740 if (M_WRITABLE(*m_head) == 0) {
2741 /* Get a writable copy. */
2742 m_new = m_dup(*m_head, M_NOWAIT);
2744 if (m_new == NULL) {
2750 if ((*m_head)->m_next != NULL ||
2751 M_TRAILINGSPACE(*m_head) < padlen) {
2752 m_new = m_defrag(*m_head, M_NOWAIT);
2753 if (m_new == NULL) {
2762 * Manually pad short frames, and zero the pad space
2763 * to avoid leaking data.
2765 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen);
2766 m_new->m_pkthdr.len += padlen;
2767 m_new->m_len = m_new->m_pkthdr.len;
2771 prod = sc->rl_ldata.rl_tx_prodidx;
2772 txd = &sc->rl_ldata.rl_tx_desc[prod];
2773 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
2774 *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2775 if (error == EFBIG) {
2776 m_new = m_collapse(*m_head, M_NOWAIT, RL_NTXSEGS);
2777 if (m_new == NULL) {
2783 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag,
2784 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2790 } else if (error != 0)
2798 /* Check for number of available descriptors. */
2799 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) {
2800 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap);
2804 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
2805 BUS_DMASYNC_PREWRITE);
2808 * Set up checksum offload. Note: checksum offload bits must
2809 * appear in all descriptors of a multi-descriptor transmit
2810 * attempt. This is according to testing done with an 8169
2811 * chip. This is a requirement.
2815 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2816 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) {
2817 csum_flags |= RL_TDESC_CMD_LGSEND;
2818 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
2819 RL_TDESC_CMD_MSSVALV2_SHIFT);
2821 csum_flags |= RL_TDESC_CMD_LGSEND |
2822 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
2823 RL_TDESC_CMD_MSSVAL_SHIFT);
2827 * Unconditionally enable IP checksum if TCP or UDP
2828 * checksum is required. Otherwise, TCP/UDP checksum
2829 * doesn't make effects.
2831 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) {
2832 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
2833 csum_flags |= RL_TDESC_CMD_IPCSUM;
2834 if (((*m_head)->m_pkthdr.csum_flags &
2836 csum_flags |= RL_TDESC_CMD_TCPCSUM;
2837 if (((*m_head)->m_pkthdr.csum_flags &
2839 csum_flags |= RL_TDESC_CMD_UDPCSUM;
2841 vlanctl |= RL_TDESC_CMD_IPCSUMV2;
2842 if (((*m_head)->m_pkthdr.csum_flags &
2844 vlanctl |= RL_TDESC_CMD_TCPCSUMV2;
2845 if (((*m_head)->m_pkthdr.csum_flags &
2847 vlanctl |= RL_TDESC_CMD_UDPCSUMV2;
2853 * Set up hardware VLAN tagging. Note: vlan tag info must
2854 * appear in all descriptors of a multi-descriptor
2855 * transmission attempt.
2857 if ((*m_head)->m_flags & M_VLANTAG)
2858 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) |
2859 RL_TDESC_VLANCTL_TAG;
2862 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) {
2863 desc = &sc->rl_ldata.rl_tx_list[prod];
2864 desc->rl_vlanctl = htole32(vlanctl);
2865 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
2866 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
2867 cmdstat = segs[i].ds_len;
2869 cmdstat |= RL_TDESC_CMD_OWN;
2870 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1)
2871 cmdstat |= RL_TDESC_CMD_EOR;
2872 desc->rl_cmdstat = htole32(cmdstat | csum_flags);
2873 sc->rl_ldata.rl_tx_free--;
2875 /* Update producer index. */
2876 sc->rl_ldata.rl_tx_prodidx = prod;
2878 /* Set EOF on the last descriptor. */
2879 ei = RL_TX_DESC_PRV(sc, prod);
2880 desc = &sc->rl_ldata.rl_tx_list[ei];
2881 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
2883 desc = &sc->rl_ldata.rl_tx_list[si];
2884 /* Set SOF and transfer ownership of packet to the chip. */
2885 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF);
2888 * Insure that the map for this transmission
2889 * is placed at the array index of the last descriptor
2890 * in this chain. (Swap last and first dmamaps.)
2892 txd_last = &sc->rl_ldata.rl_tx_desc[ei];
2893 map = txd->tx_dmamap;
2894 txd->tx_dmamap = txd_last->tx_dmamap;
2895 txd_last->tx_dmamap = map;
2896 txd_last->tx_m = *m_head;
2902 re_start(struct ifnet *ifp)
2904 struct rl_softc *sc;
2908 re_start_locked(ifp);
2913 * Main transmit routine for C+ and gigE NICs.
2916 re_start_locked(struct ifnet *ifp)
2918 struct rl_softc *sc;
2919 struct mbuf *m_head;
2925 /* XXX is this necessary ? */
2926 if (ifp->if_capenable & IFCAP_NETMAP) {
2927 struct netmap_kring *kring = &NA(ifp)->tx_rings[0];
2928 if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) {
2929 /* kick the tx unit */
2930 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2931 #ifdef RE_TX_MODERATION
2932 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2934 sc->rl_watchdog_timer = 5;
2938 #endif /* DEV_NETMAP */
2939 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2940 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
2943 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2944 sc->rl_ldata.rl_tx_free > 1;) {
2945 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2949 if (re_encap(sc, &m_head) != 0) {
2952 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2953 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2958 * If there's a BPF listener, bounce a copy of this frame
2961 ETHER_BPF_MTAP(ifp, m_head);
2967 #ifdef RE_TX_MODERATION
2968 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt)
2969 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2974 /* Flush the TX descriptors */
2976 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2977 sc->rl_ldata.rl_tx_list_map,
2978 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2980 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2982 #ifdef RE_TX_MODERATION
2984 * Use the countdown timer for interrupt moderation.
2985 * 'TX done' interrupts are disabled. Instead, we reset the
2986 * countdown timer, which will begin counting until it hits
2987 * the value in the TIMERINT register, and then trigger an
2988 * interrupt. Each time we write to the TIMERCNT register,
2989 * the timer count is reset to 0.
2991 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2995 * Set a timeout in case the chip goes out to lunch.
2997 sc->rl_watchdog_timer = 5;
3001 re_set_jumbo(struct rl_softc *sc, int jumbo)
3004 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) {
3005 pci_set_max_read_req(sc->rl_dev, 4096);
3009 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
3011 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) |
3013 switch (sc->rl_hwrev->rl_rev) {
3014 case RL_HWREV_8168DP:
3016 case RL_HWREV_8168E:
3017 CSR_WRITE_1(sc, sc->rl_cfg4,
3018 CSR_READ_1(sc, sc->rl_cfg4) | 0x01);
3021 CSR_WRITE_1(sc, sc->rl_cfg4,
3022 CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1);
3025 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) &
3026 ~RL_CFG3_JUMBO_EN0);
3027 switch (sc->rl_hwrev->rl_rev) {
3028 case RL_HWREV_8168DP:
3030 case RL_HWREV_8168E:
3031 CSR_WRITE_1(sc, sc->rl_cfg4,
3032 CSR_READ_1(sc, sc->rl_cfg4) & ~0x01);
3035 CSR_WRITE_1(sc, sc->rl_cfg4,
3036 CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1);
3039 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3041 switch (sc->rl_hwrev->rl_rev) {
3042 case RL_HWREV_8168DP:
3043 pci_set_max_read_req(sc->rl_dev, 4096);
3047 pci_set_max_read_req(sc->rl_dev, 512);
3049 pci_set_max_read_req(sc->rl_dev, 4096);
3056 struct rl_softc *sc = xsc;
3064 re_init_locked(struct rl_softc *sc)
3066 struct ifnet *ifp = sc->rl_ifp;
3067 struct mii_data *mii;
3071 uint32_t align_dummy;
3072 u_char eaddr[ETHER_ADDR_LEN];
3077 mii = device_get_softc(sc->rl_miibus);
3079 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3083 * Cancel pending I/O and free all RX/TX buffers.
3087 /* Put controller into known state. */
3091 * For C+ mode, initialize the RX descriptors and mbufs.
3093 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
3094 if (ifp->if_mtu > RL_MTU) {
3095 if (re_jrx_list_init(sc) != 0) {
3096 device_printf(sc->rl_dev,
3097 "no memory for jumbo RX buffers\n");
3101 /* Disable checksum offloading for jumbo frames. */
3102 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4);
3103 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO);
3105 if (re_rx_list_init(sc) != 0) {
3106 device_printf(sc->rl_dev,
3107 "no memory for RX buffers\n");
3112 re_set_jumbo(sc, ifp->if_mtu > RL_MTU);
3114 if (re_rx_list_init(sc) != 0) {
3115 device_printf(sc->rl_dev, "no memory for RX buffers\n");
3119 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 &&
3120 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) {
3121 if (ifp->if_mtu > RL_MTU)
3122 pci_set_max_read_req(sc->rl_dev, 512);
3124 pci_set_max_read_req(sc->rl_dev, 4096);
3127 re_tx_list_init(sc);
3130 * Enable C+ RX and TX mode, as well as VLAN stripping and
3131 * RX checksum offload. We must configure the C+ register
3132 * before all others.
3134 cfg = RL_CPLUSCMD_PCI_MRW;
3135 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
3136 cfg |= RL_CPLUSCMD_RXCSUM_ENB;
3137 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3138 cfg |= RL_CPLUSCMD_VLANSTRIP;
3139 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) {
3140 cfg |= RL_CPLUSCMD_MACSTAT_DIS;
3144 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB;
3145 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg);
3146 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC ||
3147 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) {
3149 if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0)
3151 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE)
3153 CSR_WRITE_4(sc, 0x7c, reg);
3154 /* Disable interrupt mitigation. */
3155 CSR_WRITE_2(sc, 0xe2, 0);
3158 * Disable TSO if interface MTU size is greater than MSS
3159 * allowed in controller.
3161 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) {
3162 ifp->if_capenable &= ~IFCAP_TSO4;
3163 ifp->if_hwassist &= ~CSUM_TSO;
3167 * Init our MAC address. Even though the chipset
3168 * documentation doesn't mention it, we need to enter "Config
3169 * register write enable" mode to modify the ID registers.
3171 /* Copy MAC address on stack to align. */
3172 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN);
3173 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
3174 CSR_WRITE_4(sc, RL_IDR0,
3175 htole32(*(u_int32_t *)(&eaddr.eaddr[0])));
3176 CSR_WRITE_4(sc, RL_IDR4,
3177 htole32(*(u_int32_t *)(&eaddr.eaddr[4])));
3178 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3181 * Load the addresses of the RX and TX lists into the chip.
3184 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
3185 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
3186 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
3187 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
3189 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
3190 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
3191 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
3192 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
3194 if ((sc->rl_flags & RL_FLAG_RXDV_GATED) != 0)
3195 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) &
3199 * Set the initial TX configuration.
3201 if (sc->rl_testmode) {
3202 if (sc->rl_type == RL_8169)
3203 CSR_WRITE_4(sc, RL_TXCFG,
3204 RL_TXCFG_CONFIG|RL_LOOPTEST_ON);
3206 CSR_WRITE_4(sc, RL_TXCFG,
3207 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
3209 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
3211 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
3214 * Set the initial RX configuration.
3218 /* Configure interrupt moderation. */
3219 if (sc->rl_type == RL_8169) {
3220 /* Magic from vendor. */
3221 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100);
3225 * Enable transmit and receive.
3227 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB);
3229 #ifdef DEVICE_POLLING
3231 * Disable interrupts if we are polling.
3233 if (ifp->if_capenable & IFCAP_POLLING)
3234 CSR_WRITE_2(sc, RL_IMR, 0);
3235 else /* otherwise ... */
3239 * Enable interrupts.
3241 if (sc->rl_testmode)
3242 CSR_WRITE_2(sc, RL_IMR, 0);
3244 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
3245 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS);
3247 /* Set initial TX threshold */
3248 sc->rl_txthresh = RL_TX_THRESH_INIT;
3250 /* Start RX/TX process. */
3251 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
3254 * Initialize the timer interrupt register so that
3255 * a timer interrupt will be generated once the timer
3256 * reaches a certain number of ticks. The timer is
3257 * reloaded on each transmit.
3259 #ifdef RE_TX_MODERATION
3261 * Use timer interrupt register to moderate TX interrupt
3262 * moderation, which dramatically improves TX frame rate.
3264 if (sc->rl_type == RL_8169)
3265 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
3267 CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
3270 * Use timer interrupt register to moderate RX interrupt
3273 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 &&
3275 if (sc->rl_type == RL_8169)
3276 CSR_WRITE_4(sc, RL_TIMERINT_8169,
3277 RL_USECS(sc->rl_int_rx_mod));
3279 if (sc->rl_type == RL_8169)
3280 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0));
3285 * For 8169 gigE NICs, set the max allowed RX packet
3286 * size so we can receive jumbo frames.
3288 if (sc->rl_type == RL_8169) {
3289 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
3291 * For controllers that use new jumbo frame scheme,
3292 * set maximum size of jumbo frame depending on
3293 * controller revisions.
3295 if (ifp->if_mtu > RL_MTU)
3296 CSR_WRITE_2(sc, RL_MAXRXPKTLEN,
3297 sc->rl_hwrev->rl_max_mtu +
3298 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN +
3301 CSR_WRITE_2(sc, RL_MAXRXPKTLEN,
3303 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 &&
3304 sc->rl_hwrev->rl_max_mtu == RL_MTU) {
3305 /* RTL810x has no jumbo frame support. */
3306 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN);
3308 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
3311 if (sc->rl_testmode)
3314 CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) |
3317 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3318 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3320 sc->rl_flags &= ~RL_FLAG_LINK;
3323 sc->rl_watchdog_timer = 0;
3324 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
3328 * Set media options.
3331 re_ifmedia_upd(struct ifnet *ifp)
3333 struct rl_softc *sc;
3334 struct mii_data *mii;
3338 mii = device_get_softc(sc->rl_miibus);
3340 error = mii_mediachg(mii);
3347 * Report current media status.
3350 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3352 struct rl_softc *sc;
3353 struct mii_data *mii;
3356 mii = device_get_softc(sc->rl_miibus);
3360 ifmr->ifm_active = mii->mii_media_active;
3361 ifmr->ifm_status = mii->mii_media_status;
3366 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3368 struct rl_softc *sc = ifp->if_softc;
3369 struct ifreq *ifr = (struct ifreq *) data;
3370 struct mii_data *mii;
3375 if (ifr->ifr_mtu < ETHERMIN ||
3376 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu ||
3377 ((sc->rl_flags & RL_FLAG_FASTETHER) != 0 &&
3378 ifr->ifr_mtu > RL_MTU)) {
3383 if (ifp->if_mtu != ifr->ifr_mtu) {
3384 ifp->if_mtu = ifr->ifr_mtu;
3385 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
3386 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
3387 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3390 if (ifp->if_mtu > RL_TSO_MTU &&
3391 (ifp->if_capenable & IFCAP_TSO4) != 0) {
3392 ifp->if_capenable &= ~(IFCAP_TSO4 |
3394 ifp->if_hwassist &= ~CSUM_TSO;
3396 VLAN_CAPABILITIES(ifp);
3402 if ((ifp->if_flags & IFF_UP) != 0) {
3403 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
3404 if (((ifp->if_flags ^ sc->rl_if_flags)
3405 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
3410 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3413 sc->rl_if_flags = ifp->if_flags;
3419 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3425 mii = device_get_softc(sc->rl_miibus);
3426 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3432 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3434 #ifdef DEVICE_POLLING
3435 if (mask & IFCAP_POLLING) {
3436 if (ifr->ifr_reqcap & IFCAP_POLLING) {
3437 error = ether_poll_register(re_poll, ifp);
3441 /* Disable interrupts */
3442 CSR_WRITE_2(sc, RL_IMR, 0x0000);
3443 ifp->if_capenable |= IFCAP_POLLING;
3446 error = ether_poll_deregister(ifp);
3447 /* Enable interrupts. */
3449 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
3450 ifp->if_capenable &= ~IFCAP_POLLING;
3454 #endif /* DEVICE_POLLING */
3456 if ((mask & IFCAP_TXCSUM) != 0 &&
3457 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3458 ifp->if_capenable ^= IFCAP_TXCSUM;
3459 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
3460 ifp->if_hwassist |= RE_CSUM_FEATURES;
3462 ifp->if_hwassist &= ~RE_CSUM_FEATURES;
3465 if ((mask & IFCAP_RXCSUM) != 0 &&
3466 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
3467 ifp->if_capenable ^= IFCAP_RXCSUM;
3470 if ((mask & IFCAP_TSO4) != 0 &&
3471 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
3472 ifp->if_capenable ^= IFCAP_TSO4;
3473 if ((IFCAP_TSO4 & ifp->if_capenable) != 0)
3474 ifp->if_hwassist |= CSUM_TSO;
3476 ifp->if_hwassist &= ~CSUM_TSO;
3477 if (ifp->if_mtu > RL_TSO_MTU &&
3478 (ifp->if_capenable & IFCAP_TSO4) != 0) {
3479 ifp->if_capenable &= ~IFCAP_TSO4;
3480 ifp->if_hwassist &= ~CSUM_TSO;
3483 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
3484 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
3485 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
3486 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
3487 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
3488 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3489 /* TSO over VLAN requires VLAN hardware tagging. */
3490 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
3491 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
3494 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
3495 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 |
3496 IFCAP_VLAN_HWTSO)) != 0)
3498 if ((mask & IFCAP_WOL) != 0 &&
3499 (ifp->if_capabilities & IFCAP_WOL) != 0) {
3500 if ((mask & IFCAP_WOL_UCAST) != 0)
3501 ifp->if_capenable ^= IFCAP_WOL_UCAST;
3502 if ((mask & IFCAP_WOL_MCAST) != 0)
3503 ifp->if_capenable ^= IFCAP_WOL_MCAST;
3504 if ((mask & IFCAP_WOL_MAGIC) != 0)
3505 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3507 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) {
3508 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3512 VLAN_CAPABILITIES(ifp);
3516 error = ether_ioctl(ifp, command, data);
3524 re_watchdog(struct rl_softc *sc)
3530 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0)
3535 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) {
3536 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
3538 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3539 re_start_locked(ifp);
3543 if_printf(ifp, "watchdog timeout\n");
3544 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3547 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3549 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3550 re_start_locked(ifp);
3554 * Stop the adapter and free any mbufs allocated to the
3558 re_stop(struct rl_softc *sc)
3562 struct rl_txdesc *txd;
3563 struct rl_rxdesc *rxd;
3569 sc->rl_watchdog_timer = 0;
3570 callout_stop(&sc->rl_stat_callout);
3571 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3574 * Disable accepting frames to put RX MAC into idle state.
3575 * Otherwise it's possible to get frames while stop command
3576 * execution is in progress and controller can DMA the frame
3577 * to already freed RX buffer during that period.
3579 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) &
3580 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI |
3581 RL_RXCFG_RX_BROAD));
3583 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) {
3584 for (i = RL_TIMEOUT; i > 0; i--) {
3585 if ((CSR_READ_1(sc, sc->rl_txstart) &
3586 RL_TXSTART_START) == 0)
3591 device_printf(sc->rl_dev,
3592 "stopping TX poll timed out!\n");
3593 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
3594 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) {
3595 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB |
3597 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) {
3598 for (i = RL_TIMEOUT; i > 0; i--) {
3599 if ((CSR_READ_4(sc, RL_TXCFG) &
3600 RL_TXCFG_QUEUE_EMPTY) != 0)
3605 device_printf(sc->rl_dev,
3606 "stopping TXQ timed out!\n");
3609 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
3611 CSR_WRITE_2(sc, RL_IMR, 0x0000);
3612 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
3614 if (sc->rl_head != NULL) {
3615 m_freem(sc->rl_head);
3616 sc->rl_head = sc->rl_tail = NULL;
3619 /* Free the TX list buffers. */
3620 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
3621 txd = &sc->rl_ldata.rl_tx_desc[i];
3622 if (txd->tx_m != NULL) {
3623 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
3624 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3625 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
3632 /* Free the RX list buffers. */
3633 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
3634 rxd = &sc->rl_ldata.rl_rx_desc[i];
3635 if (rxd->rx_m != NULL) {
3636 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
3637 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3638 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
3645 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
3646 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
3647 rxd = &sc->rl_ldata.rl_jrx_desc[i];
3648 if (rxd->rx_m != NULL) {
3649 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag,
3650 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3651 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag,
3661 * Device suspend routine. Stop the interface and save some PCI
3662 * settings in case the BIOS doesn't restore them properly on
3666 re_suspend(device_t dev)
3668 struct rl_softc *sc;
3670 sc = device_get_softc(dev);
3682 * Device resume routine. Restore some PCI settings in case the BIOS
3683 * doesn't, re-enable busmastering, and restart the interface if
3687 re_resume(device_t dev)
3689 struct rl_softc *sc;
3692 sc = device_get_softc(dev);
3697 /* Take controller out of sleep mode. */
3698 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
3699 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
3700 CSR_WRITE_1(sc, RL_GPIO,
3701 CSR_READ_1(sc, RL_GPIO) | 0x01);
3705 * Clear WOL matching such that normal Rx filtering
3706 * wouldn't interfere with WOL patterns.
3710 /* reinitialize interface if necessary */
3711 if (ifp->if_flags & IFF_UP)
3721 * Stop all chip I/O so that the kernel's probe routines don't
3722 * get confused by errant DMAs when rebooting.
3725 re_shutdown(device_t dev)
3727 struct rl_softc *sc;
3729 sc = device_get_softc(dev);
3734 * Mark interface as down since otherwise we will panic if
3735 * interrupt comes in later on, which can happen in some
3738 sc->rl_ifp->if_flags &= ~IFF_UP;
3746 re_set_linkspeed(struct rl_softc *sc)
3748 struct mii_softc *miisc;
3749 struct mii_data *mii;
3754 mii = device_get_softc(sc->rl_miibus);
3757 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
3758 (IFM_ACTIVE | IFM_AVALID)) {
3759 switch IFM_SUBTYPE(mii->mii_media_active) {
3770 miisc = LIST_FIRST(&mii->mii_phys);
3771 phyno = miisc->mii_phy;
3772 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3774 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0);
3775 re_miibus_writereg(sc->rl_dev, phyno,
3776 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
3777 re_miibus_writereg(sc->rl_dev, phyno,
3778 MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
3782 * Poll link state until re(4) get a 10/100Mbps link.
3784 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
3786 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
3787 == (IFM_ACTIVE | IFM_AVALID)) {
3788 switch (IFM_SUBTYPE(mii->mii_media_active)) {
3800 if (i == MII_ANEGTICKS_GIGE)
3801 device_printf(sc->rl_dev,
3802 "establishing a link failed, WOL may not work!");
3805 * No link, force MAC to have 100Mbps, full-duplex link.
3806 * MAC does not require reprogramming on resolved speed/duplex,
3807 * so this is just for completeness.
3809 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
3810 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
3814 re_setwol(struct rl_softc *sc)
3823 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
3827 /* Put controller into sleep mode. */
3828 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
3829 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
3830 CSR_WRITE_1(sc, RL_GPIO,
3831 CSR_READ_1(sc, RL_GPIO) & ~0x01);
3833 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
3835 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0)
3836 re_set_linkspeed(sc);
3837 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0)
3838 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB);
3840 /* Enable config register write. */
3841 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
3844 v = CSR_READ_1(sc, sc->rl_cfg1);
3846 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3848 CSR_WRITE_1(sc, sc->rl_cfg1, v);
3850 v = CSR_READ_1(sc, sc->rl_cfg3);
3851 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3852 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3853 v |= RL_CFG3_WOL_MAGIC;
3854 CSR_WRITE_1(sc, sc->rl_cfg3, v);
3856 v = CSR_READ_1(sc, sc->rl_cfg5);
3857 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST |
3858 RL_CFG5_WOL_LANWAKE);
3859 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
3860 v |= RL_CFG5_WOL_UCAST;
3861 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
3862 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
3863 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3864 v |= RL_CFG5_WOL_LANWAKE;
3865 CSR_WRITE_1(sc, sc->rl_cfg5, v);
3867 /* Config register write done. */
3868 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3870 if ((ifp->if_capenable & IFCAP_WOL) == 0 &&
3871 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0)
3872 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80);
3874 * It seems that hardware resets its link speed to 100Mbps in
3875 * power down mode so switching to 100Mbps in driver is not
3879 /* Request PME if WOL is requested. */
3880 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
3881 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3882 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3883 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3884 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
3888 re_clrwol(struct rl_softc *sc)
3895 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
3898 /* Enable config register write. */
3899 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
3901 v = CSR_READ_1(sc, sc->rl_cfg3);
3902 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3903 CSR_WRITE_1(sc, sc->rl_cfg3, v);
3905 /* Config register write done. */
3906 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3908 v = CSR_READ_1(sc, sc->rl_cfg5);
3909 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
3910 v &= ~RL_CFG5_WOL_LANWAKE;
3911 CSR_WRITE_1(sc, sc->rl_cfg5, v);
3915 re_add_sysctls(struct rl_softc *sc)
3917 struct sysctl_ctx_list *ctx;
3918 struct sysctl_oid_list *children;
3921 ctx = device_get_sysctl_ctx(sc->rl_dev);
3922 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
3924 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats",
3925 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I",
3926 "Statistics Information");
3927 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0)
3930 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod",
3931 CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0,
3932 sysctl_hw_re_int_mod, "I", "re RX interrupt moderation");
3933 /* Pull in device tunables. */
3934 sc->rl_int_rx_mod = RL_TIMER_DEFAULT;
3935 error = resource_int_value(device_get_name(sc->rl_dev),
3936 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod);
3938 if (sc->rl_int_rx_mod < RL_TIMER_MIN ||
3939 sc->rl_int_rx_mod > RL_TIMER_MAX) {
3940 device_printf(sc->rl_dev, "int_rx_mod value out of "
3941 "range; using default: %d\n",
3943 sc->rl_int_rx_mod = RL_TIMER_DEFAULT;
3950 re_sysctl_stats(SYSCTL_HANDLER_ARGS)
3952 struct rl_softc *sc;
3953 struct rl_stats *stats;
3954 int error, i, result;
3957 error = sysctl_handle_int(oidp, &result, 0, req);
3958 if (error || req->newptr == NULL)
3962 sc = (struct rl_softc *)arg1;
3964 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3968 bus_dmamap_sync(sc->rl_ldata.rl_stag,
3969 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD);
3970 CSR_WRITE_4(sc, RL_DUMPSTATS_HI,
3971 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr));
3972 CSR_WRITE_4(sc, RL_DUMPSTATS_LO,
3973 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr));
3974 CSR_WRITE_4(sc, RL_DUMPSTATS_LO,
3975 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr |
3976 RL_DUMPSTATS_START));
3977 for (i = RL_TIMEOUT; i > 0; i--) {
3978 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) &
3979 RL_DUMPSTATS_START) == 0)
3983 bus_dmamap_sync(sc->rl_ldata.rl_stag,
3984 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD);
3987 device_printf(sc->rl_dev,
3988 "DUMP statistics request timed out\n");
3992 stats = sc->rl_ldata.rl_stats;
3993 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev));
3994 printf("Tx frames : %ju\n",
3995 (uintmax_t)le64toh(stats->rl_tx_pkts));
3996 printf("Rx frames : %ju\n",
3997 (uintmax_t)le64toh(stats->rl_rx_pkts));
3998 printf("Tx errors : %ju\n",
3999 (uintmax_t)le64toh(stats->rl_tx_errs));
4000 printf("Rx errors : %u\n",
4001 le32toh(stats->rl_rx_errs));
4002 printf("Rx missed frames : %u\n",
4003 (uint32_t)le16toh(stats->rl_missed_pkts));
4004 printf("Rx frame alignment errs : %u\n",
4005 (uint32_t)le16toh(stats->rl_rx_framealign_errs));
4006 printf("Tx single collisions : %u\n",
4007 le32toh(stats->rl_tx_onecoll));
4008 printf("Tx multiple collisions : %u\n",
4009 le32toh(stats->rl_tx_multicolls));
4010 printf("Rx unicast frames : %ju\n",
4011 (uintmax_t)le64toh(stats->rl_rx_ucasts));
4012 printf("Rx broadcast frames : %ju\n",
4013 (uintmax_t)le64toh(stats->rl_rx_bcasts));
4014 printf("Rx multicast frames : %u\n",
4015 le32toh(stats->rl_rx_mcasts));
4016 printf("Tx aborts : %u\n",
4017 (uint32_t)le16toh(stats->rl_tx_aborts));
4018 printf("Tx underruns : %u\n",
4019 (uint32_t)le16toh(stats->rl_rx_underruns));
4026 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
4032 value = *(int *)arg1;
4033 error = sysctl_handle_int(oidp, &value, 0, req);
4034 if (error || req->newptr == NULL)
4036 if (value < low || value > high)
4038 *(int *)arg1 = value;
4044 sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS)
4047 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN,