2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1997, 1998-2003
5 * Bill Paul <wpaul@windriver.com>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
39 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
41 * Written by Bill Paul <wpaul@windriver.com>
42 * Senior Networking Software Engineer
47 * This driver is designed to support RealTek's next generation of
48 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
49 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
50 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
52 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
53 * with the older 8139 family, however it also supports a special
54 * C+ mode of operation that provides several new performance enhancing
55 * features. These include:
57 * o Descriptor based DMA mechanism. Each descriptor represents
58 * a single packet fragment. Data buffers may be aligned on
63 * o TCP/IP checksum offload for both RX and TX
65 * o High and normal priority transmit DMA rings
67 * o VLAN tag insertion and extraction
69 * o TCP large send (segmentation offload)
71 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
72 * programming API is fairly straightforward. The RX filtering, EEPROM
73 * access and PHY access is the same as it is on the older 8139 series
76 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
77 * same programming API and feature set as the 8139C+ with the following
78 * differences and additions:
84 * o GMII and TBI ports/registers for interfacing with copper
87 * o RX and TX DMA rings can have up to 1024 descriptors
88 * (the 8139C+ allows a maximum of 64)
90 * o Slight differences in register layout from the 8139C+
92 * The TX start and timer interrupt registers are at different locations
93 * on the 8169 than they are on the 8139C+. Also, the status word in the
94 * RX descriptor has a slightly different bit layout. The 8169 does not
95 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
98 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
99 * (the 'S' stands for 'single-chip'). These devices have the same
100 * programming API as the older 8169, but also have some vendor-specific
101 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
102 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
104 * This driver takes advantage of the RX and TX checksum offload and
105 * VLAN tag insertion/extraction features. It also implements TX
106 * interrupt moderation using the timer interrupt registers, which
107 * significantly reduces TX interrupt load. There is also support
108 * for jumbo frames, however the 8169/8169S/8110S can not transmit
109 * jumbo frames larger than 7440, so the max MTU possible with this
110 * driver is 7422 bytes.
113 #ifdef HAVE_KERNEL_OPTION_HEADERS
114 #include "opt_device_polling.h"
117 #include <sys/param.h>
118 #include <sys/endian.h>
119 #include <sys/systm.h>
120 #include <sys/sockio.h>
121 #include <sys/mbuf.h>
122 #include <sys/malloc.h>
123 #include <sys/module.h>
124 #include <sys/kernel.h>
125 #include <sys/socket.h>
126 #include <sys/lock.h>
127 #include <sys/mutex.h>
128 #include <sys/sysctl.h>
129 #include <sys/taskqueue.h>
132 #include <net/if_var.h>
133 #include <net/if_arp.h>
134 #include <net/ethernet.h>
135 #include <net/if_dl.h>
136 #include <net/if_media.h>
137 #include <net/if_types.h>
138 #include <net/if_vlan_var.h>
142 #include <netinet/netdump/netdump.h>
144 #include <machine/bus.h>
145 #include <machine/resource.h>
147 #include <sys/rman.h>
149 #include <dev/mii/mii.h>
150 #include <dev/mii/miivar.h>
152 #include <dev/pci/pcireg.h>
153 #include <dev/pci/pcivar.h>
155 #include <dev/rl/if_rlreg.h>
157 MODULE_DEPEND(re, pci, 1, 1, 1);
158 MODULE_DEPEND(re, ether, 1, 1, 1);
159 MODULE_DEPEND(re, miibus, 1, 1, 1);
161 /* "device miibus" required. See GENERIC if you get errors here. */
162 #include "miibus_if.h"
165 static int intr_filter = 0;
166 TUNABLE_INT("hw.re.intr_filter", &intr_filter);
167 static int msi_disable = 0;
168 TUNABLE_INT("hw.re.msi_disable", &msi_disable);
169 static int msix_disable = 0;
170 TUNABLE_INT("hw.re.msix_disable", &msix_disable);
171 static int prefer_iomap = 0;
172 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap);
174 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
177 * Various supported device vendors/types and their names.
179 static const struct rl_type re_devs[] = {
180 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0,
181 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
182 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0,
183 "D-Link DGE-530(T) Gigabit Ethernet Adapter" },
184 { RT_VENDORID, RT_DEVICEID_8139, 0,
185 "RealTek 8139C+ 10/100BaseTX" },
186 { RT_VENDORID, RT_DEVICEID_8101E, 0,
187 "RealTek 810xE PCIe 10/100baseTX" },
188 { RT_VENDORID, RT_DEVICEID_8168, 0,
189 "RealTek 8168/8111 B/C/CP/D/DP/E/F/G PCIe Gigabit Ethernet" },
190 { NCUBE_VENDORID, RT_DEVICEID_8168, 0,
191 "TP-Link TG-3468 v2 (RTL8168) Gigabit Ethernet" },
192 { RT_VENDORID, RT_DEVICEID_8169, 0,
193 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" },
194 { RT_VENDORID, RT_DEVICEID_8169SC, 0,
195 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
196 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0,
197 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
198 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0,
199 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" },
200 { USR_VENDORID, USR_DEVICEID_997902, 0,
201 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" }
204 static const struct rl_hwrev re_hwrevs[] = {
205 { RL_HWREV_8139, RL_8139, "", RL_MTU },
206 { RL_HWREV_8139A, RL_8139, "A", RL_MTU },
207 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU },
208 { RL_HWREV_8139B, RL_8139, "B", RL_MTU },
209 { RL_HWREV_8130, RL_8139, "8130", RL_MTU },
210 { RL_HWREV_8139C, RL_8139, "C", RL_MTU },
211 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU },
212 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU },
213 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU },
214 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU },
215 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU },
216 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU },
217 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU },
218 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU },
219 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU },
220 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU },
221 { RL_HWREV_8100, RL_8139, "8100", RL_MTU },
222 { RL_HWREV_8101, RL_8139, "8101", RL_MTU },
223 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU },
224 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU },
225 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU },
226 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU },
227 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU },
228 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU },
229 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU },
230 { RL_HWREV_8402, RL_8169, "8402", RL_MTU },
231 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU },
232 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU },
233 { RL_HWREV_8106E, RL_8169, "8106E", RL_MTU },
234 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU },
235 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU },
236 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K },
237 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K },
238 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K },
239 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K },
240 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K },
241 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K},
242 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K},
243 { RL_HWREV_8168EP, RL_8169, "8168EP/8111EP", RL_JUMBO_MTU_9K},
244 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K},
245 { RL_HWREV_8168G, RL_8169, "8168G/8111G", RL_JUMBO_MTU_9K},
246 { RL_HWREV_8168GU, RL_8169, "8168GU/8111GU", RL_JUMBO_MTU_9K},
247 { RL_HWREV_8168H, RL_8169, "8168H/8111H", RL_JUMBO_MTU_9K},
248 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K},
249 { RL_HWREV_8411B, RL_8169, "8411B", RL_JUMBO_MTU_9K},
253 static int re_probe (device_t);
254 static int re_attach (device_t);
255 static int re_detach (device_t);
257 static int re_encap (struct rl_softc *, struct mbuf **);
259 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int);
260 static int re_allocmem (device_t, struct rl_softc *);
261 static __inline void re_discard_rxbuf
262 (struct rl_softc *, int);
263 static int re_newbuf (struct rl_softc *, int);
264 static int re_jumbo_newbuf (struct rl_softc *, int);
265 static int re_rx_list_init (struct rl_softc *);
266 static int re_jrx_list_init (struct rl_softc *);
267 static int re_tx_list_init (struct rl_softc *);
269 static __inline void re_fixup_rx
272 static int re_rxeof (struct rl_softc *, int *);
273 static void re_txeof (struct rl_softc *);
274 #ifdef DEVICE_POLLING
275 static int re_poll (struct ifnet *, enum poll_cmd, int);
276 static int re_poll_locked (struct ifnet *, enum poll_cmd, int);
278 static int re_intr (void *);
279 static void re_intr_msi (void *);
280 static void re_tick (void *);
281 static void re_int_task (void *, int);
282 static void re_start (struct ifnet *);
283 static void re_start_locked (struct ifnet *);
284 static void re_start_tx (struct rl_softc *);
285 static int re_ioctl (struct ifnet *, u_long, caddr_t);
286 static void re_init (void *);
287 static void re_init_locked (struct rl_softc *);
288 static void re_stop (struct rl_softc *);
289 static void re_watchdog (struct rl_softc *);
290 static int re_suspend (device_t);
291 static int re_resume (device_t);
292 static int re_shutdown (device_t);
293 static int re_ifmedia_upd (struct ifnet *);
294 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *);
296 static void re_eeprom_putbyte (struct rl_softc *, int);
297 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *);
298 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int);
299 static int re_gmii_readreg (device_t, int, int);
300 static int re_gmii_writereg (device_t, int, int, int);
302 static int re_miibus_readreg (device_t, int, int);
303 static int re_miibus_writereg (device_t, int, int, int);
304 static void re_miibus_statchg (device_t);
306 static void re_set_jumbo (struct rl_softc *, int);
307 static void re_set_rxmode (struct rl_softc *);
308 static void re_reset (struct rl_softc *);
309 static void re_setwol (struct rl_softc *);
310 static void re_clrwol (struct rl_softc *);
311 static void re_set_linkspeed (struct rl_softc *);
315 #ifdef DEV_NETMAP /* see ixgbe.c for details */
316 #include <dev/netmap/if_re_netmap.h>
317 MODULE_DEPEND(re, netmap, 1, 1, 1);
318 #endif /* !DEV_NETMAP */
321 static int re_diag (struct rl_softc *);
324 static void re_add_sysctls (struct rl_softc *);
325 static int re_sysctl_stats (SYSCTL_HANDLER_ARGS);
326 static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int);
327 static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS);
329 static device_method_t re_methods[] = {
330 /* Device interface */
331 DEVMETHOD(device_probe, re_probe),
332 DEVMETHOD(device_attach, re_attach),
333 DEVMETHOD(device_detach, re_detach),
334 DEVMETHOD(device_suspend, re_suspend),
335 DEVMETHOD(device_resume, re_resume),
336 DEVMETHOD(device_shutdown, re_shutdown),
339 DEVMETHOD(miibus_readreg, re_miibus_readreg),
340 DEVMETHOD(miibus_writereg, re_miibus_writereg),
341 DEVMETHOD(miibus_statchg, re_miibus_statchg),
346 static driver_t re_driver = {
349 sizeof(struct rl_softc)
352 static devclass_t re_devclass;
354 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0);
355 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
358 CSR_WRITE_1(sc, RL_EECMD, \
359 CSR_READ_1(sc, RL_EECMD) | x)
362 CSR_WRITE_1(sc, RL_EECMD, \
363 CSR_READ_1(sc, RL_EECMD) & ~x)
366 * Send a read command and address to the EEPROM, check for ACK.
369 re_eeprom_putbyte(struct rl_softc *sc, int addr)
373 d = addr | (RL_9346_READ << sc->rl_eewidth);
376 * Feed in each bit and strobe the clock.
379 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) {
381 EE_SET(RL_EE_DATAIN);
383 EE_CLR(RL_EE_DATAIN);
394 * Read a word of data stored in the EEPROM at address 'addr.'
397 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest)
403 * Send address of word we want to read.
405 re_eeprom_putbyte(sc, addr);
408 * Start reading bits from EEPROM.
410 for (i = 0x8000; i; i >>= 1) {
413 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
423 * Read a sequence of words from the EEPROM.
426 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt)
429 u_int16_t word = 0, *ptr;
431 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
435 for (i = 0; i < cnt; i++) {
436 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL);
437 re_eeprom_getword(sc, off + i, &word);
438 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL);
439 ptr = (u_int16_t *)(dest + (i * 2));
443 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
447 re_gmii_readreg(device_t dev, int phy, int reg)
453 sc = device_get_softc(dev);
455 /* Let the rgephy driver read the GMEDIASTAT register */
457 if (reg == RL_GMEDIASTAT) {
458 rval = CSR_READ_1(sc, RL_GMEDIASTAT);
462 CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
464 for (i = 0; i < RL_PHY_TIMEOUT; i++) {
465 rval = CSR_READ_4(sc, RL_PHYAR);
466 if (rval & RL_PHYAR_BUSY)
471 if (i == RL_PHY_TIMEOUT) {
472 device_printf(sc->rl_dev, "PHY read failed\n");
477 * Controller requires a 20us delay to process next MDIO request.
481 return (rval & RL_PHYAR_PHYDATA);
485 re_gmii_writereg(device_t dev, int phy, int reg, int data)
491 sc = device_get_softc(dev);
493 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
494 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
496 for (i = 0; i < RL_PHY_TIMEOUT; i++) {
497 rval = CSR_READ_4(sc, RL_PHYAR);
498 if (!(rval & RL_PHYAR_BUSY))
503 if (i == RL_PHY_TIMEOUT) {
504 device_printf(sc->rl_dev, "PHY write failed\n");
509 * Controller requires a 20us delay to process next MDIO request.
517 re_miibus_readreg(device_t dev, int phy, int reg)
521 u_int16_t re8139_reg = 0;
523 sc = device_get_softc(dev);
525 if (sc->rl_type == RL_8169) {
526 rval = re_gmii_readreg(dev, phy, reg);
532 re8139_reg = RL_BMCR;
535 re8139_reg = RL_BMSR;
538 re8139_reg = RL_ANAR;
541 re8139_reg = RL_ANER;
544 re8139_reg = RL_LPAR;
550 * Allow the rlphy driver to read the media status
551 * register. If we have a link partner which does not
552 * support NWAY, this is the register which will tell
553 * us the results of parallel detection.
556 rval = CSR_READ_1(sc, RL_MEDIASTAT);
559 device_printf(sc->rl_dev, "bad phy register\n");
562 rval = CSR_READ_2(sc, re8139_reg);
563 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) {
564 /* 8139C+ has different bit layout. */
565 rval &= ~(BMCR_LOOP | BMCR_ISO);
571 re_miibus_writereg(device_t dev, int phy, int reg, int data)
574 u_int16_t re8139_reg = 0;
577 sc = device_get_softc(dev);
579 if (sc->rl_type == RL_8169) {
580 rval = re_gmii_writereg(dev, phy, reg, data);
586 re8139_reg = RL_BMCR;
587 if (sc->rl_type == RL_8139CPLUS) {
588 /* 8139C+ has different bit layout. */
589 data &= ~(BMCR_LOOP | BMCR_ISO);
593 re8139_reg = RL_BMSR;
596 re8139_reg = RL_ANAR;
599 re8139_reg = RL_ANER;
602 re8139_reg = RL_LPAR;
609 device_printf(sc->rl_dev, "bad phy register\n");
612 CSR_WRITE_2(sc, re8139_reg, data);
617 re_miibus_statchg(device_t dev)
621 struct mii_data *mii;
623 sc = device_get_softc(dev);
624 mii = device_get_softc(sc->rl_miibus);
626 if (mii == NULL || ifp == NULL ||
627 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
630 sc->rl_flags &= ~RL_FLAG_LINK;
631 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
632 (IFM_ACTIVE | IFM_AVALID)) {
633 switch (IFM_SUBTYPE(mii->mii_media_active)) {
636 sc->rl_flags |= RL_FLAG_LINK;
639 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0)
641 sc->rl_flags |= RL_FLAG_LINK;
648 * RealTek controllers do not provide any interface to the RX/TX
649 * MACs for resolved speed, duplex and flow-control parameters.
654 * Set the RX configuration and 64-bit multicast hash filter.
657 re_set_rxmode(struct rl_softc *sc)
660 struct ifmultiaddr *ifma;
661 uint32_t hashes[2] = { 0, 0 };
668 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD;
669 if ((sc->rl_flags & RL_FLAG_EARLYOFF) != 0)
670 rxfilt |= RL_RXCFG_EARLYOFF;
671 else if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0)
672 rxfilt |= RL_RXCFG_EARLYOFFV2;
674 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
675 if (ifp->if_flags & IFF_PROMISC)
676 rxfilt |= RL_RXCFG_RX_ALLPHYS;
678 * Unlike other hardwares, we have to explicitly set
679 * RL_RXCFG_RX_MULTI to receive multicast frames in
682 rxfilt |= RL_RXCFG_RX_MULTI;
683 hashes[0] = hashes[1] = 0xffffffff;
688 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
689 if (ifma->ifma_addr->sa_family != AF_LINK)
691 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
692 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
694 hashes[0] |= (1 << h);
696 hashes[1] |= (1 << (h - 32));
698 if_maddr_runlock(ifp);
700 if (hashes[0] != 0 || hashes[1] != 0) {
702 * For some unfathomable reason, RealTek decided to
703 * reverse the order of the multicast hash registers
704 * in the PCI Express parts. This means we have to
705 * write the hash pattern in reverse order for those
708 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) {
709 h = bswap32(hashes[0]);
710 hashes[0] = bswap32(hashes[1]);
713 rxfilt |= RL_RXCFG_RX_MULTI;
716 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168F) {
717 /* Disable multicast filtering due to silicon bug. */
718 hashes[0] = 0xffffffff;
719 hashes[1] = 0xffffffff;
723 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
724 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
725 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
729 re_reset(struct rl_softc *sc)
735 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
737 for (i = 0; i < RL_TIMEOUT; i++) {
739 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
743 device_printf(sc->rl_dev, "reset never completed!\n");
745 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0)
746 CSR_WRITE_1(sc, 0x82, 1);
747 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S)
748 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0);
754 * The following routine is designed to test for a defect on some
755 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
756 * lines connected to the bus, however for a 32-bit only card, they
757 * should be pulled high. The result of this defect is that the
758 * NIC will not work right if you plug it into a 64-bit slot: DMA
759 * operations will be done with 64-bit transfers, which will fail
760 * because the 64-bit data lines aren't connected.
762 * There's no way to work around this (short of talking a soldering
763 * iron to the board), however we can detect it. The method we use
764 * here is to put the NIC into digital loopback mode, set the receiver
765 * to promiscuous mode, and then try to send a frame. We then compare
766 * the frame data we sent to what was received. If the data matches,
767 * then the NIC is working correctly, otherwise we know the user has
768 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
769 * slot. In the latter case, there's no way the NIC can work correctly,
770 * so we print out a message on the console and abort the device attach.
774 re_diag(struct rl_softc *sc)
776 struct ifnet *ifp = sc->rl_ifp;
778 struct ether_header *eh;
779 struct rl_desc *cur_rx;
782 int total_len, i, error = 0, phyaddr;
783 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
784 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
786 /* Allocate a single mbuf */
787 MGETHDR(m0, M_NOWAIT, MT_DATA);
794 * Initialize the NIC in test mode. This sets the chip up
795 * so that it can send and receive frames, but performs the
796 * following special functions:
797 * - Puts receiver in promiscuous mode
798 * - Enables digital loopback mode
799 * - Leaves interrupts turned off
802 ifp->if_flags |= IFF_PROMISC;
804 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
806 sc->rl_flags |= RL_FLAG_LINK;
807 if (sc->rl_type == RL_8169)
812 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET);
813 for (i = 0; i < RL_TIMEOUT; i++) {
814 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR);
815 if (!(status & BMCR_RESET))
819 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP);
820 CSR_WRITE_2(sc, RL_ISR, RL_INTRS);
824 /* Put some data in the mbuf */
826 eh = mtod(m0, struct ether_header *);
827 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
828 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
829 eh->ether_type = htons(ETHERTYPE_IP);
830 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
833 * Queue the packet, start transmission.
834 * Note: IF_HANDOFF() ultimately calls re_start() for us.
837 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
839 /* XXX: re_diag must not be called when in ALTQ mode */
840 IF_HANDOFF(&ifp->if_snd, m0, ifp);
844 /* Wait for it to propagate through the chip */
847 for (i = 0; i < RL_TIMEOUT; i++) {
848 status = CSR_READ_2(sc, RL_ISR);
849 CSR_WRITE_2(sc, RL_ISR, status);
850 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
851 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
856 if (i == RL_TIMEOUT) {
857 device_printf(sc->rl_dev,
858 "diagnostic failed, failed to receive packet in"
865 * The packet should have been dumped into the first
866 * entry in the RX DMA ring. Grab it from there.
869 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
870 sc->rl_ldata.rl_rx_list_map,
871 BUS_DMASYNC_POSTREAD);
872 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
873 sc->rl_ldata.rl_rx_desc[0].rx_dmamap,
874 BUS_DMASYNC_POSTREAD);
875 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
876 sc->rl_ldata.rl_rx_desc[0].rx_dmamap);
878 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m;
879 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL;
880 eh = mtod(m0, struct ether_header *);
882 cur_rx = &sc->rl_ldata.rl_rx_list[0];
883 total_len = RL_RXBYTES(cur_rx);
884 rxstat = le32toh(cur_rx->rl_cmdstat);
886 if (total_len != ETHER_MIN_LEN) {
887 device_printf(sc->rl_dev,
888 "diagnostic failed, received short packet\n");
893 /* Test that the received packet data matches what we sent. */
895 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
896 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
897 ntohs(eh->ether_type) != ETHERTYPE_IP) {
898 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n");
899 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n",
900 dst, ":", src, ":", ETHERTYPE_IP);
901 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n",
902 eh->ether_dhost, ":", eh->ether_shost, ":",
903 ntohs(eh->ether_type));
904 device_printf(sc->rl_dev, "You may have a defective 32-bit "
905 "NIC plugged into a 64-bit PCI slot.\n");
906 device_printf(sc->rl_dev, "Please re-install the NIC in a "
907 "32-bit slot for proper operation.\n");
908 device_printf(sc->rl_dev, "Read the re(4) man page for more "
914 /* Turn interface off, release resources */
917 sc->rl_flags &= ~RL_FLAG_LINK;
918 ifp->if_flags &= ~IFF_PROMISC;
931 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
932 * IDs against our list and return a device name if we find a match.
935 re_probe(device_t dev)
937 const struct rl_type *t;
938 uint16_t devid, vendor;
939 uint16_t revid, sdevid;
942 vendor = pci_get_vendor(dev);
943 devid = pci_get_device(dev);
944 revid = pci_get_revid(dev);
945 sdevid = pci_get_subdevice(dev);
947 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) {
948 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) {
950 * Only attach to rev. 3 of the Linksys EG1032 adapter.
951 * Rev. 2 is supported by sk(4).
957 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
959 /* 8139, let rl(4) take care of this device. */
965 for (i = 0; i < nitems(re_devs); i++, t++) {
966 if (vendor == t->rl_vid && devid == t->rl_did) {
967 device_set_desc(dev, t->rl_name);
968 return (BUS_PROBE_DEFAULT);
976 * Map a single buffer address.
980 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
987 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
989 *addr = segs->ds_addr;
993 re_allocmem(device_t dev, struct rl_softc *sc)
996 bus_size_t rx_list_size, tx_list_size;
1000 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc);
1001 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc);
1004 * Allocate the parent bus DMA tag appropriate for PCI.
1005 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD
1006 * register should be set. However some RealTek chips are known
1007 * to be buggy on DAC handling, therefore disable DAC by limiting
1008 * DMA address space to 32bit. PCIe variants of RealTek chips
1009 * may not have the limitation.
1011 lowaddr = BUS_SPACE_MAXADDR;
1012 if ((sc->rl_flags & RL_FLAG_PCIE) == 0)
1013 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1014 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
1015 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL,
1016 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1017 NULL, NULL, &sc->rl_parent_tag);
1019 device_printf(dev, "could not allocate parent DMA tag\n");
1024 * Allocate map for TX mbufs.
1026 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0,
1027 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
1028 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0,
1029 NULL, NULL, &sc->rl_ldata.rl_tx_mtag);
1031 device_printf(dev, "could not allocate TX DMA tag\n");
1036 * Allocate map for RX mbufs.
1039 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
1040 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t),
1041 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1042 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL,
1043 &sc->rl_ldata.rl_jrx_mtag);
1046 "could not allocate jumbo RX DMA tag\n");
1050 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0,
1051 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1052 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag);
1054 device_printf(dev, "could not allocate RX DMA tag\n");
1059 * Allocate map for TX descriptor list.
1061 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1062 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1063 NULL, tx_list_size, 1, tx_list_size, 0,
1064 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag);
1066 device_printf(dev, "could not allocate TX DMA ring tag\n");
1070 /* Allocate DMA'able memory for the TX ring */
1072 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
1073 (void **)&sc->rl_ldata.rl_tx_list,
1074 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1075 &sc->rl_ldata.rl_tx_list_map);
1077 device_printf(dev, "could not allocate TX DMA ring\n");
1081 /* Load the map for the TX ring. */
1083 sc->rl_ldata.rl_tx_list_addr = 0;
1084 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
1085 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
1086 tx_list_size, re_dma_map_addr,
1087 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT);
1088 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) {
1089 device_printf(dev, "could not load TX DMA ring\n");
1093 /* Create DMA maps for TX buffers */
1095 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
1096 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0,
1097 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
1099 device_printf(dev, "could not create DMA map for TX\n");
1105 * Allocate map for RX descriptor list.
1107 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1108 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1109 NULL, rx_list_size, 1, rx_list_size, 0,
1110 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag);
1112 device_printf(dev, "could not create RX DMA ring tag\n");
1116 /* Allocate DMA'able memory for the RX ring */
1118 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag,
1119 (void **)&sc->rl_ldata.rl_rx_list,
1120 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1121 &sc->rl_ldata.rl_rx_list_map);
1123 device_printf(dev, "could not allocate RX DMA ring\n");
1127 /* Load the map for the RX ring. */
1129 sc->rl_ldata.rl_rx_list_addr = 0;
1130 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag,
1131 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
1132 rx_list_size, re_dma_map_addr,
1133 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT);
1134 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) {
1135 device_printf(dev, "could not load RX DMA ring\n");
1139 /* Create DMA maps for RX buffers */
1141 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
1142 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0,
1143 &sc->rl_ldata.rl_jrx_sparemap);
1146 "could not create spare DMA map for jumbo RX\n");
1149 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1150 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0,
1151 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap);
1154 "could not create DMA map for jumbo RX\n");
1159 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
1160 &sc->rl_ldata.rl_rx_sparemap);
1162 device_printf(dev, "could not create spare DMA map for RX\n");
1165 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1166 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
1167 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
1169 device_printf(dev, "could not create DMA map for RX\n");
1174 /* Create DMA map for statistics. */
1175 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0,
1176 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1177 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL,
1178 &sc->rl_ldata.rl_stag);
1180 device_printf(dev, "could not create statistics DMA tag\n");
1183 /* Allocate DMA'able memory for statistics. */
1184 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag,
1185 (void **)&sc->rl_ldata.rl_stats,
1186 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1187 &sc->rl_ldata.rl_smap);
1190 "could not allocate statistics DMA memory\n");
1193 /* Load the map for statistics. */
1194 sc->rl_ldata.rl_stats_addr = 0;
1195 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap,
1196 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr,
1197 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT);
1198 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) {
1199 device_printf(dev, "could not load statistics DMA memory\n");
1207 * Attach the interface. Allocate softc structures, do ifmedia
1208 * setup and ethernet/BPF attach.
1211 re_attach(device_t dev)
1213 u_char eaddr[ETHER_ADDR_LEN];
1214 u_int16_t as[ETHER_ADDR_LEN / 2];
1215 struct rl_softc *sc;
1217 const struct rl_hwrev *hw_rev;
1218 int capmask, error = 0, hwrev, i, msic, msixc,
1221 u_int16_t devid, re_did = 0;
1224 sc = device_get_softc(dev);
1227 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1229 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
1232 * Map control/status registers.
1234 pci_enable_busmaster(dev);
1236 devid = pci_get_device(dev);
1238 * Prefer memory space register mapping over IO space.
1239 * Because RTL8169SC does not seem to work when memory mapping
1240 * is used always activate io mapping.
1242 if (devid == RT_DEVICEID_8169SC)
1244 if (prefer_iomap == 0) {
1245 sc->rl_res_id = PCIR_BAR(1);
1246 sc->rl_res_type = SYS_RES_MEMORY;
1247 /* RTL8168/8101E seems to use different BARs. */
1248 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E)
1249 sc->rl_res_id = PCIR_BAR(2);
1251 sc->rl_res_id = PCIR_BAR(0);
1252 sc->rl_res_type = SYS_RES_IOPORT;
1254 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
1255 &sc->rl_res_id, RF_ACTIVE);
1256 if (sc->rl_res == NULL && prefer_iomap == 0) {
1257 sc->rl_res_id = PCIR_BAR(0);
1258 sc->rl_res_type = SYS_RES_IOPORT;
1259 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
1260 &sc->rl_res_id, RF_ACTIVE);
1262 if (sc->rl_res == NULL) {
1263 device_printf(dev, "couldn't map ports/memory\n");
1268 sc->rl_btag = rman_get_bustag(sc->rl_res);
1269 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
1271 msic = pci_msi_count(dev);
1272 msixc = pci_msix_count(dev);
1273 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
1274 sc->rl_flags |= RL_FLAG_PCIE;
1275 sc->rl_expcap = reg;
1278 device_printf(dev, "MSI count : %d\n", msic);
1279 device_printf(dev, "MSI-X count : %d\n", msixc);
1281 if (msix_disable > 0)
1283 if (msi_disable > 0)
1285 /* Prefer MSI-X to MSI. */
1287 msixc = RL_MSI_MESSAGES;
1289 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1291 if (sc->rl_res_pba == NULL) {
1292 device_printf(sc->rl_dev,
1293 "could not allocate MSI-X PBA resource\n");
1295 if (sc->rl_res_pba != NULL &&
1296 pci_alloc_msix(dev, &msixc) == 0) {
1297 if (msixc == RL_MSI_MESSAGES) {
1298 device_printf(dev, "Using %d MSI-X message\n",
1300 sc->rl_flags |= RL_FLAG_MSIX;
1302 pci_release_msi(dev);
1304 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) {
1305 if (sc->rl_res_pba != NULL)
1306 bus_release_resource(dev, SYS_RES_MEMORY, rid,
1308 sc->rl_res_pba = NULL;
1312 /* Prefer MSI to INTx. */
1313 if (msixc == 0 && msic > 0) {
1314 msic = RL_MSI_MESSAGES;
1315 if (pci_alloc_msi(dev, &msic) == 0) {
1316 if (msic == RL_MSI_MESSAGES) {
1317 device_printf(dev, "Using %d MSI message\n",
1319 sc->rl_flags |= RL_FLAG_MSI;
1320 /* Explicitly set MSI enable bit. */
1321 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1322 cfg = CSR_READ_1(sc, RL_CFG2);
1324 CSR_WRITE_1(sc, RL_CFG2, cfg);
1325 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1327 pci_release_msi(dev);
1329 if ((sc->rl_flags & RL_FLAG_MSI) == 0)
1333 /* Allocate interrupt */
1334 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) {
1336 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1337 RF_SHAREABLE | RF_ACTIVE);
1338 if (sc->rl_irq[0] == NULL) {
1339 device_printf(dev, "couldn't allocate IRQ resources\n");
1344 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) {
1345 sc->rl_irq[i] = bus_alloc_resource_any(dev,
1346 SYS_RES_IRQ, &rid, RF_ACTIVE);
1347 if (sc->rl_irq[i] == NULL) {
1349 "couldn't allocate IRQ resources for "
1350 "message %d\n", rid);
1357 if ((sc->rl_flags & RL_FLAG_MSI) == 0) {
1358 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1359 cfg = CSR_READ_1(sc, RL_CFG2);
1360 if ((cfg & RL_CFG2_MSI) != 0) {
1361 device_printf(dev, "turning off MSI enable bit.\n");
1362 cfg &= ~RL_CFG2_MSI;
1363 CSR_WRITE_1(sc, RL_CFG2, cfg);
1365 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1368 /* Disable ASPM L0S/L1 and CLKREQ. */
1369 if (sc->rl_expcap != 0) {
1370 cap = pci_read_config(dev, sc->rl_expcap +
1372 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) {
1373 ctl = pci_read_config(dev, sc->rl_expcap +
1375 if ((ctl & (PCIEM_LINK_CTL_ECPM |
1376 PCIEM_LINK_CTL_ASPMC))!= 0) {
1377 ctl &= ~(PCIEM_LINK_CTL_ECPM |
1378 PCIEM_LINK_CTL_ASPMC);
1379 pci_write_config(dev, sc->rl_expcap +
1380 PCIER_LINK_CTL, ctl, 2);
1381 device_printf(dev, "ASPM disabled\n");
1384 device_printf(dev, "no ASPM capability\n");
1388 hwrev = CSR_READ_4(sc, RL_TXCFG);
1389 switch (hwrev & 0x70000000) {
1392 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000);
1393 hwrev &= (RL_TXCFG_HWREV | 0x80000000);
1396 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000);
1397 sc->rl_macrev = hwrev & 0x00700000;
1398 hwrev &= RL_TXCFG_HWREV;
1401 device_printf(dev, "MAC rev. 0x%08x\n", sc->rl_macrev);
1402 while (hw_rev->rl_desc != NULL) {
1403 if (hw_rev->rl_rev == hwrev) {
1404 sc->rl_type = hw_rev->rl_type;
1405 sc->rl_hwrev = hw_rev;
1410 if (hw_rev->rl_desc == NULL) {
1411 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev);
1416 switch (hw_rev->rl_rev) {
1417 case RL_HWREV_8139CPLUS:
1418 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD;
1420 case RL_HWREV_8100E:
1421 case RL_HWREV_8101E:
1422 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER;
1424 case RL_HWREV_8102E:
1425 case RL_HWREV_8102EL:
1426 case RL_HWREV_8102EL_SPIN1:
1427 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
1428 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP |
1431 case RL_HWREV_8103E:
1432 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
1433 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP |
1434 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP;
1436 case RL_HWREV_8401E:
1437 case RL_HWREV_8105E:
1438 case RL_HWREV_8105E_SPIN1:
1439 case RL_HWREV_8106E:
1440 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1441 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1442 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD;
1445 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1446 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1447 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD |
1448 RL_FLAG_CMDSTOP_WAIT_TXQ;
1450 case RL_HWREV_8168B_SPIN1:
1451 case RL_HWREV_8168B_SPIN2:
1452 sc->rl_flags |= RL_FLAG_WOLRXENB;
1454 case RL_HWREV_8168B_SPIN3:
1455 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT;
1457 case RL_HWREV_8168C_SPIN2:
1458 sc->rl_flags |= RL_FLAG_MACSLEEP;
1460 case RL_HWREV_8168C:
1461 if (sc->rl_macrev == 0x00200000)
1462 sc->rl_flags |= RL_FLAG_MACSLEEP;
1464 case RL_HWREV_8168CP:
1465 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1466 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1467 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK;
1469 case RL_HWREV_8168D:
1470 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1471 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1472 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1473 RL_FLAG_WOL_MANLINK;
1475 case RL_HWREV_8168DP:
1476 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1477 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD |
1478 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK;
1480 case RL_HWREV_8168E:
1481 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1482 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1483 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1484 RL_FLAG_WOL_MANLINK;
1486 case RL_HWREV_8168E_VL:
1487 case RL_HWREV_8168F:
1488 sc->rl_flags |= RL_FLAG_EARLYOFF;
1491 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1492 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1493 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1494 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK;
1496 case RL_HWREV_8168EP:
1497 case RL_HWREV_8168G:
1498 case RL_HWREV_8411B:
1499 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1500 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1501 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1502 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK |
1505 case RL_HWREV_8168GU:
1506 case RL_HWREV_8168H:
1507 if (pci_get_device(dev) == RT_DEVICEID_8101E) {
1508 /* RTL8106E(US), RTL8107E */
1509 sc->rl_flags |= RL_FLAG_FASTETHER;
1511 sc->rl_flags |= RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK;
1513 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1514 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1515 RL_FLAG_AUTOPAD | RL_FLAG_CMDSTOP_WAIT_TXQ |
1518 case RL_HWREV_8169_8110SB:
1519 case RL_HWREV_8169_8110SBL:
1520 case RL_HWREV_8169_8110SC:
1521 case RL_HWREV_8169_8110SCE:
1522 sc->rl_flags |= RL_FLAG_PHYWAKE;
1525 case RL_HWREV_8169S:
1526 case RL_HWREV_8110S:
1527 sc->rl_flags |= RL_FLAG_MACRESET;
1533 if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) {
1534 sc->rl_cfg0 = RL_8139_CFG0;
1535 sc->rl_cfg1 = RL_8139_CFG1;
1537 sc->rl_cfg3 = RL_8139_CFG3;
1538 sc->rl_cfg4 = RL_8139_CFG4;
1539 sc->rl_cfg5 = RL_8139_CFG5;
1541 sc->rl_cfg0 = RL_CFG0;
1542 sc->rl_cfg1 = RL_CFG1;
1543 sc->rl_cfg2 = RL_CFG2;
1544 sc->rl_cfg3 = RL_CFG3;
1545 sc->rl_cfg4 = RL_CFG4;
1546 sc->rl_cfg5 = RL_CFG5;
1549 /* Reset the adapter. */
1555 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1556 cfg = CSR_READ_1(sc, sc->rl_cfg1);
1558 CSR_WRITE_1(sc, sc->rl_cfg1, cfg);
1559 cfg = CSR_READ_1(sc, sc->rl_cfg5);
1560 cfg &= RL_CFG5_PME_STS;
1561 CSR_WRITE_1(sc, sc->rl_cfg5, cfg);
1562 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1564 if ((sc->rl_flags & RL_FLAG_PAR) != 0) {
1566 * XXX Should have a better way to extract station
1567 * address from EEPROM.
1569 for (i = 0; i < ETHER_ADDR_LEN; i++)
1570 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
1572 sc->rl_eewidth = RL_9356_ADDR_LEN;
1573 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
1574 if (re_did != 0x8129)
1575 sc->rl_eewidth = RL_9346_ADDR_LEN;
1578 * Get station address from the EEPROM.
1580 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3);
1581 for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
1582 as[i] = le16toh(as[i]);
1583 bcopy(as, eaddr, ETHER_ADDR_LEN);
1586 if (sc->rl_type == RL_8169) {
1587 /* Set RX length mask and number of descriptors. */
1588 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
1589 sc->rl_txstart = RL_GTXSTART;
1590 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT;
1591 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT;
1593 /* Set RX length mask and number of descriptors. */
1594 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
1595 sc->rl_txstart = RL_TXSTART;
1596 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT;
1597 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT;
1600 error = re_allocmem(dev, sc);
1605 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
1607 device_printf(dev, "can not if_alloc()\n");
1612 /* Take controller out of deep sleep mode. */
1613 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
1614 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
1615 CSR_WRITE_1(sc, RL_GPIO,
1616 CSR_READ_1(sc, RL_GPIO) | 0x01);
1618 CSR_WRITE_1(sc, RL_GPIO,
1619 CSR_READ_1(sc, RL_GPIO) & ~0x01);
1622 /* Take PHY out of power down mode. */
1623 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) {
1624 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80);
1625 if (hw_rev->rl_rev == RL_HWREV_8401E)
1626 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08);
1628 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) {
1629 re_gmii_writereg(dev, 1, 0x1f, 0);
1630 re_gmii_writereg(dev, 1, 0x0e, 0);
1634 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1635 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1636 ifp->if_ioctl = re_ioctl;
1637 ifp->if_start = re_start;
1639 * RTL8168/8111C generates wrong IP checksummed frame if the
1640 * packet has IP options so disable TX checksum offloading.
1642 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C ||
1643 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2 ||
1644 sc->rl_hwrev->rl_rev == RL_HWREV_8168CP) {
1645 ifp->if_hwassist = 0;
1646 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TSO4;
1648 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP;
1649 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
1651 ifp->if_hwassist |= CSUM_TSO;
1652 ifp->if_capenable = ifp->if_capabilities;
1653 ifp->if_init = re_init;
1654 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
1655 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN;
1656 IFQ_SET_READY(&ifp->if_snd);
1658 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc);
1660 #define RE_PHYAD_INTERNAL 0
1663 phy = RE_PHYAD_INTERNAL;
1664 if (sc->rl_type == RL_8169)
1666 capmask = BMSR_DEFCAPMASK;
1667 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0)
1668 capmask &= ~BMSR_EXTSTAT;
1669 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd,
1670 re_ifmedia_sts, capmask, phy, MII_OFFSET_ANY, MIIF_DOPAUSE);
1672 device_printf(dev, "attaching PHYs failed\n");
1677 * Call MI attach routine.
1679 ether_ifattach(ifp, eaddr);
1681 /* VLAN capability setup */
1682 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1683 if (ifp->if_capabilities & IFCAP_HWCSUM)
1684 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
1685 /* Enable WOL if PM is supported. */
1686 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0)
1687 ifp->if_capabilities |= IFCAP_WOL;
1688 ifp->if_capenable = ifp->if_capabilities;
1689 ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST);
1691 * Don't enable TSO by default. It is known to generate
1692 * corrupted TCP segments(bad TCP options) under certain
1695 ifp->if_hwassist &= ~CSUM_TSO;
1696 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
1697 #ifdef DEVICE_POLLING
1698 ifp->if_capabilities |= IFCAP_POLLING;
1701 * Tell the upper layer(s) we support long frames.
1702 * Must appear after the call to ether_ifattach() because
1703 * ether_ifattach() sets ifi_hdrlen to the default value.
1705 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
1708 re_netmap_attach(sc);
1709 #endif /* DEV_NETMAP */
1713 * Perform hardware diagnostic on the original RTL8169.
1714 * Some 32-bit cards were incorrectly wired and would
1715 * malfunction if plugged into a 64-bit slot.
1717 if (hwrev == RL_HWREV_8169) {
1718 error = re_diag(sc);
1721 "attach aborted due to hardware diag failure\n");
1722 ether_ifdetach(ifp);
1728 #ifdef RE_TX_MODERATION
1731 /* Hook interrupt last to avoid having to lock softc */
1732 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 &&
1734 error = bus_setup_intr(dev, sc->rl_irq[0],
1735 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc,
1736 &sc->rl_intrhand[0]);
1738 error = bus_setup_intr(dev, sc->rl_irq[0],
1739 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc,
1740 &sc->rl_intrhand[0]);
1743 device_printf(dev, "couldn't set up irq\n");
1744 ether_ifdetach(ifp);
1748 NETDUMP_SET(ifp, re);
1758 * Shutdown hardware and free up resources. This can be called any
1759 * time after the mutex has been initialized. It is called in both
1760 * the error case in attach and the normal detach case so it needs
1761 * to be careful about only freeing resources that have actually been
1765 re_detach(device_t dev)
1767 struct rl_softc *sc;
1771 sc = device_get_softc(dev);
1773 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized"));
1775 /* These should only be active if attach succeeded */
1776 if (device_is_attached(dev)) {
1777 #ifdef DEVICE_POLLING
1778 if (ifp->if_capenable & IFCAP_POLLING)
1779 ether_poll_deregister(ifp);
1787 callout_drain(&sc->rl_stat_callout);
1788 taskqueue_drain(taskqueue_fast, &sc->rl_inttask);
1790 * Force off the IFF_UP flag here, in case someone
1791 * still had a BPF descriptor attached to this
1792 * interface. If they do, ether_ifdetach() will cause
1793 * the BPF code to try and clear the promisc mode
1794 * flag, which will bubble down to re_ioctl(),
1795 * which will try to call re_init() again. This will
1796 * turn the NIC back on and restart the MII ticker,
1797 * which will panic the system when the kernel tries
1798 * to invoke the re_tick() function that isn't there
1801 ifp->if_flags &= ~IFF_UP;
1802 ether_ifdetach(ifp);
1805 device_delete_child(dev, sc->rl_miibus);
1806 bus_generic_detach(dev);
1809 * The rest is resource deallocation, so we should already be
1813 if (sc->rl_intrhand[0] != NULL) {
1814 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
1815 sc->rl_intrhand[0] = NULL;
1820 #endif /* DEV_NETMAP */
1823 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0)
1827 if (sc->rl_irq[0] != NULL) {
1828 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]);
1829 sc->rl_irq[0] = NULL;
1831 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0)
1832 pci_release_msi(dev);
1833 if (sc->rl_res_pba) {
1835 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba);
1838 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id,
1841 /* Unload and free the RX DMA ring memory and map */
1843 if (sc->rl_ldata.rl_rx_list_tag) {
1844 if (sc->rl_ldata.rl_rx_list_addr)
1845 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag,
1846 sc->rl_ldata.rl_rx_list_map);
1847 if (sc->rl_ldata.rl_rx_list)
1848 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag,
1849 sc->rl_ldata.rl_rx_list,
1850 sc->rl_ldata.rl_rx_list_map);
1851 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag);
1854 /* Unload and free the TX DMA ring memory and map */
1856 if (sc->rl_ldata.rl_tx_list_tag) {
1857 if (sc->rl_ldata.rl_tx_list_addr)
1858 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag,
1859 sc->rl_ldata.rl_tx_list_map);
1860 if (sc->rl_ldata.rl_tx_list)
1861 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag,
1862 sc->rl_ldata.rl_tx_list,
1863 sc->rl_ldata.rl_tx_list_map);
1864 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag);
1867 /* Destroy all the RX and TX buffer maps */
1869 if (sc->rl_ldata.rl_tx_mtag) {
1870 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
1871 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap)
1872 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag,
1873 sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
1875 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag);
1877 if (sc->rl_ldata.rl_rx_mtag) {
1878 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1879 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap)
1880 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
1881 sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
1883 if (sc->rl_ldata.rl_rx_sparemap)
1884 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
1885 sc->rl_ldata.rl_rx_sparemap);
1886 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag);
1888 if (sc->rl_ldata.rl_jrx_mtag) {
1889 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1890 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap)
1891 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag,
1892 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap);
1894 if (sc->rl_ldata.rl_jrx_sparemap)
1895 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag,
1896 sc->rl_ldata.rl_jrx_sparemap);
1897 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag);
1899 /* Unload and free the stats buffer and map */
1901 if (sc->rl_ldata.rl_stag) {
1902 if (sc->rl_ldata.rl_stats_addr)
1903 bus_dmamap_unload(sc->rl_ldata.rl_stag,
1904 sc->rl_ldata.rl_smap);
1905 if (sc->rl_ldata.rl_stats)
1906 bus_dmamem_free(sc->rl_ldata.rl_stag,
1907 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap);
1908 bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1911 if (sc->rl_parent_tag)
1912 bus_dma_tag_destroy(sc->rl_parent_tag);
1914 mtx_destroy(&sc->rl_mtx);
1919 static __inline void
1920 re_discard_rxbuf(struct rl_softc *sc, int idx)
1922 struct rl_desc *desc;
1923 struct rl_rxdesc *rxd;
1926 if (sc->rl_ifp->if_mtu > RL_MTU &&
1927 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0)
1928 rxd = &sc->rl_ldata.rl_jrx_desc[idx];
1930 rxd = &sc->rl_ldata.rl_rx_desc[idx];
1931 desc = &sc->rl_ldata.rl_rx_list[idx];
1932 desc->rl_vlanctl = 0;
1933 cmdstat = rxd->rx_size;
1934 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1935 cmdstat |= RL_RDESC_CMD_EOR;
1936 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1940 re_newbuf(struct rl_softc *sc, int idx)
1943 struct rl_rxdesc *rxd;
1944 bus_dma_segment_t segs[1];
1946 struct rl_desc *desc;
1950 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1954 m->m_len = m->m_pkthdr.len = MCLBYTES;
1957 * This is part of an evil trick to deal with non-x86 platforms.
1958 * The RealTek chip requires RX buffers to be aligned on 64-bit
1959 * boundaries, but that will hose non-x86 machines. To get around
1960 * this, we leave some empty space at the start of each buffer
1961 * and for non-x86 hosts, we copy the buffer back six bytes
1962 * to achieve word alignment. This is slightly more efficient
1963 * than allocating a new buffer, copying the contents, and
1964 * discarding the old buffer.
1966 m_adj(m, RE_ETHER_ALIGN);
1968 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag,
1969 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
1974 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs));
1976 rxd = &sc->rl_ldata.rl_rx_desc[idx];
1977 if (rxd->rx_m != NULL) {
1978 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
1979 BUS_DMASYNC_POSTREAD);
1980 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap);
1984 map = rxd->rx_dmamap;
1985 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap;
1986 rxd->rx_size = segs[0].ds_len;
1987 sc->rl_ldata.rl_rx_sparemap = map;
1988 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
1989 BUS_DMASYNC_PREREAD);
1991 desc = &sc->rl_ldata.rl_rx_list[idx];
1992 desc->rl_vlanctl = 0;
1993 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
1994 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
1995 cmdstat = segs[0].ds_len;
1996 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1997 cmdstat |= RL_RDESC_CMD_EOR;
1998 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
2004 re_jumbo_newbuf(struct rl_softc *sc, int idx)
2007 struct rl_rxdesc *rxd;
2008 bus_dma_segment_t segs[1];
2010 struct rl_desc *desc;
2014 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
2017 m->m_len = m->m_pkthdr.len = MJUM9BYTES;
2019 m_adj(m, RE_ETHER_ALIGN);
2021 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag,
2022 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
2027 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs));
2029 rxd = &sc->rl_ldata.rl_jrx_desc[idx];
2030 if (rxd->rx_m != NULL) {
2031 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap,
2032 BUS_DMASYNC_POSTREAD);
2033 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap);
2037 map = rxd->rx_dmamap;
2038 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap;
2039 rxd->rx_size = segs[0].ds_len;
2040 sc->rl_ldata.rl_jrx_sparemap = map;
2041 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap,
2042 BUS_DMASYNC_PREREAD);
2044 desc = &sc->rl_ldata.rl_rx_list[idx];
2045 desc->rl_vlanctl = 0;
2046 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
2047 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
2048 cmdstat = segs[0].ds_len;
2049 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
2050 cmdstat |= RL_RDESC_CMD_EOR;
2051 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
2057 static __inline void
2058 re_fixup_rx(struct mbuf *m)
2061 uint16_t *src, *dst;
2063 src = mtod(m, uint16_t *);
2064 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src;
2066 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
2069 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN;
2074 re_tx_list_init(struct rl_softc *sc)
2076 struct rl_desc *desc;
2081 bzero(sc->rl_ldata.rl_tx_list,
2082 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc));
2083 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++)
2084 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL;
2086 re_netmap_tx_init(sc);
2087 #endif /* DEV_NETMAP */
2089 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1];
2090 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR);
2092 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2093 sc->rl_ldata.rl_tx_list_map,
2094 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2096 sc->rl_ldata.rl_tx_prodidx = 0;
2097 sc->rl_ldata.rl_tx_considx = 0;
2098 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt;
2104 re_rx_list_init(struct rl_softc *sc)
2108 bzero(sc->rl_ldata.rl_rx_list,
2109 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
2110 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
2111 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL;
2112 if ((error = re_newbuf(sc, i)) != 0)
2116 re_netmap_rx_init(sc);
2117 #endif /* DEV_NETMAP */
2119 /* Flush the RX descriptors */
2121 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2122 sc->rl_ldata.rl_rx_list_map,
2123 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2125 sc->rl_ldata.rl_rx_prodidx = 0;
2126 sc->rl_head = sc->rl_tail = NULL;
2127 sc->rl_int_rx_act = 0;
2133 re_jrx_list_init(struct rl_softc *sc)
2137 bzero(sc->rl_ldata.rl_rx_list,
2138 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
2139 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
2140 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL;
2141 if ((error = re_jumbo_newbuf(sc, i)) != 0)
2145 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2146 sc->rl_ldata.rl_rx_list_map,
2147 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2149 sc->rl_ldata.rl_rx_prodidx = 0;
2150 sc->rl_head = sc->rl_tail = NULL;
2151 sc->rl_int_rx_act = 0;
2157 * RX handler for C+ and 8169. For the gigE chips, we support
2158 * the reception of jumbo frames that have been fragmented
2159 * across multiple 2K mbuf cluster buffers.
2162 re_rxeof(struct rl_softc *sc, int *rx_npktsp)
2166 int i, rxerr, total_len;
2167 struct rl_desc *cur_rx;
2168 u_int32_t rxstat, rxvlan;
2169 int jumbo, maxpkt = 16, rx_npkts = 0;
2175 if (netmap_rx_irq(ifp, 0, &rx_npkts))
2177 #endif /* DEV_NETMAP */
2178 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0)
2183 /* Invalidate the descriptor memory */
2185 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2186 sc->rl_ldata.rl_rx_list_map,
2187 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2189 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0;
2190 i = RL_RX_DESC_NXT(sc, i)) {
2191 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2193 cur_rx = &sc->rl_ldata.rl_rx_list[i];
2194 rxstat = le32toh(cur_rx->rl_cmdstat);
2195 if ((rxstat & RL_RDESC_STAT_OWN) != 0)
2197 total_len = rxstat & sc->rl_rxlenmask;
2198 rxvlan = le32toh(cur_rx->rl_vlanctl);
2200 m = sc->rl_ldata.rl_jrx_desc[i].rx_m;
2202 m = sc->rl_ldata.rl_rx_desc[i].rx_m;
2204 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
2205 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) !=
2206 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) {
2208 * RTL8168C or later controllers do not
2209 * support multi-fragment packet.
2211 re_discard_rxbuf(sc, i);
2213 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) {
2214 if (re_newbuf(sc, i) != 0) {
2216 * If this is part of a multi-fragment packet,
2217 * discard all the pieces.
2219 if (sc->rl_head != NULL) {
2220 m_freem(sc->rl_head);
2221 sc->rl_head = sc->rl_tail = NULL;
2223 re_discard_rxbuf(sc, i);
2226 m->m_len = RE_RX_DESC_BUFLEN;
2227 if (sc->rl_head == NULL)
2228 sc->rl_head = sc->rl_tail = m;
2230 m->m_flags &= ~M_PKTHDR;
2231 sc->rl_tail->m_next = m;
2238 * NOTE: for the 8139C+, the frame length field
2239 * is always 12 bits in size, but for the gigE chips,
2240 * it is 13 bits (since the max RX frame length is 16K).
2241 * Unfortunately, all 32 bits in the status word
2242 * were already used, so to make room for the extra
2243 * length bit, RealTek took out the 'frame alignment
2244 * error' bit and shifted the other status bits
2245 * over one slot. The OWN, EOR, FS and LS bits are
2246 * still in the same places. We have already extracted
2247 * the frame length and checked the OWN bit, so rather
2248 * than using an alternate bit mapping, we shift the
2249 * status bits one space to the right so we can evaluate
2250 * them using the 8169 status as though it was in the
2251 * same format as that of the 8139C+.
2253 if (sc->rl_type == RL_8169)
2257 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be
2258 * set, but if CRC is clear, it will still be a valid frame.
2260 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) {
2262 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 &&
2264 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)
2267 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2269 * If this is part of a multi-fragment packet,
2270 * discard all the pieces.
2272 if (sc->rl_head != NULL) {
2273 m_freem(sc->rl_head);
2274 sc->rl_head = sc->rl_tail = NULL;
2276 re_discard_rxbuf(sc, i);
2282 * If allocating a replacement mbuf fails,
2283 * reload the current one.
2286 rxerr = re_jumbo_newbuf(sc, i);
2288 rxerr = re_newbuf(sc, i);
2290 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2291 if (sc->rl_head != NULL) {
2292 m_freem(sc->rl_head);
2293 sc->rl_head = sc->rl_tail = NULL;
2295 re_discard_rxbuf(sc, i);
2299 if (sc->rl_head != NULL) {
2301 m->m_len = total_len;
2303 m->m_len = total_len % RE_RX_DESC_BUFLEN;
2305 m->m_len = RE_RX_DESC_BUFLEN;
2308 * Special case: if there's 4 bytes or less
2309 * in this buffer, the mbuf can be discarded:
2310 * the last 4 bytes is the CRC, which we don't
2311 * care about anyway.
2313 if (m->m_len <= ETHER_CRC_LEN) {
2314 sc->rl_tail->m_len -=
2315 (ETHER_CRC_LEN - m->m_len);
2318 m->m_len -= ETHER_CRC_LEN;
2319 m->m_flags &= ~M_PKTHDR;
2320 sc->rl_tail->m_next = m;
2323 sc->rl_head = sc->rl_tail = NULL;
2324 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
2326 m->m_pkthdr.len = m->m_len =
2327 (total_len - ETHER_CRC_LEN);
2332 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2333 m->m_pkthdr.rcvif = ifp;
2335 /* Do RX checksumming if enabled */
2337 if (ifp->if_capenable & IFCAP_RXCSUM) {
2338 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
2339 /* Check IP header checksum */
2340 if (rxstat & RL_RDESC_STAT_PROTOID)
2341 m->m_pkthdr.csum_flags |=
2343 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
2344 m->m_pkthdr.csum_flags |=
2347 /* Check TCP/UDP checksum */
2348 if ((RL_TCPPKT(rxstat) &&
2349 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
2350 (RL_UDPPKT(rxstat) &&
2351 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
2352 m->m_pkthdr.csum_flags |=
2353 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2354 m->m_pkthdr.csum_data = 0xffff;
2358 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP
2360 if ((rxstat & RL_RDESC_STAT_PROTOID) &&
2361 (rxvlan & RL_RDESC_IPV4))
2362 m->m_pkthdr.csum_flags |=
2364 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) &&
2365 (rxvlan & RL_RDESC_IPV4))
2366 m->m_pkthdr.csum_flags |=
2368 if (((rxstat & RL_RDESC_STAT_TCP) &&
2369 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
2370 ((rxstat & RL_RDESC_STAT_UDP) &&
2371 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
2372 m->m_pkthdr.csum_flags |=
2373 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2374 m->m_pkthdr.csum_data = 0xffff;
2379 if (rxvlan & RL_RDESC_VLANCTL_TAG) {
2380 m->m_pkthdr.ether_vtag =
2381 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA));
2382 m->m_flags |= M_VLANTAG;
2385 (*ifp->if_input)(ifp, m);
2390 /* Flush the RX DMA ring */
2392 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2393 sc->rl_ldata.rl_rx_list_map,
2394 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2396 sc->rl_ldata.rl_rx_prodidx = i;
2398 if (rx_npktsp != NULL)
2399 *rx_npktsp = rx_npkts;
2407 re_txeof(struct rl_softc *sc)
2410 struct rl_txdesc *txd;
2414 cons = sc->rl_ldata.rl_tx_considx;
2415 if (cons == sc->rl_ldata.rl_tx_prodidx)
2420 if (netmap_tx_irq(ifp, 0))
2422 #endif /* DEV_NETMAP */
2423 /* Invalidate the TX descriptor list */
2424 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2425 sc->rl_ldata.rl_tx_list_map,
2426 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2428 for (; cons != sc->rl_ldata.rl_tx_prodidx;
2429 cons = RL_TX_DESC_NXT(sc, cons)) {
2430 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat);
2431 if (txstat & RL_TDESC_STAT_OWN)
2434 * We only stash mbufs in the last descriptor
2435 * in a fragment chain, which also happens to
2436 * be the only place where the TX status bits
2439 if (txstat & RL_TDESC_CMD_EOF) {
2440 txd = &sc->rl_ldata.rl_tx_desc[cons];
2441 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
2442 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2443 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
2445 KASSERT(txd->tx_m != NULL,
2446 ("%s: freeing NULL mbufs!", __func__));
2449 if (txstat & (RL_TDESC_STAT_EXCESSCOL|
2450 RL_TDESC_STAT_COLCNT))
2451 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
2452 if (txstat & RL_TDESC_STAT_TXERRSUM)
2453 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2455 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2457 sc->rl_ldata.rl_tx_free++;
2458 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2460 sc->rl_ldata.rl_tx_considx = cons;
2462 /* No changes made to the TX ring, so no flush needed */
2464 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) {
2465 #ifdef RE_TX_MODERATION
2467 * If not all descriptors have been reaped yet, reload
2468 * the timer so that we will eventually get another
2469 * interrupt that will cause us to re-enter this routine.
2470 * This is done in case the transmitter has gone idle.
2472 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2475 sc->rl_watchdog_timer = 0;
2481 struct rl_softc *sc;
2482 struct mii_data *mii;
2488 mii = device_get_softc(sc->rl_miibus);
2490 if ((sc->rl_flags & RL_FLAG_LINK) == 0)
2491 re_miibus_statchg(sc->rl_dev);
2493 * Reclaim transmitted frames here. Technically it is not
2494 * necessary to do here but it ensures periodic reclamation
2495 * regardless of Tx completion interrupt which seems to be
2496 * lost on PCIe based controllers under certain situations.
2500 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
2503 #ifdef DEVICE_POLLING
2505 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2507 struct rl_softc *sc = ifp->if_softc;
2511 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2512 rx_npkts = re_poll_locked(ifp, cmd, count);
2518 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
2520 struct rl_softc *sc = ifp->if_softc;
2525 sc->rxcycles = count;
2526 re_rxeof(sc, &rx_npkts);
2529 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2530 re_start_locked(ifp);
2532 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
2535 status = CSR_READ_2(sc, RL_ISR);
2536 if (status == 0xffff)
2539 CSR_WRITE_2(sc, RL_ISR, status);
2540 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2541 (sc->rl_flags & RL_FLAG_PCIE))
2542 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2545 * XXX check behaviour on receiver stalls.
2548 if (status & RL_ISR_SYSTEM_ERR) {
2549 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2555 #endif /* DEVICE_POLLING */
2560 struct rl_softc *sc;
2565 status = CSR_READ_2(sc, RL_ISR);
2566 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0)
2567 return (FILTER_STRAY);
2568 CSR_WRITE_2(sc, RL_IMR, 0);
2570 taskqueue_enqueue(taskqueue_fast, &sc->rl_inttask);
2572 return (FILTER_HANDLED);
2576 re_int_task(void *arg, int npending)
2578 struct rl_softc *sc;
2588 status = CSR_READ_2(sc, RL_ISR);
2589 CSR_WRITE_2(sc, RL_ISR, status);
2591 if (sc->suspended ||
2592 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2597 #ifdef DEVICE_POLLING
2598 if (ifp->if_capenable & IFCAP_POLLING) {
2604 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW))
2605 rval = re_rxeof(sc, NULL);
2608 * Some chips will ignore a second TX request issued
2609 * while an existing transmission is in progress. If
2610 * the transmitter goes idle but there are still
2611 * packets waiting to be sent, we need to restart the
2612 * channel here to flush them out. This only seems to
2613 * be required with the PCIe devices.
2615 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2616 (sc->rl_flags & RL_FLAG_PCIE))
2617 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2619 #ifdef RE_TX_MODERATION
2620 RL_ISR_TIMEOUT_EXPIRED|
2624 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL))
2627 if (status & RL_ISR_SYSTEM_ERR) {
2628 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2632 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2633 re_start_locked(ifp);
2637 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) {
2638 taskqueue_enqueue(taskqueue_fast, &sc->rl_inttask);
2642 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2646 re_intr_msi(void *xsc)
2648 struct rl_softc *sc;
2650 uint16_t intrs, status;
2656 #ifdef DEVICE_POLLING
2657 if (ifp->if_capenable & IFCAP_POLLING) {
2662 /* Disable interrupts. */
2663 CSR_WRITE_2(sc, RL_IMR, 0);
2664 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2669 intrs = RL_INTRS_CPLUS;
2670 status = CSR_READ_2(sc, RL_ISR);
2671 CSR_WRITE_2(sc, RL_ISR, status);
2672 if (sc->rl_int_rx_act > 0) {
2673 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW |
2675 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW |
2679 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR |
2680 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) {
2682 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2683 if (sc->rl_int_rx_mod != 0 &&
2684 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR |
2685 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) {
2686 /* Rearm one-shot timer. */
2687 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2688 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR |
2689 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN);
2690 sc->rl_int_rx_act = 1;
2692 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR |
2693 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN;
2694 sc->rl_int_rx_act = 0;
2700 * Some chips will ignore a second TX request issued
2701 * while an existing transmission is in progress. If
2702 * the transmitter goes idle but there are still
2703 * packets waiting to be sent, we need to restart the
2704 * channel here to flush them out. This only seems to
2705 * be required with the PCIe devices.
2707 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2708 (sc->rl_flags & RL_FLAG_PCIE))
2709 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2710 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL))
2713 if (status & RL_ISR_SYSTEM_ERR) {
2714 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2718 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2719 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2720 re_start_locked(ifp);
2721 CSR_WRITE_2(sc, RL_IMR, intrs);
2727 re_encap(struct rl_softc *sc, struct mbuf **m_head)
2729 struct rl_txdesc *txd, *txd_last;
2730 bus_dma_segment_t segs[RL_NTXSEGS];
2733 struct rl_desc *desc;
2735 int i, error, ei, si;
2737 uint32_t cmdstat, csum_flags, vlanctl;
2740 M_ASSERTPKTHDR((*m_head));
2743 * With some of the RealTek chips, using the checksum offload
2744 * support in conjunction with the autopadding feature results
2745 * in the transmission of corrupt frames. For example, if we
2746 * need to send a really small IP fragment that's less than 60
2747 * bytes in size, and IP header checksumming is enabled, the
2748 * resulting ethernet frame that appears on the wire will
2749 * have garbled payload. To work around this, if TX IP checksum
2750 * offload is enabled, we always manually pad short frames out
2751 * to the minimum ethernet frame size.
2753 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 &&
2754 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN &&
2755 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) {
2756 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len;
2757 if (M_WRITABLE(*m_head) == 0) {
2758 /* Get a writable copy. */
2759 m_new = m_dup(*m_head, M_NOWAIT);
2761 if (m_new == NULL) {
2767 if ((*m_head)->m_next != NULL ||
2768 M_TRAILINGSPACE(*m_head) < padlen) {
2769 m_new = m_defrag(*m_head, M_NOWAIT);
2770 if (m_new == NULL) {
2779 * Manually pad short frames, and zero the pad space
2780 * to avoid leaking data.
2782 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen);
2783 m_new->m_pkthdr.len += padlen;
2784 m_new->m_len = m_new->m_pkthdr.len;
2788 prod = sc->rl_ldata.rl_tx_prodidx;
2789 txd = &sc->rl_ldata.rl_tx_desc[prod];
2790 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
2791 *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2792 if (error == EFBIG) {
2793 m_new = m_collapse(*m_head, M_NOWAIT, RL_NTXSEGS);
2794 if (m_new == NULL) {
2800 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag,
2801 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2807 } else if (error != 0)
2815 /* Check for number of available descriptors. */
2816 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) {
2817 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap);
2821 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
2822 BUS_DMASYNC_PREWRITE);
2825 * Set up checksum offload. Note: checksum offload bits must
2826 * appear in all descriptors of a multi-descriptor transmit
2827 * attempt. This is according to testing done with an 8169
2828 * chip. This is a requirement.
2832 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2833 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) {
2834 csum_flags |= RL_TDESC_CMD_LGSEND;
2835 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
2836 RL_TDESC_CMD_MSSVALV2_SHIFT);
2838 csum_flags |= RL_TDESC_CMD_LGSEND |
2839 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
2840 RL_TDESC_CMD_MSSVAL_SHIFT);
2844 * Unconditionally enable IP checksum if TCP or UDP
2845 * checksum is required. Otherwise, TCP/UDP checksum
2846 * doesn't make effects.
2848 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) {
2849 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
2850 csum_flags |= RL_TDESC_CMD_IPCSUM;
2851 if (((*m_head)->m_pkthdr.csum_flags &
2853 csum_flags |= RL_TDESC_CMD_TCPCSUM;
2854 if (((*m_head)->m_pkthdr.csum_flags &
2856 csum_flags |= RL_TDESC_CMD_UDPCSUM;
2858 vlanctl |= RL_TDESC_CMD_IPCSUMV2;
2859 if (((*m_head)->m_pkthdr.csum_flags &
2861 vlanctl |= RL_TDESC_CMD_TCPCSUMV2;
2862 if (((*m_head)->m_pkthdr.csum_flags &
2864 vlanctl |= RL_TDESC_CMD_UDPCSUMV2;
2870 * Set up hardware VLAN tagging. Note: vlan tag info must
2871 * appear in all descriptors of a multi-descriptor
2872 * transmission attempt.
2874 if ((*m_head)->m_flags & M_VLANTAG)
2875 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) |
2876 RL_TDESC_VLANCTL_TAG;
2879 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) {
2880 desc = &sc->rl_ldata.rl_tx_list[prod];
2881 desc->rl_vlanctl = htole32(vlanctl);
2882 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
2883 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
2884 cmdstat = segs[i].ds_len;
2886 cmdstat |= RL_TDESC_CMD_OWN;
2887 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1)
2888 cmdstat |= RL_TDESC_CMD_EOR;
2889 desc->rl_cmdstat = htole32(cmdstat | csum_flags);
2890 sc->rl_ldata.rl_tx_free--;
2892 /* Update producer index. */
2893 sc->rl_ldata.rl_tx_prodidx = prod;
2895 /* Set EOF on the last descriptor. */
2896 ei = RL_TX_DESC_PRV(sc, prod);
2897 desc = &sc->rl_ldata.rl_tx_list[ei];
2898 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
2900 desc = &sc->rl_ldata.rl_tx_list[si];
2901 /* Set SOF and transfer ownership of packet to the chip. */
2902 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF);
2905 * Insure that the map for this transmission
2906 * is placed at the array index of the last descriptor
2907 * in this chain. (Swap last and first dmamaps.)
2909 txd_last = &sc->rl_ldata.rl_tx_desc[ei];
2910 map = txd->tx_dmamap;
2911 txd->tx_dmamap = txd_last->tx_dmamap;
2912 txd_last->tx_dmamap = map;
2913 txd_last->tx_m = *m_head;
2919 re_start(struct ifnet *ifp)
2921 struct rl_softc *sc;
2925 re_start_locked(ifp);
2930 * Main transmit routine for C+ and gigE NICs.
2933 re_start_locked(struct ifnet *ifp)
2935 struct rl_softc *sc;
2936 struct mbuf *m_head;
2942 /* XXX is this necessary ? */
2943 if (ifp->if_capenable & IFCAP_NETMAP) {
2944 struct netmap_kring *kring = NA(ifp)->tx_rings[0];
2945 if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) {
2946 /* kick the tx unit */
2947 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2948 #ifdef RE_TX_MODERATION
2949 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2951 sc->rl_watchdog_timer = 5;
2955 #endif /* DEV_NETMAP */
2957 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2958 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
2961 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2962 sc->rl_ldata.rl_tx_free > 1;) {
2963 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2967 if (re_encap(sc, &m_head) != 0) {
2970 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2971 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2976 * If there's a BPF listener, bounce a copy of this frame
2979 ETHER_BPF_MTAP(ifp, m_head);
2985 #ifdef RE_TX_MODERATION
2986 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt)
2987 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2996 re_start_tx(struct rl_softc *sc)
2999 /* Flush the TX descriptors */
3000 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
3001 sc->rl_ldata.rl_tx_list_map,
3002 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
3004 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
3006 #ifdef RE_TX_MODERATION
3008 * Use the countdown timer for interrupt moderation.
3009 * 'TX done' interrupts are disabled. Instead, we reset the
3010 * countdown timer, which will begin counting until it hits
3011 * the value in the TIMERINT register, and then trigger an
3012 * interrupt. Each time we write to the TIMERCNT register,
3013 * the timer count is reset to 0.
3015 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
3019 * Set a timeout in case the chip goes out to lunch.
3021 sc->rl_watchdog_timer = 5;
3025 re_set_jumbo(struct rl_softc *sc, int jumbo)
3028 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) {
3029 pci_set_max_read_req(sc->rl_dev, 4096);
3033 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
3035 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) |
3037 switch (sc->rl_hwrev->rl_rev) {
3038 case RL_HWREV_8168DP:
3040 case RL_HWREV_8168E:
3041 CSR_WRITE_1(sc, sc->rl_cfg4,
3042 CSR_READ_1(sc, sc->rl_cfg4) | 0x01);
3045 CSR_WRITE_1(sc, sc->rl_cfg4,
3046 CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1);
3049 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) &
3050 ~RL_CFG3_JUMBO_EN0);
3051 switch (sc->rl_hwrev->rl_rev) {
3052 case RL_HWREV_8168DP:
3054 case RL_HWREV_8168E:
3055 CSR_WRITE_1(sc, sc->rl_cfg4,
3056 CSR_READ_1(sc, sc->rl_cfg4) & ~0x01);
3059 CSR_WRITE_1(sc, sc->rl_cfg4,
3060 CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1);
3063 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3065 switch (sc->rl_hwrev->rl_rev) {
3066 case RL_HWREV_8168DP:
3067 pci_set_max_read_req(sc->rl_dev, 4096);
3071 pci_set_max_read_req(sc->rl_dev, 512);
3073 pci_set_max_read_req(sc->rl_dev, 4096);
3080 struct rl_softc *sc = xsc;
3088 re_init_locked(struct rl_softc *sc)
3090 struct ifnet *ifp = sc->rl_ifp;
3091 struct mii_data *mii;
3095 uint32_t align_dummy;
3096 u_char eaddr[ETHER_ADDR_LEN];
3101 mii = device_get_softc(sc->rl_miibus);
3103 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3107 * Cancel pending I/O and free all RX/TX buffers.
3111 /* Put controller into known state. */
3115 * For C+ mode, initialize the RX descriptors and mbufs.
3117 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
3118 if (ifp->if_mtu > RL_MTU) {
3119 if (re_jrx_list_init(sc) != 0) {
3120 device_printf(sc->rl_dev,
3121 "no memory for jumbo RX buffers\n");
3125 /* Disable checksum offloading for jumbo frames. */
3126 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4);
3127 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO);
3129 if (re_rx_list_init(sc) != 0) {
3130 device_printf(sc->rl_dev,
3131 "no memory for RX buffers\n");
3136 re_set_jumbo(sc, ifp->if_mtu > RL_MTU);
3138 if (re_rx_list_init(sc) != 0) {
3139 device_printf(sc->rl_dev, "no memory for RX buffers\n");
3143 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 &&
3144 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) {
3145 if (ifp->if_mtu > RL_MTU)
3146 pci_set_max_read_req(sc->rl_dev, 512);
3148 pci_set_max_read_req(sc->rl_dev, 4096);
3151 re_tx_list_init(sc);
3154 * Enable C+ RX and TX mode, as well as VLAN stripping and
3155 * RX checksum offload. We must configure the C+ register
3156 * before all others.
3158 cfg = RL_CPLUSCMD_PCI_MRW;
3159 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
3160 cfg |= RL_CPLUSCMD_RXCSUM_ENB;
3161 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3162 cfg |= RL_CPLUSCMD_VLANSTRIP;
3163 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) {
3164 cfg |= RL_CPLUSCMD_MACSTAT_DIS;
3168 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB;
3169 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg);
3170 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC ||
3171 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) {
3173 if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0)
3175 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE)
3177 CSR_WRITE_4(sc, 0x7c, reg);
3178 /* Disable interrupt mitigation. */
3179 CSR_WRITE_2(sc, 0xe2, 0);
3182 * Disable TSO if interface MTU size is greater than MSS
3183 * allowed in controller.
3185 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) {
3186 ifp->if_capenable &= ~IFCAP_TSO4;
3187 ifp->if_hwassist &= ~CSUM_TSO;
3191 * Init our MAC address. Even though the chipset
3192 * documentation doesn't mention it, we need to enter "Config
3193 * register write enable" mode to modify the ID registers.
3195 /* Copy MAC address on stack to align. */
3196 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN);
3197 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
3198 CSR_WRITE_4(sc, RL_IDR0,
3199 htole32(*(u_int32_t *)(&eaddr.eaddr[0])));
3200 CSR_WRITE_4(sc, RL_IDR4,
3201 htole32(*(u_int32_t *)(&eaddr.eaddr[4])));
3202 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3205 * Load the addresses of the RX and TX lists into the chip.
3208 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
3209 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
3210 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
3211 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
3213 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
3214 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
3215 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
3216 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
3218 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) {
3219 /* Disable RXDV gate. */
3220 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) &
3225 * Enable transmit and receive for pre-RTL8168G controllers.
3226 * RX/TX MACs should be enabled before RX/TX configuration.
3228 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) == 0)
3229 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB);
3232 * Set the initial TX configuration.
3234 if (sc->rl_testmode) {
3235 if (sc->rl_type == RL_8169)
3236 CSR_WRITE_4(sc, RL_TXCFG,
3237 RL_TXCFG_CONFIG|RL_LOOPTEST_ON);
3239 CSR_WRITE_4(sc, RL_TXCFG,
3240 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
3242 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
3244 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
3247 * Set the initial RX configuration.
3251 /* Configure interrupt moderation. */
3252 if (sc->rl_type == RL_8169) {
3253 /* Magic from vendor. */
3254 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100);
3258 * Enable transmit and receive for RTL8168G and later controllers.
3259 * RX/TX MACs should be enabled after RX/TX configuration.
3261 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0)
3262 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB);
3264 #ifdef DEVICE_POLLING
3266 * Disable interrupts if we are polling.
3268 if (ifp->if_capenable & IFCAP_POLLING)
3269 CSR_WRITE_2(sc, RL_IMR, 0);
3270 else /* otherwise ... */
3274 * Enable interrupts.
3276 if (sc->rl_testmode)
3277 CSR_WRITE_2(sc, RL_IMR, 0);
3279 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
3280 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS);
3282 /* Set initial TX threshold */
3283 sc->rl_txthresh = RL_TX_THRESH_INIT;
3285 /* Start RX/TX process. */
3286 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
3289 * Initialize the timer interrupt register so that
3290 * a timer interrupt will be generated once the timer
3291 * reaches a certain number of ticks. The timer is
3292 * reloaded on each transmit.
3294 #ifdef RE_TX_MODERATION
3296 * Use timer interrupt register to moderate TX interrupt
3297 * moderation, which dramatically improves TX frame rate.
3299 if (sc->rl_type == RL_8169)
3300 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
3302 CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
3305 * Use timer interrupt register to moderate RX interrupt
3308 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 &&
3310 if (sc->rl_type == RL_8169)
3311 CSR_WRITE_4(sc, RL_TIMERINT_8169,
3312 RL_USECS(sc->rl_int_rx_mod));
3314 if (sc->rl_type == RL_8169)
3315 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0));
3320 * For 8169 gigE NICs, set the max allowed RX packet
3321 * size so we can receive jumbo frames.
3323 if (sc->rl_type == RL_8169) {
3324 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
3326 * For controllers that use new jumbo frame scheme,
3327 * set maximum size of jumbo frame depending on
3328 * controller revisions.
3330 if (ifp->if_mtu > RL_MTU)
3331 CSR_WRITE_2(sc, RL_MAXRXPKTLEN,
3332 sc->rl_hwrev->rl_max_mtu +
3333 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN +
3336 CSR_WRITE_2(sc, RL_MAXRXPKTLEN,
3338 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 &&
3339 sc->rl_hwrev->rl_max_mtu == RL_MTU) {
3340 /* RTL810x has no jumbo frame support. */
3341 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN);
3343 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
3346 if (sc->rl_testmode)
3349 CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) |
3352 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3353 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3355 sc->rl_flags &= ~RL_FLAG_LINK;
3358 sc->rl_watchdog_timer = 0;
3359 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
3363 * Set media options.
3366 re_ifmedia_upd(struct ifnet *ifp)
3368 struct rl_softc *sc;
3369 struct mii_data *mii;
3373 mii = device_get_softc(sc->rl_miibus);
3375 error = mii_mediachg(mii);
3382 * Report current media status.
3385 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3387 struct rl_softc *sc;
3388 struct mii_data *mii;
3391 mii = device_get_softc(sc->rl_miibus);
3395 ifmr->ifm_active = mii->mii_media_active;
3396 ifmr->ifm_status = mii->mii_media_status;
3401 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3403 struct rl_softc *sc = ifp->if_softc;
3404 struct ifreq *ifr = (struct ifreq *) data;
3405 struct mii_data *mii;
3410 if (ifr->ifr_mtu < ETHERMIN ||
3411 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu ||
3412 ((sc->rl_flags & RL_FLAG_FASTETHER) != 0 &&
3413 ifr->ifr_mtu > RL_MTU)) {
3418 if (ifp->if_mtu != ifr->ifr_mtu) {
3419 ifp->if_mtu = ifr->ifr_mtu;
3420 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
3421 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
3422 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3425 if (ifp->if_mtu > RL_TSO_MTU &&
3426 (ifp->if_capenable & IFCAP_TSO4) != 0) {
3427 ifp->if_capenable &= ~(IFCAP_TSO4 |
3429 ifp->if_hwassist &= ~CSUM_TSO;
3431 VLAN_CAPABILITIES(ifp);
3437 if ((ifp->if_flags & IFF_UP) != 0) {
3438 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
3439 if (((ifp->if_flags ^ sc->rl_if_flags)
3440 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
3445 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3448 sc->rl_if_flags = ifp->if_flags;
3454 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3460 mii = device_get_softc(sc->rl_miibus);
3461 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3467 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3469 #ifdef DEVICE_POLLING
3470 if (mask & IFCAP_POLLING) {
3471 if (ifr->ifr_reqcap & IFCAP_POLLING) {
3472 error = ether_poll_register(re_poll, ifp);
3476 /* Disable interrupts */
3477 CSR_WRITE_2(sc, RL_IMR, 0x0000);
3478 ifp->if_capenable |= IFCAP_POLLING;
3481 error = ether_poll_deregister(ifp);
3482 /* Enable interrupts. */
3484 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
3485 ifp->if_capenable &= ~IFCAP_POLLING;
3489 #endif /* DEVICE_POLLING */
3491 if ((mask & IFCAP_TXCSUM) != 0 &&
3492 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3493 ifp->if_capenable ^= IFCAP_TXCSUM;
3494 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
3495 ifp->if_hwassist |= RE_CSUM_FEATURES;
3497 ifp->if_hwassist &= ~RE_CSUM_FEATURES;
3500 if ((mask & IFCAP_RXCSUM) != 0 &&
3501 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
3502 ifp->if_capenable ^= IFCAP_RXCSUM;
3505 if ((mask & IFCAP_TSO4) != 0 &&
3506 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
3507 ifp->if_capenable ^= IFCAP_TSO4;
3508 if ((IFCAP_TSO4 & ifp->if_capenable) != 0)
3509 ifp->if_hwassist |= CSUM_TSO;
3511 ifp->if_hwassist &= ~CSUM_TSO;
3512 if (ifp->if_mtu > RL_TSO_MTU &&
3513 (ifp->if_capenable & IFCAP_TSO4) != 0) {
3514 ifp->if_capenable &= ~IFCAP_TSO4;
3515 ifp->if_hwassist &= ~CSUM_TSO;
3518 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
3519 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
3520 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
3521 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
3522 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
3523 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3524 /* TSO over VLAN requires VLAN hardware tagging. */
3525 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
3526 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
3529 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
3530 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 |
3531 IFCAP_VLAN_HWTSO)) != 0)
3533 if ((mask & IFCAP_WOL) != 0 &&
3534 (ifp->if_capabilities & IFCAP_WOL) != 0) {
3535 if ((mask & IFCAP_WOL_UCAST) != 0)
3536 ifp->if_capenable ^= IFCAP_WOL_UCAST;
3537 if ((mask & IFCAP_WOL_MCAST) != 0)
3538 ifp->if_capenable ^= IFCAP_WOL_MCAST;
3539 if ((mask & IFCAP_WOL_MAGIC) != 0)
3540 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3542 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) {
3543 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3547 VLAN_CAPABILITIES(ifp);
3551 error = ether_ioctl(ifp, command, data);
3559 re_watchdog(struct rl_softc *sc)
3565 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0)
3570 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) {
3571 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
3573 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3574 re_start_locked(ifp);
3578 if_printf(ifp, "watchdog timeout\n");
3579 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3582 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3584 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3585 re_start_locked(ifp);
3589 * Stop the adapter and free any mbufs allocated to the
3593 re_stop(struct rl_softc *sc)
3597 struct rl_txdesc *txd;
3598 struct rl_rxdesc *rxd;
3604 sc->rl_watchdog_timer = 0;
3605 callout_stop(&sc->rl_stat_callout);
3606 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3609 * Disable accepting frames to put RX MAC into idle state.
3610 * Otherwise it's possible to get frames while stop command
3611 * execution is in progress and controller can DMA the frame
3612 * to already freed RX buffer during that period.
3614 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) &
3615 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI |
3616 RL_RXCFG_RX_BROAD));
3618 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) {
3619 /* Enable RXDV gate. */
3620 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) |
3624 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) {
3625 for (i = RL_TIMEOUT; i > 0; i--) {
3626 if ((CSR_READ_1(sc, sc->rl_txstart) &
3627 RL_TXSTART_START) == 0)
3632 device_printf(sc->rl_dev,
3633 "stopping TX poll timed out!\n");
3634 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
3635 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) {
3636 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB |
3638 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) {
3639 for (i = RL_TIMEOUT; i > 0; i--) {
3640 if ((CSR_READ_4(sc, RL_TXCFG) &
3641 RL_TXCFG_QUEUE_EMPTY) != 0)
3646 device_printf(sc->rl_dev,
3647 "stopping TXQ timed out!\n");
3650 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
3652 CSR_WRITE_2(sc, RL_IMR, 0x0000);
3653 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
3655 if (sc->rl_head != NULL) {
3656 m_freem(sc->rl_head);
3657 sc->rl_head = sc->rl_tail = NULL;
3660 /* Free the TX list buffers. */
3661 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
3662 txd = &sc->rl_ldata.rl_tx_desc[i];
3663 if (txd->tx_m != NULL) {
3664 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
3665 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3666 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
3673 /* Free the RX list buffers. */
3674 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
3675 rxd = &sc->rl_ldata.rl_rx_desc[i];
3676 if (rxd->rx_m != NULL) {
3677 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
3678 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3679 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
3686 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
3687 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
3688 rxd = &sc->rl_ldata.rl_jrx_desc[i];
3689 if (rxd->rx_m != NULL) {
3690 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag,
3691 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3692 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag,
3702 * Device suspend routine. Stop the interface and save some PCI
3703 * settings in case the BIOS doesn't restore them properly on
3707 re_suspend(device_t dev)
3709 struct rl_softc *sc;
3711 sc = device_get_softc(dev);
3723 * Device resume routine. Restore some PCI settings in case the BIOS
3724 * doesn't, re-enable busmastering, and restart the interface if
3728 re_resume(device_t dev)
3730 struct rl_softc *sc;
3733 sc = device_get_softc(dev);
3738 /* Take controller out of sleep mode. */
3739 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
3740 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
3741 CSR_WRITE_1(sc, RL_GPIO,
3742 CSR_READ_1(sc, RL_GPIO) | 0x01);
3746 * Clear WOL matching such that normal Rx filtering
3747 * wouldn't interfere with WOL patterns.
3751 /* reinitialize interface if necessary */
3752 if (ifp->if_flags & IFF_UP)
3762 * Stop all chip I/O so that the kernel's probe routines don't
3763 * get confused by errant DMAs when rebooting.
3766 re_shutdown(device_t dev)
3768 struct rl_softc *sc;
3770 sc = device_get_softc(dev);
3775 * Mark interface as down since otherwise we will panic if
3776 * interrupt comes in later on, which can happen in some
3779 sc->rl_ifp->if_flags &= ~IFF_UP;
3787 re_set_linkspeed(struct rl_softc *sc)
3789 struct mii_softc *miisc;
3790 struct mii_data *mii;
3795 mii = device_get_softc(sc->rl_miibus);
3798 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
3799 (IFM_ACTIVE | IFM_AVALID)) {
3800 switch IFM_SUBTYPE(mii->mii_media_active) {
3811 miisc = LIST_FIRST(&mii->mii_phys);
3812 phyno = miisc->mii_phy;
3813 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3815 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0);
3816 re_miibus_writereg(sc->rl_dev, phyno,
3817 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
3818 re_miibus_writereg(sc->rl_dev, phyno,
3819 MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
3823 * Poll link state until re(4) get a 10/100Mbps link.
3825 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
3827 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
3828 == (IFM_ACTIVE | IFM_AVALID)) {
3829 switch (IFM_SUBTYPE(mii->mii_media_active)) {
3841 if (i == MII_ANEGTICKS_GIGE)
3842 device_printf(sc->rl_dev,
3843 "establishing a link failed, WOL may not work!");
3846 * No link, force MAC to have 100Mbps, full-duplex link.
3847 * MAC does not require reprogramming on resolved speed/duplex,
3848 * so this is just for completeness.
3850 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
3851 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
3855 re_setwol(struct rl_softc *sc)
3864 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
3868 /* Put controller into sleep mode. */
3869 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
3870 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
3871 CSR_WRITE_1(sc, RL_GPIO,
3872 CSR_READ_1(sc, RL_GPIO) & ~0x01);
3874 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
3875 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) {
3876 /* Disable RXDV gate. */
3877 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) &
3881 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0)
3882 re_set_linkspeed(sc);
3883 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0)
3884 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB);
3886 /* Enable config register write. */
3887 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
3890 v = CSR_READ_1(sc, sc->rl_cfg1);
3892 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3894 CSR_WRITE_1(sc, sc->rl_cfg1, v);
3896 v = CSR_READ_1(sc, sc->rl_cfg3);
3897 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3898 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3899 v |= RL_CFG3_WOL_MAGIC;
3900 CSR_WRITE_1(sc, sc->rl_cfg3, v);
3902 v = CSR_READ_1(sc, sc->rl_cfg5);
3903 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST |
3904 RL_CFG5_WOL_LANWAKE);
3905 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
3906 v |= RL_CFG5_WOL_UCAST;
3907 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
3908 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
3909 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3910 v |= RL_CFG5_WOL_LANWAKE;
3911 CSR_WRITE_1(sc, sc->rl_cfg5, v);
3913 /* Config register write done. */
3914 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3916 if ((ifp->if_capenable & IFCAP_WOL) == 0 &&
3917 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0)
3918 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80);
3920 * It seems that hardware resets its link speed to 100Mbps in
3921 * power down mode so switching to 100Mbps in driver is not
3925 /* Request PME if WOL is requested. */
3926 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
3927 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3928 if ((ifp->if_capenable & IFCAP_WOL) != 0)
3929 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3930 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
3934 re_clrwol(struct rl_softc *sc)
3941 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
3944 /* Enable config register write. */
3945 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
3947 v = CSR_READ_1(sc, sc->rl_cfg3);
3948 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3949 CSR_WRITE_1(sc, sc->rl_cfg3, v);
3951 /* Config register write done. */
3952 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3954 v = CSR_READ_1(sc, sc->rl_cfg5);
3955 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
3956 v &= ~RL_CFG5_WOL_LANWAKE;
3957 CSR_WRITE_1(sc, sc->rl_cfg5, v);
3961 re_add_sysctls(struct rl_softc *sc)
3963 struct sysctl_ctx_list *ctx;
3964 struct sysctl_oid_list *children;
3967 ctx = device_get_sysctl_ctx(sc->rl_dev);
3968 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
3970 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats",
3971 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I",
3972 "Statistics Information");
3973 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0)
3976 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod",
3977 CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0,
3978 sysctl_hw_re_int_mod, "I", "re RX interrupt moderation");
3979 /* Pull in device tunables. */
3980 sc->rl_int_rx_mod = RL_TIMER_DEFAULT;
3981 error = resource_int_value(device_get_name(sc->rl_dev),
3982 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod);
3984 if (sc->rl_int_rx_mod < RL_TIMER_MIN ||
3985 sc->rl_int_rx_mod > RL_TIMER_MAX) {
3986 device_printf(sc->rl_dev, "int_rx_mod value out of "
3987 "range; using default: %d\n",
3989 sc->rl_int_rx_mod = RL_TIMER_DEFAULT;
3995 re_sysctl_stats(SYSCTL_HANDLER_ARGS)
3997 struct rl_softc *sc;
3998 struct rl_stats *stats;
3999 int error, i, result;
4002 error = sysctl_handle_int(oidp, &result, 0, req);
4003 if (error || req->newptr == NULL)
4007 sc = (struct rl_softc *)arg1;
4009 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
4013 bus_dmamap_sync(sc->rl_ldata.rl_stag,
4014 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD);
4015 CSR_WRITE_4(sc, RL_DUMPSTATS_HI,
4016 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr));
4017 CSR_WRITE_4(sc, RL_DUMPSTATS_LO,
4018 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr));
4019 CSR_WRITE_4(sc, RL_DUMPSTATS_LO,
4020 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr |
4021 RL_DUMPSTATS_START));
4022 for (i = RL_TIMEOUT; i > 0; i--) {
4023 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) &
4024 RL_DUMPSTATS_START) == 0)
4028 bus_dmamap_sync(sc->rl_ldata.rl_stag,
4029 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD);
4032 device_printf(sc->rl_dev,
4033 "DUMP statistics request timed out\n");
4037 stats = sc->rl_ldata.rl_stats;
4038 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev));
4039 printf("Tx frames : %ju\n",
4040 (uintmax_t)le64toh(stats->rl_tx_pkts));
4041 printf("Rx frames : %ju\n",
4042 (uintmax_t)le64toh(stats->rl_rx_pkts));
4043 printf("Tx errors : %ju\n",
4044 (uintmax_t)le64toh(stats->rl_tx_errs));
4045 printf("Rx errors : %u\n",
4046 le32toh(stats->rl_rx_errs));
4047 printf("Rx missed frames : %u\n",
4048 (uint32_t)le16toh(stats->rl_missed_pkts));
4049 printf("Rx frame alignment errs : %u\n",
4050 (uint32_t)le16toh(stats->rl_rx_framealign_errs));
4051 printf("Tx single collisions : %u\n",
4052 le32toh(stats->rl_tx_onecoll));
4053 printf("Tx multiple collisions : %u\n",
4054 le32toh(stats->rl_tx_multicolls));
4055 printf("Rx unicast frames : %ju\n",
4056 (uintmax_t)le64toh(stats->rl_rx_ucasts));
4057 printf("Rx broadcast frames : %ju\n",
4058 (uintmax_t)le64toh(stats->rl_rx_bcasts));
4059 printf("Rx multicast frames : %u\n",
4060 le32toh(stats->rl_rx_mcasts));
4061 printf("Tx aborts : %u\n",
4062 (uint32_t)le16toh(stats->rl_tx_aborts));
4063 printf("Tx underruns : %u\n",
4064 (uint32_t)le16toh(stats->rl_rx_underruns));
4071 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
4077 value = *(int *)arg1;
4078 error = sysctl_handle_int(oidp, &value, 0, req);
4079 if (error || req->newptr == NULL)
4081 if (value < low || value > high)
4083 *(int *)arg1 = value;
4089 sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS)
4092 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN,
4098 re_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize)
4100 struct rl_softc *sc;
4102 sc = if_getsoftc(ifp);
4104 *nrxr = sc->rl_ldata.rl_rx_desc_cnt;
4105 *ncl = NETDUMP_MAX_IN_FLIGHT;
4106 *clsize = (ifp->if_mtu > RL_MTU &&
4107 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) ? MJUM9BYTES : MCLBYTES;
4112 re_netdump_event(struct ifnet *ifp __unused, enum netdump_ev event __unused)
4117 re_netdump_transmit(struct ifnet *ifp, struct mbuf *m)
4119 struct rl_softc *sc;
4122 sc = if_getsoftc(ifp);
4123 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
4124 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
4127 error = re_encap(sc, &m);
4134 re_netdump_poll(struct ifnet *ifp, int count)
4136 struct rl_softc *sc;
4139 sc = if_getsoftc(ifp);
4140 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 ||
4141 (sc->rl_flags & RL_FLAG_LINK) == 0)
4145 error = re_rxeof(sc, NULL);
4146 if (error != 0 && error != EAGAIN)
4150 #endif /* NETDUMP */