2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
45 * This driver is designed to support RealTek's next generation of
46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
47 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S
50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
51 * with the older 8139 family, however it also supports a special
52 * C+ mode of operation that provides several new performance enhancing
53 * features. These include:
55 * o Descriptor based DMA mechanism. Each descriptor represents
56 * a single packet fragment. Data buffers may be aligned on
61 * o TCP/IP checksum offload for both RX and TX
63 * o High and normal priority transmit DMA rings
65 * o VLAN tag insertion and extraction
67 * o TCP large send (segmentation offload)
69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
70 * programming API is fairly straightforward. The RX filtering, EEPROM
71 * access and PHY access is the same as it is on the older 8139 series
74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
75 * same programming API and feature set as the 8139C+ with the following
76 * differences and additions:
82 * o GMII and TBI ports/registers for interfacing with copper
85 * o RX and TX DMA rings can have up to 1024 descriptors
86 * (the 8139C+ allows a maximum of 64)
88 * o Slight differences in register layout from the 8139C+
90 * The TX start and timer interrupt registers are at different locations
91 * on the 8169 than they are on the 8139C+. Also, the status word in the
92 * RX descriptor has a slightly different bit layout. The 8169 does not
93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
97 * (the 'S' stands for 'single-chip'). These devices have the same
98 * programming API as the older 8169, but also have some vendor-specific
99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
102 * This driver takes advantage of the RX and TX checksum offload and
103 * VLAN tag insertion/extraction features. It also implements TX
104 * interrupt moderation using the timer interrupt registers, which
105 * significantly reduces TX interrupt load. There is also support
106 * for jumbo frames, however the 8169/8169S/8110S can not transmit
107 * jumbo frames larger than 7440, so the max MTU possible with this
108 * driver is 7422 bytes.
111 #ifdef HAVE_KERNEL_OPTION_HEADERS
112 #include "opt_device_polling.h"
115 #include <sys/param.h>
116 #include <sys/endian.h>
117 #include <sys/systm.h>
118 #include <sys/sockio.h>
119 #include <sys/mbuf.h>
120 #include <sys/malloc.h>
121 #include <sys/module.h>
122 #include <sys/kernel.h>
123 #include <sys/socket.h>
126 #include <net/if_arp.h>
127 #include <net/ethernet.h>
128 #include <net/if_dl.h>
129 #include <net/if_media.h>
130 #include <net/if_types.h>
131 #include <net/if_vlan_var.h>
135 #include <machine/bus.h>
136 #include <machine/resource.h>
138 #include <sys/rman.h>
140 #include <dev/mii/mii.h>
141 #include <dev/mii/miivar.h>
143 #include <dev/pci/pcireg.h>
144 #include <dev/pci/pcivar.h>
146 MODULE_DEPEND(re, pci, 1, 1, 1);
147 MODULE_DEPEND(re, ether, 1, 1, 1);
148 MODULE_DEPEND(re, miibus, 1, 1, 1);
150 /* "device miibus" required. See GENERIC if you get errors here. */
151 #include "miibus_if.h"
154 * Default to using PIO access for this driver.
156 #define RE_USEIOSPACE
158 #include <pci/if_rlreg.h>
160 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
163 * Various supported device vendors/types and their names.
165 static struct rl_type re_devs[] = {
166 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S,
167 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
168 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS,
169 "RealTek 8139C+ 10/100BaseTX" },
170 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169,
171 "RealTek 8169 Gigabit Ethernet" },
172 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S,
173 "RealTek 8169S Single-chip Gigabit Ethernet" },
174 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169SB,
175 "RealTek 8169SB Single-chip Gigabit Ethernet" },
176 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S,
177 "RealTek 8110S Single-chip Gigabit Ethernet" },
178 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S,
179 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
180 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, RL_HWREV_8169S,
181 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" },
185 static struct rl_hwrev re_hwrevs[] = {
186 { RL_HWREV_8139, RL_8139, "" },
187 { RL_HWREV_8139A, RL_8139, "A" },
188 { RL_HWREV_8139AG, RL_8139, "A-G" },
189 { RL_HWREV_8139B, RL_8139, "B" },
190 { RL_HWREV_8130, RL_8139, "8130" },
191 { RL_HWREV_8139C, RL_8139, "C" },
192 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" },
193 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"},
194 { RL_HWREV_8169, RL_8169, "8169"},
195 { RL_HWREV_8169S, RL_8169, "8169S"},
196 { RL_HWREV_8169SB, RL_8169, "8169SB"},
197 { RL_HWREV_8110S, RL_8169, "8110S"},
198 { RL_HWREV_8100, RL_8139, "8100"},
199 { RL_HWREV_8101, RL_8139, "8101"},
203 static int re_probe (device_t);
204 static int re_attach (device_t);
205 static int re_detach (device_t);
207 static int re_encap (struct rl_softc *, struct mbuf **, int *);
209 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int);
210 static void re_dma_map_desc (void *, bus_dma_segment_t *, int,
212 static int re_allocmem (device_t, struct rl_softc *);
213 static int re_newbuf (struct rl_softc *, int, struct mbuf *);
214 static int re_rx_list_init (struct rl_softc *);
215 static int re_tx_list_init (struct rl_softc *);
217 static __inline void re_fixup_rx
220 static void re_rxeof (struct rl_softc *);
221 static void re_txeof (struct rl_softc *);
222 #ifdef DEVICE_POLLING
223 static void re_poll (struct ifnet *, enum poll_cmd, int);
224 static void re_poll_locked (struct ifnet *, enum poll_cmd, int);
226 static void re_intr (void *);
227 static void re_tick (void *);
228 static void re_start (struct ifnet *);
229 static void re_start_locked (struct ifnet *);
230 static int re_ioctl (struct ifnet *, u_long, caddr_t);
231 static void re_init (void *);
232 static void re_init_locked (struct rl_softc *);
233 static void re_stop (struct rl_softc *);
234 static void re_watchdog (struct ifnet *);
235 static int re_suspend (device_t);
236 static int re_resume (device_t);
237 static void re_shutdown (device_t);
238 static int re_ifmedia_upd (struct ifnet *);
239 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *);
241 static void re_eeprom_putbyte (struct rl_softc *, int);
242 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *);
243 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int, int);
244 static int re_gmii_readreg (device_t, int, int);
245 static int re_gmii_writereg (device_t, int, int, int);
247 static int re_miibus_readreg (device_t, int, int);
248 static int re_miibus_writereg (device_t, int, int, int);
249 static void re_miibus_statchg (device_t);
251 static void re_setmulti (struct rl_softc *);
252 static void re_reset (struct rl_softc *);
254 static int re_diag (struct rl_softc *);
257 #define RL_RES SYS_RES_IOPORT
258 #define RL_RID RL_PCI_LOIO
260 #define RL_RES SYS_RES_MEMORY
261 #define RL_RID RL_PCI_LOMEM
264 static device_method_t re_methods[] = {
265 /* Device interface */
266 DEVMETHOD(device_probe, re_probe),
267 DEVMETHOD(device_attach, re_attach),
268 DEVMETHOD(device_detach, re_detach),
269 DEVMETHOD(device_suspend, re_suspend),
270 DEVMETHOD(device_resume, re_resume),
271 DEVMETHOD(device_shutdown, re_shutdown),
274 DEVMETHOD(bus_print_child, bus_generic_print_child),
275 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
278 DEVMETHOD(miibus_readreg, re_miibus_readreg),
279 DEVMETHOD(miibus_writereg, re_miibus_writereg),
280 DEVMETHOD(miibus_statchg, re_miibus_statchg),
285 static driver_t re_driver = {
288 sizeof(struct rl_softc)
291 static devclass_t re_devclass;
293 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0);
294 DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0);
295 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
298 CSR_WRITE_1(sc, RL_EECMD, \
299 CSR_READ_1(sc, RL_EECMD) | x)
302 CSR_WRITE_1(sc, RL_EECMD, \
303 CSR_READ_1(sc, RL_EECMD) & ~x)
306 * Send a read command and address to the EEPROM, check for ACK.
309 re_eeprom_putbyte(sc, addr)
315 d = addr | sc->rl_eecmd_read;
318 * Feed in each bit and strobe the clock.
320 for (i = 0x400; i; i >>= 1) {
322 EE_SET(RL_EE_DATAIN);
324 EE_CLR(RL_EE_DATAIN);
335 * Read a word of data stored in the EEPROM at address 'addr.'
338 re_eeprom_getword(sc, addr, dest)
346 /* Enter EEPROM access mode. */
347 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
350 * Send address of word we want to read.
352 re_eeprom_putbyte(sc, addr);
354 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
357 * Start reading bits from EEPROM.
359 for (i = 0x8000; i; i >>= 1) {
362 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
368 /* Turn off EEPROM access mode. */
369 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
375 * Read a sequence of words from the EEPROM.
378 re_read_eeprom(sc, dest, off, cnt, swap)
386 u_int16_t word = 0, *ptr;
388 for (i = 0; i < cnt; i++) {
389 re_eeprom_getword(sc, off + i, &word);
390 ptr = (u_int16_t *)(dest + (i * 2));
399 re_gmii_readreg(dev, phy, reg)
410 sc = device_get_softc(dev);
412 /* Let the rgephy driver read the GMEDIASTAT register */
414 if (reg == RL_GMEDIASTAT) {
415 rval = CSR_READ_1(sc, RL_GMEDIASTAT);
419 CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
422 for (i = 0; i < RL_TIMEOUT; i++) {
423 rval = CSR_READ_4(sc, RL_PHYAR);
424 if (rval & RL_PHYAR_BUSY)
429 if (i == RL_TIMEOUT) {
430 if_printf(sc->rl_ifp, "PHY read failed\n");
434 return (rval & RL_PHYAR_PHYDATA);
438 re_gmii_writereg(dev, phy, reg, data)
446 sc = device_get_softc(dev);
448 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
449 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
452 for (i = 0; i < RL_TIMEOUT; i++) {
453 rval = CSR_READ_4(sc, RL_PHYAR);
454 if (!(rval & RL_PHYAR_BUSY))
459 if (i == RL_TIMEOUT) {
460 if_printf(sc->rl_ifp, "PHY write failed\n");
468 re_miibus_readreg(dev, phy, reg)
474 u_int16_t re8139_reg = 0;
476 sc = device_get_softc(dev);
478 if (sc->rl_type == RL_8169) {
479 rval = re_gmii_readreg(dev, phy, reg);
483 /* Pretend the internal PHY is only at address 0 */
489 re8139_reg = RL_BMCR;
492 re8139_reg = RL_BMSR;
495 re8139_reg = RL_ANAR;
498 re8139_reg = RL_ANER;
501 re8139_reg = RL_LPAR;
507 * Allow the rlphy driver to read the media status
508 * register. If we have a link partner which does not
509 * support NWAY, this is the register which will tell
510 * us the results of parallel detection.
513 rval = CSR_READ_1(sc, RL_MEDIASTAT);
516 if_printf(sc->rl_ifp, "bad phy register\n");
519 rval = CSR_READ_2(sc, re8139_reg);
524 re_miibus_writereg(dev, phy, reg, data)
529 u_int16_t re8139_reg = 0;
532 sc = device_get_softc(dev);
534 if (sc->rl_type == RL_8169) {
535 rval = re_gmii_writereg(dev, phy, reg, data);
539 /* Pretend the internal PHY is only at address 0 */
545 re8139_reg = RL_BMCR;
548 re8139_reg = RL_BMSR;
551 re8139_reg = RL_ANAR;
554 re8139_reg = RL_ANER;
557 re8139_reg = RL_LPAR;
564 if_printf(sc->rl_ifp, "bad phy register\n");
567 CSR_WRITE_2(sc, re8139_reg, data);
572 re_miibus_statchg(dev)
579 * Program the 64-bit multicast hash filter.
587 u_int32_t hashes[2] = { 0, 0 };
588 struct ifmultiaddr *ifma;
596 rxfilt = CSR_READ_4(sc, RL_RXCFG);
598 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
599 rxfilt |= RL_RXCFG_RX_MULTI;
600 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
601 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
602 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
606 /* first, zot all the existing hash bits */
607 CSR_WRITE_4(sc, RL_MAR0, 0);
608 CSR_WRITE_4(sc, RL_MAR4, 0);
610 /* now program new ones */
612 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
613 if (ifma->ifma_addr->sa_family != AF_LINK)
615 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
616 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
618 hashes[0] |= (1 << h);
620 hashes[1] |= (1 << (h - 32));
626 rxfilt |= RL_RXCFG_RX_MULTI;
628 rxfilt &= ~RL_RXCFG_RX_MULTI;
630 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
631 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
632 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
643 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
645 for (i = 0; i < RL_TIMEOUT; i++) {
647 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
651 if_printf(sc->rl_ifp, "reset never completed!\n");
653 CSR_WRITE_1(sc, 0x82, 1);
657 * The following routine is designed to test for a defect on some
658 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
659 * lines connected to the bus, however for a 32-bit only card, they
660 * should be pulled high. The result of this defect is that the
661 * NIC will not work right if you plug it into a 64-bit slot: DMA
662 * operations will be done with 64-bit transfers, which will fail
663 * because the 64-bit data lines aren't connected.
665 * There's no way to work around this (short of talking a soldering
666 * iron to the board), however we can detect it. The method we use
667 * here is to put the NIC into digital loopback mode, set the receiver
668 * to promiscuous mode, and then try to send a frame. We then compare
669 * the frame data we sent to what was received. If the data matches,
670 * then the NIC is working correctly, otherwise we know the user has
671 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
672 * slot. In the latter case, there's no way the NIC can work correctly,
673 * so we print out a message on the console and abort the device attach.
680 struct ifnet *ifp = sc->rl_ifp;
682 struct ether_header *eh;
683 struct rl_desc *cur_rx;
686 int total_len, i, error = 0;
687 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
688 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
690 /* Allocate a single mbuf */
691 MGETHDR(m0, M_DONTWAIT, MT_DATA);
698 * Initialize the NIC in test mode. This sets the chip up
699 * so that it can send and receive frames, but performs the
700 * following special functions:
701 * - Puts receiver in promiscuous mode
702 * - Enables digital loopback mode
703 * - Leaves interrupts turned off
706 ifp->if_flags |= IFF_PROMISC;
713 /* Put some data in the mbuf */
715 eh = mtod(m0, struct ether_header *);
716 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
717 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
718 eh->ether_type = htons(ETHERTYPE_IP);
719 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
722 * Queue the packet, start transmission.
723 * Note: IF_HANDOFF() ultimately calls re_start() for us.
726 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
728 /* XXX: re_diag must not be called when in ALTQ mode */
729 IF_HANDOFF(&ifp->if_snd, m0, ifp);
733 /* Wait for it to propagate through the chip */
736 for (i = 0; i < RL_TIMEOUT; i++) {
737 status = CSR_READ_2(sc, RL_ISR);
738 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
739 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
744 if (i == RL_TIMEOUT) {
745 if_printf(ifp, "diagnostic failed, failed to receive packet "
746 "in loopback mode\n");
752 * The packet should have been dumped into the first
753 * entry in the RX DMA ring. Grab it from there.
756 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
757 sc->rl_ldata.rl_rx_list_map,
758 BUS_DMASYNC_POSTREAD);
759 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
760 sc->rl_ldata.rl_rx_dmamap[0],
761 BUS_DMASYNC_POSTWRITE);
762 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
763 sc->rl_ldata.rl_rx_dmamap[0]);
765 m0 = sc->rl_ldata.rl_rx_mbuf[0];
766 sc->rl_ldata.rl_rx_mbuf[0] = NULL;
767 eh = mtod(m0, struct ether_header *);
769 cur_rx = &sc->rl_ldata.rl_rx_list[0];
770 total_len = RL_RXBYTES(cur_rx);
771 rxstat = le32toh(cur_rx->rl_cmdstat);
773 if (total_len != ETHER_MIN_LEN) {
774 if_printf(ifp, "diagnostic failed, received short packet\n");
779 /* Test that the received packet data matches what we sent. */
781 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
782 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
783 ntohs(eh->ether_type) != ETHERTYPE_IP) {
784 if_printf(ifp, "WARNING, DMA FAILURE!\n");
785 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
786 dst, ":", src, ":", ETHERTYPE_IP);
787 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
788 eh->ether_dhost, ":", eh->ether_shost, ":",
789 ntohs(eh->ether_type));
790 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
791 "into a 64-bit PCI slot.\n");
792 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
793 "for proper operation.\n");
794 if_printf(ifp, "Read the re(4) man page for more details.\n");
799 /* Turn interface off, release resources */
802 ifp->if_flags &= ~IFF_PROMISC;
813 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
814 * IDs against our list and return a device name if we find a match.
826 sc = device_get_softc(dev);
828 while (t->rl_name != NULL) {
829 if ((pci_get_vendor(dev) == t->rl_vid) &&
830 (pci_get_device(dev) == t->rl_did)) {
832 * Only attach to rev. 3 of the Linksys EG1032 adapter.
833 * Rev. 2 i supported by sk(4).
835 if ((t->rl_vid == LINKSYS_VENDORID) &&
836 (t->rl_did == LINKSYS_DEVICEID_EG1032) &&
837 (pci_get_subdevice(dev) !=
838 LINKSYS_SUBDEVICE_EG1032_REV3)) {
844 * Temporarily map the I/O space
845 * so we can read the chip ID register.
848 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
850 if (sc->rl_res == NULL) {
852 "couldn't map ports/memory\n");
855 sc->rl_btag = rman_get_bustag(sc->rl_res);
856 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
857 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
858 bus_release_resource(dev, RL_RES,
860 if (t->rl_basetype == hwrev) {
861 device_set_desc(dev, t->rl_name);
862 return (BUS_PROBE_DEFAULT);
872 * This routine takes the segment list provided as the result of
873 * a bus_dma_map_load() operation and assigns the addresses/lengths
874 * to RealTek DMA descriptors. This can be called either by the RX
875 * code or the TX code. In the RX case, we'll probably wind up mapping
876 * at most one segment. For the TX case, there could be any number of
877 * segments since TX packets may span multiple mbufs. In either case,
878 * if the number of segments is larger than the rl_maxsegs limit
879 * specified by the caller, we abort the mapping operation. Sadly,
880 * whoever designed the buffer mapping API did not provide a way to
881 * return an error from here, so we have to fake it a bit.
885 re_dma_map_desc(arg, segs, nseg, mapsize, error)
887 bus_dma_segment_t *segs;
892 struct rl_dmaload_arg *ctx;
893 struct rl_desc *d = NULL;
901 /* Signal error to caller if there's too many segments */
902 if (nseg > ctx->rl_maxsegs) {
908 * Map the segment array into descriptors. Note that we set the
909 * start-of-frame and end-of-frame markers for either TX or RX, but
910 * they really only have meaning in the TX case. (In the RX case,
911 * it's the chip that tells us where packets begin and end.)
912 * We also keep track of the end of the ring and set the
913 * end-of-ring bits as needed, and we set the ownership bits
914 * in all except the very first descriptor. (The caller will
915 * set this descriptor later when it start transmission or
921 d = &ctx->rl_ring[idx];
922 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) {
926 cmdstat = segs[i].ds_len;
927 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
928 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
930 cmdstat |= RL_TDESC_CMD_SOF;
932 cmdstat |= RL_TDESC_CMD_OWN;
933 if (idx == (RL_RX_DESC_CNT - 1))
934 cmdstat |= RL_TDESC_CMD_EOR;
935 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags);
942 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
943 ctx->rl_maxsegs = nseg;
948 * Map a single buffer address.
952 re_dma_map_addr(arg, segs, nseg, error)
954 bus_dma_segment_t *segs;
963 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
965 *addr = segs->ds_addr;
978 * Allocate map for RX mbufs.
981 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0,
982 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
983 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW,
984 NULL, NULL, &sc->rl_ldata.rl_mtag);
986 device_printf(dev, "could not allocate dma tag\n");
991 * Allocate map for TX descriptor list.
993 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
994 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
995 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
996 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag);
998 device_printf(dev, "could not allocate dma tag\n");
1002 /* Allocate DMA'able memory for the TX ring */
1004 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
1005 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1006 &sc->rl_ldata.rl_tx_list_map);
1010 /* Load the map for the TX ring. */
1012 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
1013 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
1014 RL_TX_LIST_SZ, re_dma_map_addr,
1015 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT);
1017 /* Create DMA maps for TX buffers */
1019 for (i = 0; i < RL_TX_DESC_CNT; i++) {
1020 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0,
1021 &sc->rl_ldata.rl_tx_dmamap[i]);
1023 device_printf(dev, "can't create DMA map for TX\n");
1029 * Allocate map for RX descriptor list.
1031 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1032 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1033 NULL, RL_RX_LIST_SZ, 1, RL_RX_LIST_SZ, BUS_DMA_ALLOCNOW,
1034 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag);
1036 device_printf(dev, "could not allocate dma tag\n");
1040 /* Allocate DMA'able memory for the RX ring */
1042 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag,
1043 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1044 &sc->rl_ldata.rl_rx_list_map);
1048 /* Load the map for the RX ring. */
1050 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag,
1051 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
1052 RL_RX_LIST_SZ, re_dma_map_addr,
1053 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT);
1055 /* Create DMA maps for RX buffers */
1057 for (i = 0; i < RL_RX_DESC_CNT; i++) {
1058 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0,
1059 &sc->rl_ldata.rl_rx_dmamap[i]);
1061 device_printf(dev, "can't create DMA map for RX\n");
1070 * Attach the interface. Allocate softc structures, do ifmedia
1071 * setup and ethernet/BPF attach.
1077 u_char eaddr[ETHER_ADDR_LEN];
1079 struct rl_softc *sc;
1081 struct rl_hwrev *hw_rev;
1083 u_int16_t re_did = 0;
1084 int error = 0, rid, i;
1086 sc = device_get_softc(dev);
1088 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1090 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
1093 * Map control/status registers.
1095 pci_enable_busmaster(dev);
1098 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
1101 if (sc->rl_res == NULL) {
1102 device_printf(dev, "couldn't map ports/memory\n");
1107 sc->rl_btag = rman_get_bustag(sc->rl_res);
1108 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
1110 /* Allocate interrupt */
1112 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1113 RF_SHAREABLE | RF_ACTIVE);
1115 if (sc->rl_irq == NULL) {
1116 device_printf(dev, "couldn't map interrupt\n");
1121 /* Reset the adapter. */
1127 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
1128 while (hw_rev->rl_desc != NULL) {
1129 if (hw_rev->rl_rev == hwrev) {
1130 sc->rl_type = hw_rev->rl_type;
1136 if (sc->rl_type == RL_8169) {
1138 /* Set RX length mask */
1140 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
1142 /* Force station address autoload from the EEPROM */
1144 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_AUTOLOAD);
1145 for (i = 0; i < RL_TIMEOUT; i++) {
1146 if (!(CSR_READ_1(sc, RL_EECMD) & RL_EEMODE_AUTOLOAD))
1150 if (i == RL_TIMEOUT)
1151 device_printf(dev, "eeprom autoload timed out\n");
1153 for (i = 0; i < ETHER_ADDR_LEN; i++)
1154 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
1157 /* Set RX length mask */
1159 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
1161 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
1162 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0);
1163 if (re_did != 0x8129)
1164 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
1167 * Get station address from the EEPROM.
1169 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0);
1170 for (i = 0; i < 3; i++) {
1171 eaddr[(i * 2) + 0] = as[i] & 0xff;
1172 eaddr[(i * 2) + 1] = as[i] >> 8;
1177 * Allocate the parent bus DMA tag appropriate for PCI.
1179 #define RL_NSEG_NEW 32
1180 error = bus_dma_tag_create(NULL, /* parent */
1181 1, 0, /* alignment, boundary */
1182 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1183 BUS_SPACE_MAXADDR, /* highaddr */
1184 NULL, NULL, /* filter, filterarg */
1185 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
1186 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1187 BUS_DMA_ALLOCNOW, /* flags */
1188 NULL, NULL, /* lockfunc, lockarg */
1189 &sc->rl_parent_tag);
1193 error = re_allocmem(dev, sc);
1198 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
1200 device_printf(dev, "can not if_alloc()\n");
1206 if (mii_phy_probe(dev, &sc->rl_miibus,
1207 re_ifmedia_upd, re_ifmedia_sts)) {
1208 device_printf(dev, "MII without any phy!\n");
1214 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1215 ifp->if_mtu = ETHERMTU;
1216 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1217 ifp->if_ioctl = re_ioctl;
1218 ifp->if_capabilities = IFCAP_VLAN_MTU;
1219 ifp->if_start = re_start;
1220 ifp->if_hwassist = /*RE_CSUM_FEATURES*/0;
1221 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1222 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1223 #ifdef DEVICE_POLLING
1224 ifp->if_capabilities |= IFCAP_POLLING;
1226 ifp->if_watchdog = re_watchdog;
1227 ifp->if_init = re_init;
1228 if (sc->rl_type == RL_8169)
1229 ifp->if_baudrate = 1000000000;
1231 ifp->if_baudrate = 100000000;
1232 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
1233 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN;
1234 IFQ_SET_READY(&ifp->if_snd);
1237 * Call MI attach routine.
1239 ether_ifattach(ifp, eaddr);
1241 /* Perform hardware diagnostic. */
1242 error = re_diag(sc);
1245 device_printf(dev, "attach aborted due to hardware diag failure\n");
1246 ether_ifdetach(ifp);
1250 /* Hook interrupt last to avoid having to lock softc */
1251 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1252 re_intr, sc, &sc->rl_intrhand);
1254 device_printf(dev, "couldn't set up irq\n");
1255 ether_ifdetach(ifp);
1266 * Shutdown hardware and free up resources. This can be called any
1267 * time after the mutex has been initialized. It is called in both
1268 * the error case in attach and the normal detach case so it needs
1269 * to be careful about only freeing resources that have actually been
1276 struct rl_softc *sc;
1280 sc = device_get_softc(dev);
1282 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized"));
1284 #ifdef DEVICE_POLLING
1285 if (ifp->if_capenable & IFCAP_POLLING)
1286 ether_poll_deregister(ifp);
1289 /* These should only be active if attach succeeded */
1290 if (device_is_attached(dev)) {
1297 callout_drain(&sc->rl_stat_callout);
1299 * Force off the IFF_UP flag here, in case someone
1300 * still had a BPF descriptor attached to this
1301 * interface. If they do, ether_ifdetach() will cause
1302 * the BPF code to try and clear the promisc mode
1303 * flag, which will bubble down to re_ioctl(),
1304 * which will try to call re_init() again. This will
1305 * turn the NIC back on and restart the MII ticker,
1306 * which will panic the system when the kernel tries
1307 * to invoke the re_tick() function that isn't there
1310 ifp->if_flags &= ~IFF_UP;
1311 ether_ifdetach(ifp);
1314 device_delete_child(dev, sc->rl_miibus);
1315 bus_generic_detach(dev);
1318 * The rest is resource deallocation, so we should already be
1322 if (sc->rl_intrhand)
1323 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1327 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1329 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1332 /* Unload and free the RX DMA ring memory and map */
1334 if (sc->rl_ldata.rl_rx_list_tag) {
1335 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag,
1336 sc->rl_ldata.rl_rx_list_map);
1337 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag,
1338 sc->rl_ldata.rl_rx_list,
1339 sc->rl_ldata.rl_rx_list_map);
1340 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag);
1343 /* Unload and free the TX DMA ring memory and map */
1345 if (sc->rl_ldata.rl_tx_list_tag) {
1346 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag,
1347 sc->rl_ldata.rl_tx_list_map);
1348 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag,
1349 sc->rl_ldata.rl_tx_list,
1350 sc->rl_ldata.rl_tx_list_map);
1351 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag);
1354 /* Destroy all the RX and TX buffer maps */
1356 if (sc->rl_ldata.rl_mtag) {
1357 for (i = 0; i < RL_TX_DESC_CNT; i++)
1358 bus_dmamap_destroy(sc->rl_ldata.rl_mtag,
1359 sc->rl_ldata.rl_tx_dmamap[i]);
1360 for (i = 0; i < RL_RX_DESC_CNT; i++)
1361 bus_dmamap_destroy(sc->rl_ldata.rl_mtag,
1362 sc->rl_ldata.rl_rx_dmamap[i]);
1363 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag);
1366 /* Unload and free the stats buffer and map */
1368 if (sc->rl_ldata.rl_stag) {
1369 bus_dmamap_unload(sc->rl_ldata.rl_stag,
1370 sc->rl_ldata.rl_rx_list_map);
1371 bus_dmamem_free(sc->rl_ldata.rl_stag,
1372 sc->rl_ldata.rl_stats,
1373 sc->rl_ldata.rl_smap);
1374 bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1377 if (sc->rl_parent_tag)
1378 bus_dma_tag_destroy(sc->rl_parent_tag);
1380 mtx_destroy(&sc->rl_mtx);
1386 re_newbuf(sc, idx, m)
1387 struct rl_softc *sc;
1391 struct rl_dmaload_arg arg;
1392 struct mbuf *n = NULL;
1396 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1401 m->m_data = m->m_ext.ext_buf;
1403 m->m_len = m->m_pkthdr.len = MCLBYTES;
1406 * This is part of an evil trick to deal with non-x86 platforms.
1407 * The RealTek chip requires RX buffers to be aligned on 64-bit
1408 * boundaries, but that will hose non-x86 machines. To get around
1409 * this, we leave some empty space at the start of each buffer
1410 * and for non-x86 hosts, we copy the buffer back six bytes
1411 * to achieve word alignment. This is slightly more efficient
1412 * than allocating a new buffer, copying the contents, and
1413 * discarding the old buffer.
1415 m_adj(m, RE_ETHER_ALIGN);
1421 arg.rl_ring = sc->rl_ldata.rl_rx_list;
1423 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag,
1424 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc,
1425 &arg, BUS_DMA_NOWAIT);
1426 if (error || arg.rl_maxsegs != 1) {
1432 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN);
1433 sc->rl_ldata.rl_rx_mbuf[idx] = m;
1435 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
1436 sc->rl_ldata.rl_rx_dmamap[idx],
1437 BUS_DMASYNC_PREREAD);
1443 static __inline void
1448 uint16_t *src, *dst;
1450 src = mtod(m, uint16_t *);
1451 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src;
1453 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1456 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN;
1464 struct rl_softc *sc;
1469 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ);
1470 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf,
1471 (RL_TX_DESC_CNT * sizeof(struct mbuf *)));
1473 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
1474 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE);
1475 sc->rl_ldata.rl_tx_prodidx = 0;
1476 sc->rl_ldata.rl_tx_considx = 0;
1477 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT;
1484 struct rl_softc *sc;
1488 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ);
1489 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf,
1490 (RL_RX_DESC_CNT * sizeof(struct mbuf *)));
1492 for (i = 0; i < RL_RX_DESC_CNT; i++) {
1493 if (re_newbuf(sc, i, NULL) == ENOBUFS)
1497 /* Flush the RX descriptors */
1499 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1500 sc->rl_ldata.rl_rx_list_map,
1501 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1503 sc->rl_ldata.rl_rx_prodidx = 0;
1504 sc->rl_head = sc->rl_tail = NULL;
1510 * RX handler for C+ and 8169. For the gigE chips, we support
1511 * the reception of jumbo frames that have been fragmented
1512 * across multiple 2K mbuf cluster buffers.
1516 struct rl_softc *sc;
1521 struct rl_desc *cur_rx;
1522 u_int32_t rxstat, rxvlan;
1527 i = sc->rl_ldata.rl_rx_prodidx;
1529 /* Invalidate the descriptor memory */
1531 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1532 sc->rl_ldata.rl_rx_list_map,
1533 BUS_DMASYNC_POSTREAD);
1535 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) {
1536 cur_rx = &sc->rl_ldata.rl_rx_list[i];
1537 m = sc->rl_ldata.rl_rx_mbuf[i];
1538 total_len = RL_RXBYTES(cur_rx);
1539 rxstat = le32toh(cur_rx->rl_cmdstat);
1540 rxvlan = le32toh(cur_rx->rl_vlanctl);
1542 /* Invalidate the RX mbuf and unload its map */
1544 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
1545 sc->rl_ldata.rl_rx_dmamap[i],
1546 BUS_DMASYNC_POSTWRITE);
1547 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
1548 sc->rl_ldata.rl_rx_dmamap[i]);
1550 if (!(rxstat & RL_RDESC_STAT_EOF)) {
1551 m->m_len = RE_RX_DESC_BUFLEN;
1552 if (sc->rl_head == NULL)
1553 sc->rl_head = sc->rl_tail = m;
1555 m->m_flags &= ~M_PKTHDR;
1556 sc->rl_tail->m_next = m;
1559 re_newbuf(sc, i, NULL);
1565 * NOTE: for the 8139C+, the frame length field
1566 * is always 12 bits in size, but for the gigE chips,
1567 * it is 13 bits (since the max RX frame length is 16K).
1568 * Unfortunately, all 32 bits in the status word
1569 * were already used, so to make room for the extra
1570 * length bit, RealTek took out the 'frame alignment
1571 * error' bit and shifted the other status bits
1572 * over one slot. The OWN, EOR, FS and LS bits are
1573 * still in the same places. We have already extracted
1574 * the frame length and checked the OWN bit, so rather
1575 * than using an alternate bit mapping, we shift the
1576 * status bits one space to the right so we can evaluate
1577 * them using the 8169 status as though it was in the
1578 * same format as that of the 8139C+.
1580 if (sc->rl_type == RL_8169)
1584 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be
1585 * set, but if CRC is clear, it will still be a valid frame.
1587 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 &&
1588 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) {
1591 * If this is part of a multi-fragment packet,
1592 * discard all the pieces.
1594 if (sc->rl_head != NULL) {
1595 m_freem(sc->rl_head);
1596 sc->rl_head = sc->rl_tail = NULL;
1598 re_newbuf(sc, i, m);
1604 * If allocating a replacement mbuf fails,
1605 * reload the current one.
1608 if (re_newbuf(sc, i, NULL)) {
1610 if (sc->rl_head != NULL) {
1611 m_freem(sc->rl_head);
1612 sc->rl_head = sc->rl_tail = NULL;
1614 re_newbuf(sc, i, m);
1621 if (sc->rl_head != NULL) {
1622 m->m_len = total_len % RE_RX_DESC_BUFLEN;
1624 m->m_len = RE_RX_DESC_BUFLEN;
1626 * Special case: if there's 4 bytes or less
1627 * in this buffer, the mbuf can be discarded:
1628 * the last 4 bytes is the CRC, which we don't
1629 * care about anyway.
1631 if (m->m_len <= ETHER_CRC_LEN) {
1632 sc->rl_tail->m_len -=
1633 (ETHER_CRC_LEN - m->m_len);
1636 m->m_len -= ETHER_CRC_LEN;
1637 m->m_flags &= ~M_PKTHDR;
1638 sc->rl_tail->m_next = m;
1641 sc->rl_head = sc->rl_tail = NULL;
1642 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1644 m->m_pkthdr.len = m->m_len =
1645 (total_len - ETHER_CRC_LEN);
1651 m->m_pkthdr.rcvif = ifp;
1653 /* Do RX checksumming if enabled */
1655 if (ifp->if_capenable & IFCAP_RXCSUM) {
1657 /* Check IP header checksum */
1658 if (rxstat & RL_RDESC_STAT_PROTOID)
1659 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1660 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
1661 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1663 /* Check TCP/UDP checksum */
1664 if ((RL_TCPPKT(rxstat) &&
1665 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
1666 (RL_UDPPKT(rxstat) &&
1667 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
1668 m->m_pkthdr.csum_flags |=
1669 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1670 m->m_pkthdr.csum_data = 0xffff;
1674 if (rxvlan & RL_RDESC_VLANCTL_TAG)
1675 VLAN_INPUT_TAG(ifp, m,
1676 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)), continue);
1678 (*ifp->if_input)(ifp, m);
1682 /* Flush the RX DMA ring */
1684 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1685 sc->rl_ldata.rl_rx_list_map,
1686 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1688 sc->rl_ldata.rl_rx_prodidx = i;
1693 struct rl_softc *sc;
1700 idx = sc->rl_ldata.rl_tx_considx;
1702 /* Invalidate the TX descriptor list */
1704 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
1705 sc->rl_ldata.rl_tx_list_map,
1706 BUS_DMASYNC_POSTREAD);
1708 while (idx != sc->rl_ldata.rl_tx_prodidx) {
1710 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat);
1711 if (txstat & RL_TDESC_CMD_OWN)
1715 * We only stash mbufs in the last descriptor
1716 * in a fragment chain, which also happens to
1717 * be the only place where the TX status bits
1721 if (txstat & RL_TDESC_CMD_EOF) {
1722 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]);
1723 sc->rl_ldata.rl_tx_mbuf[idx] = NULL;
1724 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
1725 sc->rl_ldata.rl_tx_dmamap[idx]);
1726 if (txstat & (RL_TDESC_STAT_EXCESSCOL|
1727 RL_TDESC_STAT_COLCNT))
1728 ifp->if_collisions++;
1729 if (txstat & RL_TDESC_STAT_TXERRSUM)
1734 sc->rl_ldata.rl_tx_free++;
1738 /* No changes made to the TX ring, so no flush needed */
1740 if (idx != sc->rl_ldata.rl_tx_considx) {
1741 sc->rl_ldata.rl_tx_considx = idx;
1742 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1747 * If not all descriptors have been released reaped yet,
1748 * reload the timer so that we will eventually get another
1749 * interrupt that will cause us to re-enter this routine.
1750 * This is done in case the transmitter has gone idle.
1752 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT)
1753 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
1760 struct rl_softc *sc;
1761 struct mii_data *mii;
1767 mii = device_get_softc(sc->rl_miibus);
1771 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
1774 #ifdef DEVICE_POLLING
1776 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1778 struct rl_softc *sc = ifp->if_softc;
1781 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1782 re_poll_locked(ifp, cmd, count);
1787 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1789 struct rl_softc *sc = ifp->if_softc;
1793 sc->rxcycles = count;
1797 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1798 re_start_locked(ifp);
1800 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1803 status = CSR_READ_2(sc, RL_ISR);
1804 if (status == 0xffff)
1807 CSR_WRITE_2(sc, RL_ISR, status);
1810 * XXX check behaviour on receiver stalls.
1813 if (status & RL_ISR_SYSTEM_ERR) {
1819 #endif /* DEVICE_POLLING */
1825 struct rl_softc *sc;
1835 if (sc->suspended || !(ifp->if_flags & IFF_UP))
1838 #ifdef DEVICE_POLLING
1839 if (ifp->if_capenable & IFCAP_POLLING)
1845 status = CSR_READ_2(sc, RL_ISR);
1846 /* If the card has gone away the read returns 0xffff. */
1847 if (status == 0xffff)
1850 CSR_WRITE_2(sc, RL_ISR, status);
1852 if ((status & RL_INTRS_CPLUS) == 0)
1855 if ((status & RL_ISR_RX_OK) ||
1856 (status & RL_ISR_RX_ERR))
1859 if ((status & RL_ISR_TIMEOUT_EXPIRED) ||
1860 (status & RL_ISR_TX_ERR) ||
1861 (status & RL_ISR_TX_DESC_UNAVAIL))
1864 if (status & RL_ISR_SYSTEM_ERR) {
1869 if (status & RL_ISR_LINKCHG) {
1870 callout_stop(&sc->rl_stat_callout);
1875 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1876 re_start_locked(ifp);
1883 re_encap(sc, m_head, idx)
1884 struct rl_softc *sc;
1885 struct mbuf **m_head;
1888 struct mbuf *m_new = NULL;
1889 struct rl_dmaload_arg arg;
1896 if (sc->rl_ldata.rl_tx_free <= 4)
1900 * Set up checksum offload. Note: checksum offload bits must
1901 * appear in all descriptors of a multi-descriptor transmit
1902 * attempt. This is according to testing done with an 8169
1903 * chip. This is a requirement.
1908 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP)
1909 arg.rl_flags |= RL_TDESC_CMD_IPCSUM;
1910 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP)
1911 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM;
1912 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP)
1913 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM;
1917 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free;
1918 if (arg.rl_maxsegs > 4)
1919 arg.rl_maxsegs -= 4;
1920 arg.rl_ring = sc->rl_ldata.rl_tx_list;
1922 map = sc->rl_ldata.rl_tx_dmamap[*idx];
1923 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map,
1924 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1926 if (error && error != EFBIG) {
1927 if_printf(sc->rl_ifp, "can't map mbuf (error %d)\n", error);
1931 /* Too many segments to map, coalesce into a single mbuf */
1933 if (error || arg.rl_maxsegs == 0) {
1934 m_new = m_defrag(*m_head, M_DONTWAIT);
1942 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free;
1943 arg.rl_ring = sc->rl_ldata.rl_tx_list;
1945 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map,
1946 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1948 if_printf(sc->rl_ifp, "can't map mbuf (error %d)\n",
1955 * Insure that the map for this transmission
1956 * is placed at the array index of the last descriptor
1957 * in this chain. (Swap last and first dmamaps.)
1959 sc->rl_ldata.rl_tx_dmamap[*idx] =
1960 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx];
1961 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map;
1963 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = *m_head;
1964 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs;
1967 * Set up hardware VLAN tagging. Note: vlan tag info must
1968 * appear in the first descriptor of a multi-descriptor
1969 * transmission attempt.
1972 mtag = VLAN_OUTPUT_TAG(sc->rl_ifp, *m_head);
1974 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl =
1975 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG);
1977 /* Transfer ownership of packet to the chip. */
1979 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |=
1980 htole32(RL_TDESC_CMD_OWN);
1981 if (*idx != arg.rl_idx)
1982 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |=
1983 htole32(RL_TDESC_CMD_OWN);
1985 RL_DESC_INC(arg.rl_idx);
1995 struct rl_softc *sc;
1999 re_start_locked(ifp);
2004 * Main transmit routine for C+ and gigE NICs.
2007 re_start_locked(ifp)
2010 struct rl_softc *sc;
2011 struct mbuf *m_head = NULL;
2012 int idx, queued = 0;
2018 idx = sc->rl_ldata.rl_tx_prodidx;
2020 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) {
2021 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2025 if (re_encap(sc, &m_head, &idx)) {
2026 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2027 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2032 * If there's a BPF listener, bounce a copy of this frame
2035 BPF_MTAP(ifp, m_head);
2043 /* Flush the TX descriptors */
2045 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2046 sc->rl_ldata.rl_tx_list_map,
2047 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2049 sc->rl_ldata.rl_tx_prodidx = idx;
2052 * RealTek put the TX poll request register in a different
2053 * location on the 8169 gigE chip. I don't know why.
2056 if (sc->rl_type == RL_8169)
2057 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START);
2059 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START);
2062 * Use the countdown timer for interrupt moderation.
2063 * 'TX done' interrupts are disabled. Instead, we reset the
2064 * countdown timer, which will begin counting until it hits
2065 * the value in the TIMERINT register, and then trigger an
2066 * interrupt. Each time we write to the TIMERCNT register,
2067 * the timer count is reset to 0.
2069 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2072 * Set a timeout in case the chip goes out to lunch.
2081 struct rl_softc *sc = xsc;
2090 struct rl_softc *sc;
2092 struct ifnet *ifp = sc->rl_ifp;
2093 struct mii_data *mii;
2094 u_int32_t rxcfg = 0;
2098 mii = device_get_softc(sc->rl_miibus);
2101 * Cancel pending I/O and free all RX/TX buffers.
2106 * Enable C+ RX and TX mode, as well as VLAN stripping and
2107 * RX checksum offload. We must configure the C+ register
2108 * before all others.
2110 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB|
2111 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW|
2112 RL_CPLUSCMD_VLANSTRIP|
2113 (ifp->if_capenable & IFCAP_RXCSUM ?
2114 RL_CPLUSCMD_RXCSUM_ENB : 0));
2117 * Init our MAC address. Even though the chipset
2118 * documentation doesn't mention it, we need to enter "Config
2119 * register write enable" mode to modify the ID registers.
2121 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
2122 CSR_WRITE_STREAM_4(sc, RL_IDR0,
2123 *(u_int32_t *)(&IFP2ENADDR(sc->rl_ifp)[0]));
2124 CSR_WRITE_STREAM_4(sc, RL_IDR4,
2125 *(u_int32_t *)(&IFP2ENADDR(sc->rl_ifp)[4]));
2126 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2129 * For C+ mode, initialize the RX descriptors and mbufs.
2131 re_rx_list_init(sc);
2132 re_tx_list_init(sc);
2135 * Enable transmit and receive.
2137 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2140 * Set the initial TX and RX configuration.
2142 if (sc->rl_testmode) {
2143 if (sc->rl_type == RL_8169)
2144 CSR_WRITE_4(sc, RL_TXCFG,
2145 RL_TXCFG_CONFIG|RL_LOOPTEST_ON);
2147 CSR_WRITE_4(sc, RL_TXCFG,
2148 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
2150 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
2151 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
2153 /* Set the individual bit to receive frames for this host only. */
2154 rxcfg = CSR_READ_4(sc, RL_RXCFG);
2155 rxcfg |= RL_RXCFG_RX_INDIV;
2157 /* If we want promiscuous mode, set the allframes bit. */
2158 if (ifp->if_flags & IFF_PROMISC)
2159 rxcfg |= RL_RXCFG_RX_ALLPHYS;
2161 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
2162 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
2165 * Set capture broadcast bit to capture broadcast frames.
2167 if (ifp->if_flags & IFF_BROADCAST)
2168 rxcfg |= RL_RXCFG_RX_BROAD;
2170 rxcfg &= ~RL_RXCFG_RX_BROAD;
2171 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
2174 * Program the multicast filter, if necessary.
2178 #ifdef DEVICE_POLLING
2180 * Disable interrupts if we are polling.
2182 if (ifp->if_capenable & IFCAP_POLLING)
2183 CSR_WRITE_2(sc, RL_IMR, 0);
2184 else /* otherwise ... */
2187 * Enable interrupts.
2189 if (sc->rl_testmode)
2190 CSR_WRITE_2(sc, RL_IMR, 0);
2192 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2194 /* Set initial TX threshold */
2195 sc->rl_txthresh = RL_TX_THRESH_INIT;
2197 /* Start RX/TX process. */
2198 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
2200 /* Enable receiver and transmitter. */
2201 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2204 * Load the addresses of the RX and TX lists into the chip.
2207 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
2208 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
2209 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
2210 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
2212 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
2213 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
2214 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
2215 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
2217 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
2220 * Initialize the timer interrupt register so that
2221 * a timer interrupt will be generated once the timer
2222 * reaches a certain number of ticks. The timer is
2223 * reloaded on each transmit. This gives us TX interrupt
2224 * moderation, which dramatically improves TX frame rate.
2226 if (sc->rl_type == RL_8169)
2227 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
2229 CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
2232 * For 8169 gigE NICs, set the max allowed RX packet
2233 * size so we can receive jumbo frames.
2235 if (sc->rl_type == RL_8169)
2236 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
2238 if (sc->rl_testmode)
2243 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
2245 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2246 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2248 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
2252 * Set media options.
2258 struct rl_softc *sc;
2259 struct mii_data *mii;
2262 mii = device_get_softc(sc->rl_miibus);
2271 * Report current media status.
2274 re_ifmedia_sts(ifp, ifmr)
2276 struct ifmediareq *ifmr;
2278 struct rl_softc *sc;
2279 struct mii_data *mii;
2282 mii = device_get_softc(sc->rl_miibus);
2287 ifmr->ifm_active = mii->mii_media_active;
2288 ifmr->ifm_status = mii->mii_media_status;
2292 re_ioctl(ifp, command, data)
2297 struct rl_softc *sc = ifp->if_softc;
2298 struct ifreq *ifr = (struct ifreq *) data;
2299 struct mii_data *mii;
2305 if (ifr->ifr_mtu > RL_JUMBO_MTU)
2307 ifp->if_mtu = ifr->ifr_mtu;
2312 if (ifp->if_flags & IFF_UP)
2314 else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2326 mii = device_get_softc(sc->rl_miibus);
2327 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2331 int mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2332 #ifdef DEVICE_POLLING
2333 if (mask & IFCAP_POLLING) {
2334 if (ifr->ifr_reqcap & IFCAP_POLLING) {
2335 error = ether_poll_register(re_poll, ifp);
2339 /* Disable interrupts */
2340 CSR_WRITE_2(sc, RL_IMR, 0x0000);
2341 ifp->if_capenable |= IFCAP_POLLING;
2345 error = ether_poll_deregister(ifp);
2346 /* Enable interrupts. */
2348 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2349 ifp->if_capenable &= ~IFCAP_POLLING;
2353 #endif /* DEVICE_POLLING */
2354 if (mask & IFCAP_HWCSUM) {
2356 ifp->if_capenable |= ifr->ifr_reqcap & IFCAP_HWCSUM;
2357 if (ifp->if_capenable & IFCAP_TXCSUM)
2358 ifp->if_hwassist = RE_CSUM_FEATURES;
2360 ifp->if_hwassist = 0;
2361 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2368 error = ether_ioctl(ifp, command, data);
2379 struct rl_softc *sc;
2383 if_printf(ifp, "watchdog timeout\n");
2394 * Stop the adapter and free any mbufs allocated to the
2399 struct rl_softc *sc;
2409 callout_stop(&sc->rl_stat_callout);
2410 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2412 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
2413 CSR_WRITE_2(sc, RL_IMR, 0x0000);
2415 if (sc->rl_head != NULL) {
2416 m_freem(sc->rl_head);
2417 sc->rl_head = sc->rl_tail = NULL;
2420 /* Free the TX list buffers. */
2422 for (i = 0; i < RL_TX_DESC_CNT; i++) {
2423 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) {
2424 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
2425 sc->rl_ldata.rl_tx_dmamap[i]);
2426 m_freem(sc->rl_ldata.rl_tx_mbuf[i]);
2427 sc->rl_ldata.rl_tx_mbuf[i] = NULL;
2431 /* Free the RX list buffers. */
2433 for (i = 0; i < RL_RX_DESC_CNT; i++) {
2434 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) {
2435 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
2436 sc->rl_ldata.rl_rx_dmamap[i]);
2437 m_freem(sc->rl_ldata.rl_rx_mbuf[i]);
2438 sc->rl_ldata.rl_rx_mbuf[i] = NULL;
2444 * Device suspend routine. Stop the interface and save some PCI
2445 * settings in case the BIOS doesn't restore them properly on
2452 struct rl_softc *sc;
2454 sc = device_get_softc(dev);
2465 * Device resume routine. Restore some PCI settings in case the BIOS
2466 * doesn't, re-enable busmastering, and restart the interface if
2473 struct rl_softc *sc;
2476 sc = device_get_softc(dev);
2482 /* reinitialize interface if necessary */
2483 if (ifp->if_flags & IFF_UP)
2493 * Stop all chip I/O so that the kernel's probe routines don't
2494 * get confused by errant DMAs when rebooting.
2500 struct rl_softc *sc;
2502 sc = device_get_softc(dev);
2507 * Mark interface as down since otherwise we will panic if
2508 * interrupt comes in later on, which can happen in some
2511 sc->rl_ifp->if_flags &= ~IFF_UP;