2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
45 * This driver is designed to support RealTek's next generation of
46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
47 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S
50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
51 * with the older 8139 family, however it also supports a special
52 * C+ mode of operation that provides several new performance enhancing
53 * features. These include:
55 * o Descriptor based DMA mechanism. Each descriptor represents
56 * a single packet fragment. Data buffers may be aligned on
61 * o TCP/IP checksum offload for both RX and TX
63 * o High and normal priority transmit DMA rings
65 * o VLAN tag insertion and extraction
67 * o TCP large send (segmentation offload)
69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
70 * programming API is fairly straightforward. The RX filtering, EEPROM
71 * access and PHY access is the same as it is on the older 8139 series
74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
75 * same programming API and feature set as the 8139C+ with the following
76 * differences and additions:
82 * o GMII and TBI ports/registers for interfacing with copper
85 * o RX and TX DMA rings can have up to 1024 descriptors
86 * (the 8139C+ allows a maximum of 64)
88 * o Slight differences in register layout from the 8139C+
90 * The TX start and timer interrupt registers are at different locations
91 * on the 8169 than they are on the 8139C+. Also, the status word in the
92 * RX descriptor has a slightly different bit layout. The 8169 does not
93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
97 * (the 'S' stands for 'single-chip'). These devices have the same
98 * programming API as the older 8169, but also have some vendor-specific
99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
102 * This driver takes advantage of the RX and TX checksum offload and
103 * VLAN tag insertion/extraction features. It also implements TX
104 * interrupt moderation using the timer interrupt registers, which
105 * significantly reduces TX interrupt load. There is also support
106 * for jumbo frames, however the 8169/8169S/8110S can not transmit
107 * jumbo frames larger than 7440, so the max MTU possible with this
108 * driver is 7422 bytes.
111 #include <sys/param.h>
112 #include <sys/endian.h>
113 #include <sys/systm.h>
114 #include <sys/sockio.h>
115 #include <sys/mbuf.h>
116 #include <sys/malloc.h>
117 #include <sys/module.h>
118 #include <sys/kernel.h>
119 #include <sys/socket.h>
122 #include <net/if_arp.h>
123 #include <net/ethernet.h>
124 #include <net/if_dl.h>
125 #include <net/if_media.h>
126 #include <net/if_types.h>
127 #include <net/if_vlan_var.h>
131 #include <machine/bus.h>
132 #include <machine/resource.h>
134 #include <sys/rman.h>
136 #include <dev/mii/mii.h>
137 #include <dev/mii/miivar.h>
139 #include <dev/pci/pcireg.h>
140 #include <dev/pci/pcivar.h>
142 MODULE_DEPEND(re, pci, 1, 1, 1);
143 MODULE_DEPEND(re, ether, 1, 1, 1);
144 MODULE_DEPEND(re, miibus, 1, 1, 1);
146 /* "controller miibus0" required. See GENERIC if you get errors here. */
147 #include "miibus_if.h"
150 * Default to using PIO access for this driver.
152 #define RE_USEIOSPACE
154 #include <pci/if_rlreg.h>
156 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
159 * Various supported device vendors/types and their names.
161 static struct rl_type re_devs[] = {
162 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS,
163 "RealTek 8139C+ 10/100BaseTX" },
164 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169,
165 "RealTek 8169 Gigabit Ethernet" },
166 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S,
167 "RealTek 8169S Single-chip Gigabit Ethernet" },
168 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169SB,
169 "RealTek 8169SB Single-chip Gigabit Ethernet" },
170 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S,
171 "RealTek 8110S Single-chip Gigabit Ethernet" },
172 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S,
173 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
177 static struct rl_hwrev re_hwrevs[] = {
178 { RL_HWREV_8139, RL_8139, "" },
179 { RL_HWREV_8139A, RL_8139, "A" },
180 { RL_HWREV_8139AG, RL_8139, "A-G" },
181 { RL_HWREV_8139B, RL_8139, "B" },
182 { RL_HWREV_8130, RL_8139, "8130" },
183 { RL_HWREV_8139C, RL_8139, "C" },
184 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" },
185 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"},
186 { RL_HWREV_8169, RL_8169, "8169"},
187 { RL_HWREV_8169S, RL_8169, "8169S"},
188 { RL_HWREV_8169SB, RL_8169, "8169SB"},
189 { RL_HWREV_8110S, RL_8169, "8110S"},
190 { RL_HWREV_8100, RL_8139, "8100"},
191 { RL_HWREV_8101, RL_8139, "8101"},
195 static int re_probe (device_t);
196 static int re_attach (device_t);
197 static int re_detach (device_t);
199 static int re_encap (struct rl_softc *, struct mbuf **, int *);
201 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int);
202 static void re_dma_map_desc (void *, bus_dma_segment_t *, int,
204 static int re_allocmem (device_t, struct rl_softc *);
205 static int re_newbuf (struct rl_softc *, int, struct mbuf *);
206 static int re_rx_list_init (struct rl_softc *);
207 static int re_tx_list_init (struct rl_softc *);
209 static __inline void re_fixup_rx
212 static void re_rxeof (struct rl_softc *);
213 static void re_txeof (struct rl_softc *);
214 #ifdef DEVICE_POLLING
215 static void re_poll (struct ifnet *, enum poll_cmd, int);
216 static void re_poll_locked (struct ifnet *, enum poll_cmd, int);
218 static void re_intr (void *);
219 static void re_tick (void *);
220 static void re_tick_locked (struct rl_softc *);
221 static void re_start (struct ifnet *);
222 static void re_start_locked (struct ifnet *);
223 static int re_ioctl (struct ifnet *, u_long, caddr_t);
224 static void re_init (void *);
225 static void re_init_locked (struct rl_softc *);
226 static void re_stop (struct rl_softc *);
227 static void re_watchdog (struct ifnet *);
228 static int re_suspend (device_t);
229 static int re_resume (device_t);
230 static void re_shutdown (device_t);
231 static int re_ifmedia_upd (struct ifnet *);
232 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *);
234 static void re_eeprom_putbyte (struct rl_softc *, int);
235 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *);
236 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int, int);
237 static int re_gmii_readreg (device_t, int, int);
238 static int re_gmii_writereg (device_t, int, int, int);
240 static int re_miibus_readreg (device_t, int, int);
241 static int re_miibus_writereg (device_t, int, int, int);
242 static void re_miibus_statchg (device_t);
244 static void re_setmulti (struct rl_softc *);
245 static void re_reset (struct rl_softc *);
247 static int re_diag (struct rl_softc *);
250 #define RL_RES SYS_RES_IOPORT
251 #define RL_RID RL_PCI_LOIO
253 #define RL_RES SYS_RES_MEMORY
254 #define RL_RID RL_PCI_LOMEM
257 static device_method_t re_methods[] = {
258 /* Device interface */
259 DEVMETHOD(device_probe, re_probe),
260 DEVMETHOD(device_attach, re_attach),
261 DEVMETHOD(device_detach, re_detach),
262 DEVMETHOD(device_suspend, re_suspend),
263 DEVMETHOD(device_resume, re_resume),
264 DEVMETHOD(device_shutdown, re_shutdown),
267 DEVMETHOD(bus_print_child, bus_generic_print_child),
268 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
271 DEVMETHOD(miibus_readreg, re_miibus_readreg),
272 DEVMETHOD(miibus_writereg, re_miibus_writereg),
273 DEVMETHOD(miibus_statchg, re_miibus_statchg),
278 static driver_t re_driver = {
281 sizeof(struct rl_softc)
284 static devclass_t re_devclass;
286 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0);
287 DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0);
288 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
291 CSR_WRITE_1(sc, RL_EECMD, \
292 CSR_READ_1(sc, RL_EECMD) | x)
295 CSR_WRITE_1(sc, RL_EECMD, \
296 CSR_READ_1(sc, RL_EECMD) & ~x)
299 * Send a read command and address to the EEPROM, check for ACK.
302 re_eeprom_putbyte(sc, addr)
308 d = addr | sc->rl_eecmd_read;
311 * Feed in each bit and strobe the clock.
313 for (i = 0x400; i; i >>= 1) {
315 EE_SET(RL_EE_DATAIN);
317 EE_CLR(RL_EE_DATAIN);
328 * Read a word of data stored in the EEPROM at address 'addr.'
331 re_eeprom_getword(sc, addr, dest)
339 /* Enter EEPROM access mode. */
340 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
343 * Send address of word we want to read.
345 re_eeprom_putbyte(sc, addr);
347 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
350 * Start reading bits from EEPROM.
352 for (i = 0x8000; i; i >>= 1) {
355 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
361 /* Turn off EEPROM access mode. */
362 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
368 * Read a sequence of words from the EEPROM.
371 re_read_eeprom(sc, dest, off, cnt, swap)
379 u_int16_t word = 0, *ptr;
381 for (i = 0; i < cnt; i++) {
382 re_eeprom_getword(sc, off + i, &word);
383 ptr = (u_int16_t *)(dest + (i * 2));
392 re_gmii_readreg(dev, phy, reg)
403 sc = device_get_softc(dev);
405 /* Let the rgephy driver read the GMEDIASTAT register */
407 if (reg == RL_GMEDIASTAT) {
408 rval = CSR_READ_1(sc, RL_GMEDIASTAT);
412 CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
415 for (i = 0; i < RL_TIMEOUT; i++) {
416 rval = CSR_READ_4(sc, RL_PHYAR);
417 if (rval & RL_PHYAR_BUSY)
422 if (i == RL_TIMEOUT) {
423 printf ("re%d: PHY read failed\n", sc->rl_unit);
427 return (rval & RL_PHYAR_PHYDATA);
431 re_gmii_writereg(dev, phy, reg, data)
439 sc = device_get_softc(dev);
441 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
442 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
445 for (i = 0; i < RL_TIMEOUT; i++) {
446 rval = CSR_READ_4(sc, RL_PHYAR);
447 if (!(rval & RL_PHYAR_BUSY))
452 if (i == RL_TIMEOUT) {
453 printf ("re%d: PHY write failed\n", sc->rl_unit);
461 re_miibus_readreg(dev, phy, reg)
467 u_int16_t re8139_reg = 0;
469 sc = device_get_softc(dev);
471 if (sc->rl_type == RL_8169) {
472 rval = re_gmii_readreg(dev, phy, reg);
476 /* Pretend the internal PHY is only at address 0 */
482 re8139_reg = RL_BMCR;
485 re8139_reg = RL_BMSR;
488 re8139_reg = RL_ANAR;
491 re8139_reg = RL_ANER;
494 re8139_reg = RL_LPAR;
500 * Allow the rlphy driver to read the media status
501 * register. If we have a link partner which does not
502 * support NWAY, this is the register which will tell
503 * us the results of parallel detection.
506 rval = CSR_READ_1(sc, RL_MEDIASTAT);
509 printf("re%d: bad phy register\n", sc->rl_unit);
512 rval = CSR_READ_2(sc, re8139_reg);
517 re_miibus_writereg(dev, phy, reg, data)
522 u_int16_t re8139_reg = 0;
525 sc = device_get_softc(dev);
527 if (sc->rl_type == RL_8169) {
528 rval = re_gmii_writereg(dev, phy, reg, data);
532 /* Pretend the internal PHY is only at address 0 */
538 re8139_reg = RL_BMCR;
541 re8139_reg = RL_BMSR;
544 re8139_reg = RL_ANAR;
547 re8139_reg = RL_ANER;
550 re8139_reg = RL_LPAR;
557 printf("re%d: bad phy register\n", sc->rl_unit);
560 CSR_WRITE_2(sc, re8139_reg, data);
565 re_miibus_statchg(dev)
572 * Program the 64-bit multicast hash filter.
580 u_int32_t hashes[2] = { 0, 0 };
581 struct ifmultiaddr *ifma;
589 rxfilt = CSR_READ_4(sc, RL_RXCFG);
591 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
592 rxfilt |= RL_RXCFG_RX_MULTI;
593 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
594 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
595 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
599 /* first, zot all the existing hash bits */
600 CSR_WRITE_4(sc, RL_MAR0, 0);
601 CSR_WRITE_4(sc, RL_MAR4, 0);
603 /* now program new ones */
604 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
605 if (ifma->ifma_addr->sa_family != AF_LINK)
607 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
608 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
610 hashes[0] |= (1 << h);
612 hashes[1] |= (1 << (h - 32));
617 rxfilt |= RL_RXCFG_RX_MULTI;
619 rxfilt &= ~RL_RXCFG_RX_MULTI;
621 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
622 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
623 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
634 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
636 for (i = 0; i < RL_TIMEOUT; i++) {
638 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
642 printf("re%d: reset never completed!\n", sc->rl_unit);
644 CSR_WRITE_1(sc, 0x82, 1);
648 * The following routine is designed to test for a defect on some
649 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
650 * lines connected to the bus, however for a 32-bit only card, they
651 * should be pulled high. The result of this defect is that the
652 * NIC will not work right if you plug it into a 64-bit slot: DMA
653 * operations will be done with 64-bit transfers, which will fail
654 * because the 64-bit data lines aren't connected.
656 * There's no way to work around this (short of talking a soldering
657 * iron to the board), however we can detect it. The method we use
658 * here is to put the NIC into digital loopback mode, set the receiver
659 * to promiscuous mode, and then try to send a frame. We then compare
660 * the frame data we sent to what was received. If the data matches,
661 * then the NIC is working correctly, otherwise we know the user has
662 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
663 * slot. In the latter case, there's no way the NIC can work correctly,
664 * so we print out a message on the console and abort the device attach.
671 struct ifnet *ifp = sc->rl_ifp;
673 struct ether_header *eh;
674 struct rl_desc *cur_rx;
677 int total_len, i, error = 0;
678 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
679 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
681 /* Allocate a single mbuf */
682 MGETHDR(m0, M_DONTWAIT, MT_DATA);
689 * Initialize the NIC in test mode. This sets the chip up
690 * so that it can send and receive frames, but performs the
691 * following special functions:
692 * - Puts receiver in promiscuous mode
693 * - Enables digital loopback mode
694 * - Leaves interrupts turned off
697 ifp->if_flags |= IFF_PROMISC;
704 /* Put some data in the mbuf */
706 eh = mtod(m0, struct ether_header *);
707 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
708 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
709 eh->ether_type = htons(ETHERTYPE_IP);
710 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
713 * Queue the packet, start transmission.
714 * Note: IF_HANDOFF() ultimately calls re_start() for us.
717 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
719 /* XXX: re_diag must not be called when in ALTQ mode */
720 IF_HANDOFF(&ifp->if_snd, m0, ifp);
724 /* Wait for it to propagate through the chip */
727 for (i = 0; i < RL_TIMEOUT; i++) {
728 status = CSR_READ_2(sc, RL_ISR);
729 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
730 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
735 if (i == RL_TIMEOUT) {
736 printf("re%d: diagnostic failed, failed to receive packet "
737 "in loopback mode\n", sc->rl_unit);
743 * The packet should have been dumped into the first
744 * entry in the RX DMA ring. Grab it from there.
747 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
748 sc->rl_ldata.rl_rx_list_map,
749 BUS_DMASYNC_POSTREAD);
750 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
751 sc->rl_ldata.rl_rx_dmamap[0],
752 BUS_DMASYNC_POSTWRITE);
753 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
754 sc->rl_ldata.rl_rx_dmamap[0]);
756 m0 = sc->rl_ldata.rl_rx_mbuf[0];
757 sc->rl_ldata.rl_rx_mbuf[0] = NULL;
758 eh = mtod(m0, struct ether_header *);
760 cur_rx = &sc->rl_ldata.rl_rx_list[0];
761 total_len = RL_RXBYTES(cur_rx);
762 rxstat = le32toh(cur_rx->rl_cmdstat);
764 if (total_len != ETHER_MIN_LEN) {
765 printf("re%d: diagnostic failed, received short packet\n",
771 /* Test that the received packet data matches what we sent. */
773 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
774 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
775 ntohs(eh->ether_type) != ETHERTYPE_IP) {
776 printf("re%d: WARNING, DMA FAILURE!\n", sc->rl_unit);
777 printf("re%d: expected TX data: %6D/%6D/0x%x\n", sc->rl_unit,
778 dst, ":", src, ":", ETHERTYPE_IP);
779 printf("re%d: received RX data: %6D/%6D/0x%x\n", sc->rl_unit,
780 eh->ether_dhost, ":", eh->ether_shost, ":",
781 ntohs(eh->ether_type));
782 printf("re%d: You may have a defective 32-bit NIC plugged "
783 "into a 64-bit PCI slot.\n", sc->rl_unit);
784 printf("re%d: Please re-install the NIC in a 32-bit slot "
785 "for proper operation.\n", sc->rl_unit);
786 printf("re%d: Read the re(4) man page for more details.\n",
792 /* Turn interface off, release resources */
795 ifp->if_flags &= ~IFF_PROMISC;
806 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
807 * IDs against our list and return a device name if we find a match.
819 sc = device_get_softc(dev);
821 while (t->rl_name != NULL) {
822 if ((pci_get_vendor(dev) == t->rl_vid) &&
823 (pci_get_device(dev) == t->rl_did)) {
826 * Temporarily map the I/O space
827 * so we can read the chip ID register.
830 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
832 if (sc->rl_res == NULL) {
834 "couldn't map ports/memory\n");
837 sc->rl_btag = rman_get_bustag(sc->rl_res);
838 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
839 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
840 bus_release_resource(dev, RL_RES,
842 if (t->rl_basetype == hwrev) {
843 device_set_desc(dev, t->rl_name);
844 return (BUS_PROBE_DEFAULT);
854 * This routine takes the segment list provided as the result of
855 * a bus_dma_map_load() operation and assigns the addresses/lengths
856 * to RealTek DMA descriptors. This can be called either by the RX
857 * code or the TX code. In the RX case, we'll probably wind up mapping
858 * at most one segment. For the TX case, there could be any number of
859 * segments since TX packets may span multiple mbufs. In either case,
860 * if the number of segments is larger than the rl_maxsegs limit
861 * specified by the caller, we abort the mapping operation. Sadly,
862 * whoever designed the buffer mapping API did not provide a way to
863 * return an error from here, so we have to fake it a bit.
867 re_dma_map_desc(arg, segs, nseg, mapsize, error)
869 bus_dma_segment_t *segs;
874 struct rl_dmaload_arg *ctx;
875 struct rl_desc *d = NULL;
883 /* Signal error to caller if there's too many segments */
884 if (nseg > ctx->rl_maxsegs) {
890 * Map the segment array into descriptors. Note that we set the
891 * start-of-frame and end-of-frame markers for either TX or RX, but
892 * they really only have meaning in the TX case. (In the RX case,
893 * it's the chip that tells us where packets begin and end.)
894 * We also keep track of the end of the ring and set the
895 * end-of-ring bits as needed, and we set the ownership bits
896 * in all except the very first descriptor. (The caller will
897 * set this descriptor later when it start transmission or
903 d = &ctx->rl_ring[idx];
904 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) {
908 cmdstat = segs[i].ds_len;
909 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
910 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
912 cmdstat |= RL_TDESC_CMD_SOF;
914 cmdstat |= RL_TDESC_CMD_OWN;
915 if (idx == (RL_RX_DESC_CNT - 1))
916 cmdstat |= RL_TDESC_CMD_EOR;
917 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags);
924 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
925 ctx->rl_maxsegs = nseg;
930 * Map a single buffer address.
934 re_dma_map_addr(arg, segs, nseg, error)
936 bus_dma_segment_t *segs;
945 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
947 *addr = segs->ds_addr;
960 * Allocate map for RX mbufs.
963 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0,
964 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
965 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW,
966 NULL, NULL, &sc->rl_ldata.rl_mtag);
968 device_printf(dev, "could not allocate dma tag\n");
973 * Allocate map for TX descriptor list.
975 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
976 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
977 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
978 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag);
980 device_printf(dev, "could not allocate dma tag\n");
984 /* Allocate DMA'able memory for the TX ring */
986 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
987 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
988 &sc->rl_ldata.rl_tx_list_map);
992 /* Load the map for the TX ring. */
994 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
995 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
996 RL_TX_LIST_SZ, re_dma_map_addr,
997 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT);
999 /* Create DMA maps for TX buffers */
1001 for (i = 0; i < RL_TX_DESC_CNT; i++) {
1002 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0,
1003 &sc->rl_ldata.rl_tx_dmamap[i]);
1005 device_printf(dev, "can't create DMA map for TX\n");
1011 * Allocate map for RX descriptor list.
1013 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1014 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1015 NULL, RL_RX_LIST_SZ, 1, RL_RX_LIST_SZ, BUS_DMA_ALLOCNOW,
1016 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag);
1018 device_printf(dev, "could not allocate dma tag\n");
1022 /* Allocate DMA'able memory for the RX ring */
1024 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag,
1025 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
1026 &sc->rl_ldata.rl_rx_list_map);
1030 /* Load the map for the RX ring. */
1032 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag,
1033 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
1034 RL_RX_LIST_SZ, re_dma_map_addr,
1035 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT);
1037 /* Create DMA maps for RX buffers */
1039 for (i = 0; i < RL_RX_DESC_CNT; i++) {
1040 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0,
1041 &sc->rl_ldata.rl_rx_dmamap[i]);
1043 device_printf(dev, "can't create DMA map for RX\n");
1052 * Attach the interface. Allocate softc structures, do ifmedia
1053 * setup and ethernet/BPF attach.
1059 u_char eaddr[ETHER_ADDR_LEN];
1061 struct rl_softc *sc;
1063 struct rl_hwrev *hw_rev;
1065 u_int16_t re_did = 0;
1066 int unit, error = 0, rid, i;
1068 sc = device_get_softc(dev);
1069 unit = device_get_unit(dev);
1071 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1074 * Map control/status registers.
1076 pci_enable_busmaster(dev);
1079 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid,
1082 if (sc->rl_res == NULL) {
1083 printf ("re%d: couldn't map ports/memory\n", unit);
1088 sc->rl_btag = rman_get_bustag(sc->rl_res);
1089 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
1091 /* Allocate interrupt */
1093 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1094 RF_SHAREABLE | RF_ACTIVE);
1096 if (sc->rl_irq == NULL) {
1097 printf("re%d: couldn't map interrupt\n", unit);
1102 /* Reset the adapter. */
1108 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
1109 while (hw_rev->rl_desc != NULL) {
1110 if (hw_rev->rl_rev == hwrev) {
1111 sc->rl_type = hw_rev->rl_type;
1117 if (sc->rl_type == RL_8169) {
1119 /* Set RX length mask */
1121 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
1123 /* Force station address autoload from the EEPROM */
1125 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_AUTOLOAD);
1126 for (i = 0; i < RL_TIMEOUT; i++) {
1127 if (!(CSR_READ_1(sc, RL_EECMD) & RL_EEMODE_AUTOLOAD))
1131 if (i == RL_TIMEOUT)
1132 printf ("re%d: eeprom autoload timed out\n", unit);
1134 for (i = 0; i < ETHER_ADDR_LEN; i++)
1135 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
1138 /* Set RX length mask */
1140 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
1142 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
1143 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0);
1144 if (re_did != 0x8129)
1145 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
1148 * Get station address from the EEPROM.
1150 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0);
1151 for (i = 0; i < 3; i++) {
1152 eaddr[(i * 2) + 0] = as[i] & 0xff;
1153 eaddr[(i * 2) + 1] = as[i] >> 8;
1160 * Allocate the parent bus DMA tag appropriate for PCI.
1162 #define RL_NSEG_NEW 32
1163 error = bus_dma_tag_create(NULL, /* parent */
1164 1, 0, /* alignment, boundary */
1165 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1166 BUS_SPACE_MAXADDR, /* highaddr */
1167 NULL, NULL, /* filter, filterarg */
1168 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
1169 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1170 BUS_DMA_ALLOCNOW, /* flags */
1171 NULL, NULL, /* lockfunc, lockarg */
1172 &sc->rl_parent_tag);
1176 error = re_allocmem(dev, sc);
1181 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
1183 printf("re%d: can not if_alloc()\n", sc->rl_unit);
1189 if (mii_phy_probe(dev, &sc->rl_miibus,
1190 re_ifmedia_upd, re_ifmedia_sts)) {
1191 printf("re%d: MII without any phy!\n", sc->rl_unit);
1197 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1198 ifp->if_mtu = ETHERMTU;
1199 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1200 ifp->if_ioctl = re_ioctl;
1201 ifp->if_capabilities = IFCAP_VLAN_MTU;
1202 ifp->if_start = re_start;
1203 ifp->if_hwassist = /*RE_CSUM_FEATURES*/0;
1204 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1205 #ifdef DEVICE_POLLING
1206 ifp->if_capabilities |= IFCAP_POLLING;
1208 ifp->if_watchdog = re_watchdog;
1209 ifp->if_init = re_init;
1210 if (sc->rl_type == RL_8169)
1211 ifp->if_baudrate = 1000000000;
1213 ifp->if_baudrate = 100000000;
1214 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
1215 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN;
1216 IFQ_SET_READY(&ifp->if_snd);
1217 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1219 callout_handle_init(&sc->rl_stat_ch);
1222 * Call MI attach routine.
1224 ether_ifattach(ifp, eaddr);
1226 /* Perform hardware diagnostic. */
1227 error = re_diag(sc);
1230 printf("re%d: attach aborted due to hardware diag failure\n",
1232 ether_ifdetach(ifp);
1237 /* Hook interrupt last to avoid having to lock softc */
1238 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1239 re_intr, sc, &sc->rl_intrhand);
1241 printf("re%d: couldn't set up irq\n", unit);
1242 ether_ifdetach(ifp);
1254 * Shutdown hardware and free up resources. This can be called any
1255 * time after the mutex has been initialized. It is called in both
1256 * the error case in attach and the normal detach case so it needs
1257 * to be careful about only freeing resources that have actually been
1264 struct rl_softc *sc;
1269 sc = device_get_softc(dev);
1271 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized"));
1273 attached = device_is_attached(dev);
1274 /* These should only be active if attach succeeded */
1276 ether_ifdetach(ifp);
1285 /* These should only be active if attach succeeded */
1289 * Force off the IFF_UP flag here, in case someone
1290 * still had a BPF descriptor attached to this
1291 * interface. If they do, ether_ifdetach() will cause
1292 * the BPF code to try and clear the promisc mode
1293 * flag, which will bubble down to re_ioctl(),
1294 * which will try to call re_init() again. This will
1295 * turn the NIC back on and restart the MII ticker,
1296 * which will panic the system when the kernel tries
1297 * to invoke the re_tick() function that isn't there
1300 ifp->if_flags &= ~IFF_UP;
1303 device_delete_child(dev, sc->rl_miibus);
1304 bus_generic_detach(dev);
1307 * The rest is resource deallocation, so we should already be
1312 if (sc->rl_intrhand)
1313 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
1315 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
1317 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1320 /* Unload and free the RX DMA ring memory and map */
1322 if (sc->rl_ldata.rl_rx_list_tag) {
1323 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag,
1324 sc->rl_ldata.rl_rx_list_map);
1325 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag,
1326 sc->rl_ldata.rl_rx_list,
1327 sc->rl_ldata.rl_rx_list_map);
1328 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag);
1331 /* Unload and free the TX DMA ring memory and map */
1333 if (sc->rl_ldata.rl_tx_list_tag) {
1334 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag,
1335 sc->rl_ldata.rl_tx_list_map);
1336 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag,
1337 sc->rl_ldata.rl_tx_list,
1338 sc->rl_ldata.rl_tx_list_map);
1339 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag);
1342 /* Destroy all the RX and TX buffer maps */
1344 if (sc->rl_ldata.rl_mtag) {
1345 for (i = 0; i < RL_TX_DESC_CNT; i++)
1346 bus_dmamap_destroy(sc->rl_ldata.rl_mtag,
1347 sc->rl_ldata.rl_tx_dmamap[i]);
1348 for (i = 0; i < RL_RX_DESC_CNT; i++)
1349 bus_dmamap_destroy(sc->rl_ldata.rl_mtag,
1350 sc->rl_ldata.rl_rx_dmamap[i]);
1351 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag);
1354 /* Unload and free the stats buffer and map */
1356 if (sc->rl_ldata.rl_stag) {
1357 bus_dmamap_unload(sc->rl_ldata.rl_stag,
1358 sc->rl_ldata.rl_rx_list_map);
1359 bus_dmamem_free(sc->rl_ldata.rl_stag,
1360 sc->rl_ldata.rl_stats,
1361 sc->rl_ldata.rl_smap);
1362 bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1365 if (sc->rl_parent_tag)
1366 bus_dma_tag_destroy(sc->rl_parent_tag);
1368 mtx_destroy(&sc->rl_mtx);
1374 re_newbuf(sc, idx, m)
1375 struct rl_softc *sc;
1379 struct rl_dmaload_arg arg;
1380 struct mbuf *n = NULL;
1384 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1389 m->m_data = m->m_ext.ext_buf;
1391 m->m_len = m->m_pkthdr.len = MCLBYTES;
1394 * This is part of an evil trick to deal with non-x86 platforms.
1395 * The RealTek chip requires RX buffers to be aligned on 64-bit
1396 * boundaries, but that will hose non-x86 machines. To get around
1397 * this, we leave some empty space at the start of each buffer
1398 * and for non-x86 hosts, we copy the buffer back six bytes
1399 * to achieve word alignment. This is slightly more efficient
1400 * than allocating a new buffer, copying the contents, and
1401 * discarding the old buffer.
1403 m_adj(m, RE_ETHER_ALIGN);
1409 arg.rl_ring = sc->rl_ldata.rl_rx_list;
1411 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag,
1412 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc,
1413 &arg, BUS_DMA_NOWAIT);
1414 if (error || arg.rl_maxsegs != 1) {
1420 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN);
1421 sc->rl_ldata.rl_rx_mbuf[idx] = m;
1423 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
1424 sc->rl_ldata.rl_rx_dmamap[idx],
1425 BUS_DMASYNC_PREREAD);
1431 static __inline void
1436 uint16_t *src, *dst;
1438 src = mtod(m, uint16_t *);
1439 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src;
1441 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1444 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN;
1452 struct rl_softc *sc;
1457 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ);
1458 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf,
1459 (RL_TX_DESC_CNT * sizeof(struct mbuf *)));
1461 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
1462 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE);
1463 sc->rl_ldata.rl_tx_prodidx = 0;
1464 sc->rl_ldata.rl_tx_considx = 0;
1465 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT;
1472 struct rl_softc *sc;
1476 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ);
1477 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf,
1478 (RL_RX_DESC_CNT * sizeof(struct mbuf *)));
1480 for (i = 0; i < RL_RX_DESC_CNT; i++) {
1481 if (re_newbuf(sc, i, NULL) == ENOBUFS)
1485 /* Flush the RX descriptors */
1487 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1488 sc->rl_ldata.rl_rx_list_map,
1489 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1491 sc->rl_ldata.rl_rx_prodidx = 0;
1492 sc->rl_head = sc->rl_tail = NULL;
1498 * RX handler for C+ and 8169. For the gigE chips, we support
1499 * the reception of jumbo frames that have been fragmented
1500 * across multiple 2K mbuf cluster buffers.
1504 struct rl_softc *sc;
1509 struct rl_desc *cur_rx;
1510 u_int32_t rxstat, rxvlan;
1515 i = sc->rl_ldata.rl_rx_prodidx;
1517 /* Invalidate the descriptor memory */
1519 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1520 sc->rl_ldata.rl_rx_list_map,
1521 BUS_DMASYNC_POSTREAD);
1523 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) {
1524 cur_rx = &sc->rl_ldata.rl_rx_list[i];
1525 m = sc->rl_ldata.rl_rx_mbuf[i];
1526 total_len = RL_RXBYTES(cur_rx);
1527 rxstat = le32toh(cur_rx->rl_cmdstat);
1528 rxvlan = le32toh(cur_rx->rl_vlanctl);
1530 /* Invalidate the RX mbuf and unload its map */
1532 bus_dmamap_sync(sc->rl_ldata.rl_mtag,
1533 sc->rl_ldata.rl_rx_dmamap[i],
1534 BUS_DMASYNC_POSTWRITE);
1535 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
1536 sc->rl_ldata.rl_rx_dmamap[i]);
1538 if (!(rxstat & RL_RDESC_STAT_EOF)) {
1539 m->m_len = RE_RX_DESC_BUFLEN;
1540 if (sc->rl_head == NULL)
1541 sc->rl_head = sc->rl_tail = m;
1543 m->m_flags &= ~M_PKTHDR;
1544 sc->rl_tail->m_next = m;
1547 re_newbuf(sc, i, NULL);
1553 * NOTE: for the 8139C+, the frame length field
1554 * is always 12 bits in size, but for the gigE chips,
1555 * it is 13 bits (since the max RX frame length is 16K).
1556 * Unfortunately, all 32 bits in the status word
1557 * were already used, so to make room for the extra
1558 * length bit, RealTek took out the 'frame alignment
1559 * error' bit and shifted the other status bits
1560 * over one slot. The OWN, EOR, FS and LS bits are
1561 * still in the same places. We have already extracted
1562 * the frame length and checked the OWN bit, so rather
1563 * than using an alternate bit mapping, we shift the
1564 * status bits one space to the right so we can evaluate
1565 * them using the 8169 status as though it was in the
1566 * same format as that of the 8139C+.
1568 if (sc->rl_type == RL_8169)
1572 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be
1573 * set, but if CRC is clear, it will still be a valid frame.
1575 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 &&
1576 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) {
1579 * If this is part of a multi-fragment packet,
1580 * discard all the pieces.
1582 if (sc->rl_head != NULL) {
1583 m_freem(sc->rl_head);
1584 sc->rl_head = sc->rl_tail = NULL;
1586 re_newbuf(sc, i, m);
1592 * If allocating a replacement mbuf fails,
1593 * reload the current one.
1596 if (re_newbuf(sc, i, NULL)) {
1598 if (sc->rl_head != NULL) {
1599 m_freem(sc->rl_head);
1600 sc->rl_head = sc->rl_tail = NULL;
1602 re_newbuf(sc, i, m);
1609 if (sc->rl_head != NULL) {
1610 m->m_len = total_len % RE_RX_DESC_BUFLEN;
1612 m->m_len = RE_RX_DESC_BUFLEN;
1614 * Special case: if there's 4 bytes or less
1615 * in this buffer, the mbuf can be discarded:
1616 * the last 4 bytes is the CRC, which we don't
1617 * care about anyway.
1619 if (m->m_len <= ETHER_CRC_LEN) {
1620 sc->rl_tail->m_len -=
1621 (ETHER_CRC_LEN - m->m_len);
1624 m->m_len -= ETHER_CRC_LEN;
1625 m->m_flags &= ~M_PKTHDR;
1626 sc->rl_tail->m_next = m;
1629 sc->rl_head = sc->rl_tail = NULL;
1630 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1632 m->m_pkthdr.len = m->m_len =
1633 (total_len - ETHER_CRC_LEN);
1639 m->m_pkthdr.rcvif = ifp;
1641 /* Do RX checksumming if enabled */
1643 if (ifp->if_capenable & IFCAP_RXCSUM) {
1645 /* Check IP header checksum */
1646 if (rxstat & RL_RDESC_STAT_PROTOID)
1647 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1648 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
1649 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1651 /* Check TCP/UDP checksum */
1652 if ((RL_TCPPKT(rxstat) &&
1653 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
1654 (RL_UDPPKT(rxstat) &&
1655 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
1656 m->m_pkthdr.csum_flags |=
1657 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1658 m->m_pkthdr.csum_data = 0xffff;
1662 if (rxvlan & RL_RDESC_VLANCTL_TAG)
1663 VLAN_INPUT_TAG(ifp, m,
1664 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)), continue);
1666 (*ifp->if_input)(ifp, m);
1670 /* Flush the RX DMA ring */
1672 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1673 sc->rl_ldata.rl_rx_list_map,
1674 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1676 sc->rl_ldata.rl_rx_prodidx = i;
1681 struct rl_softc *sc;
1688 idx = sc->rl_ldata.rl_tx_considx;
1690 /* Invalidate the TX descriptor list */
1692 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
1693 sc->rl_ldata.rl_tx_list_map,
1694 BUS_DMASYNC_POSTREAD);
1696 while (idx != sc->rl_ldata.rl_tx_prodidx) {
1698 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat);
1699 if (txstat & RL_TDESC_CMD_OWN)
1703 * We only stash mbufs in the last descriptor
1704 * in a fragment chain, which also happens to
1705 * be the only place where the TX status bits
1709 if (txstat & RL_TDESC_CMD_EOF) {
1710 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]);
1711 sc->rl_ldata.rl_tx_mbuf[idx] = NULL;
1712 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
1713 sc->rl_ldata.rl_tx_dmamap[idx]);
1714 if (txstat & (RL_TDESC_STAT_EXCESSCOL|
1715 RL_TDESC_STAT_COLCNT))
1716 ifp->if_collisions++;
1717 if (txstat & RL_TDESC_STAT_TXERRSUM)
1722 sc->rl_ldata.rl_tx_free++;
1726 /* No changes made to the TX ring, so no flush needed */
1728 if (idx != sc->rl_ldata.rl_tx_considx) {
1729 sc->rl_ldata.rl_tx_considx = idx;
1730 ifp->if_flags &= ~IFF_OACTIVE;
1735 * If not all descriptors have been released reaped yet,
1736 * reload the timer so that we will eventually get another
1737 * interrupt that will cause us to re-enter this routine.
1738 * This is done in case the transmitter has gone idle.
1740 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT)
1741 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
1748 struct rl_softc *sc;
1758 struct rl_softc *sc;
1760 struct mii_data *mii;
1764 mii = device_get_softc(sc->rl_miibus);
1768 sc->rl_stat_ch = timeout(re_tick, sc, hz);
1771 #ifdef DEVICE_POLLING
1773 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1775 struct rl_softc *sc = ifp->if_softc;
1778 re_poll_locked(ifp, cmd, count);
1783 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1785 struct rl_softc *sc = ifp->if_softc;
1789 if (!(ifp->if_capenable & IFCAP_POLLING)) {
1790 ether_poll_deregister(ifp);
1791 cmd = POLL_DEREGISTER;
1793 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1794 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
1798 sc->rxcycles = count;
1802 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1803 re_start_locked(ifp);
1805 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1808 status = CSR_READ_2(sc, RL_ISR);
1809 if (status == 0xffff)
1812 CSR_WRITE_2(sc, RL_ISR, status);
1815 * XXX check behaviour on receiver stalls.
1818 if (status & RL_ISR_SYSTEM_ERR) {
1824 #endif /* DEVICE_POLLING */
1830 struct rl_softc *sc;
1840 if (sc->suspended || !(ifp->if_flags & IFF_UP))
1843 #ifdef DEVICE_POLLING
1844 if (ifp->if_flags & IFF_POLLING)
1846 if ((ifp->if_capenable & IFCAP_POLLING) &&
1847 ether_poll_register(re_poll, ifp)) { /* ok, disable interrupts */
1848 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1849 re_poll_locked(ifp, 0, 1);
1852 #endif /* DEVICE_POLLING */
1856 status = CSR_READ_2(sc, RL_ISR);
1857 /* If the card has gone away the read returns 0xffff. */
1858 if (status == 0xffff)
1861 CSR_WRITE_2(sc, RL_ISR, status);
1863 if ((status & RL_INTRS_CPLUS) == 0)
1866 if ((status & RL_ISR_RX_OK) ||
1867 (status & RL_ISR_RX_ERR))
1870 if ((status & RL_ISR_TIMEOUT_EXPIRED) ||
1871 (status & RL_ISR_TX_ERR) ||
1872 (status & RL_ISR_TX_DESC_UNAVAIL))
1875 if (status & RL_ISR_SYSTEM_ERR) {
1880 if (status & RL_ISR_LINKCHG) {
1881 untimeout(re_tick, sc, sc->rl_stat_ch);
1886 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1887 re_start_locked(ifp);
1894 re_encap(sc, m_head, idx)
1895 struct rl_softc *sc;
1896 struct mbuf **m_head;
1899 struct mbuf *m_new = NULL;
1900 struct rl_dmaload_arg arg;
1907 if (sc->rl_ldata.rl_tx_free <= 4)
1911 * Set up checksum offload. Note: checksum offload bits must
1912 * appear in all descriptors of a multi-descriptor transmit
1913 * attempt. This is according to testing done with an 8169
1914 * chip. This is a requirement.
1919 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP)
1920 arg.rl_flags |= RL_TDESC_CMD_IPCSUM;
1921 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP)
1922 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM;
1923 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP)
1924 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM;
1928 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free;
1929 if (arg.rl_maxsegs > 4)
1930 arg.rl_maxsegs -= 4;
1931 arg.rl_ring = sc->rl_ldata.rl_tx_list;
1933 map = sc->rl_ldata.rl_tx_dmamap[*idx];
1934 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map,
1935 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1937 if (error && error != EFBIG) {
1938 printf("re%d: can't map mbuf (error %d)\n", sc->rl_unit, error);
1942 /* Too many segments to map, coalesce into a single mbuf */
1944 if (error || arg.rl_maxsegs == 0) {
1945 m_new = m_defrag(*m_head, M_DONTWAIT);
1953 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free;
1954 arg.rl_ring = sc->rl_ldata.rl_tx_list;
1956 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map,
1957 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1959 printf("re%d: can't map mbuf (error %d)\n",
1960 sc->rl_unit, error);
1966 * Insure that the map for this transmission
1967 * is placed at the array index of the last descriptor
1968 * in this chain. (Swap last and first dmamaps.)
1970 sc->rl_ldata.rl_tx_dmamap[*idx] =
1971 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx];
1972 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map;
1974 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = *m_head;
1975 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs;
1978 * Set up hardware VLAN tagging. Note: vlan tag info must
1979 * appear in the first descriptor of a multi-descriptor
1980 * transmission attempt.
1983 mtag = VLAN_OUTPUT_TAG(sc->rl_ifp, *m_head);
1985 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl =
1986 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG);
1988 /* Transfer ownership of packet to the chip. */
1990 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |=
1991 htole32(RL_TDESC_CMD_OWN);
1992 if (*idx != arg.rl_idx)
1993 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |=
1994 htole32(RL_TDESC_CMD_OWN);
1996 RL_DESC_INC(arg.rl_idx);
2006 struct rl_softc *sc;
2010 re_start_locked(ifp);
2015 * Main transmit routine for C+ and gigE NICs.
2018 re_start_locked(ifp)
2021 struct rl_softc *sc;
2022 struct mbuf *m_head = NULL;
2023 int idx, queued = 0;
2029 idx = sc->rl_ldata.rl_tx_prodidx;
2031 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) {
2032 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2036 if (re_encap(sc, &m_head, &idx)) {
2037 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2038 ifp->if_flags |= IFF_OACTIVE;
2043 * If there's a BPF listener, bounce a copy of this frame
2046 BPF_MTAP(ifp, m_head);
2054 /* Flush the TX descriptors */
2056 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2057 sc->rl_ldata.rl_tx_list_map,
2058 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2060 sc->rl_ldata.rl_tx_prodidx = idx;
2063 * RealTek put the TX poll request register in a different
2064 * location on the 8169 gigE chip. I don't know why.
2067 if (sc->rl_type == RL_8169)
2068 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START);
2070 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START);
2073 * Use the countdown timer for interrupt moderation.
2074 * 'TX done' interrupts are disabled. Instead, we reset the
2075 * countdown timer, which will begin counting until it hits
2076 * the value in the TIMERINT register, and then trigger an
2077 * interrupt. Each time we write to the TIMERCNT register,
2078 * the timer count is reset to 0.
2080 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2083 * Set a timeout in case the chip goes out to lunch.
2092 struct rl_softc *sc = xsc;
2101 struct rl_softc *sc;
2103 struct ifnet *ifp = sc->rl_ifp;
2104 struct mii_data *mii;
2105 u_int32_t rxcfg = 0;
2109 mii = device_get_softc(sc->rl_miibus);
2112 * Cancel pending I/O and free all RX/TX buffers.
2117 * Enable C+ RX and TX mode, as well as VLAN stripping and
2118 * RX checksum offload. We must configure the C+ register
2119 * before all others.
2121 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB|
2122 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW|
2123 RL_CPLUSCMD_VLANSTRIP|
2124 (ifp->if_capenable & IFCAP_RXCSUM ?
2125 RL_CPLUSCMD_RXCSUM_ENB : 0));
2128 * Init our MAC address. Even though the chipset
2129 * documentation doesn't mention it, we need to enter "Config
2130 * register write enable" mode to modify the ID registers.
2132 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
2133 CSR_WRITE_STREAM_4(sc, RL_IDR0,
2134 *(u_int32_t *)(&IFP2ENADDR(sc->rl_ifp)[0]));
2135 CSR_WRITE_STREAM_4(sc, RL_IDR4,
2136 *(u_int32_t *)(&IFP2ENADDR(sc->rl_ifp)[4]));
2137 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2140 * For C+ mode, initialize the RX descriptors and mbufs.
2142 re_rx_list_init(sc);
2143 re_tx_list_init(sc);
2146 * Enable transmit and receive.
2148 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2151 * Set the initial TX and RX configuration.
2153 if (sc->rl_testmode) {
2154 if (sc->rl_type == RL_8169)
2155 CSR_WRITE_4(sc, RL_TXCFG,
2156 RL_TXCFG_CONFIG|RL_LOOPTEST_ON);
2158 CSR_WRITE_4(sc, RL_TXCFG,
2159 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
2161 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
2162 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
2164 /* Set the individual bit to receive frames for this host only. */
2165 rxcfg = CSR_READ_4(sc, RL_RXCFG);
2166 rxcfg |= RL_RXCFG_RX_INDIV;
2168 /* If we want promiscuous mode, set the allframes bit. */
2169 if (ifp->if_flags & IFF_PROMISC)
2170 rxcfg |= RL_RXCFG_RX_ALLPHYS;
2172 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
2173 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
2176 * Set capture broadcast bit to capture broadcast frames.
2178 if (ifp->if_flags & IFF_BROADCAST)
2179 rxcfg |= RL_RXCFG_RX_BROAD;
2181 rxcfg &= ~RL_RXCFG_RX_BROAD;
2182 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
2185 * Program the multicast filter, if necessary.
2189 #ifdef DEVICE_POLLING
2191 * Disable interrupts if we are polling.
2193 if (ifp->if_flags & IFF_POLLING)
2194 CSR_WRITE_2(sc, RL_IMR, 0);
2195 else /* otherwise ... */
2196 #endif /* DEVICE_POLLING */
2198 * Enable interrupts.
2200 if (sc->rl_testmode)
2201 CSR_WRITE_2(sc, RL_IMR, 0);
2203 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2205 /* Set initial TX threshold */
2206 sc->rl_txthresh = RL_TX_THRESH_INIT;
2208 /* Start RX/TX process. */
2209 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
2211 /* Enable receiver and transmitter. */
2212 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
2215 * Load the addresses of the RX and TX lists into the chip.
2218 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
2219 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
2220 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
2221 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
2223 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
2224 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
2225 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
2226 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
2228 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
2231 * Initialize the timer interrupt register so that
2232 * a timer interrupt will be generated once the timer
2233 * reaches a certain number of ticks. The timer is
2234 * reloaded on each transmit. This gives us TX interrupt
2235 * moderation, which dramatically improves TX frame rate.
2237 if (sc->rl_type == RL_8169)
2238 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
2240 CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
2243 * For 8169 gigE NICs, set the max allowed RX packet
2244 * size so we can receive jumbo frames.
2246 if (sc->rl_type == RL_8169)
2247 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
2249 if (sc->rl_testmode)
2254 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
2256 ifp->if_flags |= IFF_RUNNING;
2257 ifp->if_flags &= ~IFF_OACTIVE;
2259 sc->rl_stat_ch = timeout(re_tick, sc, hz);
2263 * Set media options.
2269 struct rl_softc *sc;
2270 struct mii_data *mii;
2273 mii = device_get_softc(sc->rl_miibus);
2280 * Report current media status.
2283 re_ifmedia_sts(ifp, ifmr)
2285 struct ifmediareq *ifmr;
2287 struct rl_softc *sc;
2288 struct mii_data *mii;
2291 mii = device_get_softc(sc->rl_miibus);
2294 ifmr->ifm_active = mii->mii_media_active;
2295 ifmr->ifm_status = mii->mii_media_status;
2299 re_ioctl(ifp, command, data)
2304 struct rl_softc *sc = ifp->if_softc;
2305 struct ifreq *ifr = (struct ifreq *) data;
2306 struct mii_data *mii;
2311 if (ifr->ifr_mtu > RL_JUMBO_MTU)
2313 ifp->if_mtu = ifr->ifr_mtu;
2317 if (ifp->if_flags & IFF_UP)
2319 else if (ifp->if_flags & IFF_RUNNING)
2333 mii = device_get_softc(sc->rl_miibus);
2334 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2337 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_POLLING);
2338 ifp->if_capenable |=
2339 ifr->ifr_reqcap & (IFCAP_HWCSUM | IFCAP_POLLING);
2340 if (ifp->if_capenable & IFCAP_TXCSUM)
2341 ifp->if_hwassist = RE_CSUM_FEATURES;
2343 ifp->if_hwassist = 0;
2344 if (ifp->if_flags & IFF_RUNNING)
2348 error = ether_ioctl(ifp, command, data);
2359 struct rl_softc *sc;
2363 printf("re%d: watchdog timeout\n", sc->rl_unit);
2374 * Stop the adapter and free any mbufs allocated to the
2379 struct rl_softc *sc;
2389 untimeout(re_tick, sc, sc->rl_stat_ch);
2390 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2391 #ifdef DEVICE_POLLING
2392 ether_poll_deregister(ifp);
2393 #endif /* DEVICE_POLLING */
2395 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
2396 CSR_WRITE_2(sc, RL_IMR, 0x0000);
2398 if (sc->rl_head != NULL) {
2399 m_freem(sc->rl_head);
2400 sc->rl_head = sc->rl_tail = NULL;
2403 /* Free the TX list buffers. */
2405 for (i = 0; i < RL_TX_DESC_CNT; i++) {
2406 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) {
2407 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
2408 sc->rl_ldata.rl_tx_dmamap[i]);
2409 m_freem(sc->rl_ldata.rl_tx_mbuf[i]);
2410 sc->rl_ldata.rl_tx_mbuf[i] = NULL;
2414 /* Free the RX list buffers. */
2416 for (i = 0; i < RL_RX_DESC_CNT; i++) {
2417 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) {
2418 bus_dmamap_unload(sc->rl_ldata.rl_mtag,
2419 sc->rl_ldata.rl_rx_dmamap[i]);
2420 m_freem(sc->rl_ldata.rl_rx_mbuf[i]);
2421 sc->rl_ldata.rl_rx_mbuf[i] = NULL;
2427 * Device suspend routine. Stop the interface and save some PCI
2428 * settings in case the BIOS doesn't restore them properly on
2435 struct rl_softc *sc;
2437 sc = device_get_softc(dev);
2448 * Device resume routine. Restore some PCI settings in case the BIOS
2449 * doesn't, re-enable busmastering, and restart the interface if
2456 struct rl_softc *sc;
2459 sc = device_get_softc(dev);
2465 /* reinitialize interface if necessary */
2466 if (ifp->if_flags & IFF_UP)
2476 * Stop all chip I/O so that the kernel's probe routines don't
2477 * get confused by errant DMAs when rebooting.
2483 struct rl_softc *sc;
2485 sc = device_get_softc(dev);