2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * RealTek 8129/8139 PCI NIC driver
39 * Supports several extremely cheap PCI 10/100 adapters based on
40 * the RealTek chipset. Datasheets can be obtained from
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
49 * probably the worst PCI ethernet controller ever made, with the possible
50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
51 * DMA, but it has a terrible interface that nullifies any performance
52 * gains that bus-master DMA usually offers.
54 * For transmission, the chip offers a series of four TX descriptor
55 * registers. Each transmit frame must be in a contiguous buffer, aligned
56 * on a longword (32-bit) boundary. This means we almost always have to
57 * do mbuf copies in order to transmit a frame, except in the unlikely
58 * case where a) the packet fits into a single mbuf, and b) the packet
59 * is 32-bit aligned within the mbuf's data area. The presence of only
60 * four descriptor registers means that we can never have more than four
61 * packets queued for transmission at any one time.
63 * Reception is not much better. The driver has to allocate a single large
64 * buffer area (up to 64K in size) into which the chip will DMA received
65 * frames. Because we don't know where within this region received packets
66 * will begin or end, we have no choice but to copy data from the buffer
67 * area into mbufs in order to pass the packets up to the higher protocol
70 * It's impossible given this rotten design to really achieve decent
71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
72 * some equally overmuscled CPU to drive it.
74 * On the bright side, the 8139 does have a built-in PHY, although
75 * rather than using an MDIO serial interface like most other NICs, the
76 * PHY registers are directly accessible through the 8139's register
77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
80 * The 8129 chip is an older version of the 8139 that uses an external PHY
81 * chip. The 8129 has a serial MDIO interface for accessing the MII where
82 * the 8139 lets you directly access the on-board PHY registers. We need
83 * to select which interface to use depending on the chip type.
86 #ifdef HAVE_KERNEL_OPTION_HEADERS
87 #include "opt_device_polling.h"
90 #include <sys/param.h>
91 #include <sys/endian.h>
92 #include <sys/systm.h>
93 #include <sys/sockio.h>
95 #include <sys/malloc.h>
96 #include <sys/kernel.h>
97 #include <sys/module.h>
98 #include <sys/socket.h>
99 #include <sys/sysctl.h>
102 #include <net/if_var.h>
103 #include <net/if_arp.h>
104 #include <net/ethernet.h>
105 #include <net/if_dl.h>
106 #include <net/if_media.h>
107 #include <net/if_types.h>
111 #include <machine/bus.h>
112 #include <machine/resource.h>
114 #include <sys/rman.h>
116 #include <dev/mii/mii.h>
117 #include <dev/mii/mii_bitbang.h>
118 #include <dev/mii/miivar.h>
120 #include <dev/pci/pcireg.h>
121 #include <dev/pci/pcivar.h>
123 MODULE_DEPEND(rl, pci, 1, 1, 1);
124 MODULE_DEPEND(rl, ether, 1, 1, 1);
125 MODULE_DEPEND(rl, miibus, 1, 1, 1);
127 /* "device miibus" required. See GENERIC if you get errors here. */
128 #include "miibus_if.h"
130 #include <dev/rl/if_rlreg.h>
133 * Various supported device vendors/types and their names.
135 static const struct rl_type rl_devs[] = {
136 { RT_VENDORID, RT_DEVICEID_8129, RL_8129,
137 "RealTek 8129 10/100BaseTX" },
138 { RT_VENDORID, RT_DEVICEID_8139, RL_8139,
139 "RealTek 8139 10/100BaseTX" },
140 { RT_VENDORID, RT_DEVICEID_8139D, RL_8139,
141 "RealTek 8139 10/100BaseTX" },
142 { RT_VENDORID, RT_DEVICEID_8138, RL_8139,
143 "RealTek 8139 10/100BaseTX CardBus" },
144 { RT_VENDORID, RT_DEVICEID_8100, RL_8139,
145 "RealTek 8100 10/100BaseTX" },
146 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
147 "Accton MPX 5030/5038 10/100BaseTX" },
148 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
149 "Delta Electronics 8139 10/100BaseTX" },
150 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139,
151 "Addtron Technology 8139 10/100BaseTX" },
152 { DLINK_VENDORID, DLINK_DEVICEID_520TX_REVC1, RL_8139,
153 "D-Link DFE-520TX (rev. C1) 10/100BaseTX" },
154 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139,
155 "D-Link DFE-530TX+ 10/100BaseTX" },
156 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
157 "D-Link DFE-690TXD 10/100BaseTX" },
158 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
159 "Nortel Networks 10/100BaseTX" },
160 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
161 "Corega FEther CB-TXD" },
162 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
163 "Corega FEtherII CB-TXD" },
164 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
165 "Peppercon AG ROL-F" },
166 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3603TX, RL_8139,
167 "Planex FNW-3603-TX" },
168 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
169 "Planex FNW-3800-TX" },
170 { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
172 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
173 "LevelOne FPC-0106TX" },
174 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
175 "Edimax EP-4103DL CardBus" }
178 static int rl_attach(device_t);
179 static int rl_detach(device_t);
180 static void rl_dmamap_cb(void *, bus_dma_segment_t *, int, int);
181 static int rl_dma_alloc(struct rl_softc *);
182 static void rl_dma_free(struct rl_softc *);
183 static void rl_eeprom_putbyte(struct rl_softc *, int);
184 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
185 static int rl_encap(struct rl_softc *, struct mbuf **);
186 static int rl_list_tx_init(struct rl_softc *);
187 static int rl_list_rx_init(struct rl_softc *);
188 static int rl_ifmedia_upd(struct ifnet *);
189 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
190 static int rl_ioctl(struct ifnet *, u_long, caddr_t);
191 static void rl_intr(void *);
192 static void rl_init(void *);
193 static void rl_init_locked(struct rl_softc *sc);
194 static int rl_miibus_readreg(device_t, int, int);
195 static void rl_miibus_statchg(device_t);
196 static int rl_miibus_writereg(device_t, int, int, int);
197 #ifdef DEVICE_POLLING
198 static int rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
199 static int rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
201 static int rl_probe(device_t);
202 static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int);
203 static void rl_reset(struct rl_softc *);
204 static int rl_resume(device_t);
205 static int rl_rxeof(struct rl_softc *);
206 static void rl_rxfilter(struct rl_softc *);
207 static int rl_shutdown(device_t);
208 static void rl_start(struct ifnet *);
209 static void rl_start_locked(struct ifnet *);
210 static void rl_stop(struct rl_softc *);
211 static int rl_suspend(device_t);
212 static void rl_tick(void *);
213 static void rl_txeof(struct rl_softc *);
214 static void rl_watchdog(struct rl_softc *);
215 static void rl_setwol(struct rl_softc *);
216 static void rl_clrwol(struct rl_softc *);
221 static uint32_t rl_mii_bitbang_read(device_t);
222 static void rl_mii_bitbang_write(device_t, uint32_t);
224 static const struct mii_bitbang_ops rl_mii_bitbang_ops = {
226 rl_mii_bitbang_write,
228 RL_MII_DATAOUT, /* MII_BIT_MDO */
229 RL_MII_DATAIN, /* MII_BIT_MDI */
230 RL_MII_CLK, /* MII_BIT_MDC */
231 RL_MII_DIR, /* MII_BIT_DIR_HOST_PHY */
232 0, /* MII_BIT_DIR_PHY_HOST */
236 static device_method_t rl_methods[] = {
237 /* Device interface */
238 DEVMETHOD(device_probe, rl_probe),
239 DEVMETHOD(device_attach, rl_attach),
240 DEVMETHOD(device_detach, rl_detach),
241 DEVMETHOD(device_suspend, rl_suspend),
242 DEVMETHOD(device_resume, rl_resume),
243 DEVMETHOD(device_shutdown, rl_shutdown),
246 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
247 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
248 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
253 static driver_t rl_driver = {
256 sizeof(struct rl_softc)
259 static devclass_t rl_devclass;
261 DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0);
262 MODULE_PNP_INFO("U16:vendor;U16:device", pci, rl, rl_devs,
263 nitems(rl_devs) - 1);
264 DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0);
265 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
268 CSR_WRITE_1(sc, RL_EECMD, \
269 CSR_READ_1(sc, RL_EECMD) | x)
272 CSR_WRITE_1(sc, RL_EECMD, \
273 CSR_READ_1(sc, RL_EECMD) & ~x)
276 * Send a read command and address to the EEPROM, check for ACK.
279 rl_eeprom_putbyte(struct rl_softc *sc, int addr)
283 d = addr | sc->rl_eecmd_read;
286 * Feed in each bit and strobe the clock.
288 for (i = 0x400; i; i >>= 1) {
290 EE_SET(RL_EE_DATAIN);
292 EE_CLR(RL_EE_DATAIN);
303 * Read a word of data stored in the EEPROM at address 'addr.'
306 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
311 /* Enter EEPROM access mode. */
312 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
315 * Send address of word we want to read.
317 rl_eeprom_putbyte(sc, addr);
319 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
322 * Start reading bits from EEPROM.
324 for (i = 0x8000; i; i >>= 1) {
327 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
333 /* Turn off EEPROM access mode. */
334 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
340 * Read a sequence of words from the EEPROM.
343 rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap)
346 uint16_t word = 0, *ptr;
348 for (i = 0; i < cnt; i++) {
349 rl_eeprom_getword(sc, off + i, &word);
350 ptr = (uint16_t *)(dest + (i * 2));
359 * Read the MII serial port for the MII bit-bang module.
362 rl_mii_bitbang_read(device_t dev)
367 sc = device_get_softc(dev);
369 val = CSR_READ_1(sc, RL_MII);
370 CSR_BARRIER(sc, RL_MII, 1,
371 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
377 * Write the MII serial port for the MII bit-bang module.
380 rl_mii_bitbang_write(device_t dev, uint32_t val)
384 sc = device_get_softc(dev);
386 CSR_WRITE_1(sc, RL_MII, val);
387 CSR_BARRIER(sc, RL_MII, 1,
388 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
392 rl_miibus_readreg(device_t dev, int phy, int reg)
397 sc = device_get_softc(dev);
399 if (sc->rl_type == RL_8139) {
402 rl8139_reg = RL_BMCR;
405 rl8139_reg = RL_BMSR;
408 rl8139_reg = RL_ANAR;
411 rl8139_reg = RL_ANER;
414 rl8139_reg = RL_LPAR;
420 * Allow the rlphy driver to read the media status
421 * register. If we have a link partner which does not
422 * support NWAY, this is the register which will tell
423 * us the results of parallel detection.
426 return (CSR_READ_1(sc, RL_MEDIASTAT));
428 device_printf(sc->rl_dev, "bad phy register\n");
431 return (CSR_READ_2(sc, rl8139_reg));
434 return (mii_bitbang_readreg(dev, &rl_mii_bitbang_ops, phy, reg));
438 rl_miibus_writereg(device_t dev, int phy, int reg, int data)
443 sc = device_get_softc(dev);
445 if (sc->rl_type == RL_8139) {
448 rl8139_reg = RL_BMCR;
451 rl8139_reg = RL_BMSR;
454 rl8139_reg = RL_ANAR;
457 rl8139_reg = RL_ANER;
460 rl8139_reg = RL_LPAR;
467 device_printf(sc->rl_dev, "bad phy register\n");
470 CSR_WRITE_2(sc, rl8139_reg, data);
474 mii_bitbang_writereg(dev, &rl_mii_bitbang_ops, phy, reg, data);
480 rl_miibus_statchg(device_t dev)
484 struct mii_data *mii;
486 sc = device_get_softc(dev);
487 mii = device_get_softc(sc->rl_miibus);
489 if (mii == NULL || ifp == NULL ||
490 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
493 sc->rl_flags &= ~RL_FLAG_LINK;
494 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
495 (IFM_ACTIVE | IFM_AVALID)) {
496 switch (IFM_SUBTYPE(mii->mii_media_active)) {
499 sc->rl_flags |= RL_FLAG_LINK;
506 * RealTek controllers do not provide any interface to
507 * Tx/Rx MACs for resolved speed, duplex and flow-control
513 rl_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
515 uint32_t *hashes = arg;
518 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
520 hashes[0] |= (1 << h);
522 hashes[1] |= (1 << (h - 32));
528 * Program the 64-bit multicast hash filter.
531 rl_rxfilter(struct rl_softc *sc)
533 struct ifnet *ifp = sc->rl_ifp;
534 uint32_t hashes[2] = { 0, 0 };
539 rxfilt = CSR_READ_4(sc, RL_RXCFG);
540 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_BROAD |
542 /* Always accept frames destined for this host. */
543 rxfilt |= RL_RXCFG_RX_INDIV;
544 /* Set capture broadcast bit to capture broadcast frames. */
545 if (ifp->if_flags & IFF_BROADCAST)
546 rxfilt |= RL_RXCFG_RX_BROAD;
547 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
548 rxfilt |= RL_RXCFG_RX_MULTI;
549 if (ifp->if_flags & IFF_PROMISC)
550 rxfilt |= RL_RXCFG_RX_ALLPHYS;
551 hashes[0] = 0xFFFFFFFF;
552 hashes[1] = 0xFFFFFFFF;
554 /* Now program new ones. */
555 if_foreach_llmaddr(ifp, rl_hash_maddr, hashes);
556 if (hashes[0] != 0 || hashes[1] != 0)
557 rxfilt |= RL_RXCFG_RX_MULTI;
560 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
561 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
562 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
566 rl_reset(struct rl_softc *sc)
572 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
574 for (i = 0; i < RL_TIMEOUT; i++) {
576 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
580 device_printf(sc->rl_dev, "reset never completed!\n");
584 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
585 * IDs against our list and return a device name if we find a match.
588 rl_probe(device_t dev)
590 const struct rl_type *t;
591 uint16_t devid, revid, vendor;
594 vendor = pci_get_vendor(dev);
595 devid = pci_get_device(dev);
596 revid = pci_get_revid(dev);
598 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
600 /* 8139C+, let re(4) take care of this device. */
605 for (i = 0; i < nitems(rl_devs); i++, t++) {
606 if (vendor == t->rl_vid && devid == t->rl_did) {
607 device_set_desc(dev, t->rl_name);
608 return (BUS_PROBE_DEFAULT);
615 struct rl_dmamap_arg {
616 bus_addr_t rl_busaddr;
620 rl_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
622 struct rl_dmamap_arg *ctx;
627 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
629 ctx = (struct rl_dmamap_arg *)arg;
630 ctx->rl_busaddr = segs[0].ds_addr;
634 * Attach the interface. Allocate softc structures, do ifmedia
635 * setup and ethernet/BPF attach.
638 rl_attach(device_t dev)
640 uint8_t eaddr[ETHER_ADDR_LEN];
644 const struct rl_type *t;
645 struct sysctl_ctx_list *ctx;
646 struct sysctl_oid_list *children;
647 int error = 0, hwrev, i, phy, pmc, rid;
648 int prefer_iomap, unit;
652 sc = device_get_softc(dev);
653 unit = device_get_unit(dev);
656 sc->rl_twister_enable = 0;
657 snprintf(tn, sizeof(tn), "dev.rl.%d.twister_enable", unit);
658 TUNABLE_INT_FETCH(tn, &sc->rl_twister_enable);
659 ctx = device_get_sysctl_ctx(sc->rl_dev);
660 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
661 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "twister_enable", CTLFLAG_RD,
662 &sc->rl_twister_enable, 0, "");
664 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
666 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
668 pci_enable_busmaster(dev);
671 * Map control/status registers.
672 * Default to using PIO access for this driver. On SMP systems,
673 * there appear to be problems with memory mapped mode: it looks
674 * like doing too many memory mapped access back to back in rapid
675 * succession can hang the bus. I'm inclined to blame this on
676 * crummy design/construction on the part of RealTek. Memory
677 * mapped mode does appear to work on uniprocessor systems though.
680 snprintf(tn, sizeof(tn), "dev.rl.%d.prefer_iomap", unit);
681 TUNABLE_INT_FETCH(tn, &prefer_iomap);
683 sc->rl_res_id = PCIR_BAR(0);
684 sc->rl_res_type = SYS_RES_IOPORT;
685 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
686 &sc->rl_res_id, RF_ACTIVE);
688 if (prefer_iomap == 0 || sc->rl_res == NULL) {
689 sc->rl_res_id = PCIR_BAR(1);
690 sc->rl_res_type = SYS_RES_MEMORY;
691 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
692 &sc->rl_res_id, RF_ACTIVE);
694 if (sc->rl_res == NULL) {
695 device_printf(dev, "couldn't map ports/memory\n");
702 * Detect the Realtek 8139B. For some reason, this chip is very
703 * unstable when left to autoselect the media
704 * The best workaround is to set the device to the required
705 * media type or to set it to the 10 Meg speed.
707 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
709 "Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n");
712 sc->rl_btag = rman_get_bustag(sc->rl_res);
713 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
715 /* Allocate interrupt */
717 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
718 RF_SHAREABLE | RF_ACTIVE);
720 if (sc->rl_irq[0] == NULL) {
721 device_printf(dev, "couldn't map interrupt\n");
726 sc->rl_cfg0 = RL_8139_CFG0;
727 sc->rl_cfg1 = RL_8139_CFG1;
729 sc->rl_cfg3 = RL_8139_CFG3;
730 sc->rl_cfg4 = RL_8139_CFG4;
731 sc->rl_cfg5 = RL_8139_CFG5;
734 * Reset the adapter. Only take the lock here as it's needed in
735 * order to call rl_reset().
741 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
742 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
743 if (rl_did != 0x8129)
744 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
747 * Get station address from the EEPROM.
749 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0);
750 for (i = 0; i < 3; i++) {
751 eaddr[(i * 2) + 0] = as[i] & 0xff;
752 eaddr[(i * 2) + 1] = as[i] >> 8;
756 * Now read the exact device type from the EEPROM to find
757 * out if it's an 8129 or 8139.
759 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0);
763 while(t->rl_name != NULL) {
764 if (rl_did == t->rl_did) {
765 sc->rl_type = t->rl_basetype;
771 if (sc->rl_type == 0) {
772 device_printf(dev, "unknown device ID: %x assuming 8139\n",
774 sc->rl_type = RL_8139;
776 * Read RL_IDR register to get ethernet address as accessing
777 * EEPROM may not extract correct address.
779 for (i = 0; i < ETHER_ADDR_LEN; i++)
780 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
783 if ((error = rl_dma_alloc(sc)) != 0)
786 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
788 device_printf(dev, "can not if_alloc()\n");
793 #define RL_PHYAD_INTERNAL 0
797 if (sc->rl_type == RL_8139)
798 phy = RL_PHYAD_INTERNAL;
799 error = mii_attach(dev, &sc->rl_miibus, ifp, rl_ifmedia_upd,
800 rl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
802 device_printf(dev, "attaching PHYs failed\n");
807 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
808 ifp->if_mtu = ETHERMTU;
809 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
810 ifp->if_ioctl = rl_ioctl;
811 ifp->if_start = rl_start;
812 ifp->if_init = rl_init;
813 ifp->if_capabilities = IFCAP_VLAN_MTU;
814 /* Check WOL for RTL8139B or newer controllers. */
815 if (sc->rl_type == RL_8139 &&
816 pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) {
817 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
825 ifp->if_capabilities |= IFCAP_WOL;
833 ifp->if_capenable = ifp->if_capabilities;
834 ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST);
835 #ifdef DEVICE_POLLING
836 ifp->if_capabilities |= IFCAP_POLLING;
838 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
839 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
840 IFQ_SET_READY(&ifp->if_snd);
843 * Call MI attach routine.
845 ether_ifattach(ifp, eaddr);
847 /* Hook interrupt last to avoid having to lock softc */
848 error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE,
849 NULL, rl_intr, sc, &sc->rl_intrhand[0]);
851 device_printf(sc->rl_dev, "couldn't set up irq\n");
863 * Shutdown hardware and free up resources. This can be called any
864 * time after the mutex has been initialized. It is called in both
865 * the error case in attach and the normal detach case so it needs
866 * to be careful about only freeing resources that have actually been
870 rl_detach(device_t dev)
875 sc = device_get_softc(dev);
878 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
880 #ifdef DEVICE_POLLING
881 if (ifp->if_capenable & IFCAP_POLLING)
882 ether_poll_deregister(ifp);
884 /* These should only be active if attach succeeded */
885 if (device_is_attached(dev)) {
889 callout_drain(&sc->rl_stat_callout);
896 device_delete_child(dev, sc->rl_miibus);
897 bus_generic_detach(dev);
899 if (sc->rl_intrhand[0])
900 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
902 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]);
904 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id,
912 mtx_destroy(&sc->rl_mtx);
918 rl_dma_alloc(struct rl_softc *sc)
920 struct rl_dmamap_arg ctx;
924 * Allocate the parent bus DMA tag appropriate for PCI.
926 error = bus_dma_tag_create(bus_get_dma_tag(sc->rl_dev), /* parent */
927 1, 0, /* alignment, boundary */
928 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
929 BUS_SPACE_MAXADDR, /* highaddr */
930 NULL, NULL, /* filter, filterarg */
931 BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */
932 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
934 NULL, NULL, /* lockfunc, lockarg */
937 device_printf(sc->rl_dev,
938 "failed to create parent DMA tag.\n");
941 /* Create DMA tag for Rx memory block. */
942 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
943 RL_RX_8139_BUF_ALIGN, 0, /* alignment, boundary */
944 BUS_SPACE_MAXADDR, /* lowaddr */
945 BUS_SPACE_MAXADDR, /* highaddr */
946 NULL, NULL, /* filter, filterarg */
947 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, 1, /* maxsize,nsegments */
948 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, /* maxsegsize */
950 NULL, NULL, /* lockfunc, lockarg */
951 &sc->rl_cdata.rl_rx_tag);
953 device_printf(sc->rl_dev,
954 "failed to create Rx memory block DMA tag.\n");
957 /* Create DMA tag for Tx buffer. */
958 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
959 RL_TX_8139_BUF_ALIGN, 0, /* alignment, boundary */
960 BUS_SPACE_MAXADDR, /* lowaddr */
961 BUS_SPACE_MAXADDR, /* highaddr */
962 NULL, NULL, /* filter, filterarg */
963 MCLBYTES, 1, /* maxsize, nsegments */
964 MCLBYTES, /* maxsegsize */
966 NULL, NULL, /* lockfunc, lockarg */
967 &sc->rl_cdata.rl_tx_tag);
969 device_printf(sc->rl_dev, "failed to create Tx DMA tag.\n");
974 * Allocate DMA'able memory and load DMA map for Rx memory block.
976 error = bus_dmamem_alloc(sc->rl_cdata.rl_rx_tag,
977 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_WAITOK |
978 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->rl_cdata.rl_rx_dmamap);
980 device_printf(sc->rl_dev,
981 "failed to allocate Rx DMA memory block.\n");
985 error = bus_dmamap_load(sc->rl_cdata.rl_rx_tag,
986 sc->rl_cdata.rl_rx_dmamap, sc->rl_cdata.rl_rx_buf,
987 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, rl_dmamap_cb, &ctx,
989 if (error != 0 || ctx.rl_busaddr == 0) {
990 device_printf(sc->rl_dev,
991 "could not load Rx DMA memory block.\n");
994 sc->rl_cdata.rl_rx_buf_paddr = ctx.rl_busaddr;
996 /* Create DMA maps for Tx buffers. */
997 for (i = 0; i < RL_TX_LIST_CNT; i++) {
998 sc->rl_cdata.rl_tx_chain[i] = NULL;
999 sc->rl_cdata.rl_tx_dmamap[i] = NULL;
1000 error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag, 0,
1001 &sc->rl_cdata.rl_tx_dmamap[i]);
1003 device_printf(sc->rl_dev,
1004 "could not create Tx dmamap.\n");
1009 /* Leave a few bytes before the start of the RX ring buffer. */
1010 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
1011 sc->rl_cdata.rl_rx_buf += RL_RX_8139_BUF_RESERVE;
1018 rl_dma_free(struct rl_softc *sc)
1022 /* Rx memory block. */
1023 if (sc->rl_cdata.rl_rx_tag != NULL) {
1024 if (sc->rl_cdata.rl_rx_buf_paddr != 0)
1025 bus_dmamap_unload(sc->rl_cdata.rl_rx_tag,
1026 sc->rl_cdata.rl_rx_dmamap);
1027 if (sc->rl_cdata.rl_rx_buf_ptr != NULL)
1028 bus_dmamem_free(sc->rl_cdata.rl_rx_tag,
1029 sc->rl_cdata.rl_rx_buf_ptr,
1030 sc->rl_cdata.rl_rx_dmamap);
1031 sc->rl_cdata.rl_rx_buf_ptr = NULL;
1032 sc->rl_cdata.rl_rx_buf = NULL;
1033 sc->rl_cdata.rl_rx_buf_paddr = 0;
1034 bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag);
1035 sc->rl_cdata.rl_tx_tag = NULL;
1039 if (sc->rl_cdata.rl_tx_tag != NULL) {
1040 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1041 if (sc->rl_cdata.rl_tx_dmamap[i] != NULL) {
1043 sc->rl_cdata.rl_tx_tag,
1044 sc->rl_cdata.rl_tx_dmamap[i]);
1045 sc->rl_cdata.rl_tx_dmamap[i] = NULL;
1048 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag);
1049 sc->rl_cdata.rl_tx_tag = NULL;
1052 if (sc->rl_parent_tag != NULL) {
1053 bus_dma_tag_destroy(sc->rl_parent_tag);
1054 sc->rl_parent_tag = NULL;
1059 * Initialize the transmit descriptors.
1062 rl_list_tx_init(struct rl_softc *sc)
1064 struct rl_chain_data *cd;
1070 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1071 cd->rl_tx_chain[i] = NULL;
1073 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
1076 sc->rl_cdata.cur_tx = 0;
1077 sc->rl_cdata.last_tx = 0;
1083 rl_list_rx_init(struct rl_softc *sc)
1088 bzero(sc->rl_cdata.rl_rx_buf_ptr,
1089 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ);
1090 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, sc->rl_cdata.rl_rx_dmamap,
1091 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1097 * A frame has been uploaded: pass the resulting mbuf chain up to
1098 * the higher level protocols.
1100 * You know there's something wrong with a PCI bus-master chip design
1101 * when you have to use m_devget().
1103 * The receive operation is badly documented in the datasheet, so I'll
1104 * attempt to document it here. The driver provides a buffer area and
1105 * places its base address in the RX buffer start address register.
1106 * The chip then begins copying frames into the RX buffer. Each frame
1107 * is preceded by a 32-bit RX status word which specifies the length
1108 * of the frame and certain other status bits. Each frame (starting with
1109 * the status word) is also 32-bit aligned. The frame length is in the
1110 * first 16 bits of the status word; the lower 15 bits correspond with
1111 * the 'rx status register' mentioned in the datasheet.
1113 * Note: to make the Alpha happy, the frame payload needs to be aligned
1114 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1115 * as the offset argument to m_devget().
1118 rl_rxeof(struct rl_softc *sc)
1121 struct ifnet *ifp = sc->rl_ifp;
1129 uint16_t max_bytes, rx_bytes = 0;
1133 bus_dmamap_sync(sc->rl_cdata.rl_rx_tag, sc->rl_cdata.rl_rx_dmamap,
1134 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1136 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1138 /* Do not try to read past this point. */
1139 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1142 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1144 max_bytes = limit - cur_rx;
1146 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1147 #ifdef DEVICE_POLLING
1148 if (ifp->if_capenable & IFCAP_POLLING) {
1149 if (sc->rxcycles <= 0)
1154 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1155 rxstat = le32toh(*(uint32_t *)rxbufpos);
1158 * Here's a totally undocumented fact for you. When the
1159 * RealTek chip is in the process of copying a packet into
1160 * RAM for you, the length will be 0xfff0. If you spot a
1161 * packet header with this value, you need to stop. The
1162 * datasheet makes absolutely no mention of this and
1163 * RealTek should be shot for this.
1165 total_len = rxstat >> 16;
1166 if (total_len == RL_RXSTAT_UNFINISHED)
1169 if (!(rxstat & RL_RXSTAT_RXOK) ||
1170 total_len < ETHER_MIN_LEN ||
1171 total_len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) {
1172 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1173 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1178 /* No errors; receive the packet. */
1179 rx_bytes += total_len + 4;
1182 * XXX The RealTek chip includes the CRC with every
1183 * received frame, and there's no way to turn this
1184 * behavior off (at least, I can't find anything in
1185 * the manual that explains how to do it) so we have
1186 * to trim off the CRC manually.
1188 total_len -= ETHER_CRC_LEN;
1191 * Avoid trying to read more bytes than we know
1192 * the chip has prepared for us.
1194 if (rx_bytes > max_bytes)
1197 rxbufpos = sc->rl_cdata.rl_rx_buf +
1198 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1199 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1200 rxbufpos = sc->rl_cdata.rl_rx_buf;
1202 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1203 if (total_len > wrap) {
1204 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1207 m_copyback(m, wrap, total_len - wrap,
1208 sc->rl_cdata.rl_rx_buf);
1209 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1211 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1213 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1216 /* Round up to 32-bit boundary. */
1217 cur_rx = (cur_rx + 3) & ~3;
1218 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1221 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1225 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1227 (*ifp->if_input)(ifp, m);
1232 /* No need to sync Rx memory block as we didn't modify it. */
1237 * A frame was downloaded to the chip. It's safe for us to clean up
1241 rl_txeof(struct rl_softc *sc)
1243 struct ifnet *ifp = sc->rl_ifp;
1249 * Go through our tx list and free mbufs for those
1250 * frames that have been uploaded.
1253 if (RL_LAST_TXMBUF(sc) == NULL)
1255 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1256 if (!(txstat & (RL_TXSTAT_TX_OK|
1257 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1260 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (txstat & RL_TXSTAT_COLLCNT) >> 24);
1262 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc),
1263 BUS_DMASYNC_POSTWRITE);
1264 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc));
1265 m_freem(RL_LAST_TXMBUF(sc));
1266 RL_LAST_TXMBUF(sc) = NULL;
1268 * If there was a transmit underrun, bump the TX threshold.
1269 * Make sure not to overflow the 63 * 32byte we can address
1270 * with the 6 available bit.
1272 if ((txstat & RL_TXSTAT_TX_UNDERRUN) &&
1273 (sc->rl_txthresh < 2016))
1274 sc->rl_txthresh += 32;
1275 if (txstat & RL_TXSTAT_TX_OK)
1276 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1279 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1280 if ((txstat & RL_TXSTAT_TXABRT) ||
1281 (txstat & RL_TXSTAT_OUTOFWIN))
1282 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1283 oldthresh = sc->rl_txthresh;
1284 /* error recovery */
1285 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1287 /* restore original threshold */
1288 sc->rl_txthresh = oldthresh;
1291 RL_INC(sc->rl_cdata.last_tx);
1292 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1293 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1295 if (RL_LAST_TXMBUF(sc) == NULL)
1296 sc->rl_watchdog_timer = 0;
1300 rl_twister_update(struct rl_softc *sc)
1304 * Table provided by RealTek (Kinston <shangh@realtek.com.tw>) for
1305 * Linux driver. Values undocumented otherwise.
1307 static const uint32_t param[4][4] = {
1308 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1309 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1310 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1311 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1315 * Tune the so-called twister registers of the RTL8139. These
1316 * are used to compensate for impedance mismatches. The
1317 * method for tuning these registers is undocumented and the
1318 * following procedure is collected from public sources.
1320 switch (sc->rl_twister)
1324 * If we have a sufficient link, then we can proceed in
1325 * the state machine to the next stage. If not, then
1326 * disable further tuning after writing sane defaults.
1328 if (CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_LINK_OK) {
1329 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_OFF_CMD);
1330 sc->rl_twister = FIND_ROW;
1332 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_CMD);
1333 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST);
1334 CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF);
1335 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF);
1336 sc->rl_twister = DONE;
1341 * Read how long it took to see the echo to find the tuning
1344 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
1345 if (linktest == RL_CSCFG_ROW3)
1346 sc->rl_twist_row = 3;
1347 else if (linktest == RL_CSCFG_ROW2)
1348 sc->rl_twist_row = 2;
1349 else if (linktest == RL_CSCFG_ROW1)
1350 sc->rl_twist_row = 1;
1352 sc->rl_twist_row = 0;
1353 sc->rl_twist_col = 0;
1354 sc->rl_twister = SET_PARAM;
1357 if (sc->rl_twist_col == 0)
1358 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET);
1359 CSR_WRITE_4(sc, RL_PARA7C,
1360 param[sc->rl_twist_row][sc->rl_twist_col]);
1361 if (++sc->rl_twist_col == 4) {
1362 if (sc->rl_twist_row == 3)
1363 sc->rl_twister = RECHK_LONG;
1365 sc->rl_twister = DONE;
1370 * For long cables, we have to double check to make sure we
1373 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
1374 if (linktest == RL_CSCFG_ROW3)
1375 sc->rl_twister = DONE;
1377 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_RETUNE);
1378 sc->rl_twister = RETUNE;
1382 /* Retune for a shorter cable (try column 2) */
1383 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST);
1384 CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF);
1385 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF);
1386 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET);
1388 sc->rl_twist_col = 0;
1389 sc->rl_twister = SET_PARAM;
1401 struct rl_softc *sc = xsc;
1402 struct mii_data *mii;
1407 * If we're doing the twister cable calibration, then we need to defer
1408 * watchdog timeouts. This is a no-op in normal operations, but
1409 * can falsely trigger when the cable calibration takes a while and
1410 * there was traffic ready to go when rl was started.
1412 * We don't defer mii_tick since that updates the mii status, which
1413 * helps the twister process, at least according to similar patches
1414 * for the Linux driver I found online while doing the fixes. Worst
1415 * case is a few extra mii reads during calibration.
1417 mii = device_get_softc(sc->rl_miibus);
1419 if ((sc->rl_flags & RL_FLAG_LINK) == 0)
1420 rl_miibus_statchg(sc->rl_dev);
1421 if (sc->rl_twister_enable) {
1422 if (sc->rl_twister == DONE)
1425 rl_twister_update(sc);
1426 if (sc->rl_twister == DONE)
1435 callout_reset(&sc->rl_stat_callout, ticks, rl_tick, sc);
1438 #ifdef DEVICE_POLLING
1440 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1442 struct rl_softc *sc = ifp->if_softc;
1446 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1447 rx_npkts = rl_poll_locked(ifp, cmd, count);
1453 rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1455 struct rl_softc *sc = ifp->if_softc;
1460 sc->rxcycles = count;
1461 rx_npkts = rl_rxeof(sc);
1464 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1465 rl_start_locked(ifp);
1467 if (cmd == POLL_AND_CHECK_STATUS) {
1470 /* We should also check the status register. */
1471 status = CSR_READ_2(sc, RL_ISR);
1472 if (status == 0xffff)
1475 CSR_WRITE_2(sc, RL_ISR, status);
1477 /* XXX We should check behaviour on receiver stalls. */
1479 if (status & RL_ISR_SYSTEM_ERR) {
1480 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1486 #endif /* DEVICE_POLLING */
1491 struct rl_softc *sc = arg;
1492 struct ifnet *ifp = sc->rl_ifp;
1501 #ifdef DEVICE_POLLING
1502 if (ifp->if_capenable & IFCAP_POLLING)
1506 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1508 status = CSR_READ_2(sc, RL_ISR);
1509 if (status == 0xffff || (status & RL_INTRS) == 0)
1512 * Ours, disable further interrupts.
1514 CSR_WRITE_2(sc, RL_IMR, 0);
1515 for (count = 16; count > 0; count--) {
1516 CSR_WRITE_2(sc, RL_ISR, status);
1517 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1518 if (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR))
1520 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR))
1522 if (status & RL_ISR_SYSTEM_ERR) {
1523 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1529 status = CSR_READ_2(sc, RL_ISR);
1530 /* If the card has gone away, the read returns 0xffff. */
1531 if (status == 0xffff || (status & RL_INTRS) == 0)
1535 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1536 rl_start_locked(ifp);
1539 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1540 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1546 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1547 * pointers to the fragment pointers.
1550 rl_encap(struct rl_softc *sc, struct mbuf **m_head)
1553 bus_dma_segment_t txsegs[1];
1554 int error, nsegs, padlen;
1561 * Hardware doesn't auto-pad, so we have to make sure
1562 * pad short frames out to the minimum frame length.
1564 if (m->m_pkthdr.len < RL_MIN_FRAMELEN)
1565 padlen = RL_MIN_FRAMELEN - m->m_pkthdr.len;
1567 * The RealTek is brain damaged and wants longword-aligned
1568 * TX buffers, plus we can only have one fragment buffer
1569 * per packet. We have to copy pretty much all the time.
1571 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0 ||
1572 (padlen > 0 && M_TRAILINGSPACE(m) < padlen)) {
1573 m = m_defrag(*m_head, M_NOWAIT);
1584 * Make security-conscious people happy: zero out the
1585 * bytes in the pad area, since we don't know what
1586 * this mbuf cluster buffer's previous user might
1589 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1590 m->m_pkthdr.len += padlen;
1591 m->m_len = m->m_pkthdr.len;
1594 error = bus_dmamap_load_mbuf_sg(sc->rl_cdata.rl_tx_tag,
1595 RL_CUR_DMAMAP(sc), m, txsegs, &nsegs, 0);
1604 RL_CUR_TXMBUF(sc) = m;
1605 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc),
1606 BUS_DMASYNC_PREWRITE);
1607 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), RL_ADDR_LO(txsegs[0].ds_addr));
1613 * Main transmit routine.
1616 rl_start(struct ifnet *ifp)
1618 struct rl_softc *sc = ifp->if_softc;
1621 rl_start_locked(ifp);
1626 rl_start_locked(struct ifnet *ifp)
1628 struct rl_softc *sc = ifp->if_softc;
1629 struct mbuf *m_head = NULL;
1633 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1634 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
1637 while (RL_CUR_TXMBUF(sc) == NULL) {
1638 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1643 if (rl_encap(sc, &m_head)) {
1646 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1647 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1651 /* Pass a copy of this mbuf chain to the bpf subsystem. */
1652 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1654 /* Transmit the frame. */
1655 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1656 RL_TXTHRESH(sc->rl_txthresh) |
1657 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1659 RL_INC(sc->rl_cdata.cur_tx);
1661 /* Set a timeout in case the chip goes out to lunch. */
1662 sc->rl_watchdog_timer = 5;
1666 * We broke out of the loop because all our TX slots are
1667 * full. Mark the NIC as busy until it drains some of the
1668 * packets from the queue.
1670 if (RL_CUR_TXMBUF(sc) != NULL)
1671 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1677 struct rl_softc *sc = xsc;
1685 rl_init_locked(struct rl_softc *sc)
1687 struct ifnet *ifp = sc->rl_ifp;
1688 struct mii_data *mii;
1693 mii = device_get_softc(sc->rl_miibus);
1695 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1699 * Cancel pending I/O and free all RX/TX buffers.
1704 if (sc->rl_twister_enable) {
1706 * Reset twister register tuning state. The twister
1707 * registers and their tuning are undocumented, but
1708 * are necessary to cope with bad links. rl_twister =
1709 * DONE here will disable this entirely.
1711 sc->rl_twister = CHK_LINK;
1715 * Init our MAC address. Even though the chipset
1716 * documentation doesn't mention it, we need to enter "Config
1717 * register write enable" mode to modify the ID registers.
1719 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1720 bzero(eaddr, sizeof(eaddr));
1721 bcopy(IF_LLADDR(sc->rl_ifp), eaddr, ETHER_ADDR_LEN);
1722 CSR_WRITE_STREAM_4(sc, RL_IDR0, eaddr[0]);
1723 CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]);
1724 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1726 /* Init the RX memory block pointer register. */
1727 CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr +
1728 RL_RX_8139_BUF_RESERVE);
1729 /* Init TX descriptors. */
1730 rl_list_tx_init(sc);
1731 /* Init Rx memory block. */
1732 rl_list_rx_init(sc);
1735 * Enable transmit and receive.
1737 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1740 * Set the initial TX and RX configuration.
1742 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1743 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1745 /* Set RX filter. */
1748 #ifdef DEVICE_POLLING
1749 /* Disable interrupts if we are polling. */
1750 if (ifp->if_capenable & IFCAP_POLLING)
1751 CSR_WRITE_2(sc, RL_IMR, 0);
1754 /* Enable interrupts. */
1755 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1757 /* Set initial TX threshold */
1758 sc->rl_txthresh = RL_TX_THRESH_INIT;
1760 /* Start RX/TX process. */
1761 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1763 /* Enable receiver and transmitter. */
1764 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1766 sc->rl_flags &= ~RL_FLAG_LINK;
1769 CSR_WRITE_1(sc, sc->rl_cfg1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1771 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1772 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1774 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1778 * Set media options.
1781 rl_ifmedia_upd(struct ifnet *ifp)
1783 struct rl_softc *sc = ifp->if_softc;
1784 struct mii_data *mii;
1786 mii = device_get_softc(sc->rl_miibus);
1796 * Report current media status.
1799 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1801 struct rl_softc *sc = ifp->if_softc;
1802 struct mii_data *mii;
1804 mii = device_get_softc(sc->rl_miibus);
1808 ifmr->ifm_active = mii->mii_media_active;
1809 ifmr->ifm_status = mii->mii_media_status;
1814 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1816 struct ifreq *ifr = (struct ifreq *)data;
1817 struct mii_data *mii;
1818 struct rl_softc *sc = ifp->if_softc;
1819 int error = 0, mask;
1824 if (ifp->if_flags & IFF_UP) {
1825 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1826 ((ifp->if_flags ^ sc->rl_if_flags) &
1827 (IFF_PROMISC | IFF_ALLMULTI)))
1831 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1833 sc->rl_if_flags = ifp->if_flags;
1844 mii = device_get_softc(sc->rl_miibus);
1845 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1848 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1849 #ifdef DEVICE_POLLING
1850 if (ifr->ifr_reqcap & IFCAP_POLLING &&
1851 !(ifp->if_capenable & IFCAP_POLLING)) {
1852 error = ether_poll_register(rl_poll, ifp);
1856 /* Disable interrupts */
1857 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1858 ifp->if_capenable |= IFCAP_POLLING;
1863 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
1864 ifp->if_capenable & IFCAP_POLLING) {
1865 error = ether_poll_deregister(ifp);
1866 /* Enable interrupts. */
1868 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1869 ifp->if_capenable &= ~IFCAP_POLLING;
1873 #endif /* DEVICE_POLLING */
1874 if ((mask & IFCAP_WOL) != 0 &&
1875 (ifp->if_capabilities & IFCAP_WOL) != 0) {
1876 if ((mask & IFCAP_WOL_UCAST) != 0)
1877 ifp->if_capenable ^= IFCAP_WOL_UCAST;
1878 if ((mask & IFCAP_WOL_MCAST) != 0)
1879 ifp->if_capenable ^= IFCAP_WOL_MCAST;
1880 if ((mask & IFCAP_WOL_MAGIC) != 0)
1881 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1885 error = ether_ioctl(ifp, command, data);
1893 rl_watchdog(struct rl_softc *sc)
1898 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer >0)
1901 device_printf(sc->rl_dev, "watchdog timeout\n");
1902 if_inc_counter(sc->rl_ifp, IFCOUNTER_OERRORS, 1);
1906 sc->rl_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1911 * Stop the adapter and free any mbufs allocated to the
1915 rl_stop(struct rl_softc *sc)
1918 struct ifnet *ifp = sc->rl_ifp;
1922 sc->rl_watchdog_timer = 0;
1923 callout_stop(&sc->rl_stat_callout);
1924 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1925 sc->rl_flags &= ~RL_FLAG_LINK;
1927 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1928 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1929 for (i = 0; i < RL_TIMEOUT; i++) {
1931 if ((CSR_READ_1(sc, RL_COMMAND) &
1932 (RL_CMD_RX_ENB | RL_CMD_TX_ENB)) == 0)
1935 if (i == RL_TIMEOUT)
1936 device_printf(sc->rl_dev, "Unable to stop Tx/Rx MAC\n");
1939 * Free the TX list buffers.
1941 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1942 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1943 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag,
1944 sc->rl_cdata.rl_tx_dmamap[i],
1945 BUS_DMASYNC_POSTWRITE);
1946 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag,
1947 sc->rl_cdata.rl_tx_dmamap[i]);
1948 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1949 sc->rl_cdata.rl_tx_chain[i] = NULL;
1950 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1957 * Device suspend routine. Stop the interface and save some PCI
1958 * settings in case the BIOS doesn't restore them properly on
1962 rl_suspend(device_t dev)
1964 struct rl_softc *sc;
1966 sc = device_get_softc(dev);
1978 * Device resume routine. Restore some PCI settings in case the BIOS
1979 * doesn't, re-enable busmastering, and restart the interface if
1983 rl_resume(device_t dev)
1985 struct rl_softc *sc;
1990 sc = device_get_softc(dev);
1995 if ((ifp->if_capabilities & IFCAP_WOL) != 0 &&
1996 pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) {
1997 /* Disable PME and clear PME status. */
1998 pmstat = pci_read_config(sc->rl_dev,
1999 pmc + PCIR_POWER_STATUS, 2);
2000 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
2001 pmstat &= ~PCIM_PSTAT_PMEENABLE;
2002 pci_write_config(sc->rl_dev,
2003 pmc + PCIR_POWER_STATUS, pmstat, 2);
2006 * Clear WOL matching such that normal Rx filtering
2007 * wouldn't interfere with WOL patterns.
2012 /* reinitialize interface if necessary */
2013 if (ifp->if_flags & IFF_UP)
2024 * Stop all chip I/O so that the kernel's probe routines don't
2025 * get confused by errant DMAs when rebooting.
2028 rl_shutdown(device_t dev)
2030 struct rl_softc *sc;
2032 sc = device_get_softc(dev);
2037 * Mark interface as down since otherwise we will panic if
2038 * interrupt comes in later on, which can happen in some
2041 sc->rl_ifp->if_flags &= ~IFF_UP;
2049 rl_setwol(struct rl_softc *sc)
2059 if ((ifp->if_capabilities & IFCAP_WOL) == 0)
2061 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
2064 /* Enable config register write. */
2065 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
2068 v = CSR_READ_1(sc, sc->rl_cfg1);
2070 if ((ifp->if_capenable & IFCAP_WOL) != 0)
2072 CSR_WRITE_1(sc, sc->rl_cfg1, v);
2074 v = CSR_READ_1(sc, sc->rl_cfg3);
2075 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
2076 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2077 v |= RL_CFG3_WOL_MAGIC;
2078 CSR_WRITE_1(sc, sc->rl_cfg3, v);
2080 v = CSR_READ_1(sc, sc->rl_cfg5);
2081 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
2082 v &= ~RL_CFG5_WOL_LANWAKE;
2083 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
2084 v |= RL_CFG5_WOL_UCAST;
2085 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
2086 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
2087 if ((ifp->if_capenable & IFCAP_WOL) != 0)
2088 v |= RL_CFG5_WOL_LANWAKE;
2089 CSR_WRITE_1(sc, sc->rl_cfg5, v);
2091 /* Config register write done. */
2092 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2094 /* Request PME if WOL is requested. */
2095 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
2096 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2097 if ((ifp->if_capenable & IFCAP_WOL) != 0)
2098 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2099 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
2103 rl_clrwol(struct rl_softc *sc)
2109 if ((ifp->if_capabilities & IFCAP_WOL) == 0)
2112 /* Enable config register write. */
2113 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
2115 v = CSR_READ_1(sc, sc->rl_cfg3);
2116 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
2117 CSR_WRITE_1(sc, sc->rl_cfg3, v);
2119 /* Config register write done. */
2120 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2122 v = CSR_READ_1(sc, sc->rl_cfg5);
2123 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
2124 v &= ~RL_CFG5_WOL_LANWAKE;
2125 CSR_WRITE_1(sc, sc->rl_cfg5, v);