2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * RealTek 8129/8139 PCI NIC driver
39 * Supports several extremely cheap PCI 10/100 adapters based on
40 * the RealTek chipset. Datasheets can be obtained from
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
49 * probably the worst PCI ethernet controller ever made, with the possible
50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
51 * DMA, but it has a terrible interface that nullifies any performance
52 * gains that bus-master DMA usually offers.
54 * For transmission, the chip offers a series of four TX descriptor
55 * registers. Each transmit frame must be in a contiguous buffer, aligned
56 * on a longword (32-bit) boundary. This means we almost always have to
57 * do mbuf copies in order to transmit a frame, except in the unlikely
58 * case where a) the packet fits into a single mbuf, and b) the packet
59 * is 32-bit aligned within the mbuf's data area. The presence of only
60 * four descriptor registers means that we can never have more than four
61 * packets queued for transmission at any one time.
63 * Reception is not much better. The driver has to allocate a single large
64 * buffer area (up to 64K in size) into which the chip will DMA received
65 * frames. Because we don't know where within this region received packets
66 * will begin or end, we have no choice but to copy data from the buffer
67 * area into mbufs in order to pass the packets up to the higher protocol
70 * It's impossible given this rotten design to really achieve decent
71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
72 * some equally overmuscled CPU to drive it.
74 * On the bright side, the 8139 does have a built-in PHY, although
75 * rather than using an MDIO serial interface like most other NICs, the
76 * PHY registers are directly accessible through the 8139's register
77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
80 * The 8129 chip is an older version of the 8139 that uses an external PHY
81 * chip. The 8129 has a serial MDIO interface for accessing the MII where
82 * the 8139 lets you directly access the on-board PHY registers. We need
83 * to select which interface to use depending on the chip type.
86 #ifdef HAVE_KERNEL_OPTION_HEADERS
87 #include "opt_device_polling.h"
90 #include <sys/param.h>
91 #include <sys/endian.h>
92 #include <sys/systm.h>
93 #include <sys/sockio.h>
95 #include <sys/malloc.h>
96 #include <sys/kernel.h>
97 #include <sys/module.h>
98 #include <sys/socket.h>
99 #include <sys/sysctl.h>
102 #include <net/if_var.h>
103 #include <net/if_arp.h>
104 #include <net/ethernet.h>
105 #include <net/if_dl.h>
106 #include <net/if_media.h>
107 #include <net/if_types.h>
111 #include <machine/bus.h>
112 #include <machine/resource.h>
114 #include <sys/rman.h>
116 #include <dev/mii/mii.h>
117 #include <dev/mii/mii_bitbang.h>
118 #include <dev/mii/miivar.h>
120 #include <dev/pci/pcireg.h>
121 #include <dev/pci/pcivar.h>
123 MODULE_DEPEND(rl, pci, 1, 1, 1);
124 MODULE_DEPEND(rl, ether, 1, 1, 1);
125 MODULE_DEPEND(rl, miibus, 1, 1, 1);
127 /* "device miibus" required. See GENERIC if you get errors here. */
128 #include "miibus_if.h"
130 #include <dev/rl/if_rlreg.h>
133 * Various supported device vendors/types and their names.
135 static const struct rl_type rl_devs[] = {
136 { RT_VENDORID, RT_DEVICEID_8129, RL_8129,
137 "RealTek 8129 10/100BaseTX" },
138 { RT_VENDORID, RT_DEVICEID_8139, RL_8139,
139 "RealTek 8139 10/100BaseTX" },
140 { RT_VENDORID, RT_DEVICEID_8139D, RL_8139,
141 "RealTek 8139 10/100BaseTX" },
142 { RT_VENDORID, RT_DEVICEID_8138, RL_8139,
143 "RealTek 8139 10/100BaseTX CardBus" },
144 { RT_VENDORID, RT_DEVICEID_8100, RL_8139,
145 "RealTek 8100 10/100BaseTX" },
146 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
147 "Accton MPX 5030/5038 10/100BaseTX" },
148 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
149 "Delta Electronics 8139 10/100BaseTX" },
150 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139,
151 "Addtron Technology 8139 10/100BaseTX" },
152 { DLINK_VENDORID, DLINK_DEVICEID_520TX_REVC1, RL_8139,
153 "D-Link DFE-520TX (rev. C1) 10/100BaseTX" },
154 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139,
155 "D-Link DFE-530TX+ 10/100BaseTX" },
156 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
157 "D-Link DFE-690TXD 10/100BaseTX" },
158 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
159 "Nortel Networks 10/100BaseTX" },
160 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
161 "Corega FEther CB-TXD" },
162 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
163 "Corega FEtherII CB-TXD" },
164 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
165 "Peppercon AG ROL-F" },
166 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3603TX, RL_8139,
167 "Planex FNW-3603-TX" },
168 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
169 "Planex FNW-3800-TX" },
170 { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
172 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
173 "LevelOne FPC-0106TX" },
174 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
175 "Edimax EP-4103DL CardBus" }
178 static int rl_attach(device_t);
179 static int rl_detach(device_t);
180 static void rl_dmamap_cb(void *, bus_dma_segment_t *, int, int);
181 static int rl_dma_alloc(struct rl_softc *);
182 static void rl_dma_free(struct rl_softc *);
183 static void rl_eeprom_putbyte(struct rl_softc *, int);
184 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
185 static int rl_encap(struct rl_softc *, struct mbuf **);
186 static int rl_list_tx_init(struct rl_softc *);
187 static int rl_list_rx_init(struct rl_softc *);
188 static int rl_ifmedia_upd(struct ifnet *);
189 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
190 static int rl_ioctl(struct ifnet *, u_long, caddr_t);
191 static void rl_intr(void *);
192 static void rl_init(void *);
193 static void rl_init_locked(struct rl_softc *sc);
194 static int rl_miibus_readreg(device_t, int, int);
195 static void rl_miibus_statchg(device_t);
196 static int rl_miibus_writereg(device_t, int, int, int);
197 #ifdef DEVICE_POLLING
198 static int rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
199 static int rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
201 static int rl_probe(device_t);
202 static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int);
203 static void rl_reset(struct rl_softc *);
204 static int rl_resume(device_t);
205 static int rl_rxeof(struct rl_softc *);
206 static void rl_rxfilter(struct rl_softc *);
207 static int rl_shutdown(device_t);
208 static void rl_start(struct ifnet *);
209 static void rl_start_locked(struct ifnet *);
210 static void rl_stop(struct rl_softc *);
211 static int rl_suspend(device_t);
212 static void rl_tick(void *);
213 static void rl_txeof(struct rl_softc *);
214 static void rl_watchdog(struct rl_softc *);
215 static void rl_setwol(struct rl_softc *);
216 static void rl_clrwol(struct rl_softc *);
221 static uint32_t rl_mii_bitbang_read(device_t);
222 static void rl_mii_bitbang_write(device_t, uint32_t);
224 static const struct mii_bitbang_ops rl_mii_bitbang_ops = {
226 rl_mii_bitbang_write,
228 RL_MII_DATAOUT, /* MII_BIT_MDO */
229 RL_MII_DATAIN, /* MII_BIT_MDI */
230 RL_MII_CLK, /* MII_BIT_MDC */
231 RL_MII_DIR, /* MII_BIT_DIR_HOST_PHY */
232 0, /* MII_BIT_DIR_PHY_HOST */
236 static device_method_t rl_methods[] = {
237 /* Device interface */
238 DEVMETHOD(device_probe, rl_probe),
239 DEVMETHOD(device_attach, rl_attach),
240 DEVMETHOD(device_detach, rl_detach),
241 DEVMETHOD(device_suspend, rl_suspend),
242 DEVMETHOD(device_resume, rl_resume),
243 DEVMETHOD(device_shutdown, rl_shutdown),
246 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
247 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
248 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
253 static driver_t rl_driver = {
256 sizeof(struct rl_softc)
259 static devclass_t rl_devclass;
261 DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0);
262 MODULE_PNP_INFO("U16:vendor;U16:device", pci, rl, rl_devs,
263 nitems(rl_devs) - 1);
264 DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0);
265 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
268 CSR_WRITE_1(sc, RL_EECMD, \
269 CSR_READ_1(sc, RL_EECMD) | x)
272 CSR_WRITE_1(sc, RL_EECMD, \
273 CSR_READ_1(sc, RL_EECMD) & ~x)
276 * Send a read command and address to the EEPROM, check for ACK.
279 rl_eeprom_putbyte(struct rl_softc *sc, int addr)
283 d = addr | sc->rl_eecmd_read;
286 * Feed in each bit and strobe the clock.
288 for (i = 0x400; i; i >>= 1) {
290 EE_SET(RL_EE_DATAIN);
292 EE_CLR(RL_EE_DATAIN);
303 * Read a word of data stored in the EEPROM at address 'addr.'
306 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
311 /* Enter EEPROM access mode. */
312 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
315 * Send address of word we want to read.
317 rl_eeprom_putbyte(sc, addr);
319 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
322 * Start reading bits from EEPROM.
324 for (i = 0x8000; i; i >>= 1) {
327 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
333 /* Turn off EEPROM access mode. */
334 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
340 * Read a sequence of words from the EEPROM.
343 rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap)
346 uint16_t word = 0, *ptr;
348 for (i = 0; i < cnt; i++) {
349 rl_eeprom_getword(sc, off + i, &word);
350 ptr = (uint16_t *)(dest + (i * 2));
359 * Read the MII serial port for the MII bit-bang module.
362 rl_mii_bitbang_read(device_t dev)
367 sc = device_get_softc(dev);
369 val = CSR_READ_1(sc, RL_MII);
370 CSR_BARRIER(sc, RL_MII, 1,
371 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
377 * Write the MII serial port for the MII bit-bang module.
380 rl_mii_bitbang_write(device_t dev, uint32_t val)
384 sc = device_get_softc(dev);
386 CSR_WRITE_1(sc, RL_MII, val);
387 CSR_BARRIER(sc, RL_MII, 1,
388 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
392 rl_miibus_readreg(device_t dev, int phy, int reg)
397 sc = device_get_softc(dev);
399 if (sc->rl_type == RL_8139) {
402 rl8139_reg = RL_BMCR;
405 rl8139_reg = RL_BMSR;
408 rl8139_reg = RL_ANAR;
411 rl8139_reg = RL_ANER;
414 rl8139_reg = RL_LPAR;
420 * Allow the rlphy driver to read the media status
421 * register. If we have a link partner which does not
422 * support NWAY, this is the register which will tell
423 * us the results of parallel detection.
426 return (CSR_READ_1(sc, RL_MEDIASTAT));
428 device_printf(sc->rl_dev, "bad phy register\n");
431 return (CSR_READ_2(sc, rl8139_reg));
434 return (mii_bitbang_readreg(dev, &rl_mii_bitbang_ops, phy, reg));
438 rl_miibus_writereg(device_t dev, int phy, int reg, int data)
443 sc = device_get_softc(dev);
445 if (sc->rl_type == RL_8139) {
448 rl8139_reg = RL_BMCR;
451 rl8139_reg = RL_BMSR;
454 rl8139_reg = RL_ANAR;
457 rl8139_reg = RL_ANER;
460 rl8139_reg = RL_LPAR;
467 device_printf(sc->rl_dev, "bad phy register\n");
470 CSR_WRITE_2(sc, rl8139_reg, data);
474 mii_bitbang_writereg(dev, &rl_mii_bitbang_ops, phy, reg, data);
480 rl_miibus_statchg(device_t dev)
484 struct mii_data *mii;
486 sc = device_get_softc(dev);
487 mii = device_get_softc(sc->rl_miibus);
489 if (mii == NULL || ifp == NULL ||
490 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
493 sc->rl_flags &= ~RL_FLAG_LINK;
494 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
495 (IFM_ACTIVE | IFM_AVALID)) {
496 switch (IFM_SUBTYPE(mii->mii_media_active)) {
499 sc->rl_flags |= RL_FLAG_LINK;
506 * RealTek controllers do not provide any interface to
507 * Tx/Rx MACs for resolved speed, duplex and flow-control
513 rl_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
515 uint32_t *hashes = arg;
518 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
520 hashes[0] |= (1 << h);
522 hashes[1] |= (1 << (h - 32));
528 * Program the 64-bit multicast hash filter.
531 rl_rxfilter(struct rl_softc *sc)
533 struct ifnet *ifp = sc->rl_ifp;
534 uint32_t hashes[2] = { 0, 0 };
539 rxfilt = CSR_READ_4(sc, RL_RXCFG);
540 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_BROAD |
542 /* Always accept frames destined for this host. */
543 rxfilt |= RL_RXCFG_RX_INDIV;
544 /* Set capture broadcast bit to capture broadcast frames. */
545 if (ifp->if_flags & IFF_BROADCAST)
546 rxfilt |= RL_RXCFG_RX_BROAD;
547 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
548 rxfilt |= RL_RXCFG_RX_MULTI;
549 if (ifp->if_flags & IFF_PROMISC)
550 rxfilt |= RL_RXCFG_RX_ALLPHYS;
551 hashes[0] = 0xFFFFFFFF;
552 hashes[1] = 0xFFFFFFFF;
554 /* Now program new ones. */
555 if_foreach_llmaddr(ifp, rl_hash_maddr, hashes);
556 if (hashes[0] != 0 || hashes[1] != 0)
557 rxfilt |= RL_RXCFG_RX_MULTI;
560 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
561 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
562 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
566 rl_reset(struct rl_softc *sc)
572 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
574 for (i = 0; i < RL_TIMEOUT; i++) {
576 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
580 device_printf(sc->rl_dev, "reset never completed!\n");
584 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
585 * IDs against our list and return a device name if we find a match.
588 rl_probe(device_t dev)
590 const struct rl_type *t;
591 uint16_t devid, revid, vendor;
594 vendor = pci_get_vendor(dev);
595 devid = pci_get_device(dev);
596 revid = pci_get_revid(dev);
598 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
600 /* 8139C+, let re(4) take care of this device. */
605 for (i = 0; i < nitems(rl_devs); i++, t++) {
606 if (vendor == t->rl_vid && devid == t->rl_did) {
607 device_set_desc(dev, t->rl_name);
608 return (BUS_PROBE_DEFAULT);
615 struct rl_dmamap_arg {
616 bus_addr_t rl_busaddr;
620 rl_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
622 struct rl_dmamap_arg *ctx;
627 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
629 ctx = (struct rl_dmamap_arg *)arg;
630 ctx->rl_busaddr = segs[0].ds_addr;
634 * Attach the interface. Allocate softc structures, do ifmedia
635 * setup and ethernet/BPF attach.
638 rl_attach(device_t dev)
640 uint8_t eaddr[ETHER_ADDR_LEN];
644 const struct rl_type *t;
645 struct sysctl_ctx_list *ctx;
646 struct sysctl_oid_list *children;
647 int error = 0, hwrev, i, phy, pmc, rid;
648 int prefer_iomap, unit;
652 sc = device_get_softc(dev);
653 unit = device_get_unit(dev);
656 sc->rl_twister_enable = 0;
657 snprintf(tn, sizeof(tn), "dev.rl.%d.twister_enable", unit);
658 TUNABLE_INT_FETCH(tn, &sc->rl_twister_enable);
659 ctx = device_get_sysctl_ctx(sc->rl_dev);
660 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
661 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "twister_enable", CTLFLAG_RD,
662 &sc->rl_twister_enable, 0, "");
664 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
666 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
668 pci_enable_busmaster(dev);
672 * Map control/status registers.
673 * Default to using PIO access for this driver. On SMP systems,
674 * there appear to be problems with memory mapped mode: it looks
675 * like doing too many memory mapped access back to back in rapid
676 * succession can hang the bus. I'm inclined to blame this on
677 * crummy design/construction on the part of RealTek. Memory
678 * mapped mode does appear to work on uniprocessor systems though.
681 snprintf(tn, sizeof(tn), "dev.rl.%d.prefer_iomap", unit);
682 TUNABLE_INT_FETCH(tn, &prefer_iomap);
684 sc->rl_res_id = PCIR_BAR(0);
685 sc->rl_res_type = SYS_RES_IOPORT;
686 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
687 &sc->rl_res_id, RF_ACTIVE);
689 if (prefer_iomap == 0 || sc->rl_res == NULL) {
690 sc->rl_res_id = PCIR_BAR(1);
691 sc->rl_res_type = SYS_RES_MEMORY;
692 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
693 &sc->rl_res_id, RF_ACTIVE);
695 if (sc->rl_res == NULL) {
696 device_printf(dev, "couldn't map ports/memory\n");
703 * Detect the Realtek 8139B. For some reason, this chip is very
704 * unstable when left to autoselect the media
705 * The best workaround is to set the device to the required
706 * media type or to set it to the 10 Meg speed.
708 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
710 "Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n");
713 sc->rl_btag = rman_get_bustag(sc->rl_res);
714 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
716 /* Allocate interrupt */
718 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
719 RF_SHAREABLE | RF_ACTIVE);
721 if (sc->rl_irq[0] == NULL) {
722 device_printf(dev, "couldn't map interrupt\n");
727 sc->rl_cfg0 = RL_8139_CFG0;
728 sc->rl_cfg1 = RL_8139_CFG1;
730 sc->rl_cfg3 = RL_8139_CFG3;
731 sc->rl_cfg4 = RL_8139_CFG4;
732 sc->rl_cfg5 = RL_8139_CFG5;
735 * Reset the adapter. Only take the lock here as it's needed in
736 * order to call rl_reset().
742 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
743 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
744 if (rl_did != 0x8129)
745 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
748 * Get station address from the EEPROM.
750 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0);
751 for (i = 0; i < 3; i++) {
752 eaddr[(i * 2) + 0] = as[i] & 0xff;
753 eaddr[(i * 2) + 1] = as[i] >> 8;
757 * Now read the exact device type from the EEPROM to find
758 * out if it's an 8129 or 8139.
760 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0);
764 while(t->rl_name != NULL) {
765 if (rl_did == t->rl_did) {
766 sc->rl_type = t->rl_basetype;
772 if (sc->rl_type == 0) {
773 device_printf(dev, "unknown device ID: %x assuming 8139\n",
775 sc->rl_type = RL_8139;
777 * Read RL_IDR register to get ethernet address as accessing
778 * EEPROM may not extract correct address.
780 for (i = 0; i < ETHER_ADDR_LEN; i++)
781 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
784 if ((error = rl_dma_alloc(sc)) != 0)
787 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
789 device_printf(dev, "can not if_alloc()\n");
794 #define RL_PHYAD_INTERNAL 0
798 if (sc->rl_type == RL_8139)
799 phy = RL_PHYAD_INTERNAL;
800 error = mii_attach(dev, &sc->rl_miibus, ifp, rl_ifmedia_upd,
801 rl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
803 device_printf(dev, "attaching PHYs failed\n");
808 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
809 ifp->if_mtu = ETHERMTU;
810 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
811 ifp->if_ioctl = rl_ioctl;
812 ifp->if_start = rl_start;
813 ifp->if_init = rl_init;
814 ifp->if_capabilities = IFCAP_VLAN_MTU;
815 /* Check WOL for RTL8139B or newer controllers. */
816 if (sc->rl_type == RL_8139 &&
817 pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) {
818 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
826 ifp->if_capabilities |= IFCAP_WOL;
834 ifp->if_capenable = ifp->if_capabilities;
835 ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST);
836 #ifdef DEVICE_POLLING
837 ifp->if_capabilities |= IFCAP_POLLING;
839 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
840 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
841 IFQ_SET_READY(&ifp->if_snd);
844 * Call MI attach routine.
846 ether_ifattach(ifp, eaddr);
848 /* Hook interrupt last to avoid having to lock softc */
849 error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE,
850 NULL, rl_intr, sc, &sc->rl_intrhand[0]);
852 device_printf(sc->rl_dev, "couldn't set up irq\n");
864 * Shutdown hardware and free up resources. This can be called any
865 * time after the mutex has been initialized. It is called in both
866 * the error case in attach and the normal detach case so it needs
867 * to be careful about only freeing resources that have actually been
871 rl_detach(device_t dev)
876 sc = device_get_softc(dev);
879 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
881 #ifdef DEVICE_POLLING
882 if (ifp->if_capenable & IFCAP_POLLING)
883 ether_poll_deregister(ifp);
885 /* These should only be active if attach succeeded */
886 if (device_is_attached(dev)) {
890 callout_drain(&sc->rl_stat_callout);
897 device_delete_child(dev, sc->rl_miibus);
898 bus_generic_detach(dev);
900 if (sc->rl_intrhand[0])
901 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
903 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]);
905 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id,
913 mtx_destroy(&sc->rl_mtx);
919 rl_dma_alloc(struct rl_softc *sc)
921 struct rl_dmamap_arg ctx;
925 * Allocate the parent bus DMA tag appropriate for PCI.
927 error = bus_dma_tag_create(bus_get_dma_tag(sc->rl_dev), /* parent */
928 1, 0, /* alignment, boundary */
929 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
930 BUS_SPACE_MAXADDR, /* highaddr */
931 NULL, NULL, /* filter, filterarg */
932 BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */
933 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
935 NULL, NULL, /* lockfunc, lockarg */
938 device_printf(sc->rl_dev,
939 "failed to create parent DMA tag.\n");
942 /* Create DMA tag for Rx memory block. */
943 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
944 RL_RX_8139_BUF_ALIGN, 0, /* alignment, boundary */
945 BUS_SPACE_MAXADDR, /* lowaddr */
946 BUS_SPACE_MAXADDR, /* highaddr */
947 NULL, NULL, /* filter, filterarg */
948 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, 1, /* maxsize,nsegments */
949 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, /* maxsegsize */
951 NULL, NULL, /* lockfunc, lockarg */
952 &sc->rl_cdata.rl_rx_tag);
954 device_printf(sc->rl_dev,
955 "failed to create Rx memory block DMA tag.\n");
958 /* Create DMA tag for Tx buffer. */
959 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
960 RL_TX_8139_BUF_ALIGN, 0, /* alignment, boundary */
961 BUS_SPACE_MAXADDR, /* lowaddr */
962 BUS_SPACE_MAXADDR, /* highaddr */
963 NULL, NULL, /* filter, filterarg */
964 MCLBYTES, 1, /* maxsize, nsegments */
965 MCLBYTES, /* maxsegsize */
967 NULL, NULL, /* lockfunc, lockarg */
968 &sc->rl_cdata.rl_tx_tag);
970 device_printf(sc->rl_dev, "failed to create Tx DMA tag.\n");
975 * Allocate DMA'able memory and load DMA map for Rx memory block.
977 error = bus_dmamem_alloc(sc->rl_cdata.rl_rx_tag,
978 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_WAITOK |
979 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->rl_cdata.rl_rx_dmamap);
981 device_printf(sc->rl_dev,
982 "failed to allocate Rx DMA memory block.\n");
986 error = bus_dmamap_load(sc->rl_cdata.rl_rx_tag,
987 sc->rl_cdata.rl_rx_dmamap, sc->rl_cdata.rl_rx_buf,
988 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, rl_dmamap_cb, &ctx,
990 if (error != 0 || ctx.rl_busaddr == 0) {
991 device_printf(sc->rl_dev,
992 "could not load Rx DMA memory block.\n");
995 sc->rl_cdata.rl_rx_buf_paddr = ctx.rl_busaddr;
997 /* Create DMA maps for Tx buffers. */
998 for (i = 0; i < RL_TX_LIST_CNT; i++) {
999 sc->rl_cdata.rl_tx_chain[i] = NULL;
1000 sc->rl_cdata.rl_tx_dmamap[i] = NULL;
1001 error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag, 0,
1002 &sc->rl_cdata.rl_tx_dmamap[i]);
1004 device_printf(sc->rl_dev,
1005 "could not create Tx dmamap.\n");
1010 /* Leave a few bytes before the start of the RX ring buffer. */
1011 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
1012 sc->rl_cdata.rl_rx_buf += RL_RX_8139_BUF_RESERVE;
1019 rl_dma_free(struct rl_softc *sc)
1023 /* Rx memory block. */
1024 if (sc->rl_cdata.rl_rx_tag != NULL) {
1025 if (sc->rl_cdata.rl_rx_buf_paddr != 0)
1026 bus_dmamap_unload(sc->rl_cdata.rl_rx_tag,
1027 sc->rl_cdata.rl_rx_dmamap);
1028 if (sc->rl_cdata.rl_rx_buf_ptr != NULL)
1029 bus_dmamem_free(sc->rl_cdata.rl_rx_tag,
1030 sc->rl_cdata.rl_rx_buf_ptr,
1031 sc->rl_cdata.rl_rx_dmamap);
1032 sc->rl_cdata.rl_rx_buf_ptr = NULL;
1033 sc->rl_cdata.rl_rx_buf = NULL;
1034 sc->rl_cdata.rl_rx_buf_paddr = 0;
1035 bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag);
1036 sc->rl_cdata.rl_tx_tag = NULL;
1040 if (sc->rl_cdata.rl_tx_tag != NULL) {
1041 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1042 if (sc->rl_cdata.rl_tx_dmamap[i] != NULL) {
1044 sc->rl_cdata.rl_tx_tag,
1045 sc->rl_cdata.rl_tx_dmamap[i]);
1046 sc->rl_cdata.rl_tx_dmamap[i] = NULL;
1049 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag);
1050 sc->rl_cdata.rl_tx_tag = NULL;
1053 if (sc->rl_parent_tag != NULL) {
1054 bus_dma_tag_destroy(sc->rl_parent_tag);
1055 sc->rl_parent_tag = NULL;
1060 * Initialize the transmit descriptors.
1063 rl_list_tx_init(struct rl_softc *sc)
1065 struct rl_chain_data *cd;
1071 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1072 cd->rl_tx_chain[i] = NULL;
1074 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
1077 sc->rl_cdata.cur_tx = 0;
1078 sc->rl_cdata.last_tx = 0;
1084 rl_list_rx_init(struct rl_softc *sc)
1089 bzero(sc->rl_cdata.rl_rx_buf_ptr,
1090 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ);
1091 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, sc->rl_cdata.rl_rx_dmamap,
1092 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1098 * A frame has been uploaded: pass the resulting mbuf chain up to
1099 * the higher level protocols.
1101 * You know there's something wrong with a PCI bus-master chip design
1102 * when you have to use m_devget().
1104 * The receive operation is badly documented in the datasheet, so I'll
1105 * attempt to document it here. The driver provides a buffer area and
1106 * places its base address in the RX buffer start address register.
1107 * The chip then begins copying frames into the RX buffer. Each frame
1108 * is preceded by a 32-bit RX status word which specifies the length
1109 * of the frame and certain other status bits. Each frame (starting with
1110 * the status word) is also 32-bit aligned. The frame length is in the
1111 * first 16 bits of the status word; the lower 15 bits correspond with
1112 * the 'rx status register' mentioned in the datasheet.
1114 * Note: to make the Alpha happy, the frame payload needs to be aligned
1115 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1116 * as the offset argument to m_devget().
1119 rl_rxeof(struct rl_softc *sc)
1122 struct ifnet *ifp = sc->rl_ifp;
1130 uint16_t max_bytes, rx_bytes = 0;
1134 bus_dmamap_sync(sc->rl_cdata.rl_rx_tag, sc->rl_cdata.rl_rx_dmamap,
1135 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1137 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1139 /* Do not try to read past this point. */
1140 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1143 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1145 max_bytes = limit - cur_rx;
1147 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1148 #ifdef DEVICE_POLLING
1149 if (ifp->if_capenable & IFCAP_POLLING) {
1150 if (sc->rxcycles <= 0)
1155 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1156 rxstat = le32toh(*(uint32_t *)rxbufpos);
1159 * Here's a totally undocumented fact for you. When the
1160 * RealTek chip is in the process of copying a packet into
1161 * RAM for you, the length will be 0xfff0. If you spot a
1162 * packet header with this value, you need to stop. The
1163 * datasheet makes absolutely no mention of this and
1164 * RealTek should be shot for this.
1166 total_len = rxstat >> 16;
1167 if (total_len == RL_RXSTAT_UNFINISHED)
1170 if (!(rxstat & RL_RXSTAT_RXOK) ||
1171 total_len < ETHER_MIN_LEN ||
1172 total_len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) {
1173 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1174 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1179 /* No errors; receive the packet. */
1180 rx_bytes += total_len + 4;
1183 * XXX The RealTek chip includes the CRC with every
1184 * received frame, and there's no way to turn this
1185 * behavior off (at least, I can't find anything in
1186 * the manual that explains how to do it) so we have
1187 * to trim off the CRC manually.
1189 total_len -= ETHER_CRC_LEN;
1192 * Avoid trying to read more bytes than we know
1193 * the chip has prepared for us.
1195 if (rx_bytes > max_bytes)
1198 rxbufpos = sc->rl_cdata.rl_rx_buf +
1199 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1200 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1201 rxbufpos = sc->rl_cdata.rl_rx_buf;
1203 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1204 if (total_len > wrap) {
1205 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1208 m_copyback(m, wrap, total_len - wrap,
1209 sc->rl_cdata.rl_rx_buf);
1210 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1212 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1214 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1217 /* Round up to 32-bit boundary. */
1218 cur_rx = (cur_rx + 3) & ~3;
1219 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1222 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1226 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1228 (*ifp->if_input)(ifp, m);
1233 /* No need to sync Rx memory block as we didn't modify it. */
1238 * A frame was downloaded to the chip. It's safe for us to clean up
1242 rl_txeof(struct rl_softc *sc)
1244 struct ifnet *ifp = sc->rl_ifp;
1250 * Go through our tx list and free mbufs for those
1251 * frames that have been uploaded.
1254 if (RL_LAST_TXMBUF(sc) == NULL)
1256 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1257 if (!(txstat & (RL_TXSTAT_TX_OK|
1258 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1261 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (txstat & RL_TXSTAT_COLLCNT) >> 24);
1263 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc),
1264 BUS_DMASYNC_POSTWRITE);
1265 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc));
1266 m_freem(RL_LAST_TXMBUF(sc));
1267 RL_LAST_TXMBUF(sc) = NULL;
1269 * If there was a transmit underrun, bump the TX threshold.
1270 * Make sure not to overflow the 63 * 32byte we can address
1271 * with the 6 available bit.
1273 if ((txstat & RL_TXSTAT_TX_UNDERRUN) &&
1274 (sc->rl_txthresh < 2016))
1275 sc->rl_txthresh += 32;
1276 if (txstat & RL_TXSTAT_TX_OK)
1277 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1280 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1281 if ((txstat & RL_TXSTAT_TXABRT) ||
1282 (txstat & RL_TXSTAT_OUTOFWIN))
1283 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1284 oldthresh = sc->rl_txthresh;
1285 /* error recovery */
1286 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1288 /* restore original threshold */
1289 sc->rl_txthresh = oldthresh;
1292 RL_INC(sc->rl_cdata.last_tx);
1293 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1294 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1296 if (RL_LAST_TXMBUF(sc) == NULL)
1297 sc->rl_watchdog_timer = 0;
1301 rl_twister_update(struct rl_softc *sc)
1305 * Table provided by RealTek (Kinston <shangh@realtek.com.tw>) for
1306 * Linux driver. Values undocumented otherwise.
1308 static const uint32_t param[4][4] = {
1309 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1310 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1311 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1312 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1316 * Tune the so-called twister registers of the RTL8139. These
1317 * are used to compensate for impedance mismatches. The
1318 * method for tuning these registers is undocumented and the
1319 * following procedure is collected from public sources.
1321 switch (sc->rl_twister)
1325 * If we have a sufficient link, then we can proceed in
1326 * the state machine to the next stage. If not, then
1327 * disable further tuning after writing sane defaults.
1329 if (CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_LINK_OK) {
1330 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_OFF_CMD);
1331 sc->rl_twister = FIND_ROW;
1333 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_CMD);
1334 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST);
1335 CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF);
1336 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF);
1337 sc->rl_twister = DONE;
1342 * Read how long it took to see the echo to find the tuning
1345 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
1346 if (linktest == RL_CSCFG_ROW3)
1347 sc->rl_twist_row = 3;
1348 else if (linktest == RL_CSCFG_ROW2)
1349 sc->rl_twist_row = 2;
1350 else if (linktest == RL_CSCFG_ROW1)
1351 sc->rl_twist_row = 1;
1353 sc->rl_twist_row = 0;
1354 sc->rl_twist_col = 0;
1355 sc->rl_twister = SET_PARAM;
1358 if (sc->rl_twist_col == 0)
1359 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET);
1360 CSR_WRITE_4(sc, RL_PARA7C,
1361 param[sc->rl_twist_row][sc->rl_twist_col]);
1362 if (++sc->rl_twist_col == 4) {
1363 if (sc->rl_twist_row == 3)
1364 sc->rl_twister = RECHK_LONG;
1366 sc->rl_twister = DONE;
1371 * For long cables, we have to double check to make sure we
1374 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
1375 if (linktest == RL_CSCFG_ROW3)
1376 sc->rl_twister = DONE;
1378 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_RETUNE);
1379 sc->rl_twister = RETUNE;
1383 /* Retune for a shorter cable (try column 2) */
1384 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST);
1385 CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF);
1386 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF);
1387 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET);
1389 sc->rl_twist_col = 0;
1390 sc->rl_twister = SET_PARAM;
1402 struct rl_softc *sc = xsc;
1403 struct mii_data *mii;
1408 * If we're doing the twister cable calibration, then we need to defer
1409 * watchdog timeouts. This is a no-op in normal operations, but
1410 * can falsely trigger when the cable calibration takes a while and
1411 * there was traffic ready to go when rl was started.
1413 * We don't defer mii_tick since that updates the mii status, which
1414 * helps the twister process, at least according to similar patches
1415 * for the Linux driver I found online while doing the fixes. Worst
1416 * case is a few extra mii reads during calibration.
1418 mii = device_get_softc(sc->rl_miibus);
1420 if ((sc->rl_flags & RL_FLAG_LINK) == 0)
1421 rl_miibus_statchg(sc->rl_dev);
1422 if (sc->rl_twister_enable) {
1423 if (sc->rl_twister == DONE)
1426 rl_twister_update(sc);
1427 if (sc->rl_twister == DONE)
1436 callout_reset(&sc->rl_stat_callout, ticks, rl_tick, sc);
1439 #ifdef DEVICE_POLLING
1441 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1443 struct rl_softc *sc = ifp->if_softc;
1447 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1448 rx_npkts = rl_poll_locked(ifp, cmd, count);
1454 rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1456 struct rl_softc *sc = ifp->if_softc;
1461 sc->rxcycles = count;
1462 rx_npkts = rl_rxeof(sc);
1465 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1466 rl_start_locked(ifp);
1468 if (cmd == POLL_AND_CHECK_STATUS) {
1471 /* We should also check the status register. */
1472 status = CSR_READ_2(sc, RL_ISR);
1473 if (status == 0xffff)
1476 CSR_WRITE_2(sc, RL_ISR, status);
1478 /* XXX We should check behaviour on receiver stalls. */
1480 if (status & RL_ISR_SYSTEM_ERR) {
1481 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1487 #endif /* DEVICE_POLLING */
1492 struct rl_softc *sc = arg;
1493 struct ifnet *ifp = sc->rl_ifp;
1502 #ifdef DEVICE_POLLING
1503 if (ifp->if_capenable & IFCAP_POLLING)
1507 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1509 status = CSR_READ_2(sc, RL_ISR);
1510 if (status == 0xffff || (status & RL_INTRS) == 0)
1513 * Ours, disable further interrupts.
1515 CSR_WRITE_2(sc, RL_IMR, 0);
1516 for (count = 16; count > 0; count--) {
1517 CSR_WRITE_2(sc, RL_ISR, status);
1518 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1519 if (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR))
1521 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR))
1523 if (status & RL_ISR_SYSTEM_ERR) {
1524 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1530 status = CSR_READ_2(sc, RL_ISR);
1531 /* If the card has gone away, the read returns 0xffff. */
1532 if (status == 0xffff || (status & RL_INTRS) == 0)
1536 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1537 rl_start_locked(ifp);
1540 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1541 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1547 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1548 * pointers to the fragment pointers.
1551 rl_encap(struct rl_softc *sc, struct mbuf **m_head)
1554 bus_dma_segment_t txsegs[1];
1555 int error, nsegs, padlen;
1562 * Hardware doesn't auto-pad, so we have to make sure
1563 * pad short frames out to the minimum frame length.
1565 if (m->m_pkthdr.len < RL_MIN_FRAMELEN)
1566 padlen = RL_MIN_FRAMELEN - m->m_pkthdr.len;
1568 * The RealTek is brain damaged and wants longword-aligned
1569 * TX buffers, plus we can only have one fragment buffer
1570 * per packet. We have to copy pretty much all the time.
1572 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0 ||
1573 (padlen > 0 && M_TRAILINGSPACE(m) < padlen)) {
1574 m = m_defrag(*m_head, M_NOWAIT);
1585 * Make security-conscious people happy: zero out the
1586 * bytes in the pad area, since we don't know what
1587 * this mbuf cluster buffer's previous user might
1590 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1591 m->m_pkthdr.len += padlen;
1592 m->m_len = m->m_pkthdr.len;
1595 error = bus_dmamap_load_mbuf_sg(sc->rl_cdata.rl_tx_tag,
1596 RL_CUR_DMAMAP(sc), m, txsegs, &nsegs, 0);
1605 RL_CUR_TXMBUF(sc) = m;
1606 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc),
1607 BUS_DMASYNC_PREWRITE);
1608 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), RL_ADDR_LO(txsegs[0].ds_addr));
1614 * Main transmit routine.
1617 rl_start(struct ifnet *ifp)
1619 struct rl_softc *sc = ifp->if_softc;
1622 rl_start_locked(ifp);
1627 rl_start_locked(struct ifnet *ifp)
1629 struct rl_softc *sc = ifp->if_softc;
1630 struct mbuf *m_head = NULL;
1634 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1635 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
1638 while (RL_CUR_TXMBUF(sc) == NULL) {
1640 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1645 if (rl_encap(sc, &m_head)) {
1648 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1649 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1653 /* Pass a copy of this mbuf chain to the bpf subsystem. */
1654 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1656 /* Transmit the frame. */
1657 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1658 RL_TXTHRESH(sc->rl_txthresh) |
1659 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1661 RL_INC(sc->rl_cdata.cur_tx);
1663 /* Set a timeout in case the chip goes out to lunch. */
1664 sc->rl_watchdog_timer = 5;
1668 * We broke out of the loop because all our TX slots are
1669 * full. Mark the NIC as busy until it drains some of the
1670 * packets from the queue.
1672 if (RL_CUR_TXMBUF(sc) != NULL)
1673 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1679 struct rl_softc *sc = xsc;
1687 rl_init_locked(struct rl_softc *sc)
1689 struct ifnet *ifp = sc->rl_ifp;
1690 struct mii_data *mii;
1695 mii = device_get_softc(sc->rl_miibus);
1697 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1701 * Cancel pending I/O and free all RX/TX buffers.
1706 if (sc->rl_twister_enable) {
1708 * Reset twister register tuning state. The twister
1709 * registers and their tuning are undocumented, but
1710 * are necessary to cope with bad links. rl_twister =
1711 * DONE here will disable this entirely.
1713 sc->rl_twister = CHK_LINK;
1717 * Init our MAC address. Even though the chipset
1718 * documentation doesn't mention it, we need to enter "Config
1719 * register write enable" mode to modify the ID registers.
1721 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1722 bzero(eaddr, sizeof(eaddr));
1723 bcopy(IF_LLADDR(sc->rl_ifp), eaddr, ETHER_ADDR_LEN);
1724 CSR_WRITE_STREAM_4(sc, RL_IDR0, eaddr[0]);
1725 CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]);
1726 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1728 /* Init the RX memory block pointer register. */
1729 CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr +
1730 RL_RX_8139_BUF_RESERVE);
1731 /* Init TX descriptors. */
1732 rl_list_tx_init(sc);
1733 /* Init Rx memory block. */
1734 rl_list_rx_init(sc);
1737 * Enable transmit and receive.
1739 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1742 * Set the initial TX and RX configuration.
1744 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1745 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1747 /* Set RX filter. */
1750 #ifdef DEVICE_POLLING
1751 /* Disable interrupts if we are polling. */
1752 if (ifp->if_capenable & IFCAP_POLLING)
1753 CSR_WRITE_2(sc, RL_IMR, 0);
1756 /* Enable interrupts. */
1757 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1759 /* Set initial TX threshold */
1760 sc->rl_txthresh = RL_TX_THRESH_INIT;
1762 /* Start RX/TX process. */
1763 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1765 /* Enable receiver and transmitter. */
1766 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1768 sc->rl_flags &= ~RL_FLAG_LINK;
1771 CSR_WRITE_1(sc, sc->rl_cfg1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1773 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1774 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1776 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1780 * Set media options.
1783 rl_ifmedia_upd(struct ifnet *ifp)
1785 struct rl_softc *sc = ifp->if_softc;
1786 struct mii_data *mii;
1788 mii = device_get_softc(sc->rl_miibus);
1798 * Report current media status.
1801 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1803 struct rl_softc *sc = ifp->if_softc;
1804 struct mii_data *mii;
1806 mii = device_get_softc(sc->rl_miibus);
1810 ifmr->ifm_active = mii->mii_media_active;
1811 ifmr->ifm_status = mii->mii_media_status;
1816 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1818 struct ifreq *ifr = (struct ifreq *)data;
1819 struct mii_data *mii;
1820 struct rl_softc *sc = ifp->if_softc;
1821 int error = 0, mask;
1826 if (ifp->if_flags & IFF_UP) {
1827 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1828 ((ifp->if_flags ^ sc->rl_if_flags) &
1829 (IFF_PROMISC | IFF_ALLMULTI)))
1833 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1835 sc->rl_if_flags = ifp->if_flags;
1846 mii = device_get_softc(sc->rl_miibus);
1847 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1850 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1851 #ifdef DEVICE_POLLING
1852 if (ifr->ifr_reqcap & IFCAP_POLLING &&
1853 !(ifp->if_capenable & IFCAP_POLLING)) {
1854 error = ether_poll_register(rl_poll, ifp);
1858 /* Disable interrupts */
1859 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1860 ifp->if_capenable |= IFCAP_POLLING;
1865 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
1866 ifp->if_capenable & IFCAP_POLLING) {
1867 error = ether_poll_deregister(ifp);
1868 /* Enable interrupts. */
1870 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1871 ifp->if_capenable &= ~IFCAP_POLLING;
1875 #endif /* DEVICE_POLLING */
1876 if ((mask & IFCAP_WOL) != 0 &&
1877 (ifp->if_capabilities & IFCAP_WOL) != 0) {
1878 if ((mask & IFCAP_WOL_UCAST) != 0)
1879 ifp->if_capenable ^= IFCAP_WOL_UCAST;
1880 if ((mask & IFCAP_WOL_MCAST) != 0)
1881 ifp->if_capenable ^= IFCAP_WOL_MCAST;
1882 if ((mask & IFCAP_WOL_MAGIC) != 0)
1883 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1887 error = ether_ioctl(ifp, command, data);
1895 rl_watchdog(struct rl_softc *sc)
1900 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer >0)
1903 device_printf(sc->rl_dev, "watchdog timeout\n");
1904 if_inc_counter(sc->rl_ifp, IFCOUNTER_OERRORS, 1);
1908 sc->rl_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1913 * Stop the adapter and free any mbufs allocated to the
1917 rl_stop(struct rl_softc *sc)
1920 struct ifnet *ifp = sc->rl_ifp;
1924 sc->rl_watchdog_timer = 0;
1925 callout_stop(&sc->rl_stat_callout);
1926 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1927 sc->rl_flags &= ~RL_FLAG_LINK;
1929 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1930 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1931 for (i = 0; i < RL_TIMEOUT; i++) {
1933 if ((CSR_READ_1(sc, RL_COMMAND) &
1934 (RL_CMD_RX_ENB | RL_CMD_TX_ENB)) == 0)
1937 if (i == RL_TIMEOUT)
1938 device_printf(sc->rl_dev, "Unable to stop Tx/Rx MAC\n");
1941 * Free the TX list buffers.
1943 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1944 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1945 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag,
1946 sc->rl_cdata.rl_tx_dmamap[i],
1947 BUS_DMASYNC_POSTWRITE);
1948 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag,
1949 sc->rl_cdata.rl_tx_dmamap[i]);
1950 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1951 sc->rl_cdata.rl_tx_chain[i] = NULL;
1952 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1959 * Device suspend routine. Stop the interface and save some PCI
1960 * settings in case the BIOS doesn't restore them properly on
1964 rl_suspend(device_t dev)
1966 struct rl_softc *sc;
1968 sc = device_get_softc(dev);
1980 * Device resume routine. Restore some PCI settings in case the BIOS
1981 * doesn't, re-enable busmastering, and restart the interface if
1985 rl_resume(device_t dev)
1987 struct rl_softc *sc;
1992 sc = device_get_softc(dev);
1997 if ((ifp->if_capabilities & IFCAP_WOL) != 0 &&
1998 pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) {
1999 /* Disable PME and clear PME status. */
2000 pmstat = pci_read_config(sc->rl_dev,
2001 pmc + PCIR_POWER_STATUS, 2);
2002 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
2003 pmstat &= ~PCIM_PSTAT_PMEENABLE;
2004 pci_write_config(sc->rl_dev,
2005 pmc + PCIR_POWER_STATUS, pmstat, 2);
2008 * Clear WOL matching such that normal Rx filtering
2009 * wouldn't interfere with WOL patterns.
2014 /* reinitialize interface if necessary */
2015 if (ifp->if_flags & IFF_UP)
2026 * Stop all chip I/O so that the kernel's probe routines don't
2027 * get confused by errant DMAs when rebooting.
2030 rl_shutdown(device_t dev)
2032 struct rl_softc *sc;
2034 sc = device_get_softc(dev);
2039 * Mark interface as down since otherwise we will panic if
2040 * interrupt comes in later on, which can happen in some
2043 sc->rl_ifp->if_flags &= ~IFF_UP;
2051 rl_setwol(struct rl_softc *sc)
2061 if ((ifp->if_capabilities & IFCAP_WOL) == 0)
2063 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
2066 /* Enable config register write. */
2067 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
2070 v = CSR_READ_1(sc, sc->rl_cfg1);
2072 if ((ifp->if_capenable & IFCAP_WOL) != 0)
2074 CSR_WRITE_1(sc, sc->rl_cfg1, v);
2076 v = CSR_READ_1(sc, sc->rl_cfg3);
2077 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
2078 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2079 v |= RL_CFG3_WOL_MAGIC;
2080 CSR_WRITE_1(sc, sc->rl_cfg3, v);
2082 v = CSR_READ_1(sc, sc->rl_cfg5);
2083 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
2084 v &= ~RL_CFG5_WOL_LANWAKE;
2085 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
2086 v |= RL_CFG5_WOL_UCAST;
2087 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
2088 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
2089 if ((ifp->if_capenable & IFCAP_WOL) != 0)
2090 v |= RL_CFG5_WOL_LANWAKE;
2091 CSR_WRITE_1(sc, sc->rl_cfg5, v);
2093 /* Config register write done. */
2094 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2096 /* Request PME if WOL is requested. */
2097 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
2098 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2099 if ((ifp->if_capenable & IFCAP_WOL) != 0)
2100 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2101 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
2105 rl_clrwol(struct rl_softc *sc)
2111 if ((ifp->if_capabilities & IFCAP_WOL) == 0)
2114 /* Enable config register write. */
2115 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
2117 v = CSR_READ_1(sc, sc->rl_cfg3);
2118 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
2119 CSR_WRITE_1(sc, sc->rl_cfg3, v);
2121 /* Config register write done. */
2122 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2124 v = CSR_READ_1(sc, sc->rl_cfg5);
2125 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
2126 v &= ~RL_CFG5_WOL_LANWAKE;
2127 CSR_WRITE_1(sc, sc->rl_cfg5, v);