2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * RealTek 8129/8139 PCI NIC driver
39 * Supports several extremely cheap PCI 10/100 adapters based on
40 * the RealTek chipset. Datasheets can be obtained from
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
49 * probably the worst PCI ethernet controller ever made, with the possible
50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
51 * DMA, but it has a terrible interface that nullifies any performance
52 * gains that bus-master DMA usually offers.
54 * For transmission, the chip offers a series of four TX descriptor
55 * registers. Each transmit frame must be in a contiguous buffer, aligned
56 * on a longword (32-bit) boundary. This means we almost always have to
57 * do mbuf copies in order to transmit a frame, except in the unlikely
58 * case where a) the packet fits into a single mbuf, and b) the packet
59 * is 32-bit aligned within the mbuf's data area. The presence of only
60 * four descriptor registers means that we can never have more than four
61 * packets queued for transmission at any one time.
63 * Reception is not much better. The driver has to allocate a single large
64 * buffer area (up to 64K in size) into which the chip will DMA received
65 * frames. Because we don't know where within this region received packets
66 * will begin or end, we have no choice but to copy data from the buffer
67 * area into mbufs in order to pass the packets up to the higher protocol
70 * It's impossible given this rotten design to really achieve decent
71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
72 * some equally overmuscled CPU to drive it.
74 * On the bright side, the 8139 does have a built-in PHY, although
75 * rather than using an MDIO serial interface like most other NICs, the
76 * PHY registers are directly accessible through the 8139's register
77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
80 * The 8129 chip is an older version of the 8139 that uses an external PHY
81 * chip. The 8129 has a serial MDIO interface for accessing the MII where
82 * the 8139 lets you directly access the on-board PHY registers. We need
83 * to select which interface to use depending on the chip type.
86 #ifdef HAVE_KERNEL_OPTION_HEADERS
87 #include "opt_device_polling.h"
90 #include <sys/param.h>
91 #include <sys/endian.h>
92 #include <sys/systm.h>
93 #include <sys/sockio.h>
95 #include <sys/malloc.h>
96 #include <sys/kernel.h>
97 #include <sys/module.h>
98 #include <sys/socket.h>
99 #include <sys/sysctl.h>
102 #include <net/if_var.h>
103 #include <net/if_arp.h>
104 #include <net/ethernet.h>
105 #include <net/if_dl.h>
106 #include <net/if_media.h>
107 #include <net/if_types.h>
111 #include <machine/bus.h>
112 #include <machine/resource.h>
114 #include <sys/rman.h>
116 #include <dev/mii/mii.h>
117 #include <dev/mii/mii_bitbang.h>
118 #include <dev/mii/miivar.h>
120 #include <dev/pci/pcireg.h>
121 #include <dev/pci/pcivar.h>
123 MODULE_DEPEND(rl, pci, 1, 1, 1);
124 MODULE_DEPEND(rl, ether, 1, 1, 1);
125 MODULE_DEPEND(rl, miibus, 1, 1, 1);
127 /* "device miibus" required. See GENERIC if you get errors here. */
128 #include "miibus_if.h"
130 #include <dev/rl/if_rlreg.h>
133 * Various supported device vendors/types and their names.
135 static const struct rl_type rl_devs[] = {
136 { RT_VENDORID, RT_DEVICEID_8129, RL_8129,
137 "RealTek 8129 10/100BaseTX" },
138 { RT_VENDORID, RT_DEVICEID_8139, RL_8139,
139 "RealTek 8139 10/100BaseTX" },
140 { RT_VENDORID, RT_DEVICEID_8139D, RL_8139,
141 "RealTek 8139 10/100BaseTX" },
142 { RT_VENDORID, RT_DEVICEID_8138, RL_8139,
143 "RealTek 8139 10/100BaseTX CardBus" },
144 { RT_VENDORID, RT_DEVICEID_8100, RL_8139,
145 "RealTek 8100 10/100BaseTX" },
146 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
147 "Accton MPX 5030/5038 10/100BaseTX" },
148 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
149 "Delta Electronics 8139 10/100BaseTX" },
150 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139,
151 "Addtron Technology 8139 10/100BaseTX" },
152 { DLINK_VENDORID, DLINK_DEVICEID_520TX_REVC1, RL_8139,
153 "D-Link DFE-520TX (rev. C1) 10/100BaseTX" },
154 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139,
155 "D-Link DFE-530TX+ 10/100BaseTX" },
156 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
157 "D-Link DFE-690TXD 10/100BaseTX" },
158 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
159 "Nortel Networks 10/100BaseTX" },
160 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
161 "Corega FEther CB-TXD" },
162 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
163 "Corega FEtherII CB-TXD" },
164 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
165 "Peppercon AG ROL-F" },
166 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3603TX, RL_8139,
167 "Planex FNW-3603-TX" },
168 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
169 "Planex FNW-3800-TX" },
170 { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
172 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
173 "LevelOne FPC-0106TX" },
174 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
175 "Edimax EP-4103DL CardBus" }
178 static int rl_attach(device_t);
179 static int rl_detach(device_t);
180 static void rl_dmamap_cb(void *, bus_dma_segment_t *, int, int);
181 static int rl_dma_alloc(struct rl_softc *);
182 static void rl_dma_free(struct rl_softc *);
183 static void rl_eeprom_putbyte(struct rl_softc *, int);
184 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
185 static int rl_encap(struct rl_softc *, struct mbuf **);
186 static int rl_list_tx_init(struct rl_softc *);
187 static int rl_list_rx_init(struct rl_softc *);
188 static int rl_ifmedia_upd(if_t);
189 static void rl_ifmedia_sts(if_t, struct ifmediareq *);
190 static int rl_ioctl(if_t, u_long, caddr_t);
191 static void rl_intr(void *);
192 static void rl_init(void *);
193 static void rl_init_locked(struct rl_softc *sc);
194 static int rl_miibus_readreg(device_t, int, int);
195 static void rl_miibus_statchg(device_t);
196 static int rl_miibus_writereg(device_t, int, int, int);
197 #ifdef DEVICE_POLLING
198 static int rl_poll(if_t ifp, enum poll_cmd cmd, int count);
199 static int rl_poll_locked(if_t ifp, enum poll_cmd cmd, int count);
201 static int rl_probe(device_t);
202 static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int);
203 static void rl_reset(struct rl_softc *);
204 static int rl_resume(device_t);
205 static int rl_rxeof(struct rl_softc *);
206 static void rl_rxfilter(struct rl_softc *);
207 static int rl_shutdown(device_t);
208 static void rl_start(if_t);
209 static void rl_start_locked(if_t);
210 static void rl_stop(struct rl_softc *);
211 static int rl_suspend(device_t);
212 static void rl_tick(void *);
213 static void rl_txeof(struct rl_softc *);
214 static void rl_watchdog(struct rl_softc *);
215 static void rl_setwol(struct rl_softc *);
216 static void rl_clrwol(struct rl_softc *);
221 static uint32_t rl_mii_bitbang_read(device_t);
222 static void rl_mii_bitbang_write(device_t, uint32_t);
224 static const struct mii_bitbang_ops rl_mii_bitbang_ops = {
226 rl_mii_bitbang_write,
228 RL_MII_DATAOUT, /* MII_BIT_MDO */
229 RL_MII_DATAIN, /* MII_BIT_MDI */
230 RL_MII_CLK, /* MII_BIT_MDC */
231 RL_MII_DIR, /* MII_BIT_DIR_HOST_PHY */
232 0, /* MII_BIT_DIR_PHY_HOST */
236 static device_method_t rl_methods[] = {
237 /* Device interface */
238 DEVMETHOD(device_probe, rl_probe),
239 DEVMETHOD(device_attach, rl_attach),
240 DEVMETHOD(device_detach, rl_detach),
241 DEVMETHOD(device_suspend, rl_suspend),
242 DEVMETHOD(device_resume, rl_resume),
243 DEVMETHOD(device_shutdown, rl_shutdown),
246 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
247 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
248 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
253 static driver_t rl_driver = {
256 sizeof(struct rl_softc)
259 DRIVER_MODULE(rl, pci, rl_driver, 0, 0);
260 MODULE_PNP_INFO("U16:vendor;U16:device", pci, rl, rl_devs,
261 nitems(rl_devs) - 1);
262 DRIVER_MODULE(rl, cardbus, rl_driver, 0, 0);
263 DRIVER_MODULE(miibus, rl, miibus_driver, 0, 0);
266 CSR_WRITE_1(sc, RL_EECMD, \
267 CSR_READ_1(sc, RL_EECMD) | x)
270 CSR_WRITE_1(sc, RL_EECMD, \
271 CSR_READ_1(sc, RL_EECMD) & ~x)
274 * Send a read command and address to the EEPROM, check for ACK.
277 rl_eeprom_putbyte(struct rl_softc *sc, int addr)
281 d = addr | sc->rl_eecmd_read;
284 * Feed in each bit and strobe the clock.
286 for (i = 0x400; i; i >>= 1) {
288 EE_SET(RL_EE_DATAIN);
290 EE_CLR(RL_EE_DATAIN);
301 * Read a word of data stored in the EEPROM at address 'addr.'
304 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
309 /* Enter EEPROM access mode. */
310 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
313 * Send address of word we want to read.
315 rl_eeprom_putbyte(sc, addr);
317 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
320 * Start reading bits from EEPROM.
322 for (i = 0x8000; i; i >>= 1) {
325 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
331 /* Turn off EEPROM access mode. */
332 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
338 * Read a sequence of words from the EEPROM.
341 rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap)
344 uint16_t word = 0, *ptr;
346 for (i = 0; i < cnt; i++) {
347 rl_eeprom_getword(sc, off + i, &word);
348 ptr = (uint16_t *)(dest + (i * 2));
357 * Read the MII serial port for the MII bit-bang module.
360 rl_mii_bitbang_read(device_t dev)
365 sc = device_get_softc(dev);
367 val = CSR_READ_1(sc, RL_MII);
368 CSR_BARRIER(sc, RL_MII, 1,
369 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
375 * Write the MII serial port for the MII bit-bang module.
378 rl_mii_bitbang_write(device_t dev, uint32_t val)
382 sc = device_get_softc(dev);
384 CSR_WRITE_1(sc, RL_MII, val);
385 CSR_BARRIER(sc, RL_MII, 1,
386 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
390 rl_miibus_readreg(device_t dev, int phy, int reg)
395 sc = device_get_softc(dev);
397 if (sc->rl_type == RL_8139) {
400 rl8139_reg = RL_BMCR;
403 rl8139_reg = RL_BMSR;
406 rl8139_reg = RL_ANAR;
409 rl8139_reg = RL_ANER;
412 rl8139_reg = RL_LPAR;
418 * Allow the rlphy driver to read the media status
419 * register. If we have a link partner which does not
420 * support NWAY, this is the register which will tell
421 * us the results of parallel detection.
424 return (CSR_READ_1(sc, RL_MEDIASTAT));
426 device_printf(sc->rl_dev, "bad phy register\n");
429 return (CSR_READ_2(sc, rl8139_reg));
432 return (mii_bitbang_readreg(dev, &rl_mii_bitbang_ops, phy, reg));
436 rl_miibus_writereg(device_t dev, int phy, int reg, int data)
441 sc = device_get_softc(dev);
443 if (sc->rl_type == RL_8139) {
446 rl8139_reg = RL_BMCR;
449 rl8139_reg = RL_BMSR;
452 rl8139_reg = RL_ANAR;
455 rl8139_reg = RL_ANER;
458 rl8139_reg = RL_LPAR;
465 device_printf(sc->rl_dev, "bad phy register\n");
468 CSR_WRITE_2(sc, rl8139_reg, data);
472 mii_bitbang_writereg(dev, &rl_mii_bitbang_ops, phy, reg, data);
478 rl_miibus_statchg(device_t dev)
482 struct mii_data *mii;
484 sc = device_get_softc(dev);
485 mii = device_get_softc(sc->rl_miibus);
487 if (mii == NULL || ifp == NULL ||
488 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
491 sc->rl_flags &= ~RL_FLAG_LINK;
492 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
493 (IFM_ACTIVE | IFM_AVALID)) {
494 switch (IFM_SUBTYPE(mii->mii_media_active)) {
497 sc->rl_flags |= RL_FLAG_LINK;
504 * RealTek controllers do not provide any interface to
505 * Tx/Rx MACs for resolved speed, duplex and flow-control
511 rl_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
513 uint32_t *hashes = arg;
516 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26;
518 hashes[0] |= (1 << h);
520 hashes[1] |= (1 << (h - 32));
526 * Program the 64-bit multicast hash filter.
529 rl_rxfilter(struct rl_softc *sc)
531 if_t ifp = sc->rl_ifp;
532 uint32_t hashes[2] = { 0, 0 };
537 rxfilt = CSR_READ_4(sc, RL_RXCFG);
538 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_BROAD |
540 /* Always accept frames destined for this host. */
541 rxfilt |= RL_RXCFG_RX_INDIV;
542 /* Set capture broadcast bit to capture broadcast frames. */
543 if (if_getflags(ifp) & IFF_BROADCAST)
544 rxfilt |= RL_RXCFG_RX_BROAD;
545 if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) {
546 rxfilt |= RL_RXCFG_RX_MULTI;
547 if (if_getflags(ifp) & IFF_PROMISC)
548 rxfilt |= RL_RXCFG_RX_ALLPHYS;
549 hashes[0] = 0xFFFFFFFF;
550 hashes[1] = 0xFFFFFFFF;
552 /* Now program new ones. */
553 if_foreach_llmaddr(ifp, rl_hash_maddr, hashes);
554 if (hashes[0] != 0 || hashes[1] != 0)
555 rxfilt |= RL_RXCFG_RX_MULTI;
558 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
559 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
560 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
564 rl_reset(struct rl_softc *sc)
570 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
572 for (i = 0; i < RL_TIMEOUT; i++) {
574 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
578 device_printf(sc->rl_dev, "reset never completed!\n");
582 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
583 * IDs against our list and return a device name if we find a match.
586 rl_probe(device_t dev)
588 const struct rl_type *t;
589 uint16_t devid, revid, vendor;
592 vendor = pci_get_vendor(dev);
593 devid = pci_get_device(dev);
594 revid = pci_get_revid(dev);
596 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
598 /* 8139C+, let re(4) take care of this device. */
603 for (i = 0; i < nitems(rl_devs); i++, t++) {
604 if (vendor == t->rl_vid && devid == t->rl_did) {
605 device_set_desc(dev, t->rl_name);
606 return (BUS_PROBE_DEFAULT);
613 struct rl_dmamap_arg {
614 bus_addr_t rl_busaddr;
618 rl_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
620 struct rl_dmamap_arg *ctx;
625 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
627 ctx = (struct rl_dmamap_arg *)arg;
628 ctx->rl_busaddr = segs[0].ds_addr;
632 * Attach the interface. Allocate softc structures, do ifmedia
633 * setup and ethernet/BPF attach.
636 rl_attach(device_t dev)
638 uint8_t eaddr[ETHER_ADDR_LEN];
642 const struct rl_type *t;
643 struct sysctl_ctx_list *ctx;
644 struct sysctl_oid_list *children;
645 int error = 0, hwrev, i, phy, pmc, rid;
646 int prefer_iomap, unit;
650 sc = device_get_softc(dev);
651 unit = device_get_unit(dev);
654 sc->rl_twister_enable = 0;
655 snprintf(tn, sizeof(tn), "dev.rl.%d.twister_enable", unit);
656 TUNABLE_INT_FETCH(tn, &sc->rl_twister_enable);
657 ctx = device_get_sysctl_ctx(sc->rl_dev);
658 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
659 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "twister_enable", CTLFLAG_RD,
660 &sc->rl_twister_enable, 0, "");
662 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
664 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
666 pci_enable_busmaster(dev);
669 * Map control/status registers.
670 * Default to using PIO access for this driver. On SMP systems,
671 * there appear to be problems with memory mapped mode: it looks
672 * like doing too many memory mapped access back to back in rapid
673 * succession can hang the bus. I'm inclined to blame this on
674 * crummy design/construction on the part of RealTek. Memory
675 * mapped mode does appear to work on uniprocessor systems though.
678 snprintf(tn, sizeof(tn), "dev.rl.%d.prefer_iomap", unit);
679 TUNABLE_INT_FETCH(tn, &prefer_iomap);
681 sc->rl_res_id = PCIR_BAR(0);
682 sc->rl_res_type = SYS_RES_IOPORT;
683 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
684 &sc->rl_res_id, RF_ACTIVE);
686 if (prefer_iomap == 0 || sc->rl_res == NULL) {
687 sc->rl_res_id = PCIR_BAR(1);
688 sc->rl_res_type = SYS_RES_MEMORY;
689 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
690 &sc->rl_res_id, RF_ACTIVE);
692 if (sc->rl_res == NULL) {
693 device_printf(dev, "couldn't map ports/memory\n");
700 * Detect the Realtek 8139B. For some reason, this chip is very
701 * unstable when left to autoselect the media
702 * The best workaround is to set the device to the required
703 * media type or to set it to the 10 Meg speed.
705 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
707 "Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n");
710 sc->rl_btag = rman_get_bustag(sc->rl_res);
711 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
713 /* Allocate interrupt */
715 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
716 RF_SHAREABLE | RF_ACTIVE);
718 if (sc->rl_irq[0] == NULL) {
719 device_printf(dev, "couldn't map interrupt\n");
724 sc->rl_cfg0 = RL_8139_CFG0;
725 sc->rl_cfg1 = RL_8139_CFG1;
727 sc->rl_cfg3 = RL_8139_CFG3;
728 sc->rl_cfg4 = RL_8139_CFG4;
729 sc->rl_cfg5 = RL_8139_CFG5;
732 * Reset the adapter. Only take the lock here as it's needed in
733 * order to call rl_reset().
739 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
740 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
741 if (rl_did != 0x8129)
742 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
745 * Get station address from the EEPROM.
747 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0);
748 for (i = 0; i < 3; i++) {
749 eaddr[(i * 2) + 0] = as[i] & 0xff;
750 eaddr[(i * 2) + 1] = as[i] >> 8;
754 * Now read the exact device type from the EEPROM to find
755 * out if it's an 8129 or 8139.
757 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0);
761 while(t->rl_name != NULL) {
762 if (rl_did == t->rl_did) {
763 sc->rl_type = t->rl_basetype;
769 if (sc->rl_type == 0) {
770 device_printf(dev, "unknown device ID: %x assuming 8139\n",
772 sc->rl_type = RL_8139;
774 * Read RL_IDR register to get ethernet address as accessing
775 * EEPROM may not extract correct address.
777 for (i = 0; i < ETHER_ADDR_LEN; i++)
778 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
781 if ((error = rl_dma_alloc(sc)) != 0)
784 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
786 device_printf(dev, "can not if_alloc()\n");
791 #define RL_PHYAD_INTERNAL 0
795 if (sc->rl_type == RL_8139)
796 phy = RL_PHYAD_INTERNAL;
797 error = mii_attach(dev, &sc->rl_miibus, ifp, rl_ifmedia_upd,
798 rl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
800 device_printf(dev, "attaching PHYs failed\n");
804 if_setsoftc(ifp, sc);
805 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
806 if_setmtu(ifp, ETHERMTU);
807 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
808 if_setioctlfn(ifp, rl_ioctl);
809 if_setstartfn(ifp, rl_start);
810 if_setinitfn(ifp, rl_init);
811 if_setcapabilities(ifp, IFCAP_VLAN_MTU);
812 /* Check WOL for RTL8139B or newer controllers. */
813 if (sc->rl_type == RL_8139 &&
814 pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) {
815 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
823 if_setcapabilitiesbit(ifp, IFCAP_WOL, 0);
831 if_setcapenable(ifp, if_getcapabilities(ifp));
832 if_setcapenablebit(ifp, 0, (IFCAP_WOL_UCAST | IFCAP_WOL_MCAST));
833 #ifdef DEVICE_POLLING
834 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
836 if_setsendqlen(ifp, ifqmaxlen);
837 if_setsendqready(ifp);
840 * Call MI attach routine.
842 ether_ifattach(ifp, eaddr);
844 /* Hook interrupt last to avoid having to lock softc */
845 error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE,
846 NULL, rl_intr, sc, &sc->rl_intrhand[0]);
848 device_printf(sc->rl_dev, "couldn't set up irq\n");
860 * Shutdown hardware and free up resources. This can be called any
861 * time after the mutex has been initialized. It is called in both
862 * the error case in attach and the normal detach case so it needs
863 * to be careful about only freeing resources that have actually been
867 rl_detach(device_t dev)
872 sc = device_get_softc(dev);
875 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
877 #ifdef DEVICE_POLLING
878 if (if_getcapenable(ifp) & IFCAP_POLLING)
879 ether_poll_deregister(ifp);
881 /* These should only be active if attach succeeded */
882 if (device_is_attached(dev)) {
886 callout_drain(&sc->rl_stat_callout);
893 device_delete_child(dev, sc->rl_miibus);
894 bus_generic_detach(dev);
896 if (sc->rl_intrhand[0])
897 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
899 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]);
901 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id,
909 mtx_destroy(&sc->rl_mtx);
915 rl_dma_alloc(struct rl_softc *sc)
917 struct rl_dmamap_arg ctx;
921 * Allocate the parent bus DMA tag appropriate for PCI.
923 error = bus_dma_tag_create(bus_get_dma_tag(sc->rl_dev), /* parent */
924 1, 0, /* alignment, boundary */
925 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
926 BUS_SPACE_MAXADDR, /* highaddr */
927 NULL, NULL, /* filter, filterarg */
928 BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */
929 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
931 NULL, NULL, /* lockfunc, lockarg */
934 device_printf(sc->rl_dev,
935 "failed to create parent DMA tag.\n");
938 /* Create DMA tag for Rx memory block. */
939 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
940 RL_RX_8139_BUF_ALIGN, 0, /* alignment, boundary */
941 BUS_SPACE_MAXADDR, /* lowaddr */
942 BUS_SPACE_MAXADDR, /* highaddr */
943 NULL, NULL, /* filter, filterarg */
944 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, 1, /* maxsize,nsegments */
945 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, /* maxsegsize */
947 NULL, NULL, /* lockfunc, lockarg */
948 &sc->rl_cdata.rl_rx_tag);
950 device_printf(sc->rl_dev,
951 "failed to create Rx memory block DMA tag.\n");
954 /* Create DMA tag for Tx buffer. */
955 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
956 RL_TX_8139_BUF_ALIGN, 0, /* alignment, boundary */
957 BUS_SPACE_MAXADDR, /* lowaddr */
958 BUS_SPACE_MAXADDR, /* highaddr */
959 NULL, NULL, /* filter, filterarg */
960 MCLBYTES, 1, /* maxsize, nsegments */
961 MCLBYTES, /* maxsegsize */
963 NULL, NULL, /* lockfunc, lockarg */
964 &sc->rl_cdata.rl_tx_tag);
966 device_printf(sc->rl_dev, "failed to create Tx DMA tag.\n");
971 * Allocate DMA'able memory and load DMA map for Rx memory block.
973 error = bus_dmamem_alloc(sc->rl_cdata.rl_rx_tag,
974 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_WAITOK |
975 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->rl_cdata.rl_rx_dmamap);
977 device_printf(sc->rl_dev,
978 "failed to allocate Rx DMA memory block.\n");
982 error = bus_dmamap_load(sc->rl_cdata.rl_rx_tag,
983 sc->rl_cdata.rl_rx_dmamap, sc->rl_cdata.rl_rx_buf,
984 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, rl_dmamap_cb, &ctx,
986 if (error != 0 || ctx.rl_busaddr == 0) {
987 device_printf(sc->rl_dev,
988 "could not load Rx DMA memory block.\n");
991 sc->rl_cdata.rl_rx_buf_paddr = ctx.rl_busaddr;
993 /* Create DMA maps for Tx buffers. */
994 for (i = 0; i < RL_TX_LIST_CNT; i++) {
995 sc->rl_cdata.rl_tx_chain[i] = NULL;
996 sc->rl_cdata.rl_tx_dmamap[i] = NULL;
997 error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag, 0,
998 &sc->rl_cdata.rl_tx_dmamap[i]);
1000 device_printf(sc->rl_dev,
1001 "could not create Tx dmamap.\n");
1006 /* Leave a few bytes before the start of the RX ring buffer. */
1007 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
1008 sc->rl_cdata.rl_rx_buf += RL_RX_8139_BUF_RESERVE;
1015 rl_dma_free(struct rl_softc *sc)
1019 /* Rx memory block. */
1020 if (sc->rl_cdata.rl_rx_tag != NULL) {
1021 if (sc->rl_cdata.rl_rx_buf_paddr != 0)
1022 bus_dmamap_unload(sc->rl_cdata.rl_rx_tag,
1023 sc->rl_cdata.rl_rx_dmamap);
1024 if (sc->rl_cdata.rl_rx_buf_ptr != NULL)
1025 bus_dmamem_free(sc->rl_cdata.rl_rx_tag,
1026 sc->rl_cdata.rl_rx_buf_ptr,
1027 sc->rl_cdata.rl_rx_dmamap);
1028 sc->rl_cdata.rl_rx_buf_ptr = NULL;
1029 sc->rl_cdata.rl_rx_buf = NULL;
1030 sc->rl_cdata.rl_rx_buf_paddr = 0;
1031 bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag);
1032 sc->rl_cdata.rl_tx_tag = NULL;
1036 if (sc->rl_cdata.rl_tx_tag != NULL) {
1037 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1038 if (sc->rl_cdata.rl_tx_dmamap[i] != NULL) {
1040 sc->rl_cdata.rl_tx_tag,
1041 sc->rl_cdata.rl_tx_dmamap[i]);
1042 sc->rl_cdata.rl_tx_dmamap[i] = NULL;
1045 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag);
1046 sc->rl_cdata.rl_tx_tag = NULL;
1049 if (sc->rl_parent_tag != NULL) {
1050 bus_dma_tag_destroy(sc->rl_parent_tag);
1051 sc->rl_parent_tag = NULL;
1056 * Initialize the transmit descriptors.
1059 rl_list_tx_init(struct rl_softc *sc)
1061 struct rl_chain_data *cd;
1067 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1068 cd->rl_tx_chain[i] = NULL;
1070 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
1073 sc->rl_cdata.cur_tx = 0;
1074 sc->rl_cdata.last_tx = 0;
1080 rl_list_rx_init(struct rl_softc *sc)
1085 bzero(sc->rl_cdata.rl_rx_buf_ptr,
1086 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ);
1087 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, sc->rl_cdata.rl_rx_dmamap,
1088 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1094 * A frame has been uploaded: pass the resulting mbuf chain up to
1095 * the higher level protocols.
1097 * You know there's something wrong with a PCI bus-master chip design
1098 * when you have to use m_devget().
1100 * The receive operation is badly documented in the datasheet, so I'll
1101 * attempt to document it here. The driver provides a buffer area and
1102 * places its base address in the RX buffer start address register.
1103 * The chip then begins copying frames into the RX buffer. Each frame
1104 * is preceded by a 32-bit RX status word which specifies the length
1105 * of the frame and certain other status bits. Each frame (starting with
1106 * the status word) is also 32-bit aligned. The frame length is in the
1107 * first 16 bits of the status word; the lower 15 bits correspond with
1108 * the 'rx status register' mentioned in the datasheet.
1110 * Note: to make the Alpha happy, the frame payload needs to be aligned
1111 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1112 * as the offset argument to m_devget().
1115 rl_rxeof(struct rl_softc *sc)
1118 if_t ifp = sc->rl_ifp;
1126 uint16_t max_bytes, rx_bytes = 0;
1130 bus_dmamap_sync(sc->rl_cdata.rl_rx_tag, sc->rl_cdata.rl_rx_dmamap,
1131 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1133 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1135 /* Do not try to read past this point. */
1136 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1139 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1141 max_bytes = limit - cur_rx;
1143 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1144 #ifdef DEVICE_POLLING
1145 if (if_getcapenable(ifp) & IFCAP_POLLING) {
1146 if (sc->rxcycles <= 0)
1151 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1152 rxstat = le32toh(*(uint32_t *)rxbufpos);
1155 * Here's a totally undocumented fact for you. When the
1156 * RealTek chip is in the process of copying a packet into
1157 * RAM for you, the length will be 0xfff0. If you spot a
1158 * packet header with this value, you need to stop. The
1159 * datasheet makes absolutely no mention of this and
1160 * RealTek should be shot for this.
1162 total_len = rxstat >> 16;
1163 if (total_len == RL_RXSTAT_UNFINISHED)
1166 if (!(rxstat & RL_RXSTAT_RXOK) ||
1167 total_len < ETHER_MIN_LEN ||
1168 total_len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) {
1169 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1170 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1175 /* No errors; receive the packet. */
1176 rx_bytes += total_len + 4;
1179 * XXX The RealTek chip includes the CRC with every
1180 * received frame, and there's no way to turn this
1181 * behavior off (at least, I can't find anything in
1182 * the manual that explains how to do it) so we have
1183 * to trim off the CRC manually.
1185 total_len -= ETHER_CRC_LEN;
1188 * Avoid trying to read more bytes than we know
1189 * the chip has prepared for us.
1191 if (rx_bytes > max_bytes)
1194 rxbufpos = sc->rl_cdata.rl_rx_buf +
1195 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1196 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1197 rxbufpos = sc->rl_cdata.rl_rx_buf;
1199 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1200 if (total_len > wrap) {
1201 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1204 m_copyback(m, wrap, total_len - wrap,
1205 sc->rl_cdata.rl_rx_buf);
1206 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1208 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1210 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1213 /* Round up to 32-bit boundary. */
1214 cur_rx = (cur_rx + 3) & ~3;
1215 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1218 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1222 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1229 /* No need to sync Rx memory block as we didn't modify it. */
1234 * A frame was downloaded to the chip. It's safe for us to clean up
1238 rl_txeof(struct rl_softc *sc)
1240 if_t ifp = sc->rl_ifp;
1246 * Go through our tx list and free mbufs for those
1247 * frames that have been uploaded.
1250 if (RL_LAST_TXMBUF(sc) == NULL)
1252 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1253 if (!(txstat & (RL_TXSTAT_TX_OK|
1254 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1257 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (txstat & RL_TXSTAT_COLLCNT) >> 24);
1259 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc),
1260 BUS_DMASYNC_POSTWRITE);
1261 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc));
1262 m_freem(RL_LAST_TXMBUF(sc));
1263 RL_LAST_TXMBUF(sc) = NULL;
1265 * If there was a transmit underrun, bump the TX threshold.
1266 * Make sure not to overflow the 63 * 32byte we can address
1267 * with the 6 available bit.
1269 if ((txstat & RL_TXSTAT_TX_UNDERRUN) &&
1270 (sc->rl_txthresh < 2016))
1271 sc->rl_txthresh += 32;
1272 if (txstat & RL_TXSTAT_TX_OK)
1273 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1276 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1277 if ((txstat & RL_TXSTAT_TXABRT) ||
1278 (txstat & RL_TXSTAT_OUTOFWIN))
1279 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1280 oldthresh = sc->rl_txthresh;
1281 /* error recovery */
1282 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1284 /* restore original threshold */
1285 sc->rl_txthresh = oldthresh;
1288 RL_INC(sc->rl_cdata.last_tx);
1289 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1290 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1292 if (RL_LAST_TXMBUF(sc) == NULL)
1293 sc->rl_watchdog_timer = 0;
1297 rl_twister_update(struct rl_softc *sc)
1301 * Table provided by RealTek (Kinston <shangh@realtek.com.tw>) for
1302 * Linux driver. Values undocumented otherwise.
1304 static const uint32_t param[4][4] = {
1305 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1306 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1307 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1308 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1312 * Tune the so-called twister registers of the RTL8139. These
1313 * are used to compensate for impedance mismatches. The
1314 * method for tuning these registers is undocumented and the
1315 * following procedure is collected from public sources.
1317 switch (sc->rl_twister)
1321 * If we have a sufficient link, then we can proceed in
1322 * the state machine to the next stage. If not, then
1323 * disable further tuning after writing sane defaults.
1325 if (CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_LINK_OK) {
1326 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_OFF_CMD);
1327 sc->rl_twister = FIND_ROW;
1329 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_CMD);
1330 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST);
1331 CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF);
1332 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF);
1333 sc->rl_twister = DONE;
1338 * Read how long it took to see the echo to find the tuning
1341 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
1342 if (linktest == RL_CSCFG_ROW3)
1343 sc->rl_twist_row = 3;
1344 else if (linktest == RL_CSCFG_ROW2)
1345 sc->rl_twist_row = 2;
1346 else if (linktest == RL_CSCFG_ROW1)
1347 sc->rl_twist_row = 1;
1349 sc->rl_twist_row = 0;
1350 sc->rl_twist_col = 0;
1351 sc->rl_twister = SET_PARAM;
1354 if (sc->rl_twist_col == 0)
1355 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET);
1356 CSR_WRITE_4(sc, RL_PARA7C,
1357 param[sc->rl_twist_row][sc->rl_twist_col]);
1358 if (++sc->rl_twist_col == 4) {
1359 if (sc->rl_twist_row == 3)
1360 sc->rl_twister = RECHK_LONG;
1362 sc->rl_twister = DONE;
1367 * For long cables, we have to double check to make sure we
1370 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
1371 if (linktest == RL_CSCFG_ROW3)
1372 sc->rl_twister = DONE;
1374 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_RETUNE);
1375 sc->rl_twister = RETUNE;
1379 /* Retune for a shorter cable (try column 2) */
1380 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST);
1381 CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF);
1382 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF);
1383 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET);
1385 sc->rl_twist_col = 0;
1386 sc->rl_twister = SET_PARAM;
1398 struct rl_softc *sc = xsc;
1399 struct mii_data *mii;
1404 * If we're doing the twister cable calibration, then we need to defer
1405 * watchdog timeouts. This is a no-op in normal operations, but
1406 * can falsely trigger when the cable calibration takes a while and
1407 * there was traffic ready to go when rl was started.
1409 * We don't defer mii_tick since that updates the mii status, which
1410 * helps the twister process, at least according to similar patches
1411 * for the Linux driver I found online while doing the fixes. Worst
1412 * case is a few extra mii reads during calibration.
1414 mii = device_get_softc(sc->rl_miibus);
1416 if ((sc->rl_flags & RL_FLAG_LINK) == 0)
1417 rl_miibus_statchg(sc->rl_dev);
1418 if (sc->rl_twister_enable) {
1419 if (sc->rl_twister == DONE)
1422 rl_twister_update(sc);
1423 if (sc->rl_twister == DONE)
1432 callout_reset(&sc->rl_stat_callout, ticks, rl_tick, sc);
1435 #ifdef DEVICE_POLLING
1437 rl_poll(if_t ifp, enum poll_cmd cmd, int count)
1439 struct rl_softc *sc = if_getsoftc(ifp);
1443 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1444 rx_npkts = rl_poll_locked(ifp, cmd, count);
1450 rl_poll_locked(if_t ifp, enum poll_cmd cmd, int count)
1452 struct rl_softc *sc = if_getsoftc(ifp);
1457 sc->rxcycles = count;
1458 rx_npkts = rl_rxeof(sc);
1461 if (!if_sendq_empty(ifp))
1462 rl_start_locked(ifp);
1464 if (cmd == POLL_AND_CHECK_STATUS) {
1467 /* We should also check the status register. */
1468 status = CSR_READ_2(sc, RL_ISR);
1469 if (status == 0xffff)
1472 CSR_WRITE_2(sc, RL_ISR, status);
1474 /* XXX We should check behaviour on receiver stalls. */
1476 if (status & RL_ISR_SYSTEM_ERR) {
1477 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1483 #endif /* DEVICE_POLLING */
1488 struct rl_softc *sc = arg;
1489 if_t ifp = sc->rl_ifp;
1498 #ifdef DEVICE_POLLING
1499 if (if_getcapenable(ifp) & IFCAP_POLLING)
1503 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
1505 status = CSR_READ_2(sc, RL_ISR);
1506 if (status == 0xffff || (status & RL_INTRS) == 0)
1509 * Ours, disable further interrupts.
1511 CSR_WRITE_2(sc, RL_IMR, 0);
1512 for (count = 16; count > 0; count--) {
1513 CSR_WRITE_2(sc, RL_ISR, status);
1514 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
1515 if (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR))
1517 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR))
1519 if (status & RL_ISR_SYSTEM_ERR) {
1520 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1526 status = CSR_READ_2(sc, RL_ISR);
1527 /* If the card has gone away, the read returns 0xffff. */
1528 if (status == 0xffff || (status & RL_INTRS) == 0)
1532 if (!if_sendq_empty(ifp))
1533 rl_start_locked(ifp);
1536 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1537 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1543 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1544 * pointers to the fragment pointers.
1547 rl_encap(struct rl_softc *sc, struct mbuf **m_head)
1550 bus_dma_segment_t txsegs[1];
1551 int error, nsegs, padlen;
1558 * Hardware doesn't auto-pad, so we have to make sure
1559 * pad short frames out to the minimum frame length.
1561 if (m->m_pkthdr.len < RL_MIN_FRAMELEN)
1562 padlen = RL_MIN_FRAMELEN - m->m_pkthdr.len;
1564 * The RealTek is brain damaged and wants longword-aligned
1565 * TX buffers, plus we can only have one fragment buffer
1566 * per packet. We have to copy pretty much all the time.
1568 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0 ||
1569 (padlen > 0 && M_TRAILINGSPACE(m) < padlen)) {
1570 m = m_defrag(*m_head, M_NOWAIT);
1581 * Make security-conscious people happy: zero out the
1582 * bytes in the pad area, since we don't know what
1583 * this mbuf cluster buffer's previous user might
1586 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1587 m->m_pkthdr.len += padlen;
1588 m->m_len = m->m_pkthdr.len;
1591 error = bus_dmamap_load_mbuf_sg(sc->rl_cdata.rl_tx_tag,
1592 RL_CUR_DMAMAP(sc), m, txsegs, &nsegs, 0);
1601 RL_CUR_TXMBUF(sc) = m;
1602 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc),
1603 BUS_DMASYNC_PREWRITE);
1604 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), RL_ADDR_LO(txsegs[0].ds_addr));
1610 * Main transmit routine.
1615 struct rl_softc *sc = if_getsoftc(ifp);
1618 rl_start_locked(ifp);
1623 rl_start_locked(if_t ifp)
1625 struct rl_softc *sc = if_getsoftc(ifp);
1626 struct mbuf *m_head = NULL;
1630 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1631 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
1634 while (RL_CUR_TXMBUF(sc) == NULL) {
1635 m_head = if_dequeue(ifp);
1640 if (rl_encap(sc, &m_head)) {
1643 if_sendq_prepend(ifp, m_head);
1644 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1648 /* Pass a copy of this mbuf chain to the bpf subsystem. */
1649 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1651 /* Transmit the frame. */
1652 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1653 RL_TXTHRESH(sc->rl_txthresh) |
1654 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1656 RL_INC(sc->rl_cdata.cur_tx);
1658 /* Set a timeout in case the chip goes out to lunch. */
1659 sc->rl_watchdog_timer = 5;
1663 * We broke out of the loop because all our TX slots are
1664 * full. Mark the NIC as busy until it drains some of the
1665 * packets from the queue.
1667 if (RL_CUR_TXMBUF(sc) != NULL)
1668 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1674 struct rl_softc *sc = xsc;
1682 rl_init_locked(struct rl_softc *sc)
1684 if_t ifp = sc->rl_ifp;
1685 struct mii_data *mii;
1690 mii = device_get_softc(sc->rl_miibus);
1692 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1696 * Cancel pending I/O and free all RX/TX buffers.
1701 if (sc->rl_twister_enable) {
1703 * Reset twister register tuning state. The twister
1704 * registers and their tuning are undocumented, but
1705 * are necessary to cope with bad links. rl_twister =
1706 * DONE here will disable this entirely.
1708 sc->rl_twister = CHK_LINK;
1712 * Init our MAC address. Even though the chipset
1713 * documentation doesn't mention it, we need to enter "Config
1714 * register write enable" mode to modify the ID registers.
1716 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1717 bzero(eaddr, sizeof(eaddr));
1718 bcopy(if_getlladdr(sc->rl_ifp), eaddr, ETHER_ADDR_LEN);
1719 CSR_WRITE_STREAM_4(sc, RL_IDR0, eaddr[0]);
1720 CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]);
1721 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1723 /* Init the RX memory block pointer register. */
1724 CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr +
1725 RL_RX_8139_BUF_RESERVE);
1726 /* Init TX descriptors. */
1727 rl_list_tx_init(sc);
1728 /* Init Rx memory block. */
1729 rl_list_rx_init(sc);
1732 * Enable transmit and receive.
1734 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1737 * Set the initial TX and RX configuration.
1739 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1740 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1742 /* Set RX filter. */
1745 #ifdef DEVICE_POLLING
1746 /* Disable interrupts if we are polling. */
1747 if (if_getcapenable(ifp) & IFCAP_POLLING)
1748 CSR_WRITE_2(sc, RL_IMR, 0);
1751 /* Enable interrupts. */
1752 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1754 /* Set initial TX threshold */
1755 sc->rl_txthresh = RL_TX_THRESH_INIT;
1757 /* Start RX/TX process. */
1758 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1760 /* Enable receiver and transmitter. */
1761 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1763 sc->rl_flags &= ~RL_FLAG_LINK;
1766 CSR_WRITE_1(sc, sc->rl_cfg1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1768 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
1769 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1771 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1775 * Set media options.
1778 rl_ifmedia_upd(if_t ifp)
1780 struct rl_softc *sc = if_getsoftc(ifp);
1781 struct mii_data *mii;
1783 mii = device_get_softc(sc->rl_miibus);
1793 * Report current media status.
1796 rl_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
1798 struct rl_softc *sc = if_getsoftc(ifp);
1799 struct mii_data *mii;
1801 mii = device_get_softc(sc->rl_miibus);
1805 ifmr->ifm_active = mii->mii_media_active;
1806 ifmr->ifm_status = mii->mii_media_status;
1811 rl_ioctl(if_t ifp, u_long command, caddr_t data)
1813 struct ifreq *ifr = (struct ifreq *)data;
1814 struct mii_data *mii;
1815 struct rl_softc *sc = if_getsoftc(ifp);
1816 int error = 0, mask;
1821 if (if_getflags(ifp) & IFF_UP) {
1822 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
1823 ((if_getflags(ifp) ^ sc->rl_if_flags) &
1824 (IFF_PROMISC | IFF_ALLMULTI)))
1828 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1830 sc->rl_if_flags = if_getflags(ifp);
1841 mii = device_get_softc(sc->rl_miibus);
1842 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1845 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1846 #ifdef DEVICE_POLLING
1847 if (ifr->ifr_reqcap & IFCAP_POLLING &&
1848 !(if_getcapenable(ifp) & IFCAP_POLLING)) {
1849 error = ether_poll_register(rl_poll, ifp);
1853 /* Disable interrupts */
1854 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1855 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
1860 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
1861 if_getcapenable(ifp) & IFCAP_POLLING) {
1862 error = ether_poll_deregister(ifp);
1863 /* Enable interrupts. */
1865 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1866 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
1870 #endif /* DEVICE_POLLING */
1871 if ((mask & IFCAP_WOL) != 0 &&
1872 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) {
1873 if ((mask & IFCAP_WOL_UCAST) != 0)
1874 if_togglecapenable(ifp, IFCAP_WOL_UCAST);
1875 if ((mask & IFCAP_WOL_MCAST) != 0)
1876 if_togglecapenable(ifp, IFCAP_WOL_MCAST);
1877 if ((mask & IFCAP_WOL_MAGIC) != 0)
1878 if_togglecapenable(ifp, IFCAP_WOL_MAGIC);
1882 error = ether_ioctl(ifp, command, data);
1890 rl_watchdog(struct rl_softc *sc)
1895 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer >0)
1898 device_printf(sc->rl_dev, "watchdog timeout\n");
1899 if_inc_counter(sc->rl_ifp, IFCOUNTER_OERRORS, 1);
1903 if_setdrvflagbits(sc->rl_ifp, 0, IFF_DRV_RUNNING);
1908 * Stop the adapter and free any mbufs allocated to the
1912 rl_stop(struct rl_softc *sc)
1915 if_t ifp = sc->rl_ifp;
1919 sc->rl_watchdog_timer = 0;
1920 callout_stop(&sc->rl_stat_callout);
1921 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
1922 sc->rl_flags &= ~RL_FLAG_LINK;
1924 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1925 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1926 for (i = 0; i < RL_TIMEOUT; i++) {
1928 if ((CSR_READ_1(sc, RL_COMMAND) &
1929 (RL_CMD_RX_ENB | RL_CMD_TX_ENB)) == 0)
1932 if (i == RL_TIMEOUT)
1933 device_printf(sc->rl_dev, "Unable to stop Tx/Rx MAC\n");
1936 * Free the TX list buffers.
1938 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1939 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1940 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag,
1941 sc->rl_cdata.rl_tx_dmamap[i],
1942 BUS_DMASYNC_POSTWRITE);
1943 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag,
1944 sc->rl_cdata.rl_tx_dmamap[i]);
1945 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1946 sc->rl_cdata.rl_tx_chain[i] = NULL;
1947 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1954 * Device suspend routine. Stop the interface and save some PCI
1955 * settings in case the BIOS doesn't restore them properly on
1959 rl_suspend(device_t dev)
1961 struct rl_softc *sc;
1963 sc = device_get_softc(dev);
1975 * Device resume routine. Restore some PCI settings in case the BIOS
1976 * doesn't, re-enable busmastering, and restart the interface if
1980 rl_resume(device_t dev)
1982 struct rl_softc *sc;
1987 sc = device_get_softc(dev);
1992 if ((if_getcapabilities(ifp) & IFCAP_WOL) != 0 &&
1993 pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) {
1994 /* Disable PME and clear PME status. */
1995 pmstat = pci_read_config(sc->rl_dev,
1996 pmc + PCIR_POWER_STATUS, 2);
1997 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
1998 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1999 pci_write_config(sc->rl_dev,
2000 pmc + PCIR_POWER_STATUS, pmstat, 2);
2003 * Clear WOL matching such that normal Rx filtering
2004 * wouldn't interfere with WOL patterns.
2009 /* reinitialize interface if necessary */
2010 if (if_getflags(ifp) & IFF_UP)
2021 * Stop all chip I/O so that the kernel's probe routines don't
2022 * get confused by errant DMAs when rebooting.
2025 rl_shutdown(device_t dev)
2027 struct rl_softc *sc;
2029 sc = device_get_softc(dev);
2034 * Mark interface as down since otherwise we will panic if
2035 * interrupt comes in later on, which can happen in some
2038 if_setflagbits(sc->rl_ifp, 0, IFF_UP);
2046 rl_setwol(struct rl_softc *sc)
2056 if ((if_getcapabilities(ifp) & IFCAP_WOL) == 0)
2058 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
2061 /* Enable config register write. */
2062 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
2065 v = CSR_READ_1(sc, sc->rl_cfg1);
2067 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
2069 CSR_WRITE_1(sc, sc->rl_cfg1, v);
2071 v = CSR_READ_1(sc, sc->rl_cfg3);
2072 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
2073 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0)
2074 v |= RL_CFG3_WOL_MAGIC;
2075 CSR_WRITE_1(sc, sc->rl_cfg3, v);
2077 v = CSR_READ_1(sc, sc->rl_cfg5);
2078 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
2079 v &= ~RL_CFG5_WOL_LANWAKE;
2080 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) != 0)
2081 v |= RL_CFG5_WOL_UCAST;
2082 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0)
2083 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
2084 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
2085 v |= RL_CFG5_WOL_LANWAKE;
2086 CSR_WRITE_1(sc, sc->rl_cfg5, v);
2088 /* Config register write done. */
2089 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2091 /* Request PME if WOL is requested. */
2092 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
2093 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2094 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
2095 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2096 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
2100 rl_clrwol(struct rl_softc *sc)
2106 if ((if_getcapabilities(ifp) & IFCAP_WOL) == 0)
2109 /* Enable config register write. */
2110 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
2112 v = CSR_READ_1(sc, sc->rl_cfg3);
2113 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
2114 CSR_WRITE_1(sc, sc->rl_cfg3, v);
2116 /* Config register write done. */
2117 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2119 v = CSR_READ_1(sc, sc->rl_cfg5);
2120 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
2121 v &= ~RL_CFG5_WOL_LANWAKE;
2122 CSR_WRITE_1(sc, sc->rl_cfg5, v);