2 * Copyright (c) Comtrol Corporation <support@comtrol.com>
5 * Redistribution and use in source and binary forms, with or without
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34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * rp.c - for RocketPort FreeBSD
41 #include "opt_compat.h"
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/endian.h>
46 #include <sys/fcntl.h>
47 #include <sys/malloc.h>
48 #include <sys/serial.h>
51 #include <sys/kernel.h>
52 #include <machine/resource.h>
53 #include <machine/bus.h>
58 #include <dev/rp/rpreg.h>
59 #include <dev/rp/rpvar.h>
61 static const char RocketPortVersion[] = "3.02";
63 static Byte_t RData[RDATASIZE] =
65 0x00, 0x09, 0xf6, 0x82,
66 0x02, 0x09, 0x86, 0xfb,
67 0x04, 0x09, 0x00, 0x0a,
68 0x06, 0x09, 0x01, 0x0a,
69 0x08, 0x09, 0x8a, 0x13,
70 0x0a, 0x09, 0xc5, 0x11,
71 0x0c, 0x09, 0x86, 0x85,
72 0x0e, 0x09, 0x20, 0x0a,
73 0x10, 0x09, 0x21, 0x0a,
74 0x12, 0x09, 0x41, 0xff,
75 0x14, 0x09, 0x82, 0x00,
76 0x16, 0x09, 0x82, 0x7b,
77 0x18, 0x09, 0x8a, 0x7d,
78 0x1a, 0x09, 0x88, 0x81,
79 0x1c, 0x09, 0x86, 0x7a,
80 0x1e, 0x09, 0x84, 0x81,
81 0x20, 0x09, 0x82, 0x7c,
82 0x22, 0x09, 0x0a, 0x0a
85 static Byte_t RRegData[RREGDATASIZE]=
87 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
88 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
89 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
90 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
91 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
92 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
93 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
94 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
95 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
96 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
97 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
98 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
99 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
103 /* IRQ number to MUDBAC register 2 mapping */
106 0,0,0,0x10,0x20,0x30,0,0,0,0x40,0x50,0x60,0x70,0,0,0x80
110 Byte_t rp_sBitMapClrTbl[8] =
112 0xfe,0xfd,0xfb,0xf7,0xef,0xdf,0xbf,0x7f
115 Byte_t rp_sBitMapSetTbl[8] =
117 0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80
120 static void rpfree(void *);
122 /***************************************************************************
123 Function: sReadAiopID
124 Purpose: Read the AIOP idenfication number directly from an AIOP.
125 Call: sReadAiopID(CtlP, aiop)
126 CONTROLLER_T *CtlP; Ptr to controller structure
128 Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
129 is replace by an identifying number.
130 Flag AIOPID_NULL if no valid AIOP is found
131 Warnings: No context switches are allowed while executing this function.
134 int sReadAiopID(CONTROLLER_T *CtlP, int aiop)
136 Byte_t AiopID; /* ID byte from AIOP */
138 rp_writeaiop1(CtlP, aiop, _CMD_REG, RESET_ALL); /* reset AIOP */
139 rp_writeaiop1(CtlP, aiop, _CMD_REG, 0x0);
140 AiopID = rp_readaiop1(CtlP, aiop, _CHN_STAT0) & 0x07;
143 else /* AIOP does not exist */
147 /***************************************************************************
148 Function: sReadAiopNumChan
149 Purpose: Read the number of channels available in an AIOP directly from
151 Call: sReadAiopNumChan(CtlP, aiop)
152 CONTROLLER_T *CtlP; Ptr to controller structure
154 Return: int: The number of channels available
155 Comments: The number of channels is determined by write/reads from identical
156 offsets within the SRAM address spaces for channels 0 and 4.
157 If the channel 4 space is mirrored to channel 0 it is a 4 channel
158 AIOP, otherwise it is an 8 channel.
159 Warnings: No context switches are allowed while executing this function.
161 int sReadAiopNumChan(CONTROLLER_T *CtlP, int aiop)
165 rp_writeaiop4(CtlP, aiop, _INDX_ADDR,0x12340000L); /* write to chan 0 SRAM */
166 rp_writeaiop2(CtlP, aiop, _INDX_ADDR,0); /* read from SRAM, chan 0 */
167 x = rp_readaiop2(CtlP, aiop, _INDX_DATA);
168 rp_writeaiop2(CtlP, aiop, _INDX_ADDR,0x4000); /* read from SRAM, chan 4 */
169 y = rp_readaiop2(CtlP, aiop, _INDX_DATA);
170 if(x != y) /* if different must be 8 chan */
176 /***************************************************************************
178 Purpose: Initialization of a channel and channel structure
179 Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
180 CONTROLLER_T *CtlP; Ptr to controller structure
181 CHANNEL_T *ChP; Ptr to channel structure
182 int AiopNum; AIOP number within controller
183 int ChanNum; Channel number within AIOP
184 Return: int: TRUE if initialization succeeded, FALSE if it fails because channel
185 number exceeds number of channels available in AIOP.
186 Comments: This function must be called before a channel can be used.
187 Warnings: No range checking on any of the parameters is done.
189 No context switches are allowed while executing this function.
191 int sInitChan( CONTROLLER_T *CtlP,
200 if(ChanNum >= CtlP->AiopNumChan[AiopNum])
201 return(FALSE); /* exceeds num chans in AIOP */
203 /* Channel, AIOP, and controller identifiers */
205 ChP->ChanID = CtlP->AiopID[AiopNum];
206 ChP->AiopNum = AiopNum;
207 ChP->ChanNum = ChanNum;
209 /* Initialize the channel from the RData array */
210 for(i=0; i < RDATASIZE; i+=4)
213 R[1] = RData[i+1] + 0x10 * ChanNum;
216 rp_writech4(ChP,_INDX_ADDR,le32dec(R));
220 for(i=0; i < RREGDATASIZE; i+=4)
222 ChR[i] = RRegData[i];
223 ChR[i+1] = RRegData[i+1] + 0x10 * ChanNum;
224 ChR[i+2] = RRegData[i+2];
225 ChR[i+3] = RRegData[i+3];
228 /* Indexed registers */
229 ChOff = (Word_t)ChanNum * 0x1000;
231 ChP->BaudDiv[0] = (Byte_t)(ChOff + _BAUD);
232 ChP->BaudDiv[1] = (Byte_t)((ChOff + _BAUD) >> 8);
233 ChP->BaudDiv[2] = (Byte_t)BRD9600;
234 ChP->BaudDiv[3] = (Byte_t)(BRD9600 >> 8);
235 rp_writech4(ChP,_INDX_ADDR,le32dec(ChP->BaudDiv));
237 ChP->TxControl[0] = (Byte_t)(ChOff + _TX_CTRL);
238 ChP->TxControl[1] = (Byte_t)((ChOff + _TX_CTRL) >> 8);
239 ChP->TxControl[2] = 0;
240 ChP->TxControl[3] = 0;
241 rp_writech4(ChP,_INDX_ADDR,le32dec(ChP->TxControl));
243 ChP->RxControl[0] = (Byte_t)(ChOff + _RX_CTRL);
244 ChP->RxControl[1] = (Byte_t)((ChOff + _RX_CTRL) >> 8);
245 ChP->RxControl[2] = 0;
246 ChP->RxControl[3] = 0;
247 rp_writech4(ChP,_INDX_ADDR,le32dec(ChP->RxControl));
249 ChP->TxEnables[0] = (Byte_t)(ChOff + _TX_ENBLS);
250 ChP->TxEnables[1] = (Byte_t)((ChOff + _TX_ENBLS) >> 8);
251 ChP->TxEnables[2] = 0;
252 ChP->TxEnables[3] = 0;
253 rp_writech4(ChP,_INDX_ADDR,le32dec(ChP->TxEnables));
255 ChP->TxCompare[0] = (Byte_t)(ChOff + _TXCMP1);
256 ChP->TxCompare[1] = (Byte_t)((ChOff + _TXCMP1) >> 8);
257 ChP->TxCompare[2] = 0;
258 ChP->TxCompare[3] = 0;
259 rp_writech4(ChP,_INDX_ADDR,le32dec(ChP->TxCompare));
261 ChP->TxReplace1[0] = (Byte_t)(ChOff + _TXREP1B1);
262 ChP->TxReplace1[1] = (Byte_t)((ChOff + _TXREP1B1) >> 8);
263 ChP->TxReplace1[2] = 0;
264 ChP->TxReplace1[3] = 0;
265 rp_writech4(ChP,_INDX_ADDR,le32dec(ChP->TxReplace1));
267 ChP->TxReplace2[0] = (Byte_t)(ChOff + _TXREP2);
268 ChP->TxReplace2[1] = (Byte_t)((ChOff + _TXREP2) >> 8);
269 ChP->TxReplace2[2] = 0;
270 ChP->TxReplace2[3] = 0;
271 rp_writech4(ChP,_INDX_ADDR,le32dec(ChP->TxReplace2));
273 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
274 ChP->TxFIFO = ChOff + _TX_FIFO;
276 rp_writech1(ChP,_CMD_REG,(Byte_t)ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
277 rp_writech1(ChP,_CMD_REG,(Byte_t)ChanNum); /* remove reset Tx FIFO count */
278 rp_writech2(ChP,_INDX_ADDR,ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
279 rp_writech2(ChP,_INDX_DATA,0);
280 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
281 ChP->RxFIFO = ChOff + _RX_FIFO;
283 rp_writech1(ChP,_CMD_REG,(Byte_t)ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
284 rp_writech1(ChP,_CMD_REG,(Byte_t)ChanNum); /* remove reset Rx FIFO count */
285 rp_writech2(ChP,_INDX_ADDR,ChP->RxFIFOPtrs); /* clear Rx out ptr */
286 rp_writech2(ChP,_INDX_DATA,0);
287 rp_writech2(ChP,_INDX_ADDR,ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
288 rp_writech2(ChP,_INDX_DATA,0);
289 ChP->TxPrioCnt = ChOff + _TXP_CNT;
290 rp_writech2(ChP,_INDX_ADDR,ChP->TxPrioCnt);
291 rp_writech1(ChP,_INDX_DATA,0);
292 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
293 rp_writech2(ChP,_INDX_ADDR,ChP->TxPrioPtr);
294 rp_writech1(ChP,_INDX_DATA,0);
295 ChP->TxPrioBuf = ChOff + _TXP_BUF;
296 sEnRxProcessor(ChP); /* start the Rx processor */
301 /***************************************************************************
302 Function: sStopRxProcessor
303 Purpose: Stop the receive processor from processing a channel.
304 Call: sStopRxProcessor(ChP)
305 CHANNEL_T *ChP; Ptr to channel structure
307 Comments: The receive processor can be started again with sStartRxProcessor().
308 This function causes the receive processor to skip over the
309 stopped channel. It does not stop it from processing other channels.
311 Warnings: No context switches are allowed while executing this function.
313 Do not leave the receive processor stopped for more than one
316 After calling this function a delay of 4 uS is required to ensure
317 that the receive processor is no longer processing this channel.
319 void sStopRxProcessor(CHANNEL_T *ChP)
327 rp_writech4(ChP,_INDX_ADDR,le32dec(R));
330 /***************************************************************************
331 Function: sFlushRxFIFO
332 Purpose: Flush the Rx FIFO
333 Call: sFlushRxFIFO(ChP)
334 CHANNEL_T *ChP; Ptr to channel structure
336 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
337 while it is being flushed the receive processor is stopped
338 and the transmitter is disabled. After these operations a
339 4 uS delay is done before clearing the pointers to allow
340 the receive processor to stop. These items are handled inside
342 Warnings: No context switches are allowed while executing this function.
344 void sFlushRxFIFO(CHANNEL_T *ChP)
347 Byte_t Ch; /* channel number within AIOP */
348 int RxFIFOEnabled; /* TRUE if Rx FIFO enabled */
350 if(sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
351 return; /* don't need to flush */
353 RxFIFOEnabled = FALSE;
354 if(ChP->R[0x32] == 0x08) /* Rx FIFO is enabled */
356 RxFIFOEnabled = TRUE;
357 sDisRxFIFO(ChP); /* disable it */
358 for(i=0; i < 2000/200; i++) /* delay 2 uS to allow proc to disable FIFO*/
359 rp_readch1(ChP,_INT_CHAN); /* depends on bus i/o timing */
361 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
362 Ch = (Byte_t)sGetChanNum(ChP);
363 rp_writech1(ChP,_CMD_REG,Ch | RESRXFCNT); /* apply reset Rx FIFO count */
364 rp_writech1(ChP,_CMD_REG,Ch); /* remove reset Rx FIFO count */
365 rp_writech2(ChP,_INDX_ADDR,ChP->RxFIFOPtrs); /* clear Rx out ptr */
366 rp_writech2(ChP,_INDX_DATA,0);
367 rp_writech2(ChP,_INDX_ADDR,ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
368 rp_writech2(ChP,_INDX_DATA,0);
370 sEnRxFIFO(ChP); /* enable Rx FIFO */
373 /***************************************************************************
374 Function: sFlushTxFIFO
375 Purpose: Flush the Tx FIFO
376 Call: sFlushTxFIFO(ChP)
377 CHANNEL_T *ChP; Ptr to channel structure
379 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
380 while it is being flushed the receive processor is stopped
381 and the transmitter is disabled. After these operations a
382 4 uS delay is done before clearing the pointers to allow
383 the receive processor to stop. These items are handled inside
385 Warnings: No context switches are allowed while executing this function.
387 void sFlushTxFIFO(CHANNEL_T *ChP)
390 Byte_t Ch; /* channel number within AIOP */
391 int TxEnabled; /* TRUE if transmitter enabled */
393 if(sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
394 return; /* don't need to flush */
397 if(ChP->TxControl[3] & TX_ENABLE)
400 sDisTransmit(ChP); /* disable transmitter */
402 sStopRxProcessor(ChP); /* stop Rx processor */
403 for(i = 0; i < 4000/200; i++) /* delay 4 uS to allow proc to stop */
404 rp_readch1(ChP,_INT_CHAN); /* depends on bus i/o timing */
405 Ch = (Byte_t)sGetChanNum(ChP);
406 rp_writech1(ChP,_CMD_REG,Ch | RESTXFCNT); /* apply reset Tx FIFO count */
407 rp_writech1(ChP,_CMD_REG,Ch); /* remove reset Tx FIFO count */
408 rp_writech2(ChP,_INDX_ADDR,ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
409 rp_writech2(ChP,_INDX_DATA,0);
411 sEnTransmit(ChP); /* enable transmitter */
412 sStartRxProcessor(ChP); /* restart Rx processor */
415 /***************************************************************************
416 Function: sWriteTxPrioByte
417 Purpose: Write a byte of priority transmit data to a channel
418 Call: sWriteTxPrioByte(ChP,Data)
419 CHANNEL_T *ChP; Ptr to channel structure
420 Byte_t Data; The transmit data byte
422 Return: int: 1 if the bytes is successfully written, otherwise 0.
424 Comments: The priority byte is transmitted before any data in the Tx FIFO.
426 Warnings: No context switches are allowed while executing this function.
428 int sWriteTxPrioByte(CHANNEL_T *ChP, Byte_t Data)
430 Byte_t DWBuf[4]; /* buffer for double word writes */
432 if(sGetTxCnt(ChP) > 1) /* write it to Tx priority buffer */
434 rp_writech2(ChP,_INDX_ADDR,ChP->TxPrioCnt); /* get priority buffer status */
435 if(rp_readch1(ChP,_INDX_DATA) & PRI_PEND) /* priority buffer busy */
436 return(0); /* nothing sent */
438 le16enc(DWBuf,ChP->TxPrioBuf); /* data byte address */
440 DWBuf[2] = Data; /* data byte value */
441 DWBuf[3] = 0; /* priority buffer pointer */
442 rp_writech4(ChP,_INDX_ADDR,le32dec(DWBuf)); /* write it out */
444 le16enc(DWBuf,ChP->TxPrioCnt); /* Tx priority count address */
446 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
447 DWBuf[3] = 0; /* priority buffer pointer */
448 rp_writech4(ChP,_INDX_ADDR,le32dec(DWBuf)); /* write it out */
450 else /* write it to Tx FIFO */
452 sWriteTxByte(ChP,sGetTxRxDataIO(ChP),Data);
454 return(1); /* 1 byte sent */
457 /***************************************************************************
458 Function: sEnInterrupts
459 Purpose: Enable one or more interrupts for a channel
460 Call: sEnInterrupts(ChP,Flags)
461 CHANNEL_T *ChP; Ptr to channel structure
462 Word_t Flags: Interrupt enable flags, can be any combination
463 of the following flags:
464 TXINT_EN: Interrupt on Tx FIFO empty
465 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
467 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
468 MCINT_EN: Interrupt on modem input change
469 CHANINT_EN: Allow channel interrupt signal to the AIOP's
470 Interrupt Channel Register.
472 Comments: If an interrupt enable flag is set in Flags, that interrupt will be
473 enabled. If an interrupt enable flag is not set in Flags, that
474 interrupt will not be changed. Interrupts can be disabled with
475 function sDisInterrupts().
477 This function sets the appropriate bit for the channel in the AIOP's
478 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
479 this channel's bit to be set in the AIOP's Interrupt Channel Register.
481 Interrupts must also be globally enabled before channel interrupts
482 will be passed on to the host. This is done with function
485 In some cases it may be desirable to disable interrupts globally but
486 enable channel interrupts. This would allow the global interrupt
487 status register to be used to determine which AIOPs need service.
489 void sEnInterrupts(CHANNEL_T *ChP,Word_t Flags)
491 Byte_t Mask; /* Interrupt Mask Register */
494 ((Byte_t)Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
496 rp_writech4(ChP,_INDX_ADDR,le32dec(ChP->RxControl));
498 ChP->TxControl[2] |= ((Byte_t)Flags & TXINT_EN);
500 rp_writech4(ChP,_INDX_ADDR,le32dec(ChP->TxControl));
502 if(Flags & CHANINT_EN)
504 Mask = rp_readch1(ChP,_INT_MASK) | rp_sBitMapSetTbl[ChP->ChanNum];
505 rp_writech1(ChP,_INT_MASK,Mask);
509 /***************************************************************************
510 Function: sDisInterrupts
511 Purpose: Disable one or more interrupts for a channel
512 Call: sDisInterrupts(ChP,Flags)
513 CHANNEL_T *ChP; Ptr to channel structure
514 Word_t Flags: Interrupt flags, can be any combination
515 of the following flags:
516 TXINT_EN: Interrupt on Tx FIFO empty
517 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
519 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
520 MCINT_EN: Interrupt on modem input change
521 CHANINT_EN: Disable channel interrupt signal to the
522 AIOP's Interrupt Channel Register.
524 Comments: If an interrupt flag is set in Flags, that interrupt will be
525 disabled. If an interrupt flag is not set in Flags, that
526 interrupt will not be changed. Interrupts can be enabled with
527 function sEnInterrupts().
529 This function clears the appropriate bit for the channel in the AIOP's
530 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
531 this channel's bit from being set in the AIOP's Interrupt Channel
534 void sDisInterrupts(CHANNEL_T *ChP,Word_t Flags)
536 Byte_t Mask; /* Interrupt Mask Register */
539 ~((Byte_t)Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
540 rp_writech4(ChP,_INDX_ADDR,le32dec(ChP->RxControl));
541 ChP->TxControl[2] &= ~((Byte_t)Flags & TXINT_EN);
542 rp_writech4(ChP,_INDX_ADDR,le32dec(ChP->TxControl));
544 if(Flags & CHANINT_EN)
546 Mask = rp_readch1(ChP,_INT_MASK) & rp_sBitMapClrTbl[ChP->ChanNum];
547 rp_writech1(ChP,_INT_MASK,Mask);
551 /*********************************************************************
552 Begin FreeBsd-specific driver code
553 **********************************************************************/
555 struct callout_handle rp_callout_handle;
557 static int rp_num_ports_open = 0;
558 static int rp_ndevs = 0;
560 static int rp_num_ports[4]; /* Number of ports on each controller */
562 #define POLL_INTERVAL 1
564 #define RP_ISMULTIPORT(dev) ((dev)->id_flags & 0x1)
565 #define RP_MPMASTER(dev) (((dev)->id_flags >> 8) & 0xff)
566 #define RP_NOTAST4(dev) ((dev)->id_flags & 0x04)
568 static struct rp_port *p_rp_addr[4];
569 static struct rp_port *p_rp_table[MAX_RP_PORTS];
570 #define rp_addr(unit) (p_rp_addr[unit])
571 #define rp_table(port) (p_rp_table[port])
574 * The top-level routines begin here
577 static void rpclose(struct tty *tp);
578 static void rphardclose(struct tty *tp);
579 static int rpmodem(struct tty *, int, int);
580 static int rpparam(struct tty *, struct termios *);
581 static void rpstart(struct tty *);
582 static int rpioctl(struct tty *, u_long, caddr_t, struct thread *);
583 static int rpopen(struct tty *);
585 static void rp_do_receive(struct rp_port *rp, struct tty *tp,
586 CHANNEL_t *cp, unsigned int ChanStatus)
588 unsigned int CharNStat;
589 int ToRecv, ch, err = 0;
591 ToRecv = sGetRxCnt(cp);
595 /* If status indicates there are errored characters in the
596 FIFO, then enter status mode (a word in FIFO holds
597 characters and status)
600 if(ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
601 if(!(ChanStatus & STATMODE)) {
602 ChanStatus |= STATMODE;
607 if we previously entered status mode then read down the
608 FIFO one word at a time, pulling apart the character and
609 the status. Update error counters depending on status.
612 if(ChanStatus & STATMODE) {
614 CharNStat = rp_readch2(cp,sGetTxRxDataIO(cp));
615 ch = CharNStat & 0xff;
617 if((CharNStat & STMBREAK) || (CharNStat & STMFRAMEH))
619 else if (CharNStat & STMPARITYH)
621 else if (CharNStat & STMRCVROVRH) {
626 ttydisc_rint(tp, ch, err);
630 After emtying FIFO in status mode, turn off status mode
633 if(sGetRxCnt(cp) == 0) {
634 sDisRxStatusMode(cp);
637 ToRecv = sGetRxCnt(cp);
639 ch = rp_readch1(cp,sGetTxRxDataIO(cp));
640 ttydisc_rint(tp, ch & 0xff, err);
644 ttydisc_rint_done(tp);
648 static void rp_handle_port(struct rp_port *rp)
652 unsigned int IntMask, ChanStatus;
657 cp = &rp->rp_channel;
659 IntMask = sGetChanIntID(cp);
660 IntMask = IntMask & rp->rp_intmask;
661 ChanStatus = sGetChanStatus(cp);
662 if(IntMask & RXF_TRIG)
663 rp_do_receive(rp, tp, cp, ChanStatus);
664 if(IntMask & DELTA_CD) {
665 if(ChanStatus & CD_ACT) {
666 (void)ttydisc_modem(tp, 1);
668 (void)ttydisc_modem(tp, 0);
671 /* oldcts = rp->rp_cts;
672 rp->rp_cts = ((ChanStatus & CTS_ACT) != 0);
673 if(oldcts != rp->rp_cts) {
674 printf("CTS change (now %s)... on port %d\n", rp->rp_cts ? "on" : "off", rp->rp_port);
679 static void rp_do_poll(void *not_used)
684 int unit, aiop, ch, line, count;
685 unsigned char CtlMask, AiopMask;
687 for(unit = 0; unit < rp_ndevs; unit++) {
690 CtlMask = ctl->ctlmask(ctl);
691 for(aiop=0; CtlMask; CtlMask >>=1, aiop++) {
693 AiopMask = sGetAiopIntStatus(ctl, aiop);
694 for(ch = 0; AiopMask; AiopMask >>=1, ch++) {
696 line = (unit << 5) | (aiop << 3) | ch;
704 for(line = 0, rp = rp_addr(unit); line < rp_num_ports[unit];
708 count = sGetTxCnt(&rp->rp_channel);
710 (count <= rp->rp_restart)) {
716 if(rp_num_ports_open)
717 rp_callout_handle = timeout(rp_do_poll,
718 (void *)NULL, POLL_INTERVAL);
721 static struct ttydevsw rp_tty_class = {
722 .tsw_flags = TF_INITLOCK|TF_CALLOUT,
724 .tsw_close = rpclose,
725 .tsw_outwakeup = rpstart,
726 .tsw_ioctl = rpioctl,
727 .tsw_param = rpparam,
728 .tsw_modem = rpmodem,
736 struct rp_port *rp = softc;
737 CONTROLLER_t *ctlp = rp->rp_ctlp;
739 atomic_subtract_32(&ctlp->free, 1);
743 rp_attachcommon(CONTROLLER_T *ctlp, int num_aiops, int num_ports)
747 int aiop, chan, port;
748 int ChanStatus, line, count;
753 unit = device_get_unit(ctlp->dev);
755 printf("RocketPort%d (Version %s) %d ports.\n", unit,
756 RocketPortVersion, num_ports);
757 rp_num_ports[unit] = num_ports;
758 callout_handle_init(&rp_callout_handle);
760 ctlp->rp = rp = (struct rp_port *)
761 malloc(sizeof(struct rp_port) * num_ports, M_DEVBUF, M_NOWAIT | M_ZERO);
763 device_printf(ctlp->dev, "rp_attachcommon: Could not malloc rp_ports structures.\n");
768 count = unit * 32; /* board times max ports per card SG */
770 bzero(rp, sizeof(struct rp_port) * num_ports);
774 for(aiop=0; aiop < num_aiops; aiop++) {
775 num_chan = sGetAiopNumChan(ctlp, aiop);
776 for(chan=0; chan < num_chan; chan++, port++, rp++) {
777 rp->rp_tty = tp = tty_alloc(&rp_tty_class, rp);
784 rp->rp_intmask = RXF_TRIG | TXFIFO_MT | SRC_INT |
785 DELTA_CD | DELTA_CTS | DELTA_DSR;
787 ChanStatus = sGetChanStatus(&rp->rp_channel);
789 if(sInitChan(ctlp, &rp->rp_channel, aiop, chan) == 0) {
790 device_printf(ctlp->dev, "RocketPort sInitChan(%d, %d, %d) failed.\n",
795 ChanStatus = sGetChanStatus(&rp->rp_channel);
796 rp->rp_cts = (ChanStatus & CTS_ACT) != 0;
797 line = (unit << 5) | (aiop << 3) | chan;
799 tty_makedev(tp, NULL, "R%r%r", unit, port);
804 mtx_init(&ctlp->hwmtx, "rp_hwmtx", NULL, MTX_DEF);
805 ctlp->hwmtx_init = 1;
809 rp_releaseresource(ctlp);
815 rp_releaseresource(CONTROLLER_t *ctlp)
821 unit = device_get_unit(ctlp->dev);
822 if (rp_addr(unit) != NULL) {
823 for (i = 0; i < rp_num_ports[unit]; i++) {
824 rp = rp_addr(unit) + i;
825 atomic_add_32(&ctlp->free, 1);
826 tty_lock(rp->rp_tty);
827 tty_rel_gone(rp->rp_tty);
831 while (ctlp->free != 0) {
832 pause("rpwt", hz / 10);
835 if (ctlp->rp != NULL) {
836 for (i = 0 ; i < sizeof(p_rp_addr) / sizeof(*p_rp_addr) ; i++)
837 if (p_rp_addr[i] == ctlp->rp)
839 for (i = 0 ; i < sizeof(p_rp_table) / sizeof(*p_rp_table) ; i++)
840 if (p_rp_table[i] == ctlp->rp)
841 p_rp_table[i] = NULL;
842 free(ctlp->rp, M_DEVBUF);
850 untimeout(rp_do_poll, (void *)NULL, rp_callout_handle);
854 rpopen(struct tty *tp)
858 unsigned int IntMask, ChanStatus;
865 rp->rp_channel.TxControl[3] =
866 ((rp->rp_channel.TxControl[3]
867 & ~(SET_RTS | SET_DTR)) | flags);
868 rp_writech4(&rp->rp_channel,_INDX_ADDR,
869 le32dec(rp->rp_channel.TxControl));
870 sSetRxTrigger(&rp->rp_channel, TRIG_1);
871 sDisRxStatusMode(&rp->rp_channel);
872 sFlushRxFIFO(&rp->rp_channel);
873 sFlushTxFIFO(&rp->rp_channel);
875 sEnInterrupts(&rp->rp_channel,
876 (TXINT_EN|MCINT_EN|RXINT_EN|SRCINT_EN|CHANINT_EN));
877 sSetRxTrigger(&rp->rp_channel, TRIG_1);
879 sDisRxStatusMode(&rp->rp_channel);
880 sClrTxXOFF(&rp->rp_channel);
882 /* sDisRTSFlowCtl(&rp->rp_channel);
883 sDisCTSFlowCtl(&rp->rp_channel);
885 sDisTxSoftFlowCtl(&rp->rp_channel);
887 sStartRxProcessor(&rp->rp_channel);
889 sEnRxFIFO(&rp->rp_channel);
890 sEnTransmit(&rp->rp_channel);
892 /* sSetDTR(&rp->rp_channel);
893 sSetRTS(&rp->rp_channel);
898 IntMask = sGetChanIntID(&rp->rp_channel);
899 IntMask = IntMask & rp->rp_intmask;
900 ChanStatus = sGetChanStatus(&rp->rp_channel);
902 if(rp_num_ports_open == 1)
903 rp_callout_handle = timeout(rp_do_poll,
904 (void *)NULL, POLL_INTERVAL);
906 device_busy(rp->rp_ctlp->dev);
911 rpclose(struct tty *tp)
917 device_unbusy(rp->rp_ctlp->dev);
921 rphardclose(struct tty *tp)
927 cp = &rp->rp_channel;
932 sDisInterrupts(cp, TXINT_EN|MCINT_EN|RXINT_EN|SRCINT_EN|CHANINT_EN);
935 sDisTxSoftFlowCtl(cp);
939 if(tp->t_cflag&HUPCL || !(tp->t_state&TS_ISOPEN) || !tp->t_actout) {
942 if(ISCALLOUT(tp->t_dev)) {
945 tp->t_actout = FALSE;
946 wakeup(&tp->t_actout);
947 wakeup(TSA_CARR_ON(tp));
952 rpioctl(struct tty *tp, u_long cmd, caddr_t data, struct thread *td)
959 sSendBreak(&rp->rp_channel);
962 sClrBreak(&rp->rp_channel);
970 rpmodem(struct tty *tp, int sigon, int sigoff)
976 if (sigon != 0 || sigoff != 0) {
980 if (sigoff & SER_DTR)
984 if (sigoff & SER_RTS)
986 rp->rp_channel.TxControl[3] &= ~i;
987 rp->rp_channel.TxControl[3] |= j;
988 rp_writech4(&rp->rp_channel,_INDX_ADDR,
989 le32dec(rp->rp_channel.TxControl));
991 i = sGetChanStatusLo(&rp->rp_channel);
992 j = rp->rp_channel.TxControl[3];
1014 {B0, 0}, {B50, BRD50}, {B75, BRD75},
1015 {B110, BRD110}, {B134, BRD134}, {B150, BRD150},
1016 {B200, BRD200}, {B300, BRD300}, {B600, BRD600},
1017 {B1200, BRD1200}, {B1800, BRD1800}, {B2400, BRD2400},
1018 {B4800, BRD4800}, {B9600, BRD9600}, {B19200, BRD19200},
1019 {B38400, BRD38400}, {B7200, BRD7200}, {B14400, BRD14400},
1020 {B57600, BRD57600}, {B76800, BRD76800},
1021 {B115200, BRD115200}, {B230400, BRD230400},
1025 static int rp_convert_baud(int baud) {
1028 for (i = 0; baud_table[i].baud >= 0; i++) {
1029 if (baud_table[i].baud == baud)
1033 return baud_table[i].conversion;
1043 int cflag, iflag, oflag, lflag;
1050 cp = &rp->rp_channel;
1054 devshift = umynor / 32;
1055 devshift = 1 << devshift;
1056 if ( devshift & RPCLOCAL ) {
1064 ospeed = rp_convert_baud(t->c_ispeed);
1065 if(ospeed < 0 || t->c_ispeed != t->c_ospeed)
1068 if(t->c_ospeed == 0) {
1072 rp->rp_fifo_lw = ((t->c_ospeed*2) / 1000) +1;
1074 /* Set baud rate ----- we only pay attention to ispeed */
1077 sSetBaud(cp, ospeed);
1079 if(cflag & CSTOPB) {
1085 if(cflag & PARENB) {
1087 if(cflag & PARODD) {
1096 if((cflag & CSIZE) == CS8) {
1098 rp->rp_imask = 0xFF;
1101 rp->rp_imask = 0x7F;
1104 if(iflag & ISTRIP) {
1105 rp->rp_imask &= 0x7F;
1108 if(cflag & CLOCAL) {
1109 rp->rp_intmask &= ~DELTA_CD;
1111 rp->rp_intmask |= DELTA_CD;
1114 /* Put flow control stuff here */
1116 if(cflag & CCTS_OFLOW) {
1122 if(cflag & CRTS_IFLOW) {
1123 rp->rp_rts_iflow = 1;
1125 rp->rp_rts_iflow = 0;
1128 if(cflag & CRTS_IFLOW) {
1138 rpstart(struct tty *tp)
1144 int i, count, wcount;
1147 cp = &rp->rp_channel;
1148 flags = rp->rp_channel.TxControl[3];
1150 if(rp->rp_xmit_stopped) {
1152 rp->rp_xmit_stopped = 0;
1155 xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1156 count = ttydisc_getc(tp, &rp->TxBuf, xmit_fifo_room);
1157 if(xmit_fifo_room > 0) {
1158 for( i = 0, wcount = count >> 1; wcount > 0; i += 2, wcount-- ) {
1159 rp_writech2(cp, sGetTxRxDataIO(cp), le16dec(&rp->TxBuf[i]));
1162 rp_writech1(cp, sGetTxRxDataIO(cp), rp->TxBuf[(count-1)]);