2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) Comtrol Corporation <support@comtrol.com>
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38 * Begin OS-specific defines - rpreg.h - for RocketPort FreeBSD
41 typedef uint8_t Byte_t;
42 typedef uint8_t ByteIO_t;
44 typedef uint16_t Word_t;
45 typedef uint16_t WordIO_t;
47 typedef uint32_t DWord_t;
48 typedef uint32_t DWordIO_t;
50 #define rp_readio(size, ctlp, rid, offset) \
51 (bus_read_##size(ctlp->io[rid], offset))
52 #define rp_readmultiio(size, ctlp, rid, offset, addr, count) \
53 (bus_read_multi_##size(ctlp->io[rid], offset, addr, count))
54 #define rp_writeio(size, ctlp, rid, offset, data) \
55 (bus_write_##size(ctlp->io[rid], offset, data))
56 #define rp_writemultiio(size, ctlp, rid, offset, addr, count) \
57 (bus_write_multi_##size(ctlp->io[rid], offset, addr, count))
59 #define rp_readio1(ctlp, rid, offset) rp_readio(1, ctlp, rid, offset)
60 #define rp_readio2(ctlp, rid, offset) rp_readio(2, ctlp, rid, offset)
61 #define rp_readio4(ctlp, rid, offset) rp_readio(4, ctlp, rid, offset)
62 #define rp_writeio1(ctlp, rid, offset, data) rp_writeio(1, ctlp, rid, offset, data)
63 #define rp_writeio2(ctlp, rid, offset, data) rp_writeio(2, ctlp, rid, offset, data)
64 #define rp_writeio4(ctlp, rid, offset, data) rp_writeio(4, ctlp, rid, offset, data)
65 #define rp_readmultiio1(ctlp, rid, offset, addr, count) rp_readmultiio(1, ctlp, rid, offset, addr, count)
66 #define rp_readmultiio2(ctlp, rid, offset, addr, count) rp_readmultiio(2, ctlp, rid, offset, addr, count)
67 #define rp_readmultiio4(ctlp, rid, offset, addr, count) rp_readmultiio(4, ctlp, rid, offset, addr, count)
68 #define rp_writemultiio1(ctlp, rid, offset, addr, count) rp_writemultiio(1, ctlp, rid, offset, addr, count)
69 #define rp_writemultiio2(ctlp, rid, offset, addr, count) rp_writemultiio(2, ctlp, rid, offset, addr, count)
70 #define rp_writemultiio4(ctlp, rid, offset, addr, count) rp_writemultiio(4, ctlp, rid, offset, addr, count)
72 #define rp_readaiop1(ctlp, aiop, offset) \
73 (rp_readio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset)))
74 #define rp_readaiop2(ctlp, aiop, offset) \
75 (rp_readio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset)))
76 #define rp_readaiop4(ctlp, aiop, offset) \
77 (rp_readio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset)))
78 #define rp_readmultiaiop1(ctlp, aiop, offset, addr, count) \
79 (rp_readmultiio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
80 #define rp_readmultiaiop2(ctlp, aiop, offset, addr, count) \
81 (rp_readmultiio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
82 #define rp_readmultiaiop4(ctlp, aiop, offset, addr, count) \
83 (rp_readmultiio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
84 #define rp_writeaiop1(ctlp, aiop, offset, data) \
85 (rp_writeio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data))
86 #define rp_writeaiop2(ctlp, aiop, offset, data) \
87 (rp_writeio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data))
88 #define rp_writeaiop4(ctlp, aiop, offset, data) \
89 (rp_writeio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), data))
90 #define rp_writemultiaiop1(ctlp, aiop, offset, addr, count) \
91 (rp_writemultiio1((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
92 #define rp_writemultiaiop2(ctlp, aiop, offset, addr, count) \
93 (rp_writemultiio2((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
94 #define rp_writemultiaiop4(ctlp, aiop, offset, addr, count) \
95 (rp_writemultiio4((ctlp), (ctlp)->aiop2rid(aiop, offset), (ctlp)->aiop2off(aiop, offset), addr, count))
97 #define rp_readch1(chp, offset) \
98 (rp_readaiop1((chp)->CtlP, (chp)->AiopNum, offset))
99 #define rp_readch2(chp, offset) \
100 (rp_readaiop2((chp)->CtlP, (chp)->AiopNum, offset))
101 #define rp_readch4(chp, offset) \
102 (rp_readaiop4((chp)->CtlP, (chp)->AiopNum, offset))
103 #define rp_readmultich1(chp, offset, addr, count) \
104 (rp_readmultiaiop1((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
105 #define rp_readmultich2(chp, offset, addr, count) \
106 (rp_readmultiaiop2((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
107 #define rp_readmultich4(chp, offset, addr, count) \
108 (rp_readmultiaiop4((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
109 #define rp_writech1(chp, offset, data) \
110 (rp_writeaiop1((chp)->CtlP, (chp)->AiopNum, offset, data))
111 #define rp_writech2(chp, offset, data) \
112 (rp_writeaiop2((chp)->CtlP, (chp)->AiopNum, offset, data))
113 #define rp_writech4(chp, offset, data) \
114 (rp_writeaiop4((chp)->CtlP, (chp)->AiopNum, offset, data))
115 #define rp_writemultich1(chp, offset, addr, count) \
116 (rp_writemultiaiop1((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
117 #define rp_writemultich2(chp, offset, addr, count) \
118 (rp_writemultiaiop2((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
119 #define rp_writemultich4(chp, offset, addr, count) \
120 (rp_writemultiaiop4((chp)->CtlP, (chp)->AiopNum, offset, addr, count))
123 * End of OS-specific defines
129 #define AIOP_CTL_SIZE 4
130 #define CHAN_AIOP_SIZE 8
131 #define MAX_PORTS_PER_AIOP 8
132 #define MAX_AIOPS_PER_BOARD 4
133 #define MAX_PORTS_PER_BOARD 32
135 /* Controller ID numbers */
136 #define CTLID_NULL -1 /* no controller exists */
137 #define CTLID_0001 0x0001 /* controller release 1 */
139 /* AIOP ID numbers, identifies AIOP type implementing channel */
140 #define AIOPID_NULL -1 /* no AIOP or channel exists */
141 #define AIOPID_0001 0x0001 /* AIOP release 1 */
143 #define NULLDEV -1 /* identifies non-existant device */
144 #define NULLCTL -1 /* identifies non-existant controller */
145 #define NULLCTLPTR (CONTROLLER_T *)0 /* identifies non-existant controller */
146 #define NULLAIOP -1 /* identifies non-existant AIOP */
147 #define NULLCHAN -1 /* identifies non-existant channel */
149 /************************************************************************
150 Global Register Offsets - Direct Access - Fixed values
151 ************************************************************************/
153 #define _CMD_REG 0x38 /* Command Register 8 Write */
154 #define _INT_CHAN 0x39 /* Interrupt Channel Register 8 Read */
155 #define _INT_MASK 0x3A /* Interrupt Mask Register 8 Read / Write */
156 #define _UNUSED 0x3B /* Unused 8 */
157 #define _INDX_ADDR 0x3C /* Index Register Address 16 Write */
158 #define _INDX_DATA 0x3E /* Index Register Data 8/16 Read / Write */
160 /************************************************************************
161 Channel Register Offsets for 1st channel in AIOP - Direct Access
162 ************************************************************************/
163 #define _TD0 0x00 /* Transmit Data 16 Write */
164 #define _RD0 0x00 /* Receive Data 16 Read */
165 #define _CHN_STAT0 0x20 /* Channel Status 8/16 Read / Write */
166 #define _FIFO_CNT0 0x10 /* Transmit/Receive FIFO Count 16 Read */
167 #define _INT_ID0 0x30 /* Interrupt Identification 8 Read */
169 /************************************************************************
170 Tx Control Register Offsets - Indexed - External - Fixed
171 ************************************************************************/
172 #define _TX_ENBLS 0x980 /* Tx Processor Enables Register 8 Read / Write */
173 #define _TXCMP1 0x988 /* Transmit Compare Value #1 8 Read / Write */
174 #define _TXCMP2 0x989 /* Transmit Compare Value #2 8 Read / Write */
175 #define _TXREP1B1 0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */
176 #define _TXREP1B2 0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */
177 #define _TXREP2 0x98C /* Transmit Replace Value #2 8 Read / Write */
179 /************************************************************************
181 ************************************************************************/
182 #define RXFIFO_DATA 0x5f
183 #define RXFIFO_OUT 0x5c
184 #define RXFIFO_EN 0x08
185 #define RXFIFO_DIS 0xa7
187 /************************************************************************
188 Memory Controller Register Offsets - Indexed - External - Fixed
189 ************************************************************************/
190 #define _RX_FIFO 0x000 /* Rx FIFO */
191 #define _TX_FIFO 0x800 /* Tx FIFO */
192 #define _RXF_OUTP 0x990 /* Rx FIFO OUT pointer 16 Read / Write */
193 #define _RXF_INP 0x992 /* Rx FIFO IN pointer 16 Read / Write */
194 #define _TXF_OUTP 0x994 /* Tx FIFO OUT pointer 8 Read / Write */
195 #define _TXF_INP 0x995 /* Tx FIFO IN pointer 8 Read / Write */
196 #define _TXP_CNT 0x996 /* Tx Priority Count 8 Read / Write */
197 #define _TXP_PNTR 0x997 /* Tx Priority Pointer 8 Read / Write */
199 #define PRI_PEND 0x80 /* Priority data pending (bit7, Tx pri cnt) */
200 #define TXFIFO_SIZE 255 /* size of Tx FIFO */
201 #define RXFIFO_SIZE 1023 /* size of Rx FIFO */
203 /************************************************************************
204 Tx Priority Buffer - Indexed - External - Fixed
205 ************************************************************************/
206 #define _TXP_BUF 0x9C0 /* Tx Priority Buffer 32 Bytes Read / Write */
207 #define TXP_SIZE 0x20 /* 32 bytes */
209 /************************************************************************
210 Channel Register Offsets - Indexed - Internal - Fixed
211 ************************************************************************/
213 #define _TX_CTRL 0xFF0 /* Transmit Control 16 Write */
214 #define _RX_CTRL 0xFF2 /* Receive Control 8 Write */
215 #define _BAUD 0xFF4 /* Baud Rate 16 Write */
216 #define _CLK_PRE 0xFF6 /* Clock Prescaler 8 Write */
218 #define CLOCK_PRESC 0x19 /* mod 9 (divide by 10) prescale */
244 #define STMBREAK 0x08 /* BREAK */
245 #define STMFRAME 0x04 /* framing error */
246 #define STMRCVROVR 0x02 /* receiver over run error */
247 #define STMPARITY 0x01 /* parity error */
248 #define STMERROR (STMBREAK | STMFRAME | STMPARITY)
249 #define STMBREAKH 0x800 /* BREAK */
250 #define STMFRAMEH 0x400 /* framing error */
251 #define STMRCVROVRH 0x200 /* receiver over run error */
252 #define STMPARITYH 0x100 /* parity error */
253 #define STMERRORH (STMBREAKH | STMFRAMEH | STMPARITYH)
255 #define CTS_ACT 0x20 /* CTS input asserted */
256 #define DSR_ACT 0x10 /* DSR input asserted */
257 #define CD_ACT 0x08 /* CD input asserted */
258 #define TXFIFOMT 0x04 /* Tx FIFO is empty */
259 #define TXSHRMT 0x02 /* Tx shift register is empty */
260 #define RDA 0x01 /* Rx data available */
261 #define DRAINED (TXFIFOMT | TXSHRMT) /* indicates Tx is drained */
263 #define STATMODE 0x8000 /* status mode enable bit */
264 #define RXFOVERFL 0x2000 /* receive FIFO overflow */
265 #define RX2MATCH 0x1000 /* receive compare byte 2 match */
266 #define RX1MATCH 0x0800 /* receive compare byte 1 match */
267 #define RXBREAK 0x0400 /* received BREAK */
268 #define RXFRAME 0x0200 /* received framing error */
269 #define RXPARITY 0x0100 /* received parity error */
270 #define STATERROR (RXBREAK | RXFRAME | RXPARITY)
272 #define CTSFC_EN 0x80 /* CTS flow control enable bit */
273 #define RTSTOG_EN 0x40 /* RTS toggle enable bit */
274 #define TXINT_EN 0x10 /* transmit interrupt enable */
275 #define STOP2 0x08 /* enable 2 stop bits (0 = 1 stop) */
276 #define PARITY_EN 0x04 /* enable parity (0 = no parity) */
277 #define EVEN_PAR 0x02 /* even parity (0 = odd parity) */
278 #define DATA8BIT 0x01 /* 8 bit data (0 = 7 bit data) */
280 #define SETBREAK 0x10 /* send break condition (must clear) */
281 #define LOCALLOOP 0x08 /* local loopback set for test */
282 #define SET_DTR 0x04 /* assert DTR */
283 #define SET_RTS 0x02 /* assert RTS */
284 #define TX_ENABLE 0x01 /* enable transmitter */
286 #define RTSFC_EN 0x40 /* RTS flow control enable */
287 #define RXPROC_EN 0x20 /* receive processor enable */
288 #define TRIG_NO 0x00 /* Rx FIFO trigger level 0 (no trigger) */
289 #define TRIG_1 0x08 /* trigger level 1 char */
290 #define TRIG_1_2 0x10 /* trigger level 1/2 */
291 #define TRIG_7_8 0x18 /* trigger level 7/8 */
292 #define TRIG_MASK 0x18 /* trigger level mask */
293 #define SRCINT_EN 0x04 /* special Rx condition interrupt enable */
294 #define RXINT_EN 0x02 /* Rx interrupt enable */
295 #define MCINT_EN 0x01 /* modem change interrupt enable */
297 #define RXF_TRIG 0x20 /* Rx FIFO trigger level interrupt */
298 #define TXFIFO_MT 0x10 /* Tx FIFO empty interrupt */
299 #define SRC_INT 0x08 /* special receive condition interrupt */
300 #define DELTA_CD 0x04 /* CD change interrupt */
301 #define DELTA_CTS 0x02 /* CTS change interrupt */
302 #define DELTA_DSR 0x01 /* DSR change interrupt */
304 #define REP1W2_EN 0x10 /* replace byte 1 with 2 bytes enable */
305 #define IGN2_EN 0x08 /* ignore byte 2 enable */
306 #define IGN1_EN 0x04 /* ignore byte 1 enable */
307 #define COMP2_EN 0x02 /* compare byte 2 enable */
308 #define COMP1_EN 0x01 /* compare byte 1 enable */
310 #define RESET_ALL 0x80 /* reset AIOP (all channels) */
311 #define TXOVERIDE 0x40 /* Transmit software off override */
312 #define RESETUART 0x20 /* reset channel's UART */
313 #define RESTXFCNT 0x10 /* reset channel's Tx FIFO count register */
314 #define RESRXFCNT 0x08 /* reset channel's Rx FIFO count register */
316 #define INTSTAT0 0x01 /* AIOP 0 interrupt status */
317 #define INTSTAT1 0x02 /* AIOP 1 interrupt status */
318 #define INTSTAT2 0x04 /* AIOP 2 interrupt status */
319 #define INTSTAT3 0x08 /* AIOP 3 interrupt status */
321 #define INTR_EN 0x08 /* allow interrupts to host */
322 #define INT_STROB 0x04 /* strobe and clear interrupt line (EOI) */
324 #define CHAN3_EN 0x08 /* enable AIOP 3 */
325 #define CHAN2_EN 0x04 /* enable AIOP 2 */
326 #define CHAN1_EN 0x02 /* enable AIOP 1 */
327 #define CHAN0_EN 0x01 /* enable AIOP 0 */
328 #define FREQ_DIS 0x00
329 #define FREQ_274HZ 0x60
330 #define FREQ_137HZ 0x50
331 #define FREQ_69HZ 0x40
332 #define FREQ_34HZ 0x30
333 #define FREQ_17HZ 0x20
334 #define FREQ_9HZ 0x10
335 #define PERIODIC_ONLY 0x80 /* only PERIODIC interrupt */
337 #define CHANINT_EN 0x0100 /* flags to enable/disable channel ints */
340 #define RREGDATASIZE 52
350 struct CONTROLLER_str;
353 /* The types of bus-specific methods */
354 typedef int rp_aiop2rid_t(int, int);
355 typedef int rp_aiop2off_t(int, int);
356 typedef unsigned char rp_ctlmask_t(struct CONTROLLER_str *);
358 /* Controller level information structure */
359 struct CONTROLLER_str
363 int AiopID[AIOP_CTL_SIZE];
364 int AiopNumChan[AIOP_CTL_SIZE];
366 struct mtx hwmtx; /* Spinlock protecting hardware. */
371 /* Device and resource management */
372 device_t dev; /* device */
373 int io_num; /* Number of IO resources */
374 int *io_rid; /* IO resource IDs */
375 struct resource **io; /* IO resources */
377 struct rp_port *rp; /* port */
380 struct cdev **dev_nodes;
382 /* Bus-specific properties */
385 /* Bus-specific methods */
386 rp_aiop2rid_t *aiop2rid; /* (aiop, offset) -> rid */
387 rp_aiop2off_t *aiop2off; /* (aiop, offset) -> off */
388 rp_ctlmask_t *ctlmask; /* Int status */
390 typedef struct CONTROLLER_str CONTROLLER_T;
391 typedef CONTROLLER_T CONTROLLER_t;
393 /* Channel level information structure */
409 Byte_t R[RREGDATASIZE];
416 Byte_t TxReplace1[4];
417 Byte_t TxReplace2[4];
420 typedef struct CHANNEL_str CHANNEL_T;
421 typedef CHANNEL_T CHANNEL_t;
422 typedef CHANNEL_T * CHANPTR_T;
424 #define CHNOFF_TXRXDATA(chp) ((chp)->ChanNum * 2 + _TD0)
425 #define CHNOFF_CHANSTAT(chp) ((chp)->ChanNum * 2 + _CHN_STAT0)
426 #define CHNOFF_TXRXCOUNT(chp) ((chp)->ChanNum * 2 + _FIFO_CNT0)
427 #define CHNOFF_INTID(chp) ((chp)->ChanNum + _INT_ID0)
429 /***************************************************************************
431 Purpose: Stop sending a transmit BREAK signal
433 CHANNEL_T *ChP; Ptr to channel structure
435 #define sClrBreak(ChP) \
437 (ChP)->TxControl[3] &= ~SETBREAK; \
438 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
441 /***************************************************************************
443 Purpose: Clr the DTR output
445 CHANNEL_T *ChP; Ptr to channel structure
447 #define sClrDTR(ChP) \
449 (ChP)->TxControl[3] &= ~SET_DTR; \
450 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
453 /***************************************************************************
455 Purpose: Clr the RTS output
457 CHANNEL_T *ChP; Ptr to channel structure
459 #define sClrRTS(ChP) \
461 (ChP)->TxControl[3] &= ~SET_RTS; \
462 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
465 /***************************************************************************
467 Purpose: Clear any existing transmit software flow control off condition
468 Call: sClrTxXOFF(ChP)
469 CHANNEL_T *ChP; Ptr to channel structure
471 #define sClrTxXOFF(ChP) \
473 rp_writech1(ChP,_CMD_REG,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \
474 rp_writech1(ChP,_CMD_REG,(Byte_t)(ChP)->ChanNum); \
477 /***************************************************************************
478 Function: sDisCTSFlowCtl
479 Purpose: Disable output flow control using CTS
480 Call: sDisCTSFlowCtl(ChP)
481 CHANNEL_T *ChP; Ptr to channel structure
483 #define sDisCTSFlowCtl(ChP) \
485 (ChP)->TxControl[2] &= ~CTSFC_EN; \
486 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
489 /***************************************************************************
491 Purpose: Disable parity
492 Call: sDisParity(ChP)
493 CHANNEL_T *ChP; Ptr to channel structure
494 Comments: Function sSetParity() can be used in place of functions sEnParity(),
495 sDisParity(), sSetOddParity(), and sSetEvenParity().
497 #define sDisParity(ChP) \
499 (ChP)->TxControl[2] &= ~PARITY_EN; \
500 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
503 /***************************************************************************
505 Purpose: Disable Rx FIFO
506 Call: sDisRxFIFO(ChP)
507 CHANNEL_T *ChP; Ptr to channel structure
509 #define sDisRxFIFO(ChP) \
511 (ChP)->R[0x32] = 0x0a; \
512 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->R + 0x30)); \
515 /***************************************************************************
516 Function: sDisRxStatusMode
517 Purpose: Disable the Rx status mode
518 Call: sDisRxStatusMode(ChP)
519 CHANNEL_T *ChP; Ptr to channel structure
520 Comments: This takes the channel out of the receive status mode. All
521 subsequent reads of receive data using sReadRxWord() will return
524 #define sDisRxStatusMode(ChP) rp_writech2(ChP,CHNOFF_CHANSTAT(ChP),0)
526 /***************************************************************************
527 Function: sDisTransmit
528 Purpose: Disable transmit
529 Call: sDisTransmit(ChP)
530 CHANNEL_T *ChP; Ptr to channel structure
531 This disables movement of Tx data from the Tx FIFO into the 1 byte
532 Tx buffer. Therefore there could be up to a 2 byte latency
533 between the time sDisTransmit() is called and the transmit buffer
534 and transmit shift register going completely empty.
536 #define sDisTransmit(ChP) \
538 (ChP)->TxControl[3] &= ~TX_ENABLE; \
539 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
542 /***************************************************************************
543 Function: sDisTxSoftFlowCtl
544 Purpose: Disable Tx Software Flow Control
545 Call: sDisTxSoftFlowCtl(ChP)
546 CHANNEL_T *ChP; Ptr to channel structure
548 #define sDisTxSoftFlowCtl(ChP) \
550 (ChP)->R[0x06] = 0x8a; \
551 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->R + 0x04)); \
554 /***************************************************************************
555 Function: sEnCTSFlowCtl
556 Purpose: Enable output flow control using CTS
557 Call: sEnCTSFlowCtl(ChP)
558 CHANNEL_T *ChP; Ptr to channel structure
560 #define sEnCTSFlowCtl(ChP) \
562 (ChP)->TxControl[2] |= CTSFC_EN; \
563 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
566 /***************************************************************************
568 Purpose: Enable parity
570 CHANNEL_T *ChP; Ptr to channel structure
571 Comments: Function sSetParity() can be used in place of functions sEnParity(),
572 sDisParity(), sSetOddParity(), and sSetEvenParity().
574 Warnings: Before enabling parity odd or even parity should be chosen using
575 functions sSetOddParity() or sSetEvenParity().
577 #define sEnParity(ChP) \
579 (ChP)->TxControl[2] |= PARITY_EN; \
580 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
583 /***************************************************************************
584 Function: sEnRTSFlowCtl
587 #define sEnRTSFlowCtl(ChP) \
589 (ChP)->TxControl[2] &= ~RTSTOG_EN; \
590 (ChP)->TxControl[3] &= ~SET_RTS; \
591 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
592 (ChP)->RxControl[2] |= RTSFC_EN; \
593 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->RxControl)); \
596 /***************************************************************************
597 Function: sDisRTSFlowCtl
600 #define sDisRTSFlowCtl(ChP) \
602 (ChP)->RxControl[2] &= ~RTSFC_EN; \
603 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->RxControl)); \
606 /***************************************************************************
608 Purpose: Enable Rx FIFO
610 CHANNEL_T *ChP; Ptr to channel structure
612 #define sEnRxFIFO(ChP) \
614 (ChP)->R[0x32] = 0x08; \
615 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->R + 0x30)); \
618 /***************************************************************************
619 Function: sEnRxProcessor
620 Purpose: Enable the receive processor
621 Call: sEnRxProcessor(ChP)
622 CHANNEL_T *ChP; Ptr to channel structure
623 Comments: This function is used to start the receive processor. When
624 the channel is in the reset state the receive processor is not
625 running. This is done to prevent the receive processor from
626 executing invalid microcode instructions prior to the
627 downloading of the microcode.
629 Warnings: This function must be called after valid microcode has been
630 downloaded to the AIOP, and it must not be called before the
631 microcode has been downloaded.
633 #define sEnRxProcessor(ChP) \
635 (ChP)->RxControl[2] |= RXPROC_EN; \
636 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->RxControl)); \
639 /***************************************************************************
640 Function: sEnRxStatusMode
641 Purpose: Enable the Rx status mode
642 Call: sEnRxStatusMode(ChP)
643 CHANNEL_T *ChP; Ptr to channel structure
644 Comments: This places the channel in the receive status mode. All subsequent
645 reads of receive data using sReadRxWord() will return a data byte
646 in the low word and a status byte in the high word.
649 #define sEnRxStatusMode(ChP) rp_writech2(ChP,CHNOFF_CHANSTAT(ChP),STATMODE)
651 /***************************************************************************
652 Function: sEnTransmit
653 Purpose: Enable transmit
654 Call: sEnTransmit(ChP)
655 CHANNEL_T *ChP; Ptr to channel structure
657 #define sEnTransmit(ChP) \
659 (ChP)->TxControl[3] |= TX_ENABLE; \
660 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
663 /***************************************************************************
664 Function: sGetAiopIntStatus
665 Purpose: Get the AIOP interrupt status
666 Call: sGetAiopIntStatus(CtlP,AiopNum)
667 CONTROLLER_T *CtlP; Ptr to controller structure
668 int AiopNum; AIOP number
669 Return: Byte_t: The AIOP interrupt status. Bits 0 through 7
670 represent channels 0 through 7 respectively. If a
671 bit is set that channel is interrupting.
673 #define sGetAiopIntStatus(CtlP,AIOPNUM) rp_readaiop1(CtlP,AIOPNUM,_INT_CHAN)
675 /***************************************************************************
676 Function: sGetAiopNumChan
677 Purpose: Get the number of channels supported by an AIOP
678 Call: sGetAiopNumChan(CtlP,AiopNum)
679 CONTROLLER_T *CtlP; Ptr to controller structure
680 int AiopNum; AIOP number
681 Return: int: The number of channels supported by the AIOP
683 #define sGetAiopNumChan(CtlP,AIOPNUM) CtlP->AiopNumChan[AIOPNUM]
685 /***************************************************************************
686 Function: sGetChanIntID
687 Purpose: Get a channel's interrupt identification byte
688 Call: sGetChanIntID(ChP)
689 CHANNEL_T *ChP; Ptr to channel structure
690 Return: Byte_t: The channel interrupt ID. Can be any
691 combination of the following flags:
692 RXF_TRIG: Rx FIFO trigger level interrupt
693 TXFIFO_MT: Tx FIFO empty interrupt
694 SRC_INT: Special receive condition interrupt
695 DELTA_CD: CD change interrupt
696 DELTA_CTS: CTS change interrupt
697 DELTA_DSR: DSR change interrupt
699 #define sGetChanIntID(ChP) (rp_readch1(ChP,(ChP)->ChanNum+_INT_ID0) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR))
701 /***************************************************************************
702 Function: sGetChanNum
703 Purpose: Get the number of a channel within an AIOP
704 Call: sGetChanNum(ChP)
705 CHANNEL_T *ChP; Ptr to channel structure
706 Return: int: Channel number within AIOP, or NULLCHAN if channel does
709 #define sGetChanNum(ChP) (ChP)->ChanNum
711 /***************************************************************************
712 Function: sGetChanStatus
713 Purpose: Get the channel status
714 Call: sGetChanStatus(ChP)
715 CHANNEL_T *ChP; Ptr to channel structure
716 Return: Word_t: The channel status. Can be any combination of
719 CTS_ACT: CTS input asserted
720 DSR_ACT: DSR input asserted
721 CD_ACT: CD input asserted
722 TXFIFOMT: Tx FIFO is empty
723 TXSHRMT: Tx shift register is empty
724 RDA: Rx data available
727 STATMODE: status mode enable bit
728 RXFOVERFL: receive FIFO overflow
729 RX2MATCH: receive compare byte 2 match
730 RX1MATCH: receive compare byte 1 match
731 RXBREAK: received BREAK
732 RXFRAME: received framing error
733 RXPARITY: received parity error
734 Warnings: This function will clear the high byte flags in the Channel
737 #define sGetChanStatus(ChP) rp_readch2(ChP,CHNOFF_CHANSTAT(ChP))
739 /***************************************************************************
740 Function: sGetChanStatusLo
741 Purpose: Get the low byte only of the channel status
742 Call: sGetChanStatusLo(ChP)
743 CHANNEL_T *ChP; Ptr to channel structure
744 Return: Byte_t: The channel status low byte. Can be any combination
745 of the following flags:
746 CTS_ACT: CTS input asserted
747 DSR_ACT: DSR input asserted
748 CD_ACT: CD input asserted
749 TXFIFOMT: Tx FIFO is empty
750 TXSHRMT: Tx shift register is empty
751 RDA: Rx data available
753 #define sGetChanStatusLo(ChP) rp_readch1(ChP,CHNOFF_CHANSTAT(ChP))
755 /***************************************************************************
757 Purpose: Get the number of data bytes in the Rx FIFO
759 CHANNEL_T *ChP; Ptr to channel structure
760 Return: int: The number of data bytes in the Rx FIFO.
761 Comments: Byte read of count register is required to obtain Rx count.
764 #define sGetRxCnt(ChP) rp_readch2(ChP,CHNOFF_TXRXCOUNT(ChP))
766 /***************************************************************************
768 Purpose: Get the number of data bytes in the Tx FIFO
770 CHANNEL_T *ChP; Ptr to channel structure
771 Return: Byte_t: The number of data bytes in the Tx FIFO.
772 Comments: Byte read of count register is required to obtain Tx count.
775 #define sGetTxCnt(ChP) rp_readch1(ChP,CHNOFF_TXRXCOUNT(ChP))
777 /*****************************************************************************
778 Function: sGetTxRxDataIO
779 Purpose: Get the offset of a channel's TxRx Data register
780 Call: sGetTxRxDataIO(ChP)
781 CHANNEL_T *ChP; Ptr to channel structure
782 Return: WordIO_t: offset of a channel's TxRx Data register
784 #define sGetTxRxDataIO(ChP) CHNOFF_TXRXDATA(ChP)
786 /***************************************************************************
787 Function: sInitChanDefaults
788 Purpose: Initialize a channel structure to its default state.
789 Call: sInitChanDefaults(ChP)
790 CHANNEL_T *ChP; Ptr to the channel structure
791 Comments: This function must be called once for every channel structure
792 that exists before any other SSCI calls can be made.
795 #define sInitChanDefaults(ChP) \
797 (ChP)->CtlP = NULLCTLPTR; \
798 (ChP)->AiopNum = NULLAIOP; \
799 (ChP)->ChanID = AIOPID_NULL; \
800 (ChP)->ChanNum = NULLCHAN; \
803 /***************************************************************************
804 Function: sResetAiopByNum
805 Purpose: Reset the AIOP by number
806 Call: sResetAiopByNum(CTLP,AIOPNUM)
807 CONTROLLER_T CTLP; Ptr to controller structure
810 #define sResetAiopByNum(CTLP,AIOPNUM) \
812 rp_writeaiop1(CTLP,AIOPNUM,_CMD_REG,RESET_ALL); \
813 rp_writeaiop1(CTLP,AIOPNUM,_CMD_REG,0x0); \
816 /***************************************************************************
818 Purpose: Send a transmit BREAK signal
819 Call: sSendBreak(ChP)
820 CHANNEL_T *ChP; Ptr to channel structure
822 #define sSendBreak(ChP) \
824 (ChP)->TxControl[3] |= SETBREAK; \
825 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
828 /***************************************************************************
830 Purpose: Set baud rate
831 Call: sSetBaud(ChP,Divisor)
832 CHANNEL_T *ChP; Ptr to channel structure
833 Word_t Divisor; 16 bit baud rate divisor for channel
835 #define sSetBaud(ChP,DIVISOR) \
837 (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \
838 (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \
839 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->BaudDiv)); \
842 /***************************************************************************
844 Purpose: Set data bits to 7
846 CHANNEL_T *ChP; Ptr to channel structure
848 #define sSetData7(ChP) \
850 (ChP)->TxControl[2] &= ~DATA8BIT; \
851 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
854 /***************************************************************************
856 Purpose: Set data bits to 8
858 CHANNEL_T *ChP; Ptr to channel structure
860 #define sSetData8(ChP) \
862 (ChP)->TxControl[2] |= DATA8BIT; \
863 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
866 /***************************************************************************
868 Purpose: Set the DTR output
870 CHANNEL_T *ChP; Ptr to channel structure
872 #define sSetDTR(ChP) \
874 (ChP)->TxControl[3] |= SET_DTR; \
875 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
878 /***************************************************************************
879 Function: sSetEvenParity
880 Purpose: Set even parity
881 Call: sSetEvenParity(ChP)
882 CHANNEL_T *ChP; Ptr to channel structure
883 Comments: Function sSetParity() can be used in place of functions sEnParity(),
884 sDisParity(), sSetOddParity(), and sSetEvenParity().
886 Warnings: This function has no effect unless parity is enabled with function
889 #define sSetEvenParity(ChP) \
891 (ChP)->TxControl[2] |= EVEN_PAR; \
892 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
895 /***************************************************************************
896 Function: sSetOddParity
897 Purpose: Set odd parity
898 Call: sSetOddParity(ChP)
899 CHANNEL_T *ChP; Ptr to channel structure
900 Comments: Function sSetParity() can be used in place of functions sEnParity(),
901 sDisParity(), sSetOddParity(), and sSetEvenParity().
903 Warnings: This function has no effect unless parity is enabled with function
906 #define sSetOddParity(ChP) \
908 (ChP)->TxControl[2] &= ~EVEN_PAR; \
909 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
912 /***************************************************************************
914 Purpose: Set the RTS output
916 CHANNEL_T *ChP; Ptr to channel structure
918 #define sSetRTS(ChP) \
920 (ChP)->TxControl[3] |= SET_RTS; \
921 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
924 /***************************************************************************
925 Function: sSetRxTrigger
926 Purpose: Set the Rx FIFO trigger level
927 Call: sSetRxProcessor(ChP,Level)
928 CHANNEL_T *ChP; Ptr to channel structure
929 Byte_t Level; Number of characters in Rx FIFO at which the
930 interrupt will be generated. Can be any of the following flags:
933 TRIG_1: 1 character in FIFO
934 TRIG_1_2: FIFO 1/2 full
935 TRIG_7_8: FIFO 7/8 full
936 Comments: An interrupt will be generated when the trigger level is reached
937 only if function sEnInterrupt() has been called with flag
938 RXINT_EN set. The RXF_TRIG flag in the Interrupt Idenfification
939 register will be set whenever the trigger level is reached
940 regardless of the setting of RXINT_EN.
943 #define sSetRxTrigger(ChP,LEVEL) \
945 (ChP)->RxControl[2] &= ~TRIG_MASK; \
946 (ChP)->RxControl[2] |= LEVEL; \
947 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->RxControl)); \
950 /***************************************************************************
952 Purpose: Set stop bits to 1
954 CHANNEL_T *ChP; Ptr to channel structure
956 #define sSetStop1(ChP) \
958 (ChP)->TxControl[2] &= ~STOP2; \
959 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
962 /***************************************************************************
964 Purpose: Set stop bits to 2
966 CHANNEL_T *ChP; Ptr to channel structure
968 #define sSetStop2(ChP) \
970 (ChP)->TxControl[2] |= STOP2; \
971 rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->TxControl)); \
974 /***************************************************************************
975 Function: sStartRxProcessor
976 Purpose: Start a channel's receive processor
977 Call: sStartRxProcessor(ChP)
978 CHANNEL_T *ChP; Ptr to channel structure
979 Comments: This function is used to start a Rx processor after it was
980 stopped with sStopRxProcessor() or sStopSWInFlowCtl(). It
981 will restart both the Rx processor and software input flow control.
984 #define sStartRxProcessor(ChP) rp_writech4(ChP,_INDX_ADDR,le32dec((ChP)->R))
986 /***************************************************************************
987 Function: sWriteTxByte
988 Purpose: Write a transmit data byte to a channel.
989 CHANNEL_T *ChP; Ptr to channel structure
990 ByteIO_t io: Channel transmit register I/O address. This can
991 be obtained with sGetTxRxDataIO().
992 Byte_t Data; The transmit data byte.
993 Warnings: This function writes the data byte without checking to see if
994 sMaxTxSize is exceeded in the Tx FIFO.
996 #define sWriteTxByte(ChP,IO,DATA) rp_writech1(ChP,IO,DATA)
998 int sReadAiopID(CONTROLLER_T *CtlP, int aiop);
999 int sReadAiopNumChan(CONTROLLER_T *CtlP, int aiop);
1000 int sInitChan( CONTROLLER_T *CtlP,
1004 Byte_t sGetRxErrStatus(CHANNEL_T *ChP);
1005 void sStopRxProcessor(CHANNEL_T *ChP);
1006 void sStopSWInFlowCtl(CHANNEL_T *ChP);
1007 void sFlushRxFIFO(CHANNEL_T *ChP);
1008 void sFlushTxFIFO(CHANNEL_T *ChP);
1009 int sWriteTxPrioByte(CHANNEL_T *ChP, Byte_t Data);
1010 void sEnInterrupts(CHANNEL_T *ChP,Word_t Flags);
1011 void sDisInterrupts(CHANNEL_T *ChP,Word_t Flags);
1012 int rp_attachcommon(CONTROLLER_T *ctlp, int num_aiops, int num_ports);
1013 void rp_releaseresource(CONTROLLER_t *ctlp);
1014 static __inline void
1015 rp_lock(CONTROLLER_T *CtlP)
1017 if (CtlP->hwmtx_init != 0)
1018 mtx_lock(&CtlP->hwmtx);
1020 static __inline void
1021 rp_unlock(CONTROLLER_T *CtlP)
1023 if (CtlP->hwmtx_init != 0)
1024 mtx_unlock(&CtlP->hwmtx);
1028 extern Byte_t R[RDATASIZE];
1029 extern CONTROLLER_T sController[CTL_SIZE];
1030 extern Byte_t sIRQMap[16];
1032 extern Byte_t rp_sBitMapClrTbl[8];
1033 extern Byte_t rp_sBitMapSetTbl[8];