2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2015-2016, Stanislav Galabov
5 * Copyright (c) 2014, Aleksandr A. Mityaev
6 * Copyright (c) 2011, Aleksandr Rybalko
8 * by Alexander Egorenkov <egorenar@gmail.com>
9 * and by Damien Bergamini <damien.bergamini@free.fr>
10 * All rights reserved.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice unmodified, this list of conditions, and the following
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
42 #include <net/if_var.h>
43 #include <net/if_arp.h>
44 #include <net/ethernet.h>
45 #include <net/if_dl.h>
46 #include <net/if_media.h>
47 #include <net/if_types.h>
48 #include <net/if_vlan_var.h>
52 #include <machine/bus.h>
53 #include <machine/cache.h>
54 #include <machine/cpufunc.h>
55 #include <machine/resource.h>
56 #include <vm/vm_param.h>
59 #include <machine/pmap.h>
63 #include "opt_platform.h"
64 #include "opt_rt305x.h"
67 #include <dev/ofw/openfirm.h>
68 #include <dev/ofw/ofw_bus.h>
69 #include <dev/ofw/ofw_bus_subr.h>
72 #include <dev/mii/mii.h>
73 #include <dev/mii/miivar.h>
76 #include <dev/mdio/mdio.h>
77 #include <dev/etherswitch/miiproxy.h>
82 #include <mips/rt305x/rt305x_sysctlvar.h>
83 #include <mips/rt305x/rt305xreg.h>
86 #ifdef IF_RT_PHY_SUPPORT
87 #include "miibus_if.h"
93 #define RT_MAX_AGG_SIZE 3840
95 #define RT_TX_DATA_SEG0_SIZE MJUMPAGESIZE
97 #define RT_MS(_v, _f) (((_v) & _f) >> _f##_S)
98 #define RT_SM(_v, _f) (((_v) << _f##_S) & _f)
100 #define RT_TX_WATCHDOG_TIMEOUT 5
102 #define RT_CHIPID_RT2880 0x2880
103 #define RT_CHIPID_RT3050 0x3050
104 #define RT_CHIPID_RT5350 0x5350
105 #define RT_CHIPID_MT7620 0x7620
106 #define RT_CHIPID_MT7621 0x7621
109 /* more specific and new models should go first */
110 static const struct ofw_compat_data rt_compat_data[] = {
111 { "ralink,rt2880-eth", RT_CHIPID_RT2880 },
112 { "ralink,rt3050-eth", RT_CHIPID_RT3050 },
113 { "ralink,rt3352-eth", RT_CHIPID_RT3050 },
114 { "ralink,rt3883-eth", RT_CHIPID_RT3050 },
115 { "ralink,rt5350-eth", RT_CHIPID_RT5350 },
116 { "ralink,mt7620a-eth", RT_CHIPID_MT7620 },
117 { "mediatek,mt7620-eth", RT_CHIPID_MT7620 },
118 { "ralink,mt7621-eth", RT_CHIPID_MT7621 },
119 { "mediatek,mt7621-eth", RT_CHIPID_MT7621 },
125 * Static function prototypes
127 static int rt_probe(device_t dev);
128 static int rt_attach(device_t dev);
129 static int rt_detach(device_t dev);
130 static int rt_shutdown(device_t dev);
131 static int rt_suspend(device_t dev);
132 static int rt_resume(device_t dev);
133 static void rt_init_locked(void *priv);
134 static void rt_init(void *priv);
135 static void rt_stop_locked(void *priv);
136 static void rt_stop(void *priv);
137 static void rt_start(struct ifnet *ifp);
138 static int rt_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
139 static void rt_periodic(void *arg);
140 static void rt_tx_watchdog(void *arg);
141 static void rt_intr(void *arg);
142 static void rt_rt5350_intr(void *arg);
143 static void rt_tx_coherent_intr(struct rt_softc *sc);
144 static void rt_rx_coherent_intr(struct rt_softc *sc);
145 static void rt_rx_delay_intr(struct rt_softc *sc);
146 static void rt_tx_delay_intr(struct rt_softc *sc);
147 static void rt_rx_intr(struct rt_softc *sc, int qid);
148 static void rt_tx_intr(struct rt_softc *sc, int qid);
149 static void rt_rx_done_task(void *context, int pending);
150 static void rt_tx_done_task(void *context, int pending);
151 static void rt_periodic_task(void *context, int pending);
152 static int rt_rx_eof(struct rt_softc *sc,
153 struct rt_softc_rx_ring *ring, int limit);
154 static void rt_tx_eof(struct rt_softc *sc,
155 struct rt_softc_tx_ring *ring);
156 static void rt_update_stats(struct rt_softc *sc);
157 static void rt_watchdog(struct rt_softc *sc);
158 static void rt_update_raw_counters(struct rt_softc *sc);
159 static void rt_intr_enable(struct rt_softc *sc, uint32_t intr_mask);
160 static void rt_intr_disable(struct rt_softc *sc, uint32_t intr_mask);
161 static int rt_txrx_enable(struct rt_softc *sc);
162 static int rt_alloc_rx_ring(struct rt_softc *sc,
163 struct rt_softc_rx_ring *ring, int qid);
164 static void rt_reset_rx_ring(struct rt_softc *sc,
165 struct rt_softc_rx_ring *ring);
166 static void rt_free_rx_ring(struct rt_softc *sc,
167 struct rt_softc_rx_ring *ring);
168 static int rt_alloc_tx_ring(struct rt_softc *sc,
169 struct rt_softc_tx_ring *ring, int qid);
170 static void rt_reset_tx_ring(struct rt_softc *sc,
171 struct rt_softc_tx_ring *ring);
172 static void rt_free_tx_ring(struct rt_softc *sc,
173 struct rt_softc_tx_ring *ring);
174 static void rt_dma_map_addr(void *arg, bus_dma_segment_t *segs,
175 int nseg, int error);
176 static void rt_sysctl_attach(struct rt_softc *sc);
177 #ifdef IF_RT_PHY_SUPPORT
178 void rt_miibus_statchg(device_t);
180 #if defined(IF_RT_PHY_SUPPORT) || defined(RT_MDIO)
181 static int rt_miibus_readreg(device_t, int, int);
182 static int rt_miibus_writereg(device_t, int, int, int);
184 static int rt_ifmedia_upd(struct ifnet *);
185 static void rt_ifmedia_sts(struct ifnet *, struct ifmediareq *);
187 static SYSCTL_NODE(_hw, OID_AUTO, rt, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
188 "RT driver parameters");
190 static int rt_debug = 0;
191 SYSCTL_INT(_hw_rt, OID_AUTO, debug, CTLFLAG_RWTUN, &rt_debug, 0,
196 rt_probe(device_t dev)
198 struct rt_softc *sc = device_get_softc(dev);
201 const struct ofw_compat_data * cd;
203 cd = ofw_bus_search_compatible(dev, rt_compat_data);
204 if (cd->ocd_data == 0)
207 sc->rt_chipid = (unsigned int)(cd->ocd_data);
210 sc->rt_chipid = RT_CHIPID_MT7620;
211 #elif defined(MT7621)
212 sc->rt_chipid = RT_CHIPID_MT7621;
213 #elif defined(RT5350)
214 sc->rt_chipid = RT_CHIPID_RT5350;
216 sc->rt_chipid = RT_CHIPID_RT3050;
219 snprintf(buf, sizeof(buf), "Ralink %cT%x onChip Ethernet driver",
220 sc->rt_chipid >= 0x7600 ? 'M' : 'R', sc->rt_chipid);
221 device_set_desc_copy(dev, buf);
222 return (BUS_PROBE_GENERIC);
226 * macaddr_atoi - translate string MAC address to uint8_t array
229 macaddr_atoi(const char *str, uint8_t *mac)
232 unsigned int amac[ETHER_ADDR_LEN]; /* Aligned version */
234 count = sscanf(str, "%x%*c%x%*c%x%*c%x%*c%x%*c%x",
235 &amac[0], &amac[1], &amac[2],
236 &amac[3], &amac[4], &amac[5]);
237 if (count < ETHER_ADDR_LEN) {
238 memset(mac, 0, ETHER_ADDR_LEN);
242 /* Copy aligned to result */
243 for (i = 0; i < ETHER_ADDR_LEN; i ++)
244 mac[i] = (amac[i] & 0xff);
249 #ifdef USE_GENERATED_MAC_ADDRESS
251 * generate_mac(uin8_t *mac)
252 * This is MAC address generator for cases when real device MAC address
253 * unknown or not yet accessible.
254 * Use 'b','s','d' signature and 3 octets from CRC32 on kenv.
255 * MAC = 'b', 's', 'd', CRC[3]^CRC[2], CRC[1], CRC[0]
257 * Output - MAC address, that do not change between reboots, if hints or
258 * bootloader info unchange.
261 generate_mac(uint8_t *mac)
265 uint32_t crc = 0xffffffff;
267 /* Generate CRC32 on kenv */
268 for (cp = kenvp[0]; cp != NULL; cp = kenvp[++i]) {
269 crc = calculate_crc32c(crc, cp, strlen(cp) + 1);
276 mac[3] = (crc >> 24) ^ ((crc >> 16) & 0xff);
277 mac[4] = (crc >> 8) & 0xff;
283 * ether_request_mac - try to find usable MAC address.
286 ether_request_mac(device_t dev, uint8_t *mac)
291 * "ethaddr" is passed via envp on RedBoot platforms
292 * "kmac" is passed via argv on RouterBOOT platforms
294 #if defined(RT305X_UBOOT) || defined(__REDBOOT__) || defined(__ROUTERBOOT__)
295 if ((var = kern_getenv("ethaddr")) != NULL ||
296 (var = kern_getenv("kmac")) != NULL ) {
298 if(!macaddr_atoi(var, mac)) {
299 printf("%s: use %s macaddr from KENV\n",
300 device_get_nameunit(dev), var);
310 * hint.[dev].[unit].macaddr
312 if (!resource_string_value(device_get_name(dev),
313 device_get_unit(dev), "macaddr", (const char **)&var)) {
315 if(!macaddr_atoi(var, mac)) {
316 printf("%s: use %s macaddr from hints\n",
317 device_get_nameunit(dev), var);
322 #ifdef USE_GENERATED_MAC_ADDRESS
325 device_printf(dev, "use generated %02x:%02x:%02x:%02x:%02x:%02x "
326 "macaddr\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
336 device_printf(dev, "use hardcoded 00:18:e7:d5:83:90 macaddr\n");
346 reset_freng(struct rt_softc *sc)
348 /* XXX hard reset kills everything so skip it ... */
353 rt_attach(device_t dev)
359 sc = device_get_softc(dev);
362 mtx_init(&sc->lock, device_get_nameunit(dev), MTX_NETWORK_LOCK,
363 MTX_DEF | MTX_RECURSE);
366 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
367 RF_ACTIVE | RF_SHAREABLE);
368 if (sc->mem == NULL) {
369 device_printf(dev, "could not allocate memory resource\n");
374 sc->bst = rman_get_bustag(sc->mem);
375 sc->bsh = rman_get_bushandle(sc->mem);
378 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
380 if (sc->irq == NULL) {
382 "could not allocate interrupt resource\n");
388 sc->debug = rt_debug;
390 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
391 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
392 "debug", CTLFLAG_RW, &sc->debug, 0, "rt debug level");
399 if (sc->rt_chipid == RT_CHIPID_MT7620) {
400 sc->csum_fail_ip = MT7620_RXD_SRC_IP_CSUM_FAIL;
401 sc->csum_fail_l4 = MT7620_RXD_SRC_L4_CSUM_FAIL;
402 } else if (sc->rt_chipid == RT_CHIPID_MT7621) {
403 sc->csum_fail_ip = MT7621_RXD_SRC_IP_CSUM_FAIL;
404 sc->csum_fail_l4 = MT7621_RXD_SRC_L4_CSUM_FAIL;
406 sc->csum_fail_ip = RT305X_RXD_SRC_IP_CSUM_FAIL;
407 sc->csum_fail_l4 = RT305X_RXD_SRC_L4_CSUM_FAIL;
410 /* Fill in soc-specific registers map */
411 switch(sc->rt_chipid) {
412 case RT_CHIPID_MT7620:
413 case RT_CHIPID_MT7621:
414 sc->gdma1_base = MT7620_GDMA1_BASE;
416 case RT_CHIPID_RT5350:
417 device_printf(dev, "%cT%x Ethernet MAC (rev 0x%08x)\n",
418 sc->rt_chipid >= 0x7600 ? 'M' : 'R',
419 sc->rt_chipid, sc->mac_rev);
420 /* RT5350: No GDMA, PSE, CDMA, PPE */
421 RT_WRITE(sc, GE_PORT_BASE + 0x0C00, // UDPCS, TCPCS, IPCS=1
422 RT_READ(sc, GE_PORT_BASE + 0x0C00) | (0x7<<16));
423 sc->delay_int_cfg=RT5350_PDMA_BASE+RT5350_DELAY_INT_CFG;
424 sc->fe_int_status=RT5350_FE_INT_STATUS;
425 sc->fe_int_enable=RT5350_FE_INT_ENABLE;
426 sc->pdma_glo_cfg=RT5350_PDMA_BASE+RT5350_PDMA_GLO_CFG;
427 sc->pdma_rst_idx=RT5350_PDMA_BASE+RT5350_PDMA_RST_IDX;
428 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
429 sc->tx_base_ptr[i]=RT5350_PDMA_BASE+RT5350_TX_BASE_PTR(i);
430 sc->tx_max_cnt[i]=RT5350_PDMA_BASE+RT5350_TX_MAX_CNT(i);
431 sc->tx_ctx_idx[i]=RT5350_PDMA_BASE+RT5350_TX_CTX_IDX(i);
432 sc->tx_dtx_idx[i]=RT5350_PDMA_BASE+RT5350_TX_DTX_IDX(i);
435 sc->rx_base_ptr[0]=RT5350_PDMA_BASE+RT5350_RX_BASE_PTR0;
436 sc->rx_max_cnt[0]=RT5350_PDMA_BASE+RT5350_RX_MAX_CNT0;
437 sc->rx_calc_idx[0]=RT5350_PDMA_BASE+RT5350_RX_CALC_IDX0;
438 sc->rx_drx_idx[0]=RT5350_PDMA_BASE+RT5350_RX_DRX_IDX0;
439 sc->rx_base_ptr[1]=RT5350_PDMA_BASE+RT5350_RX_BASE_PTR1;
440 sc->rx_max_cnt[1]=RT5350_PDMA_BASE+RT5350_RX_MAX_CNT1;
441 sc->rx_calc_idx[1]=RT5350_PDMA_BASE+RT5350_RX_CALC_IDX1;
442 sc->rx_drx_idx[1]=RT5350_PDMA_BASE+RT5350_RX_DRX_IDX1;
443 sc->int_rx_done_mask=RT5350_INT_RXQ0_DONE;
444 sc->int_tx_done_mask=RT5350_INT_TXQ0_DONE;
447 device_printf(dev, "RT305XF Ethernet MAC (rev 0x%08x)\n",
449 sc->gdma1_base = GDMA1_BASE;
450 sc->delay_int_cfg=PDMA_BASE+DELAY_INT_CFG;
451 sc->fe_int_status=GE_PORT_BASE+FE_INT_STATUS;
452 sc->fe_int_enable=GE_PORT_BASE+FE_INT_ENABLE;
453 sc->pdma_glo_cfg=PDMA_BASE+PDMA_GLO_CFG;
454 sc->pdma_rst_idx=PDMA_BASE+PDMA_RST_IDX;
455 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
456 sc->tx_base_ptr[i]=PDMA_BASE+TX_BASE_PTR(i);
457 sc->tx_max_cnt[i]=PDMA_BASE+TX_MAX_CNT(i);
458 sc->tx_ctx_idx[i]=PDMA_BASE+TX_CTX_IDX(i);
459 sc->tx_dtx_idx[i]=PDMA_BASE+TX_DTX_IDX(i);
462 sc->rx_base_ptr[0]=PDMA_BASE+RX_BASE_PTR0;
463 sc->rx_max_cnt[0]=PDMA_BASE+RX_MAX_CNT0;
464 sc->rx_calc_idx[0]=PDMA_BASE+RX_CALC_IDX0;
465 sc->rx_drx_idx[0]=PDMA_BASE+RX_DRX_IDX0;
466 sc->int_rx_done_mask=INT_RX_DONE;
467 sc->int_tx_done_mask=INT_TXQ0_DONE;
470 if (sc->gdma1_base != 0)
471 RT_WRITE(sc, sc->gdma1_base + GDMA_FWD_CFG,
473 GDM_ICS_EN | /* Enable IP Csum */
474 GDM_TCS_EN | /* Enable TCP Csum */
475 GDM_UCS_EN | /* Enable UDP Csum */
476 GDM_STRPCRC | /* Strip CRC from packet */
477 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* fwd UCast to CPU */
478 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* fwd BCast to CPU */
479 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* fwd MCast to CPU */
480 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* fwd Other to CPU */
483 if (sc->rt_chipid == RT_CHIPID_RT2880)
484 RT_WRITE(sc, MDIO_CFG, MDIO_2880_100T_INIT);
486 /* allocate Tx and Rx rings */
487 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
488 error = rt_alloc_tx_ring(sc, &sc->tx_ring[i], i);
490 device_printf(dev, "could not allocate Tx ring #%d\n",
496 sc->tx_ring_mgtqid = 5;
497 for (i = 0; i < sc->rx_ring_count; i++) {
498 error = rt_alloc_rx_ring(sc, &sc->rx_ring[i], i);
500 device_printf(dev, "could not allocate Rx ring\n");
505 callout_init(&sc->periodic_ch, 0);
506 callout_init_mtx(&sc->tx_watchdog_ch, &sc->lock, 0);
508 ifp = sc->ifp = if_alloc(IFT_ETHER);
510 device_printf(dev, "could not if_alloc()\n");
516 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
517 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
518 ifp->if_init = rt_init;
519 ifp->if_ioctl = rt_ioctl;
520 ifp->if_start = rt_start;
521 #define RT_TX_QLEN 256
523 IFQ_SET_MAXLEN(&ifp->if_snd, RT_TX_QLEN);
524 ifp->if_snd.ifq_drv_maxlen = RT_TX_QLEN;
525 IFQ_SET_READY(&ifp->if_snd);
527 #ifdef IF_RT_PHY_SUPPORT
528 error = mii_attach(dev, &sc->rt_miibus, ifp, rt_ifmedia_upd,
529 rt_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
531 device_printf(dev, "attaching PHYs failed\n");
536 ifmedia_init(&sc->rt_ifmedia, 0, rt_ifmedia_upd, rt_ifmedia_sts);
537 ifmedia_add(&sc->rt_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0,
539 ifmedia_set(&sc->rt_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX);
541 #endif /* IF_RT_PHY_SUPPORT */
543 ether_request_mac(dev, sc->mac_addr);
544 ether_ifattach(ifp, sc->mac_addr);
547 * Tell the upper layer(s) we support long frames.
549 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
550 ifp->if_capabilities |= IFCAP_VLAN_MTU;
551 ifp->if_capenable |= IFCAP_VLAN_MTU;
552 ifp->if_capabilities |= IFCAP_RXCSUM|IFCAP_TXCSUM;
553 ifp->if_capenable |= IFCAP_RXCSUM|IFCAP_TXCSUM;
555 /* init task queue */
556 NET_TASK_INIT(&sc->rx_done_task, 0, rt_rx_done_task, sc);
557 TASK_INIT(&sc->tx_done_task, 0, rt_tx_done_task, sc);
558 TASK_INIT(&sc->periodic_task, 0, rt_periodic_task, sc);
560 sc->rx_process_limit = 100;
562 sc->taskqueue = taskqueue_create("rt_taskq", M_NOWAIT,
563 taskqueue_thread_enqueue, &sc->taskqueue);
565 taskqueue_start_threads(&sc->taskqueue, 1, PI_NET, "%s taskq",
566 device_get_nameunit(sc->dev));
568 rt_sysctl_attach(sc);
570 /* set up interrupt */
571 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
572 NULL, (sc->rt_chipid == RT_CHIPID_RT5350 ||
573 sc->rt_chipid == RT_CHIPID_MT7620 ||
574 sc->rt_chipid == RT_CHIPID_MT7621) ? rt_rt5350_intr : rt_intr,
577 printf("%s: could not set up interrupt\n",
578 device_get_nameunit(dev));
582 device_printf(dev, "debug var at %#08x\n", (u_int)&(sc->debug));
588 /* free Tx and Rx rings */
589 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
590 rt_free_tx_ring(sc, &sc->tx_ring[i]);
592 for (i = 0; i < sc->rx_ring_count; i++)
593 rt_free_rx_ring(sc, &sc->rx_ring[i]);
595 mtx_destroy(&sc->lock);
598 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
602 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
612 rt_ifmedia_upd(struct ifnet *ifp)
615 #ifdef IF_RT_PHY_SUPPORT
616 struct mii_data *mii;
617 struct mii_softc *miisc;
623 mii = device_get_softc(sc->rt_miibus);
624 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
626 error = mii_mediachg(mii);
631 #else /* !IF_RT_PHY_SUPPORT */
634 struct ifmedia_entry *ife;
637 ifm = &sc->rt_ifmedia;
640 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
643 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
644 device_printf(sc->dev,
645 "AUTO is not supported for multiphy MAC");
653 #endif /* IF_RT_PHY_SUPPORT */
657 * Report current media status.
660 rt_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
662 #ifdef IF_RT_PHY_SUPPORT
664 struct mii_data *mii;
669 mii = device_get_softc(sc->rt_miibus);
671 ifmr->ifm_active = mii->mii_media_active;
672 ifmr->ifm_status = mii->mii_media_status;
673 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
674 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
676 #else /* !IF_RT_PHY_SUPPORT */
678 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
679 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
680 #endif /* IF_RT_PHY_SUPPORT */
684 rt_detach(device_t dev)
690 sc = device_get_softc(dev);
693 RT_DPRINTF(sc, RT_DEBUG_ANY, "detaching\n");
697 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
699 callout_stop(&sc->periodic_ch);
700 callout_stop(&sc->tx_watchdog_ch);
702 taskqueue_drain(sc->taskqueue, &sc->rx_done_task);
703 taskqueue_drain(sc->taskqueue, &sc->tx_done_task);
704 taskqueue_drain(sc->taskqueue, &sc->periodic_task);
706 /* free Tx and Rx rings */
707 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
708 rt_free_tx_ring(sc, &sc->tx_ring[i]);
709 for (i = 0; i < sc->rx_ring_count; i++)
710 rt_free_rx_ring(sc, &sc->rx_ring[i]);
714 #ifdef IF_RT_PHY_SUPPORT
715 if (sc->rt_miibus != NULL)
716 device_delete_child(dev, sc->rt_miibus);
722 taskqueue_free(sc->taskqueue);
724 mtx_destroy(&sc->lock);
726 bus_generic_detach(dev);
727 bus_teardown_intr(dev, sc->irq, sc->irqh);
728 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq);
729 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem);
735 rt_shutdown(device_t dev)
739 sc = device_get_softc(dev);
740 RT_DPRINTF(sc, RT_DEBUG_ANY, "shutting down\n");
747 rt_suspend(device_t dev)
751 sc = device_get_softc(dev);
752 RT_DPRINTF(sc, RT_DEBUG_ANY, "suspending\n");
759 rt_resume(device_t dev)
764 sc = device_get_softc(dev);
767 RT_DPRINTF(sc, RT_DEBUG_ANY, "resuming\n");
769 if (ifp->if_flags & IFF_UP)
776 * rt_init_locked - Run initialization process having locked mtx.
779 rt_init_locked(void *priv)
783 #ifdef IF_RT_PHY_SUPPORT
784 struct mii_data *mii;
791 #ifdef IF_RT_PHY_SUPPORT
792 mii = device_get_softc(sc->rt_miibus);
795 RT_DPRINTF(sc, RT_DEBUG_ANY, "initializing\n");
797 RT_SOFTC_ASSERT_LOCKED(sc);
800 //RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET);
801 //rt305x_sysctl_set(SYSCTL_RSTCTRL, SYSCTL_RSTCTRL_FRENG);
803 /* Fwd to CPU (uni|broad|multi)cast and Unknown */
804 if (sc->gdma1_base != 0)
805 RT_WRITE(sc, sc->gdma1_base + GDMA_FWD_CFG,
807 GDM_ICS_EN | /* Enable IP Csum */
808 GDM_TCS_EN | /* Enable TCP Csum */
809 GDM_UCS_EN | /* Enable UDP Csum */
810 GDM_STRPCRC | /* Strip CRC from packet */
811 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* fwd UCast to CPU */
812 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* fwd BCast to CPU */
813 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* fwd MCast to CPU */
814 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* fwd Other to CPU */
817 /* disable DMA engine */
818 RT_WRITE(sc, sc->pdma_glo_cfg, 0);
819 RT_WRITE(sc, sc->pdma_rst_idx, 0xffffffff);
821 /* wait while DMA engine is busy */
822 for (ntries = 0; ntries < 100; ntries++) {
823 tmp = RT_READ(sc, sc->pdma_glo_cfg);
824 if (!(tmp & (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)))
830 device_printf(sc->dev, "timeout waiting for DMA engine\n");
834 /* reset Rx and Tx rings */
835 tmp = FE_RST_DRX_IDX0 |
841 RT_WRITE(sc, sc->pdma_rst_idx, tmp);
843 /* XXX switch set mac address */
844 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
845 rt_reset_tx_ring(sc, &sc->tx_ring[i]);
847 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
848 /* update TX_BASE_PTRx */
849 RT_WRITE(sc, sc->tx_base_ptr[i],
850 sc->tx_ring[i].desc_phys_addr);
851 RT_WRITE(sc, sc->tx_max_cnt[i],
852 RT_SOFTC_TX_RING_DESC_COUNT);
853 RT_WRITE(sc, sc->tx_ctx_idx[i], 0);
857 for (i = 0; i < sc->rx_ring_count; i++)
858 rt_reset_rx_ring(sc, &sc->rx_ring[i]);
860 /* update RX_BASE_PTRx */
861 for (i = 0; i < sc->rx_ring_count; i++) {
862 RT_WRITE(sc, sc->rx_base_ptr[i],
863 sc->rx_ring[i].desc_phys_addr);
864 RT_WRITE(sc, sc->rx_max_cnt[i],
865 RT_SOFTC_RX_RING_DATA_COUNT);
866 RT_WRITE(sc, sc->rx_calc_idx[i],
867 RT_SOFTC_RX_RING_DATA_COUNT - 1);
870 /* write back DDONE, 16byte burst enable RX/TX DMA */
871 tmp = FE_TX_WB_DDONE | FE_DMA_BT_SIZE16 | FE_RX_DMA_EN | FE_TX_DMA_EN;
872 if (sc->rt_chipid == RT_CHIPID_MT7620 ||
873 sc->rt_chipid == RT_CHIPID_MT7621)
875 RT_WRITE(sc, sc->pdma_glo_cfg, tmp);
877 /* disable interrupts mitigation */
878 RT_WRITE(sc, sc->delay_int_cfg, 0);
880 /* clear pending interrupts */
881 RT_WRITE(sc, sc->fe_int_status, 0xffffffff);
883 /* enable interrupts */
884 if (sc->rt_chipid == RT_CHIPID_RT5350 ||
885 sc->rt_chipid == RT_CHIPID_MT7620 ||
886 sc->rt_chipid == RT_CHIPID_MT7621)
887 tmp = RT5350_INT_TX_COHERENT |
888 RT5350_INT_RX_COHERENT |
889 RT5350_INT_TXQ3_DONE |
890 RT5350_INT_TXQ2_DONE |
891 RT5350_INT_TXQ1_DONE |
892 RT5350_INT_TXQ0_DONE |
893 RT5350_INT_RXQ1_DONE |
894 RT5350_INT_RXQ0_DONE;
913 sc->intr_enable_mask = tmp;
915 RT_WRITE(sc, sc->fe_int_enable, tmp);
917 if (rt_txrx_enable(sc) != 0)
920 #ifdef IF_RT_PHY_SUPPORT
921 if (mii) mii_mediachg(mii);
922 #endif /* IF_RT_PHY_SUPPORT */
924 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
925 ifp->if_drv_flags |= IFF_DRV_RUNNING;
927 sc->periodic_round = 0;
929 callout_reset(&sc->periodic_ch, hz / 10, rt_periodic, sc);
938 * rt_init - lock and initialize device.
952 * rt_stop_locked - stop TX/RX w/ lock
955 rt_stop_locked(void *priv)
963 RT_DPRINTF(sc, RT_DEBUG_ANY, "stopping\n");
965 RT_SOFTC_ASSERT_LOCKED(sc);
967 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
968 callout_stop(&sc->periodic_ch);
969 callout_stop(&sc->tx_watchdog_ch);
971 taskqueue_block(sc->taskqueue);
974 * Sometime rt_stop_locked called from isr and we get panic
975 * When found, I fix it
978 taskqueue_drain(sc->taskqueue, &sc->rx_done_task);
979 taskqueue_drain(sc->taskqueue, &sc->tx_done_task);
980 taskqueue_drain(sc->taskqueue, &sc->periodic_task);
984 /* disable interrupts */
985 RT_WRITE(sc, sc->fe_int_enable, 0);
987 if(sc->rt_chipid != RT_CHIPID_RT5350 &&
988 sc->rt_chipid != RT_CHIPID_MT7620 &&
989 sc->rt_chipid != RT_CHIPID_MT7621) {
991 RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET);
994 if (sc->gdma1_base != 0)
995 RT_WRITE(sc, sc->gdma1_base + GDMA_FWD_CFG,
997 GDM_ICS_EN | /* Enable IP Csum */
998 GDM_TCS_EN | /* Enable TCP Csum */
999 GDM_UCS_EN | /* Enable UDP Csum */
1000 GDM_STRPCRC | /* Strip CRC from packet */
1001 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* fwd UCast to CPU */
1002 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* fwd BCast to CPU */
1003 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* fwd MCast to CPU */
1004 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* fwd Other to CPU */
1011 struct rt_softc *sc;
1016 RT_SOFTC_UNLOCK(sc);
1020 * rt_tx_data - transmit packet.
1023 rt_tx_data(struct rt_softc *sc, struct mbuf *m, int qid)
1026 struct rt_softc_tx_ring *ring;
1027 struct rt_softc_tx_data *data;
1028 struct rt_txdesc *desc;
1030 bus_dma_segment_t dma_seg[RT_SOFTC_MAX_SCATTER];
1031 int error, ndmasegs, ndescs, i;
1033 KASSERT(qid >= 0 && qid < RT_SOFTC_TX_RING_COUNT,
1034 ("%s: Tx data: invalid qid=%d\n",
1035 device_get_nameunit(sc->dev), qid));
1037 RT_SOFTC_TX_RING_ASSERT_LOCKED(&sc->tx_ring[qid]);
1040 ring = &sc->tx_ring[qid];
1041 desc = &ring->desc[ring->desc_cur];
1042 data = &ring->data[ring->data_cur];
1044 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag, data->dma_map, m,
1045 dma_seg, &ndmasegs, 0);
1047 /* too many fragments, linearize */
1049 RT_DPRINTF(sc, RT_DEBUG_TX,
1050 "could not load mbuf DMA map, trying to linearize "
1051 "mbuf: ndmasegs=%d, len=%d, error=%d\n",
1052 ndmasegs, m->m_pkthdr.len, error);
1054 m_d = m_collapse(m, M_NOWAIT, 16);
1062 sc->tx_defrag_packets++;
1064 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag,
1065 data->dma_map, m, dma_seg, &ndmasegs, 0);
1067 device_printf(sc->dev, "could not load mbuf DMA map: "
1068 "ndmasegs=%d, len=%d, error=%d\n",
1069 ndmasegs, m->m_pkthdr.len, error);
1075 if (m->m_pkthdr.len == 0)
1078 /* determine how many Tx descs are required */
1079 ndescs = 1 + ndmasegs / 2;
1080 if ((ring->desc_queued + ndescs) >
1081 (RT_SOFTC_TX_RING_DESC_COUNT - 2)) {
1082 RT_DPRINTF(sc, RT_DEBUG_TX,
1083 "there are not enough Tx descs\n");
1085 sc->no_tx_desc_avail++;
1087 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
1094 /* set up Tx descs */
1095 for (i = 0; i < ndmasegs; i += 2) {
1097 /* TODO: this needs to be refined as MT7620 for example has
1098 * a different word3 layout than RT305x and RT5350 (the last
1099 * one doesn't use word3 at all). And so does MT7621...
1102 if (sc->rt_chipid != RT_CHIPID_MT7621) {
1103 /* Set destination */
1104 if (sc->rt_chipid != RT_CHIPID_MT7620)
1105 desc->dst = (TXDSCR_DST_PORT_GDMA1);
1107 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1108 desc->dst |= (TXDSCR_IP_CSUM_GEN |
1109 TXDSCR_UDP_CSUM_GEN | TXDSCR_TCP_CSUM_GEN);
1123 desc->sdp0 = htole32(dma_seg[i].ds_addr);
1124 desc->sdl0 = htole16(dma_seg[i].ds_len |
1125 ( ((i+1) == ndmasegs )?RT_TXDESC_SDL0_LASTSEG:0 ));
1127 if ((i+1) < ndmasegs) {
1128 desc->sdp1 = htole32(dma_seg[i+1].ds_addr);
1129 desc->sdl1 = htole16(dma_seg[i+1].ds_len |
1130 ( ((i+2) == ndmasegs )?RT_TXDESC_SDL1_LASTSEG:0 ));
1136 if ((i+2) < ndmasegs) {
1137 ring->desc_queued++;
1138 ring->desc_cur = (ring->desc_cur + 1) %
1139 RT_SOFTC_TX_RING_DESC_COUNT;
1141 desc = &ring->desc[ring->desc_cur];
1144 RT_DPRINTF(sc, RT_DEBUG_TX, "sending data: len=%d, ndmasegs=%d, "
1145 "DMA ds_len=%d/%d/%d/%d/%d\n",
1146 m->m_pkthdr.len, ndmasegs,
1147 (int) dma_seg[0].ds_len,
1148 (int) dma_seg[1].ds_len,
1149 (int) dma_seg[2].ds_len,
1150 (int) dma_seg[3].ds_len,
1151 (int) dma_seg[4].ds_len);
1153 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map,
1154 BUS_DMASYNC_PREWRITE);
1155 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
1156 BUS_DMASYNC_PREWRITE);
1157 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
1158 BUS_DMASYNC_PREWRITE);
1160 ring->desc_queued++;
1161 ring->desc_cur = (ring->desc_cur + 1) % RT_SOFTC_TX_RING_DESC_COUNT;
1163 ring->data_queued++;
1164 ring->data_cur = (ring->data_cur + 1) % RT_SOFTC_TX_RING_DATA_COUNT;
1167 RT_WRITE(sc, sc->tx_ctx_idx[qid], ring->desc_cur);
1173 * rt_start - start Transmit/Receive
1176 rt_start(struct ifnet *ifp)
1178 struct rt_softc *sc;
1180 int qid = 0 /* XXX must check QoS priority */;
1184 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1188 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1192 m->m_pkthdr.rcvif = NULL;
1194 RT_SOFTC_TX_RING_LOCK(&sc->tx_ring[qid]);
1196 if (sc->tx_ring[qid].data_queued >=
1197 RT_SOFTC_TX_RING_DATA_COUNT) {
1198 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]);
1200 RT_DPRINTF(sc, RT_DEBUG_TX,
1201 "if_start: Tx ring with qid=%d is full\n", qid);
1205 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1206 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1208 sc->tx_data_queue_full[qid]++;
1213 if (rt_tx_data(sc, m, qid) != 0) {
1214 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]);
1216 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1221 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]);
1222 sc->tx_timer = RT_TX_WATCHDOG_TIMEOUT;
1223 callout_reset(&sc->tx_watchdog_ch, hz, rt_tx_watchdog, sc);
1228 * rt_update_promisc - set/clear promiscuous mode. Unused yet, because
1229 * filtering done by attached Ethernet switch.
1232 rt_update_promisc(struct ifnet *ifp)
1234 struct rt_softc *sc;
1237 printf("%s: %s promiscuous mode\n",
1238 device_get_nameunit(sc->dev),
1239 (ifp->if_flags & IFF_PROMISC) ? "entering" : "leaving");
1243 * rt_ioctl - ioctl handler.
1246 rt_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1248 struct rt_softc *sc;
1250 #ifdef IF_RT_PHY_SUPPORT
1251 struct mii_data *mii;
1252 #endif /* IF_RT_PHY_SUPPORT */
1253 int error, startall;
1256 ifr = (struct ifreq *) data;
1264 if (ifp->if_flags & IFF_UP) {
1265 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1266 if ((ifp->if_flags ^ sc->if_flags) &
1268 rt_update_promisc(ifp);
1274 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1277 sc->if_flags = ifp->if_flags;
1278 RT_SOFTC_UNLOCK(sc);
1282 #ifdef IF_RT_PHY_SUPPORT
1283 mii = device_get_softc(sc->rt_miibus);
1284 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1286 error = ifmedia_ioctl(ifp, ifr, &sc->rt_ifmedia, cmd);
1287 #endif /* IF_RT_PHY_SUPPORT */
1290 error = ether_ioctl(ifp, cmd, data);
1297 * rt_periodic - Handler of PERIODIC interrupt
1300 rt_periodic(void *arg)
1302 struct rt_softc *sc;
1305 RT_DPRINTF(sc, RT_DEBUG_PERIODIC, "periodic\n");
1306 taskqueue_enqueue(sc->taskqueue, &sc->periodic_task);
1310 * rt_tx_watchdog - Handler of TX Watchdog
1313 rt_tx_watchdog(void *arg)
1315 struct rt_softc *sc;
1321 if (sc->tx_timer == 0)
1324 if (--sc->tx_timer == 0) {
1325 device_printf(sc->dev, "Tx watchdog timeout: resetting\n");
1328 * XXX: Commented out, because reset break input.
1333 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1334 sc->tx_watchdog_timeouts++;
1336 callout_reset(&sc->tx_watchdog_ch, hz, rt_tx_watchdog, sc);
1340 * rt_cnt_ppe_af - Handler of PPE Counter Table Almost Full interrupt
1343 rt_cnt_ppe_af(struct rt_softc *sc)
1346 RT_DPRINTF(sc, RT_DEBUG_INTR, "PPE Counter Table Almost Full\n");
1350 * rt_cnt_gdm_af - Handler of GDMA 1 & 2 Counter Table Almost Full interrupt
1353 rt_cnt_gdm_af(struct rt_softc *sc)
1356 RT_DPRINTF(sc, RT_DEBUG_INTR,
1357 "GDMA 1 & 2 Counter Table Almost Full\n");
1361 * rt_pse_p2_fc - Handler of PSE port2 (GDMA 2) flow control interrupt
1364 rt_pse_p2_fc(struct rt_softc *sc)
1367 RT_DPRINTF(sc, RT_DEBUG_INTR,
1368 "PSE port2 (GDMA 2) flow control asserted.\n");
1372 * rt_gdm_crc_drop - Handler of GDMA 1/2 discard a packet due to CRC error
1376 rt_gdm_crc_drop(struct rt_softc *sc)
1379 RT_DPRINTF(sc, RT_DEBUG_INTR,
1380 "GDMA 1 & 2 discard a packet due to CRC error\n");
1384 * rt_pse_buf_drop - Handler of buffer sharing limitation interrupt
1387 rt_pse_buf_drop(struct rt_softc *sc)
1390 RT_DPRINTF(sc, RT_DEBUG_INTR,
1391 "PSE discards a packet due to buffer sharing limitation\n");
1395 * rt_gdm_other_drop - Handler of discard on other reason interrupt
1398 rt_gdm_other_drop(struct rt_softc *sc)
1401 RT_DPRINTF(sc, RT_DEBUG_INTR,
1402 "GDMA 1 & 2 discard a packet due to other reason\n");
1406 * rt_pse_p1_fc - Handler of PSE port1 (GDMA 1) flow control interrupt
1409 rt_pse_p1_fc(struct rt_softc *sc)
1412 RT_DPRINTF(sc, RT_DEBUG_INTR,
1413 "PSE port1 (GDMA 1) flow control asserted.\n");
1417 * rt_pse_p0_fc - Handler of PSE port0 (CDMA) flow control interrupt
1420 rt_pse_p0_fc(struct rt_softc *sc)
1423 RT_DPRINTF(sc, RT_DEBUG_INTR,
1424 "PSE port0 (CDMA) flow control asserted.\n");
1428 * rt_pse_fq_empty - Handler of PSE free Q empty threshold reached interrupt
1431 rt_pse_fq_empty(struct rt_softc *sc)
1434 RT_DPRINTF(sc, RT_DEBUG_INTR,
1435 "PSE free Q empty threshold reached & forced drop "
1436 "condition occurred.\n");
1440 * rt_intr - main ISR
1445 struct rt_softc *sc;
1452 /* acknowledge interrupts */
1453 status = RT_READ(sc, sc->fe_int_status);
1454 RT_WRITE(sc, sc->fe_int_status, status);
1456 RT_DPRINTF(sc, RT_DEBUG_INTR, "interrupt: status=0x%08x\n", status);
1458 if (status == 0xffffffff || /* device likely went away */
1459 status == 0) /* not for us */
1464 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1467 if (status & CNT_PPE_AF)
1470 if (status & CNT_GDM_AF)
1473 if (status & PSE_P2_FC)
1476 if (status & GDM_CRC_DROP)
1477 rt_gdm_crc_drop(sc);
1479 if (status & PSE_BUF_DROP)
1480 rt_pse_buf_drop(sc);
1482 if (status & GDM_OTHER_DROP)
1483 rt_gdm_other_drop(sc);
1485 if (status & PSE_P1_FC)
1488 if (status & PSE_P0_FC)
1491 if (status & PSE_FQ_EMPTY)
1492 rt_pse_fq_empty(sc);
1494 if (status & INT_TX_COHERENT)
1495 rt_tx_coherent_intr(sc);
1497 if (status & INT_RX_COHERENT)
1498 rt_rx_coherent_intr(sc);
1500 if (status & RX_DLY_INT)
1501 rt_rx_delay_intr(sc);
1503 if (status & TX_DLY_INT)
1504 rt_tx_delay_intr(sc);
1506 if (status & INT_RX_DONE)
1509 if (status & INT_TXQ3_DONE)
1512 if (status & INT_TXQ2_DONE)
1515 if (status & INT_TXQ1_DONE)
1518 if (status & INT_TXQ0_DONE)
1523 * rt_rt5350_intr - main ISR for Ralink 5350 SoC
1526 rt_rt5350_intr(void *arg)
1528 struct rt_softc *sc;
1535 /* acknowledge interrupts */
1536 status = RT_READ(sc, sc->fe_int_status);
1537 RT_WRITE(sc, sc->fe_int_status, status);
1539 RT_DPRINTF(sc, RT_DEBUG_INTR, "interrupt: status=0x%08x\n", status);
1541 if (status == 0xffffffff || /* device likely went away */
1542 status == 0) /* not for us */
1547 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1550 if (status & RT5350_INT_TX_COHERENT)
1551 rt_tx_coherent_intr(sc);
1552 if (status & RT5350_INT_RX_COHERENT)
1553 rt_rx_coherent_intr(sc);
1554 if (status & RT5350_RX_DLY_INT)
1555 rt_rx_delay_intr(sc);
1556 if (status & RT5350_TX_DLY_INT)
1557 rt_tx_delay_intr(sc);
1558 if (status & RT5350_INT_RXQ1_DONE)
1560 if (status & RT5350_INT_RXQ0_DONE)
1562 if (status & RT5350_INT_TXQ3_DONE)
1564 if (status & RT5350_INT_TXQ2_DONE)
1566 if (status & RT5350_INT_TXQ1_DONE)
1568 if (status & RT5350_INT_TXQ0_DONE)
1573 rt_tx_coherent_intr(struct rt_softc *sc)
1578 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx coherent interrupt\n");
1580 sc->tx_coherent_interrupts++;
1582 /* restart DMA engine */
1583 tmp = RT_READ(sc, sc->pdma_glo_cfg);
1584 tmp &= ~(FE_TX_WB_DDONE | FE_TX_DMA_EN);
1585 RT_WRITE(sc, sc->pdma_glo_cfg, tmp);
1587 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
1588 rt_reset_tx_ring(sc, &sc->tx_ring[i]);
1590 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
1591 RT_WRITE(sc, sc->tx_base_ptr[i],
1592 sc->tx_ring[i].desc_phys_addr);
1593 RT_WRITE(sc, sc->tx_max_cnt[i],
1594 RT_SOFTC_TX_RING_DESC_COUNT);
1595 RT_WRITE(sc, sc->tx_ctx_idx[i], 0);
1602 * rt_rx_coherent_intr
1605 rt_rx_coherent_intr(struct rt_softc *sc)
1610 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx coherent interrupt\n");
1612 sc->rx_coherent_interrupts++;
1614 /* restart DMA engine */
1615 tmp = RT_READ(sc, sc->pdma_glo_cfg);
1616 tmp &= ~(FE_RX_DMA_EN);
1617 RT_WRITE(sc, sc->pdma_glo_cfg, tmp);
1620 for (i = 0; i < sc->rx_ring_count; i++)
1621 rt_reset_rx_ring(sc, &sc->rx_ring[i]);
1623 for (i = 0; i < sc->rx_ring_count; i++) {
1624 RT_WRITE(sc, sc->rx_base_ptr[i],
1625 sc->rx_ring[i].desc_phys_addr);
1626 RT_WRITE(sc, sc->rx_max_cnt[i],
1627 RT_SOFTC_RX_RING_DATA_COUNT);
1628 RT_WRITE(sc, sc->rx_calc_idx[i],
1629 RT_SOFTC_RX_RING_DATA_COUNT - 1);
1636 * rt_rx_intr - a packet received
1639 rt_rx_intr(struct rt_softc *sc, int qid)
1641 KASSERT(qid >= 0 && qid < sc->rx_ring_count,
1642 ("%s: Rx interrupt: invalid qid=%d\n",
1643 device_get_nameunit(sc->dev), qid));
1645 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx interrupt\n");
1646 sc->rx_interrupts[qid]++;
1649 if (!(sc->intr_disable_mask & (sc->int_rx_done_mask << qid))) {
1650 rt_intr_disable(sc, (sc->int_rx_done_mask << qid));
1651 taskqueue_enqueue(sc->taskqueue, &sc->rx_done_task);
1654 sc->intr_pending_mask |= (sc->int_rx_done_mask << qid);
1655 RT_SOFTC_UNLOCK(sc);
1659 rt_rx_delay_intr(struct rt_softc *sc)
1662 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx delay interrupt\n");
1663 sc->rx_delay_interrupts++;
1667 rt_tx_delay_intr(struct rt_softc *sc)
1670 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx delay interrupt\n");
1671 sc->tx_delay_interrupts++;
1675 * rt_tx_intr - Transsmition of packet done
1678 rt_tx_intr(struct rt_softc *sc, int qid)
1681 KASSERT(qid >= 0 && qid < RT_SOFTC_TX_RING_COUNT,
1682 ("%s: Tx interrupt: invalid qid=%d\n",
1683 device_get_nameunit(sc->dev), qid));
1685 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx interrupt: qid=%d\n", qid);
1687 sc->tx_interrupts[qid]++;
1690 if (!(sc->intr_disable_mask & (sc->int_tx_done_mask << qid))) {
1691 rt_intr_disable(sc, (sc->int_tx_done_mask << qid));
1692 taskqueue_enqueue(sc->taskqueue, &sc->tx_done_task);
1695 sc->intr_pending_mask |= (sc->int_tx_done_mask << qid);
1696 RT_SOFTC_UNLOCK(sc);
1700 * rt_rx_done_task - run RX task
1703 rt_rx_done_task(void *context, int pending)
1705 struct rt_softc *sc;
1712 RT_DPRINTF(sc, RT_DEBUG_RX, "Rx done task\n");
1714 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1717 sc->intr_pending_mask &= ~sc->int_rx_done_mask;
1719 again = rt_rx_eof(sc, &sc->rx_ring[0], sc->rx_process_limit);
1723 if ((sc->intr_pending_mask & sc->int_rx_done_mask) || again) {
1724 RT_DPRINTF(sc, RT_DEBUG_RX,
1725 "Rx done task: scheduling again\n");
1726 taskqueue_enqueue(sc->taskqueue, &sc->rx_done_task);
1728 rt_intr_enable(sc, sc->int_rx_done_mask);
1731 RT_SOFTC_UNLOCK(sc);
1735 * rt_tx_done_task - check for pending TX task in all queues
1738 rt_tx_done_task(void *context, int pending)
1740 struct rt_softc *sc;
1748 RT_DPRINTF(sc, RT_DEBUG_TX, "Tx done task\n");
1750 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1753 for (i = RT_SOFTC_TX_RING_COUNT - 1; i >= 0; i--) {
1754 if (sc->intr_pending_mask & (sc->int_tx_done_mask << i)) {
1755 sc->intr_pending_mask &= ~(sc->int_tx_done_mask << i);
1756 rt_tx_eof(sc, &sc->tx_ring[i]);
1762 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1764 if(sc->rt_chipid == RT_CHIPID_RT5350 ||
1765 sc->rt_chipid == RT_CHIPID_MT7620 ||
1766 sc->rt_chipid == RT_CHIPID_MT7621)
1768 RT5350_INT_TXQ3_DONE |
1769 RT5350_INT_TXQ2_DONE |
1770 RT5350_INT_TXQ1_DONE |
1771 RT5350_INT_TXQ0_DONE);
1781 rt_intr_enable(sc, ~sc->intr_pending_mask &
1782 (sc->intr_disable_mask & intr_mask));
1784 if (sc->intr_pending_mask & intr_mask) {
1785 RT_DPRINTF(sc, RT_DEBUG_TX,
1786 "Tx done task: scheduling again\n");
1787 taskqueue_enqueue(sc->taskqueue, &sc->tx_done_task);
1790 RT_SOFTC_UNLOCK(sc);
1792 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1797 * rt_periodic_task - run periodic task
1800 rt_periodic_task(void *context, int pending)
1802 struct rt_softc *sc;
1808 RT_DPRINTF(sc, RT_DEBUG_PERIODIC, "periodic task: round=%lu\n",
1809 sc->periodic_round);
1811 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1815 sc->periodic_round++;
1816 rt_update_stats(sc);
1818 if ((sc->periodic_round % 10) == 0) {
1819 rt_update_raw_counters(sc);
1823 RT_SOFTC_UNLOCK(sc);
1824 callout_reset(&sc->periodic_ch, hz / 10, rt_periodic, sc);
1828 * rt_rx_eof - check for frames that done by DMA engine and pass it into
1829 * network subsystem.
1832 rt_rx_eof(struct rt_softc *sc, struct rt_softc_rx_ring *ring, int limit)
1835 /* struct rt_softc_rx_ring *ring; */
1836 struct rt_rxdesc *desc;
1837 struct rt_softc_rx_data *data;
1838 struct mbuf *m, *mnew;
1839 bus_dma_segment_t segs[1];
1840 bus_dmamap_t dma_map;
1841 uint32_t index, desc_flags;
1842 int error, nsegs, len, nframes;
1845 /* ring = &sc->rx_ring[0]; */
1849 while (limit != 0) {
1850 index = RT_READ(sc, sc->rx_drx_idx[0]);
1851 if (ring->cur == index)
1854 desc = &ring->desc[ring->cur];
1855 data = &ring->data[ring->cur];
1857 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
1858 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1861 if ( sc->debug & RT_DEBUG_RX ) {
1862 printf("\nRX Descriptor[%#08x] dump:\n", (u_int)desc);
1863 hexdump(desc, 16, 0, 0);
1864 printf("-----------------------------------\n");
1868 /* XXX Sometime device don`t set DDONE bit */
1870 if (!(desc->sdl0 & htole16(RT_RXDESC_SDL0_DDONE))) {
1871 RT_DPRINTF(sc, RT_DEBUG_RX, "DDONE=0, try next\n");
1876 len = le16toh(desc->sdl0) & 0x3fff;
1877 RT_DPRINTF(sc, RT_DEBUG_RX, "new frame len=%d\n", len);
1881 mnew = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
1884 sc->rx_mbuf_alloc_errors++;
1885 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1889 mnew->m_len = mnew->m_pkthdr.len = MJUMPAGESIZE;
1891 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag,
1892 ring->spare_dma_map, mnew, segs, &nsegs, BUS_DMA_NOWAIT);
1894 RT_DPRINTF(sc, RT_DEBUG_RX,
1895 "could not load Rx mbuf DMA map: "
1896 "error=%d, nsegs=%d\n",
1901 sc->rx_mbuf_dmamap_errors++;
1902 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1907 KASSERT(nsegs == 1, ("%s: too many DMA segments",
1908 device_get_nameunit(sc->dev)));
1910 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
1911 BUS_DMASYNC_POSTREAD);
1912 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
1914 dma_map = data->dma_map;
1915 data->dma_map = ring->spare_dma_map;
1916 ring->spare_dma_map = dma_map;
1918 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
1919 BUS_DMASYNC_PREREAD);
1922 desc_flags = desc->word3;
1925 /* Add 2 for proper align of RX IP header */
1926 desc->sdp0 = htole32(segs[0].ds_addr+2);
1927 desc->sdl0 = htole32(segs[0].ds_len-2);
1930 RT_DPRINTF(sc, RT_DEBUG_RX,
1931 "Rx frame: rxdesc flags=0x%08x\n", desc_flags);
1933 m->m_pkthdr.rcvif = ifp;
1934 /* Add 2 to fix data align, after sdp0 = addr + 2 */
1936 m->m_pkthdr.len = m->m_len = len;
1938 /* check for crc errors */
1939 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1940 /*check for valid checksum*/
1941 if (desc_flags & (sc->csum_fail_ip|sc->csum_fail_l4)) {
1942 RT_DPRINTF(sc, RT_DEBUG_RX,
1943 "rxdesc: crc error\n");
1945 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1947 if (!(ifp->if_flags & IFF_PROMISC)) {
1952 if ((desc_flags & sc->csum_fail_ip) == 0) {
1953 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1954 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1955 m->m_pkthdr.csum_data = 0xffff;
1957 m->m_flags &= ~M_HASFCS;
1960 (*ifp->if_input)(ifp, m);
1962 desc->sdl0 &= ~htole16(RT_RXDESC_SDL0_DDONE);
1964 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
1965 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1967 ring->cur = (ring->cur + 1) % RT_SOFTC_RX_RING_DATA_COUNT;
1973 RT_WRITE(sc, sc->rx_calc_idx[0],
1974 RT_SOFTC_RX_RING_DATA_COUNT - 1);
1976 RT_WRITE(sc, sc->rx_calc_idx[0],
1979 RT_DPRINTF(sc, RT_DEBUG_RX, "Rx eof: nframes=%d\n", nframes);
1981 sc->rx_packets += nframes;
1983 return (limit == 0);
1987 * rt_tx_eof - check for successful transmitted frames and mark their
1988 * descriptor as free.
1991 rt_tx_eof(struct rt_softc *sc, struct rt_softc_tx_ring *ring)
1994 struct rt_txdesc *desc;
1995 struct rt_softc_tx_data *data;
1997 int ndescs, nframes;
2005 index = RT_READ(sc, sc->tx_dtx_idx[ring->qid]);
2006 if (ring->desc_next == index)
2011 desc = &ring->desc[ring->desc_next];
2013 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2014 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2016 if (desc->sdl0 & htole16(RT_TXDESC_SDL0_LASTSEG) ||
2017 desc->sdl1 & htole16(RT_TXDESC_SDL1_LASTSEG)) {
2020 data = &ring->data[ring->data_next];
2022 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
2023 BUS_DMASYNC_POSTWRITE);
2024 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
2030 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2032 RT_SOFTC_TX_RING_LOCK(ring);
2033 ring->data_queued--;
2034 ring->data_next = (ring->data_next + 1) %
2035 RT_SOFTC_TX_RING_DATA_COUNT;
2036 RT_SOFTC_TX_RING_UNLOCK(ring);
2039 desc->sdl0 &= ~htole16(RT_TXDESC_SDL0_DDONE);
2041 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2042 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2044 RT_SOFTC_TX_RING_LOCK(ring);
2045 ring->desc_queued--;
2046 ring->desc_next = (ring->desc_next + 1) %
2047 RT_SOFTC_TX_RING_DESC_COUNT;
2048 RT_SOFTC_TX_RING_UNLOCK(ring);
2051 RT_DPRINTF(sc, RT_DEBUG_TX,
2052 "Tx eof: qid=%d, ndescs=%d, nframes=%d\n", ring->qid, ndescs,
2057 * rt_update_stats - query statistics counters and update related variables.
2060 rt_update_stats(struct rt_softc *sc)
2065 RT_DPRINTF(sc, RT_DEBUG_STATS, "update statistic: \n");
2066 /* XXX do update stats here */
2070 * rt_watchdog - reinit device on watchdog event.
2073 rt_watchdog(struct rt_softc *sc)
2079 if(sc->rt_chipid != RT_CHIPID_RT5350 &&
2080 sc->rt_chipid != RT_CHIPID_MT7620 &&
2081 sc->rt_chipid != RT_CHIPID_MT7621) {
2082 tmp = RT_READ(sc, PSE_BASE + CDMA_OQ_STA);
2084 RT_DPRINTF(sc, RT_DEBUG_WATCHDOG,
2085 "watchdog: PSE_IQ_STA=0x%08x\n", tmp);
2087 /* XXX: do not reset */
2089 if (((tmp >> P0_IQ_PCNT_SHIFT) & 0xff) != 0) {
2090 sc->tx_queue_not_empty[0]++;
2092 for (ntries = 0; ntries < 10; ntries++) {
2093 tmp = RT_READ(sc, PSE_BASE + PSE_IQ_STA);
2094 if (((tmp >> P0_IQ_PCNT_SHIFT) & 0xff) == 0)
2101 if (((tmp >> P1_IQ_PCNT_SHIFT) & 0xff) != 0) {
2102 sc->tx_queue_not_empty[1]++;
2104 for (ntries = 0; ntries < 10; ntries++) {
2105 tmp = RT_READ(sc, PSE_BASE + PSE_IQ_STA);
2106 if (((tmp >> P1_IQ_PCNT_SHIFT) & 0xff) == 0)
2116 * rt_update_raw_counters - update counters.
2119 rt_update_raw_counters(struct rt_softc *sc)
2122 sc->tx_bytes += RT_READ(sc, CNTR_BASE + GDMA_TX_GBCNT0);
2123 sc->tx_packets += RT_READ(sc, CNTR_BASE + GDMA_TX_GPCNT0);
2124 sc->tx_skip += RT_READ(sc, CNTR_BASE + GDMA_TX_SKIPCNT0);
2125 sc->tx_collision+= RT_READ(sc, CNTR_BASE + GDMA_TX_COLCNT0);
2127 sc->rx_bytes += RT_READ(sc, CNTR_BASE + GDMA_RX_GBCNT0);
2128 sc->rx_packets += RT_READ(sc, CNTR_BASE + GDMA_RX_GPCNT0);
2129 sc->rx_crc_err += RT_READ(sc, CNTR_BASE + GDMA_RX_CSUM_ERCNT0);
2130 sc->rx_short_err+= RT_READ(sc, CNTR_BASE + GDMA_RX_SHORT_ERCNT0);
2131 sc->rx_long_err += RT_READ(sc, CNTR_BASE + GDMA_RX_LONG_ERCNT0);
2132 sc->rx_phy_err += RT_READ(sc, CNTR_BASE + GDMA_RX_FERCNT0);
2133 sc->rx_fifo_overflows+= RT_READ(sc, CNTR_BASE + GDMA_RX_OERCNT0);
2137 rt_intr_enable(struct rt_softc *sc, uint32_t intr_mask)
2141 sc->intr_disable_mask &= ~intr_mask;
2142 tmp = sc->intr_enable_mask & ~sc->intr_disable_mask;
2143 RT_WRITE(sc, sc->fe_int_enable, tmp);
2147 rt_intr_disable(struct rt_softc *sc, uint32_t intr_mask)
2151 sc->intr_disable_mask |= intr_mask;
2152 tmp = sc->intr_enable_mask & ~sc->intr_disable_mask;
2153 RT_WRITE(sc, sc->fe_int_enable, tmp);
2157 * rt_txrx_enable - enable TX/RX DMA
2160 rt_txrx_enable(struct rt_softc *sc)
2168 /* enable Tx/Rx DMA engine */
2169 for (ntries = 0; ntries < 200; ntries++) {
2170 tmp = RT_READ(sc, sc->pdma_glo_cfg);
2171 if (!(tmp & (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)))
2177 if (ntries == 200) {
2178 device_printf(sc->dev, "timeout waiting for DMA engine\n");
2184 tmp |= FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
2185 RT_WRITE(sc, sc->pdma_glo_cfg, tmp);
2187 /* XXX set Rx filter */
2192 * rt_alloc_rx_ring - allocate RX DMA ring buffer
2195 rt_alloc_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring, int qid)
2197 struct rt_rxdesc *desc;
2198 struct rt_softc_rx_data *data;
2199 bus_dma_segment_t segs[1];
2200 int i, nsegs, error;
2202 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2203 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2204 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc), 1,
2205 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc),
2206 0, NULL, NULL, &ring->desc_dma_tag);
2208 device_printf(sc->dev,
2209 "could not create Rx desc DMA tag\n");
2213 error = bus_dmamem_alloc(ring->desc_dma_tag, (void **) &ring->desc,
2214 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_dma_map);
2216 device_printf(sc->dev,
2217 "could not allocate Rx desc DMA memory\n");
2221 error = bus_dmamap_load(ring->desc_dma_tag, ring->desc_dma_map,
2223 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc),
2224 rt_dma_map_addr, &ring->desc_phys_addr, 0);
2226 device_printf(sc->dev, "could not load Rx desc DMA map\n");
2230 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2231 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2232 MJUMPAGESIZE, 1, MJUMPAGESIZE, 0, NULL, NULL,
2233 &ring->data_dma_tag);
2235 device_printf(sc->dev,
2236 "could not create Rx data DMA tag\n");
2240 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) {
2241 desc = &ring->desc[i];
2242 data = &ring->data[i];
2244 error = bus_dmamap_create(ring->data_dma_tag, 0,
2247 device_printf(sc->dev, "could not create Rx data DMA "
2252 data->m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
2254 if (data->m == NULL) {
2255 device_printf(sc->dev, "could not allocate Rx mbuf\n");
2260 data->m->m_len = data->m->m_pkthdr.len = MJUMPAGESIZE;
2262 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag,
2263 data->dma_map, data->m, segs, &nsegs, BUS_DMA_NOWAIT);
2265 device_printf(sc->dev,
2266 "could not load Rx mbuf DMA map\n");
2270 KASSERT(nsegs == 1, ("%s: too many DMA segments",
2271 device_get_nameunit(sc->dev)));
2273 /* Add 2 for proper align of RX IP header */
2274 desc->sdp0 = htole32(segs[0].ds_addr+2);
2275 desc->sdl0 = htole32(segs[0].ds_len-2);
2278 error = bus_dmamap_create(ring->data_dma_tag, 0,
2279 &ring->spare_dma_map);
2281 device_printf(sc->dev,
2282 "could not create Rx spare DMA map\n");
2286 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2287 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2292 rt_free_rx_ring(sc, ring);
2297 * rt_reset_rx_ring - reset RX ring buffer
2300 rt_reset_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring)
2302 struct rt_rxdesc *desc;
2305 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) {
2306 desc = &ring->desc[i];
2307 desc->sdl0 &= ~htole16(RT_RXDESC_SDL0_DDONE);
2310 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2311 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2316 * rt_free_rx_ring - free memory used by RX ring buffer
2319 rt_free_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring)
2321 struct rt_softc_rx_data *data;
2324 if (ring->desc != NULL) {
2325 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2326 BUS_DMASYNC_POSTWRITE);
2327 bus_dmamap_unload(ring->desc_dma_tag, ring->desc_dma_map);
2328 bus_dmamem_free(ring->desc_dma_tag, ring->desc,
2329 ring->desc_dma_map);
2332 if (ring->desc_dma_tag != NULL)
2333 bus_dma_tag_destroy(ring->desc_dma_tag);
2335 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) {
2336 data = &ring->data[i];
2338 if (data->m != NULL) {
2339 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
2340 BUS_DMASYNC_POSTREAD);
2341 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
2345 if (data->dma_map != NULL)
2346 bus_dmamap_destroy(ring->data_dma_tag, data->dma_map);
2349 if (ring->spare_dma_map != NULL)
2350 bus_dmamap_destroy(ring->data_dma_tag, ring->spare_dma_map);
2352 if (ring->data_dma_tag != NULL)
2353 bus_dma_tag_destroy(ring->data_dma_tag);
2357 * rt_alloc_tx_ring - allocate TX ring buffer
2360 rt_alloc_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring, int qid)
2362 struct rt_softc_tx_data *data;
2365 mtx_init(&ring->lock, device_get_nameunit(sc->dev), NULL, MTX_DEF);
2367 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2368 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2369 RT_SOFTC_TX_RING_DESC_COUNT * sizeof(struct rt_txdesc), 1,
2370 RT_SOFTC_TX_RING_DESC_COUNT * sizeof(struct rt_txdesc),
2371 0, NULL, NULL, &ring->desc_dma_tag);
2373 device_printf(sc->dev,
2374 "could not create Tx desc DMA tag\n");
2378 error = bus_dmamem_alloc(ring->desc_dma_tag, (void **) &ring->desc,
2379 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_dma_map);
2381 device_printf(sc->dev,
2382 "could not allocate Tx desc DMA memory\n");
2386 error = bus_dmamap_load(ring->desc_dma_tag, ring->desc_dma_map,
2387 ring->desc, (RT_SOFTC_TX_RING_DESC_COUNT *
2388 sizeof(struct rt_txdesc)), rt_dma_map_addr,
2389 &ring->desc_phys_addr, 0);
2391 device_printf(sc->dev, "could not load Tx desc DMA map\n");
2395 ring->desc_queued = 0;
2397 ring->desc_next = 0;
2399 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2400 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2401 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE, 1,
2402 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE,
2403 0, NULL, NULL, &ring->seg0_dma_tag);
2405 device_printf(sc->dev,
2406 "could not create Tx seg0 DMA tag\n");
2410 error = bus_dmamem_alloc(ring->seg0_dma_tag, (void **) &ring->seg0,
2411 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->seg0_dma_map);
2413 device_printf(sc->dev,
2414 "could not allocate Tx seg0 DMA memory\n");
2418 error = bus_dmamap_load(ring->seg0_dma_tag, ring->seg0_dma_map,
2420 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE,
2421 rt_dma_map_addr, &ring->seg0_phys_addr, 0);
2423 device_printf(sc->dev, "could not load Tx seg0 DMA map\n");
2427 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2428 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2429 MJUMPAGESIZE, RT_SOFTC_MAX_SCATTER, MJUMPAGESIZE, 0, NULL, NULL,
2430 &ring->data_dma_tag);
2432 device_printf(sc->dev,
2433 "could not create Tx data DMA tag\n");
2437 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) {
2438 data = &ring->data[i];
2440 error = bus_dmamap_create(ring->data_dma_tag, 0,
2443 device_printf(sc->dev, "could not create Tx data DMA "
2449 ring->data_queued = 0;
2451 ring->data_next = 0;
2457 rt_free_tx_ring(sc, ring);
2462 * rt_reset_tx_ring - reset TX ring buffer to empty state
2465 rt_reset_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring)
2467 struct rt_softc_tx_data *data;
2468 struct rt_txdesc *desc;
2471 for (i = 0; i < RT_SOFTC_TX_RING_DESC_COUNT; i++) {
2472 desc = &ring->desc[i];
2478 ring->desc_queued = 0;
2480 ring->desc_next = 0;
2482 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2483 BUS_DMASYNC_PREWRITE);
2485 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map,
2486 BUS_DMASYNC_PREWRITE);
2488 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) {
2489 data = &ring->data[i];
2491 if (data->m != NULL) {
2492 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
2493 BUS_DMASYNC_POSTWRITE);
2494 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
2500 ring->data_queued = 0;
2502 ring->data_next = 0;
2506 * rt_free_tx_ring - free RX ring buffer
2509 rt_free_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring)
2511 struct rt_softc_tx_data *data;
2514 if (ring->desc != NULL) {
2515 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2516 BUS_DMASYNC_POSTWRITE);
2517 bus_dmamap_unload(ring->desc_dma_tag, ring->desc_dma_map);
2518 bus_dmamem_free(ring->desc_dma_tag, ring->desc,
2519 ring->desc_dma_map);
2522 if (ring->desc_dma_tag != NULL)
2523 bus_dma_tag_destroy(ring->desc_dma_tag);
2525 if (ring->seg0 != NULL) {
2526 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map,
2527 BUS_DMASYNC_POSTWRITE);
2528 bus_dmamap_unload(ring->seg0_dma_tag, ring->seg0_dma_map);
2529 bus_dmamem_free(ring->seg0_dma_tag, ring->seg0,
2530 ring->seg0_dma_map);
2533 if (ring->seg0_dma_tag != NULL)
2534 bus_dma_tag_destroy(ring->seg0_dma_tag);
2536 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) {
2537 data = &ring->data[i];
2539 if (data->m != NULL) {
2540 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
2541 BUS_DMASYNC_POSTWRITE);
2542 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
2546 if (data->dma_map != NULL)
2547 bus_dmamap_destroy(ring->data_dma_tag, data->dma_map);
2550 if (ring->data_dma_tag != NULL)
2551 bus_dma_tag_destroy(ring->data_dma_tag);
2553 mtx_destroy(&ring->lock);
2557 * rt_dma_map_addr - get address of busdma segment
2560 rt_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2565 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
2567 *(bus_addr_t *) arg = segs[0].ds_addr;
2571 * rt_sysctl_attach - attach sysctl nodes for NIC counters.
2574 rt_sysctl_attach(struct rt_softc *sc)
2576 struct sysctl_ctx_list *ctx;
2577 struct sysctl_oid *tree;
2578 struct sysctl_oid *stats;
2580 ctx = device_get_sysctl_ctx(sc->dev);
2581 tree = device_get_sysctl_tree(sc->dev);
2583 /* statistic counters */
2584 stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
2585 "stats", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "statistic");
2587 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2588 "interrupts", CTLFLAG_RD, &sc->interrupts,
2591 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2592 "tx_coherent_interrupts", CTLFLAG_RD, &sc->tx_coherent_interrupts,
2593 "Tx coherent interrupts");
2595 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2596 "rx_coherent_interrupts", CTLFLAG_RD, &sc->rx_coherent_interrupts,
2597 "Rx coherent interrupts");
2599 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2600 "rx_interrupts", CTLFLAG_RD, &sc->rx_interrupts[0],
2603 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2604 "rx_delay_interrupts", CTLFLAG_RD, &sc->rx_delay_interrupts,
2605 "Rx delay interrupts");
2607 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2608 "TXQ3_interrupts", CTLFLAG_RD, &sc->tx_interrupts[3],
2609 "Tx AC3 interrupts");
2611 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2612 "TXQ2_interrupts", CTLFLAG_RD, &sc->tx_interrupts[2],
2613 "Tx AC2 interrupts");
2615 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2616 "TXQ1_interrupts", CTLFLAG_RD, &sc->tx_interrupts[1],
2617 "Tx AC1 interrupts");
2619 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2620 "TXQ0_interrupts", CTLFLAG_RD, &sc->tx_interrupts[0],
2621 "Tx AC0 interrupts");
2623 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2624 "tx_delay_interrupts", CTLFLAG_RD, &sc->tx_delay_interrupts,
2625 "Tx delay interrupts");
2627 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2628 "TXQ3_desc_queued", CTLFLAG_RD, &sc->tx_ring[3].desc_queued,
2629 0, "Tx AC3 descriptors queued");
2631 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2632 "TXQ3_data_queued", CTLFLAG_RD, &sc->tx_ring[3].data_queued,
2633 0, "Tx AC3 data queued");
2635 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2636 "TXQ2_desc_queued", CTLFLAG_RD, &sc->tx_ring[2].desc_queued,
2637 0, "Tx AC2 descriptors queued");
2639 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2640 "TXQ2_data_queued", CTLFLAG_RD, &sc->tx_ring[2].data_queued,
2641 0, "Tx AC2 data queued");
2643 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2644 "TXQ1_desc_queued", CTLFLAG_RD, &sc->tx_ring[1].desc_queued,
2645 0, "Tx AC1 descriptors queued");
2647 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2648 "TXQ1_data_queued", CTLFLAG_RD, &sc->tx_ring[1].data_queued,
2649 0, "Tx AC1 data queued");
2651 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2652 "TXQ0_desc_queued", CTLFLAG_RD, &sc->tx_ring[0].desc_queued,
2653 0, "Tx AC0 descriptors queued");
2655 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2656 "TXQ0_data_queued", CTLFLAG_RD, &sc->tx_ring[0].data_queued,
2657 0, "Tx AC0 data queued");
2659 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2660 "TXQ3_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[3],
2661 "Tx AC3 data queue full");
2663 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2664 "TXQ2_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[2],
2665 "Tx AC2 data queue full");
2667 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2668 "TXQ1_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[1],
2669 "Tx AC1 data queue full");
2671 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2672 "TXQ0_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[0],
2673 "Tx AC0 data queue full");
2675 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2676 "tx_watchdog_timeouts", CTLFLAG_RD, &sc->tx_watchdog_timeouts,
2677 "Tx watchdog timeouts");
2679 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2680 "tx_defrag_packets", CTLFLAG_RD, &sc->tx_defrag_packets,
2681 "Tx defragmented packets");
2683 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2684 "no_tx_desc_avail", CTLFLAG_RD, &sc->no_tx_desc_avail,
2685 "no Tx descriptors available");
2687 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2688 "rx_mbuf_alloc_errors", CTLFLAG_RD, &sc->rx_mbuf_alloc_errors,
2689 "Rx mbuf allocation errors");
2691 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2692 "rx_mbuf_dmamap_errors", CTLFLAG_RD, &sc->rx_mbuf_dmamap_errors,
2693 "Rx mbuf DMA mapping errors");
2695 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2696 "tx_queue_0_not_empty", CTLFLAG_RD, &sc->tx_queue_not_empty[0],
2697 "Tx queue 0 not empty");
2699 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2700 "tx_queue_1_not_empty", CTLFLAG_RD, &sc->tx_queue_not_empty[1],
2701 "Tx queue 1 not empty");
2703 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2704 "rx_packets", CTLFLAG_RD, &sc->rx_packets,
2707 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2708 "rx_crc_errors", CTLFLAG_RD, &sc->rx_crc_err,
2711 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2712 "rx_phy_errors", CTLFLAG_RD, &sc->rx_phy_err,
2715 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2716 "rx_dup_packets", CTLFLAG_RD, &sc->rx_dup_packets,
2717 "Rx duplicate packets");
2719 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2720 "rx_fifo_overflows", CTLFLAG_RD, &sc->rx_fifo_overflows,
2721 "Rx FIFO overflows");
2723 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2724 "rx_bytes", CTLFLAG_RD, &sc->rx_bytes,
2727 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2728 "rx_long_err", CTLFLAG_RD, &sc->rx_long_err,
2729 "Rx too long frame errors");
2731 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2732 "rx_short_err", CTLFLAG_RD, &sc->rx_short_err,
2733 "Rx too short frame errors");
2735 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2736 "tx_bytes", CTLFLAG_RD, &sc->tx_bytes,
2739 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2740 "tx_packets", CTLFLAG_RD, &sc->tx_packets,
2743 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2744 "tx_skip", CTLFLAG_RD, &sc->tx_skip,
2745 "Tx skip count for GDMA ports");
2747 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2748 "tx_collision", CTLFLAG_RD, &sc->tx_collision,
2749 "Tx collision count for GDMA ports");
2752 #if defined(IF_RT_PHY_SUPPORT) || defined(RT_MDIO)
2753 /* This code is only work RT2880 and same chip. */
2754 /* TODO: make RT3052 and later support code. But nobody need it? */
2756 rt_miibus_readreg(device_t dev, int phy, int reg)
2758 struct rt_softc *sc = device_get_softc(dev);
2762 * PSEUDO_PHYAD is a special value for indicate switch attached.
2763 * No one PHY use PSEUDO_PHYAD (0x1e) address.
2767 /* Fake PHY ID for bfeswitch attach */
2770 return (BMSR_EXTSTAT|BMSR_MEDIAMASK);
2772 return (0x40); /* As result of faking */
2773 case MII_PHYIDR2: /* PHY will detect as */
2774 return (0x6250); /* bfeswitch */
2779 /* Wait prev command done if any */
2780 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2781 dat = ((phy << MDIO_PHY_ADDR_SHIFT) & MDIO_PHY_ADDR_MASK) |
2782 ((reg << MDIO_PHYREG_ADDR_SHIFT) & MDIO_PHYREG_ADDR_MASK);
2783 RT_WRITE(sc, MDIO_ACCESS, dat);
2784 RT_WRITE(sc, MDIO_ACCESS, dat | MDIO_CMD_ONGO);
2785 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2787 return (RT_READ(sc, MDIO_ACCESS) & MDIO_PHY_DATA_MASK);
2791 rt_miibus_writereg(device_t dev, int phy, int reg, int val)
2793 struct rt_softc *sc = device_get_softc(dev);
2796 /* Wait prev command done if any */
2797 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2799 ((phy << MDIO_PHY_ADDR_SHIFT) & MDIO_PHY_ADDR_MASK) |
2800 ((reg << MDIO_PHYREG_ADDR_SHIFT) & MDIO_PHYREG_ADDR_MASK) |
2801 (val & MDIO_PHY_DATA_MASK);
2802 RT_WRITE(sc, MDIO_ACCESS, dat);
2803 RT_WRITE(sc, MDIO_ACCESS, dat | MDIO_CMD_ONGO);
2804 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2810 #ifdef IF_RT_PHY_SUPPORT
2812 rt_miibus_statchg(device_t dev)
2814 struct rt_softc *sc = device_get_softc(dev);
2815 struct mii_data *mii;
2817 mii = device_get_softc(sc->rt_miibus);
2819 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
2820 (IFM_ACTIVE | IFM_AVALID)) {
2821 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2824 /* XXX check link here */
2832 #endif /* IF_RT_PHY_SUPPORT */
2834 static device_method_t rt_dev_methods[] =
2836 DEVMETHOD(device_probe, rt_probe),
2837 DEVMETHOD(device_attach, rt_attach),
2838 DEVMETHOD(device_detach, rt_detach),
2839 DEVMETHOD(device_shutdown, rt_shutdown),
2840 DEVMETHOD(device_suspend, rt_suspend),
2841 DEVMETHOD(device_resume, rt_resume),
2843 #ifdef IF_RT_PHY_SUPPORT
2845 DEVMETHOD(miibus_readreg, rt_miibus_readreg),
2846 DEVMETHOD(miibus_writereg, rt_miibus_writereg),
2847 DEVMETHOD(miibus_statchg, rt_miibus_statchg),
2853 static driver_t rt_driver =
2857 sizeof(struct rt_softc)
2860 static devclass_t rt_dev_class;
2862 DRIVER_MODULE(rt, nexus, rt_driver, rt_dev_class, 0, 0);
2864 DRIVER_MODULE(rt, simplebus, rt_driver, rt_dev_class, 0, 0);
2867 MODULE_DEPEND(rt, ether, 1, 1, 1);
2868 MODULE_DEPEND(rt, miibus, 1, 1, 1);
2871 MODULE_DEPEND(rt, mdio, 1, 1, 1);
2873 static int rtmdio_probe(device_t);
2874 static int rtmdio_attach(device_t);
2875 static int rtmdio_detach(device_t);
2877 static struct mtx miibus_mtx;
2879 MTX_SYSINIT(miibus_mtx, &miibus_mtx, "rt mii lock", MTX_DEF);
2882 * Declare an additional, separate driver for accessing the MDIO bus.
2884 static device_method_t rtmdio_methods[] = {
2885 /* Device interface */
2886 DEVMETHOD(device_probe, rtmdio_probe),
2887 DEVMETHOD(device_attach, rtmdio_attach),
2888 DEVMETHOD(device_detach, rtmdio_detach),
2891 DEVMETHOD(bus_add_child, device_add_child_ordered),
2894 DEVMETHOD(mdio_readreg, rt_miibus_readreg),
2895 DEVMETHOD(mdio_writereg, rt_miibus_writereg),
2898 DEFINE_CLASS_0(rtmdio, rtmdio_driver, rtmdio_methods,
2899 sizeof(struct rt_softc));
2900 static devclass_t rtmdio_devclass;
2902 DRIVER_MODULE(miiproxy, rt, miiproxy_driver, miiproxy_devclass, 0, 0);
2903 DRIVER_MODULE(rtmdio, simplebus, rtmdio_driver, rtmdio_devclass, 0, 0);
2904 DRIVER_MODULE(mdio, rtmdio, mdio_driver, mdio_devclass, 0, 0);
2907 rtmdio_probe(device_t dev)
2909 if (!ofw_bus_status_okay(dev))
2912 if (!ofw_bus_is_compatible(dev, "ralink,rt2880-mdio"))
2915 device_set_desc(dev, "FV built-in ethernet interface, MDIO controller");
2920 rtmdio_attach(device_t dev)
2922 struct rt_softc *sc;
2925 sc = device_get_softc(dev);
2928 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
2929 &sc->mem_rid, RF_ACTIVE | RF_SHAREABLE);
2930 if (sc->mem == NULL) {
2931 device_printf(dev, "couldn't map memory\n");
2936 sc->bst = rman_get_bustag(sc->mem);
2937 sc->bsh = rman_get_bushandle(sc->mem);
2939 bus_generic_probe(dev);
2940 bus_enumerate_hinted_children(dev);
2941 error = bus_generic_attach(dev);
2947 rtmdio_detach(device_t dev)