2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2015-2016, Stanislav Galabov
5 * Copyright (c) 2014, Aleksandr A. Mityaev
6 * Copyright (c) 2011, Aleksandr Rybalko
8 * by Alexander Egorenkov <egorenar@gmail.com>
9 * and by Damien Bergamini <damien.bergamini@free.fr>
10 * All rights reserved.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice unmodified, this list of conditions, and the following
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
44 #include <net/if_var.h>
45 #include <net/if_arp.h>
46 #include <net/ethernet.h>
47 #include <net/if_dl.h>
48 #include <net/if_media.h>
49 #include <net/if_types.h>
50 #include <net/if_vlan_var.h>
54 #include <machine/bus.h>
55 #include <machine/cache.h>
56 #include <machine/cpufunc.h>
57 #include <machine/resource.h>
58 #include <vm/vm_param.h>
61 #include <machine/pmap.h>
65 #include "opt_platform.h"
66 #include "opt_rt305x.h"
69 #include <dev/ofw/openfirm.h>
70 #include <dev/ofw/ofw_bus.h>
71 #include <dev/ofw/ofw_bus_subr.h>
74 #include <dev/mii/mii.h>
75 #include <dev/mii/miivar.h>
78 #include <dev/mdio/mdio.h>
79 #include <dev/etherswitch/miiproxy.h>
84 #include <mips/rt305x/rt305x_sysctlvar.h>
85 #include <mips/rt305x/rt305xreg.h>
88 #ifdef IF_RT_PHY_SUPPORT
89 #include "miibus_if.h"
95 #define RT_MAX_AGG_SIZE 3840
97 #define RT_TX_DATA_SEG0_SIZE MJUMPAGESIZE
99 #define RT_MS(_v, _f) (((_v) & _f) >> _f##_S)
100 #define RT_SM(_v, _f) (((_v) << _f##_S) & _f)
102 #define RT_TX_WATCHDOG_TIMEOUT 5
104 #define RT_CHIPID_RT2880 0x2880
105 #define RT_CHIPID_RT3050 0x3050
106 #define RT_CHIPID_RT3883 0x3883
107 #define RT_CHIPID_RT5350 0x5350
108 #define RT_CHIPID_MT7620 0x7620
109 #define RT_CHIPID_MT7621 0x7621
112 /* more specific and new models should go first */
113 static const struct ofw_compat_data rt_compat_data[] = {
114 { "ralink,rt2880-eth", RT_CHIPID_RT2880 },
115 { "ralink,rt3050-eth", RT_CHIPID_RT3050 },
116 { "ralink,rt3352-eth", RT_CHIPID_RT3050 },
117 { "ralink,rt3883-eth", RT_CHIPID_RT3883 },
118 { "ralink,rt5350-eth", RT_CHIPID_RT5350 },
119 { "ralink,mt7620a-eth", RT_CHIPID_MT7620 },
120 { "mediatek,mt7620-eth", RT_CHIPID_MT7620 },
121 { "ralink,mt7621-eth", RT_CHIPID_MT7621 },
122 { "mediatek,mt7621-eth", RT_CHIPID_MT7621 },
128 * Static function prototypes
130 static int rt_probe(device_t dev);
131 static int rt_attach(device_t dev);
132 static int rt_detach(device_t dev);
133 static int rt_shutdown(device_t dev);
134 static int rt_suspend(device_t dev);
135 static int rt_resume(device_t dev);
136 static void rt_init_locked(void *priv);
137 static void rt_init(void *priv);
138 static void rt_stop_locked(void *priv);
139 static void rt_stop(void *priv);
140 static void rt_start(struct ifnet *ifp);
141 static int rt_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
142 static void rt_tx_watchdog(void *arg);
143 static void rt_intr(void *arg);
144 static void rt_rt5350_intr(void *arg);
145 static void rt_tx_coherent_intr(struct rt_softc *sc);
146 static void rt_rx_coherent_intr(struct rt_softc *sc);
147 static void rt_rx_delay_intr(struct rt_softc *sc);
148 static void rt_tx_delay_intr(struct rt_softc *sc);
149 static void rt_rx_intr(struct rt_softc *sc, int qid);
150 static void rt_tx_intr(struct rt_softc *sc, int qid);
151 static void rt_rx_done_task(void *context, int pending);
152 static void rt_tx_done_task(void *context, int pending);
153 static void rt_periodic_task(void *context, int pending);
154 static int rt_rx_eof(struct rt_softc *sc,
155 struct rt_softc_rx_ring *ring, int limit);
156 static void rt_tx_eof(struct rt_softc *sc,
157 struct rt_softc_tx_ring *ring);
158 static void rt_update_stats(struct rt_softc *sc);
159 static void rt_watchdog(struct rt_softc *sc);
160 static void rt_update_raw_counters(struct rt_softc *sc);
161 static void rt_intr_enable(struct rt_softc *sc, uint32_t intr_mask);
162 static void rt_intr_disable(struct rt_softc *sc, uint32_t intr_mask);
163 static int rt_txrx_enable(struct rt_softc *sc);
164 static int rt_alloc_rx_ring(struct rt_softc *sc,
165 struct rt_softc_rx_ring *ring, int qid);
166 static void rt_reset_rx_ring(struct rt_softc *sc,
167 struct rt_softc_rx_ring *ring);
168 static void rt_free_rx_ring(struct rt_softc *sc,
169 struct rt_softc_rx_ring *ring);
170 static int rt_alloc_tx_ring(struct rt_softc *sc,
171 struct rt_softc_tx_ring *ring, int qid);
172 static void rt_reset_tx_ring(struct rt_softc *sc,
173 struct rt_softc_tx_ring *ring);
174 static void rt_free_tx_ring(struct rt_softc *sc,
175 struct rt_softc_tx_ring *ring);
176 static void rt_dma_map_addr(void *arg, bus_dma_segment_t *segs,
177 int nseg, int error);
178 static void rt_sysctl_attach(struct rt_softc *sc);
179 #ifdef IF_RT_PHY_SUPPORT
180 void rt_miibus_statchg(device_t);
182 #if defined(IF_RT_PHY_SUPPORT) || defined(RT_MDIO)
183 static int rt_miibus_readreg(device_t, int, int);
184 static int rt_miibus_writereg(device_t, int, int, int);
186 static int rt_ifmedia_upd(struct ifnet *);
187 static void rt_ifmedia_sts(struct ifnet *, struct ifmediareq *);
189 static SYSCTL_NODE(_hw, OID_AUTO, rt, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
190 "RT driver parameters");
192 static int rt_debug = 0;
193 SYSCTL_INT(_hw_rt, OID_AUTO, debug, CTLFLAG_RWTUN, &rt_debug, 0,
198 rt_probe(device_t dev)
200 struct rt_softc *sc = device_get_softc(dev);
203 const struct ofw_compat_data * cd;
205 cd = ofw_bus_search_compatible(dev, rt_compat_data);
206 if (cd->ocd_data == 0)
209 sc->rt_chipid = (unsigned int)(cd->ocd_data);
212 sc->rt_chipid = RT_CHIPID_MT7620;
213 #elif defined(MT7621)
214 sc->rt_chipid = RT_CHIPID_MT7621;
215 #elif defined(RT5350)
216 sc->rt_chipid = RT_CHIPID_RT5350;
218 sc->rt_chipid = RT_CHIPID_RT3050;
221 snprintf(buf, sizeof(buf), "Ralink %cT%x onChip Ethernet driver",
222 sc->rt_chipid >= 0x7600 ? 'M' : 'R', sc->rt_chipid);
223 device_set_desc_copy(dev, buf);
224 return (BUS_PROBE_GENERIC);
228 * macaddr_atoi - translate string MAC address to uint8_t array
231 macaddr_atoi(const char *str, uint8_t *mac)
234 unsigned int amac[ETHER_ADDR_LEN]; /* Aligned version */
236 count = sscanf(str, "%x%*c%x%*c%x%*c%x%*c%x%*c%x",
237 &amac[0], &amac[1], &amac[2],
238 &amac[3], &amac[4], &amac[5]);
239 if (count < ETHER_ADDR_LEN) {
240 memset(mac, 0, ETHER_ADDR_LEN);
244 /* Copy aligned to result */
245 for (i = 0; i < ETHER_ADDR_LEN; i ++)
246 mac[i] = (amac[i] & 0xff);
251 #ifdef USE_GENERATED_MAC_ADDRESS
253 * generate_mac(uin8_t *mac)
254 * This is MAC address generator for cases when real device MAC address
255 * unknown or not yet accessible.
256 * Use 'b','s','d' signature and 3 octets from CRC32 on kenv.
257 * MAC = 'b', 's', 'd', CRC[3]^CRC[2], CRC[1], CRC[0]
259 * Output - MAC address, that do not change between reboots, if hints or
260 * bootloader info unchange.
263 generate_mac(uint8_t *mac)
267 uint32_t crc = 0xffffffff;
269 /* Generate CRC32 on kenv */
270 for (cp = kenvp[0]; cp != NULL; cp = kenvp[++i]) {
271 crc = calculate_crc32c(crc, cp, strlen(cp) + 1);
278 mac[3] = (crc >> 24) ^ ((crc >> 16) & 0xff);
279 mac[4] = (crc >> 8) & 0xff;
285 * ether_request_mac - try to find usable MAC address.
288 ether_request_mac(device_t dev, uint8_t *mac)
293 * "ethaddr" is passed via envp on RedBoot platforms
294 * "kmac" is passed via argv on RouterBOOT platforms
296 #if defined(RT305X_UBOOT) || defined(__REDBOOT__) || defined(__ROUTERBOOT__)
297 if ((var = kern_getenv("ethaddr")) != NULL ||
298 (var = kern_getenv("kmac")) != NULL ) {
299 if(!macaddr_atoi(var, mac)) {
300 printf("%s: use %s macaddr from KENV\n",
301 device_get_nameunit(dev), var);
311 * hint.[dev].[unit].macaddr
313 if (!resource_string_value(device_get_name(dev),
314 device_get_unit(dev), "macaddr", &var)) {
315 if(!macaddr_atoi(var, mac)) {
316 printf("%s: use %s macaddr from hints\n",
317 device_get_nameunit(dev), var);
322 #ifdef USE_GENERATED_MAC_ADDRESS
325 device_printf(dev, "use generated %02x:%02x:%02x:%02x:%02x:%02x "
326 "macaddr\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
336 device_printf(dev, "use hardcoded 00:18:e7:d5:83:90 macaddr\n");
346 reset_freng(struct rt_softc *sc)
348 /* XXX hard reset kills everything so skip it ... */
353 rt_attach(device_t dev)
363 sc = device_get_softc(dev);
367 node = ofw_bus_get_node(sc->dev);
370 mtx_init(&sc->lock, device_get_nameunit(dev), MTX_NETWORK_LOCK,
371 MTX_DEF | MTX_RECURSE);
374 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
375 RF_ACTIVE | RF_SHAREABLE);
376 if (sc->mem == NULL) {
377 device_printf(dev, "could not allocate memory resource\n");
382 sc->bst = rman_get_bustag(sc->mem);
383 sc->bsh = rman_get_bushandle(sc->mem);
386 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
388 if (sc->irq == NULL) {
390 "could not allocate interrupt resource\n");
396 sc->debug = rt_debug;
398 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
399 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
400 "debug", CTLFLAG_RW, &sc->debug, 0, "rt debug level");
406 if (sc->rt_chipid == RT_CHIPID_MT7620) {
407 sc->csum_fail_ip = MT7620_RXD_SRC_IP_CSUM_FAIL;
408 sc->csum_fail_l4 = MT7620_RXD_SRC_L4_CSUM_FAIL;
409 } else if (sc->rt_chipid == RT_CHIPID_MT7621) {
410 sc->csum_fail_ip = MT7621_RXD_SRC_IP_CSUM_FAIL;
411 sc->csum_fail_l4 = MT7621_RXD_SRC_L4_CSUM_FAIL;
413 sc->csum_fail_ip = RT305X_RXD_SRC_IP_CSUM_FAIL;
414 sc->csum_fail_l4 = RT305X_RXD_SRC_L4_CSUM_FAIL;
417 /* Fill in soc-specific registers map */
418 switch(sc->rt_chipid) {
419 case RT_CHIPID_MT7620:
420 case RT_CHIPID_MT7621:
421 sc->gdma1_base = MT7620_GDMA1_BASE;
423 case RT_CHIPID_RT5350:
424 device_printf(dev, "%cT%x Ethernet MAC (rev 0x%08x)\n",
425 sc->rt_chipid >= 0x7600 ? 'M' : 'R',
426 sc->rt_chipid, sc->mac_rev);
427 /* RT5350: No GDMA, PSE, CDMA, PPE */
428 RT_WRITE(sc, GE_PORT_BASE + 0x0C00, // UDPCS, TCPCS, IPCS=1
429 RT_READ(sc, GE_PORT_BASE + 0x0C00) | (0x7<<16));
430 sc->delay_int_cfg=RT5350_PDMA_BASE+RT5350_DELAY_INT_CFG;
431 sc->fe_int_status=RT5350_FE_INT_STATUS;
432 sc->fe_int_enable=RT5350_FE_INT_ENABLE;
433 sc->pdma_glo_cfg=RT5350_PDMA_BASE+RT5350_PDMA_GLO_CFG;
434 sc->pdma_rst_idx=RT5350_PDMA_BASE+RT5350_PDMA_RST_IDX;
435 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
436 sc->tx_base_ptr[i]=RT5350_PDMA_BASE+RT5350_TX_BASE_PTR(i);
437 sc->tx_max_cnt[i]=RT5350_PDMA_BASE+RT5350_TX_MAX_CNT(i);
438 sc->tx_ctx_idx[i]=RT5350_PDMA_BASE+RT5350_TX_CTX_IDX(i);
439 sc->tx_dtx_idx[i]=RT5350_PDMA_BASE+RT5350_TX_DTX_IDX(i);
442 sc->rx_base_ptr[0]=RT5350_PDMA_BASE+RT5350_RX_BASE_PTR0;
443 sc->rx_max_cnt[0]=RT5350_PDMA_BASE+RT5350_RX_MAX_CNT0;
444 sc->rx_calc_idx[0]=RT5350_PDMA_BASE+RT5350_RX_CALC_IDX0;
445 sc->rx_drx_idx[0]=RT5350_PDMA_BASE+RT5350_RX_DRX_IDX0;
446 sc->rx_base_ptr[1]=RT5350_PDMA_BASE+RT5350_RX_BASE_PTR1;
447 sc->rx_max_cnt[1]=RT5350_PDMA_BASE+RT5350_RX_MAX_CNT1;
448 sc->rx_calc_idx[1]=RT5350_PDMA_BASE+RT5350_RX_CALC_IDX1;
449 sc->rx_drx_idx[1]=RT5350_PDMA_BASE+RT5350_RX_DRX_IDX1;
450 sc->int_rx_done_mask=RT5350_INT_RXQ0_DONE;
451 sc->int_tx_done_mask=RT5350_INT_TXQ0_DONE;
454 device_printf(dev, "RT305XF Ethernet MAC (rev 0x%08x)\n",
456 sc->gdma1_base = GDMA1_BASE;
457 sc->delay_int_cfg=PDMA_BASE+DELAY_INT_CFG;
458 sc->fe_int_status=GE_PORT_BASE+FE_INT_STATUS;
459 sc->fe_int_enable=GE_PORT_BASE+FE_INT_ENABLE;
460 sc->pdma_glo_cfg=PDMA_BASE+PDMA_GLO_CFG;
461 sc->pdma_rst_idx=PDMA_BASE+PDMA_RST_IDX;
462 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
463 sc->tx_base_ptr[i]=PDMA_BASE+TX_BASE_PTR(i);
464 sc->tx_max_cnt[i]=PDMA_BASE+TX_MAX_CNT(i);
465 sc->tx_ctx_idx[i]=PDMA_BASE+TX_CTX_IDX(i);
466 sc->tx_dtx_idx[i]=PDMA_BASE+TX_DTX_IDX(i);
469 sc->rx_base_ptr[0]=PDMA_BASE+RX_BASE_PTR0;
470 sc->rx_max_cnt[0]=PDMA_BASE+RX_MAX_CNT0;
471 sc->rx_calc_idx[0]=PDMA_BASE+RX_CALC_IDX0;
472 sc->rx_drx_idx[0]=PDMA_BASE+RX_DRX_IDX0;
473 sc->int_rx_done_mask=INT_RX_DONE;
474 sc->int_tx_done_mask=INT_TXQ0_DONE;
477 if (sc->gdma1_base != 0)
478 RT_WRITE(sc, sc->gdma1_base + GDMA_FWD_CFG,
480 GDM_ICS_EN | /* Enable IP Csum */
481 GDM_TCS_EN | /* Enable TCP Csum */
482 GDM_UCS_EN | /* Enable UDP Csum */
483 GDM_STRPCRC | /* Strip CRC from packet */
484 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* fwd UCast to CPU */
485 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* fwd BCast to CPU */
486 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* fwd MCast to CPU */
487 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* fwd Other to CPU */
491 if (sc->rt_chipid == RT_CHIPID_RT2880 ||
492 sc->rt_chipid == RT_CHIPID_RT3883) {
493 if (OF_getprop(node, "port-mode", fdtval, sizeof(fdtval)) > 0 &&
494 strcmp(fdtval, "gigasw") == 0)
495 RT_WRITE(sc, MDIO_CFG, MDIO_2880_GIGA_INIT);
497 RT_WRITE(sc, MDIO_CFG, MDIO_2880_100T_INIT);
501 /* allocate Tx and Rx rings */
502 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
503 error = rt_alloc_tx_ring(sc, &sc->tx_ring[i], i);
505 device_printf(dev, "could not allocate Tx ring #%d\n",
511 sc->tx_ring_mgtqid = 5;
512 for (i = 0; i < sc->rx_ring_count; i++) {
513 error = rt_alloc_rx_ring(sc, &sc->rx_ring[i], i);
515 device_printf(dev, "could not allocate Rx ring\n");
520 callout_init_mtx(&sc->tx_watchdog_ch, &sc->lock, 0);
522 ifp = sc->ifp = if_alloc(IFT_ETHER);
524 device_printf(dev, "could not if_alloc()\n");
530 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
531 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
532 ifp->if_init = rt_init;
533 ifp->if_ioctl = rt_ioctl;
534 ifp->if_start = rt_start;
535 #define RT_TX_QLEN 256
537 IFQ_SET_MAXLEN(&ifp->if_snd, RT_TX_QLEN);
538 ifp->if_snd.ifq_drv_maxlen = RT_TX_QLEN;
539 IFQ_SET_READY(&ifp->if_snd);
541 #ifdef IF_RT_PHY_SUPPORT
542 error = mii_attach(dev, &sc->rt_miibus, ifp, rt_ifmedia_upd,
543 rt_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
545 device_printf(dev, "attaching PHYs failed\n");
550 ifmedia_init(&sc->rt_ifmedia, 0, rt_ifmedia_upd, rt_ifmedia_sts);
551 ifmedia_add(&sc->rt_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0,
553 ifmedia_set(&sc->rt_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX);
555 #endif /* IF_RT_PHY_SUPPORT */
557 ether_request_mac(dev, sc->mac_addr);
558 ether_ifattach(ifp, sc->mac_addr);
561 * Tell the upper layer(s) we support long frames.
563 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
564 ifp->if_capabilities |= IFCAP_VLAN_MTU;
565 ifp->if_capenable |= IFCAP_VLAN_MTU;
566 ifp->if_capabilities |= IFCAP_RXCSUM|IFCAP_TXCSUM;
567 ifp->if_capenable |= IFCAP_RXCSUM|IFCAP_TXCSUM;
569 /* init task queue */
570 NET_TASK_INIT(&sc->rx_done_task, 0, rt_rx_done_task, sc);
571 TASK_INIT(&sc->tx_done_task, 0, rt_tx_done_task, sc);
573 sc->rx_process_limit = 100;
575 sc->taskqueue = taskqueue_create("rt_taskq", M_NOWAIT,
576 taskqueue_thread_enqueue, &sc->taskqueue);
578 taskqueue_start_threads(&sc->taskqueue, 1, PI_NET, "%s taskq",
579 device_get_nameunit(sc->dev));
581 TIMEOUT_TASK_INIT(sc->taskqueue, &sc->periodic_task, 0,
582 rt_periodic_task, sc);
584 rt_sysctl_attach(sc);
586 /* set up interrupt */
587 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
588 NULL, (sc->rt_chipid == RT_CHIPID_RT5350 ||
589 sc->rt_chipid == RT_CHIPID_MT7620 ||
590 sc->rt_chipid == RT_CHIPID_MT7621) ? rt_rt5350_intr : rt_intr,
593 printf("%s: could not set up interrupt\n",
594 device_get_nameunit(dev));
598 device_printf(dev, "debug var at %#08x\n", (u_int)&(sc->debug));
604 /* free Tx and Rx rings */
605 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
606 rt_free_tx_ring(sc, &sc->tx_ring[i]);
608 for (i = 0; i < sc->rx_ring_count; i++)
609 rt_free_rx_ring(sc, &sc->rx_ring[i]);
611 mtx_destroy(&sc->lock);
614 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
618 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
628 rt_ifmedia_upd(struct ifnet *ifp)
631 #ifdef IF_RT_PHY_SUPPORT
632 struct mii_data *mii;
633 struct mii_softc *miisc;
639 mii = device_get_softc(sc->rt_miibus);
640 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
642 error = mii_mediachg(mii);
647 #else /* !IF_RT_PHY_SUPPORT */
650 struct ifmedia_entry *ife;
653 ifm = &sc->rt_ifmedia;
656 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
659 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
660 device_printf(sc->dev,
661 "AUTO is not supported for multiphy MAC");
669 #endif /* IF_RT_PHY_SUPPORT */
673 * Report current media status.
676 rt_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
678 #ifdef IF_RT_PHY_SUPPORT
680 struct mii_data *mii;
685 mii = device_get_softc(sc->rt_miibus);
687 ifmr->ifm_active = mii->mii_media_active;
688 ifmr->ifm_status = mii->mii_media_status;
689 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
690 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
692 #else /* !IF_RT_PHY_SUPPORT */
694 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
695 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
696 #endif /* IF_RT_PHY_SUPPORT */
700 rt_detach(device_t dev)
706 sc = device_get_softc(dev);
709 RT_DPRINTF(sc, RT_DEBUG_ANY, "detaching\n");
712 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
713 callout_stop(&sc->tx_watchdog_ch);
716 taskqueue_drain(sc->taskqueue, &sc->rx_done_task);
717 taskqueue_drain(sc->taskqueue, &sc->tx_done_task);
718 taskqueue_drain_timeout(sc->taskqueue, &sc->periodic_task);
720 /* free Tx and Rx rings */
722 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
723 rt_free_tx_ring(sc, &sc->tx_ring[i]);
724 for (i = 0; i < sc->rx_ring_count; i++)
725 rt_free_rx_ring(sc, &sc->rx_ring[i]);
728 #ifdef IF_RT_PHY_SUPPORT
729 if (sc->rt_miibus != NULL)
730 device_delete_child(dev, sc->rt_miibus);
736 taskqueue_free(sc->taskqueue);
738 mtx_destroy(&sc->lock);
740 bus_generic_detach(dev);
741 bus_teardown_intr(dev, sc->irq, sc->irqh);
742 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq);
743 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem);
749 rt_shutdown(device_t dev)
753 sc = device_get_softc(dev);
754 RT_DPRINTF(sc, RT_DEBUG_ANY, "shutting down\n");
761 rt_suspend(device_t dev)
765 sc = device_get_softc(dev);
766 RT_DPRINTF(sc, RT_DEBUG_ANY, "suspending\n");
773 rt_resume(device_t dev)
778 sc = device_get_softc(dev);
781 RT_DPRINTF(sc, RT_DEBUG_ANY, "resuming\n");
783 if (ifp->if_flags & IFF_UP)
790 * rt_init_locked - Run initialization process having locked mtx.
793 rt_init_locked(void *priv)
797 #ifdef IF_RT_PHY_SUPPORT
798 struct mii_data *mii;
805 #ifdef IF_RT_PHY_SUPPORT
806 mii = device_get_softc(sc->rt_miibus);
809 RT_DPRINTF(sc, RT_DEBUG_ANY, "initializing\n");
811 RT_SOFTC_ASSERT_LOCKED(sc);
814 //RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET);
815 //rt305x_sysctl_set(SYSCTL_RSTCTRL, SYSCTL_RSTCTRL_FRENG);
817 /* Fwd to CPU (uni|broad|multi)cast and Unknown */
818 if (sc->gdma1_base != 0)
819 RT_WRITE(sc, sc->gdma1_base + GDMA_FWD_CFG,
821 GDM_ICS_EN | /* Enable IP Csum */
822 GDM_TCS_EN | /* Enable TCP Csum */
823 GDM_UCS_EN | /* Enable UDP Csum */
824 GDM_STRPCRC | /* Strip CRC from packet */
825 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* fwd UCast to CPU */
826 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* fwd BCast to CPU */
827 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* fwd MCast to CPU */
828 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* fwd Other to CPU */
831 /* disable DMA engine */
832 RT_WRITE(sc, sc->pdma_glo_cfg, 0);
833 RT_WRITE(sc, sc->pdma_rst_idx, 0xffffffff);
835 /* wait while DMA engine is busy */
836 for (ntries = 0; ntries < 100; ntries++) {
837 tmp = RT_READ(sc, sc->pdma_glo_cfg);
838 if (!(tmp & (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)))
844 device_printf(sc->dev, "timeout waiting for DMA engine\n");
848 /* reset Rx and Tx rings */
849 tmp = FE_RST_DRX_IDX0 |
855 RT_WRITE(sc, sc->pdma_rst_idx, tmp);
857 /* XXX switch set mac address */
858 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
859 rt_reset_tx_ring(sc, &sc->tx_ring[i]);
861 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
862 /* update TX_BASE_PTRx */
863 RT_WRITE(sc, sc->tx_base_ptr[i],
864 sc->tx_ring[i].desc_phys_addr);
865 RT_WRITE(sc, sc->tx_max_cnt[i],
866 RT_SOFTC_TX_RING_DESC_COUNT);
867 RT_WRITE(sc, sc->tx_ctx_idx[i], 0);
871 for (i = 0; i < sc->rx_ring_count; i++)
872 rt_reset_rx_ring(sc, &sc->rx_ring[i]);
874 /* update RX_BASE_PTRx */
875 for (i = 0; i < sc->rx_ring_count; i++) {
876 RT_WRITE(sc, sc->rx_base_ptr[i],
877 sc->rx_ring[i].desc_phys_addr);
878 RT_WRITE(sc, sc->rx_max_cnt[i],
879 RT_SOFTC_RX_RING_DATA_COUNT);
880 RT_WRITE(sc, sc->rx_calc_idx[i],
881 RT_SOFTC_RX_RING_DATA_COUNT - 1);
884 /* write back DDONE, 16byte burst enable RX/TX DMA */
885 tmp = FE_TX_WB_DDONE | FE_DMA_BT_SIZE16 | FE_RX_DMA_EN | FE_TX_DMA_EN;
886 if (sc->rt_chipid == RT_CHIPID_MT7620 ||
887 sc->rt_chipid == RT_CHIPID_MT7621)
889 RT_WRITE(sc, sc->pdma_glo_cfg, tmp);
891 /* disable interrupts mitigation */
892 RT_WRITE(sc, sc->delay_int_cfg, 0);
894 /* clear pending interrupts */
895 RT_WRITE(sc, sc->fe_int_status, 0xffffffff);
897 /* enable interrupts */
898 if (sc->rt_chipid == RT_CHIPID_RT5350 ||
899 sc->rt_chipid == RT_CHIPID_MT7620 ||
900 sc->rt_chipid == RT_CHIPID_MT7621)
901 tmp = RT5350_INT_TX_COHERENT |
902 RT5350_INT_RX_COHERENT |
903 RT5350_INT_TXQ3_DONE |
904 RT5350_INT_TXQ2_DONE |
905 RT5350_INT_TXQ1_DONE |
906 RT5350_INT_TXQ0_DONE |
907 RT5350_INT_RXQ1_DONE |
908 RT5350_INT_RXQ0_DONE;
927 sc->intr_enable_mask = tmp;
929 RT_WRITE(sc, sc->fe_int_enable, tmp);
931 if (rt_txrx_enable(sc) != 0)
934 #ifdef IF_RT_PHY_SUPPORT
935 if (mii) mii_mediachg(mii);
936 #endif /* IF_RT_PHY_SUPPORT */
938 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
939 ifp->if_drv_flags |= IFF_DRV_RUNNING;
941 sc->periodic_round = 0;
943 taskqueue_enqueue_timeout(sc->taskqueue, &sc->periodic_task, hz / 10);
952 * rt_init - lock and initialize device.
966 * rt_stop_locked - stop TX/RX w/ lock
969 rt_stop_locked(void *priv)
977 RT_DPRINTF(sc, RT_DEBUG_ANY, "stopping\n");
979 RT_SOFTC_ASSERT_LOCKED(sc);
981 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
982 callout_stop(&sc->tx_watchdog_ch);
984 taskqueue_block(sc->taskqueue);
987 * Sometime rt_stop_locked called from isr and we get panic
988 * When found, I fix it
991 taskqueue_drain(sc->taskqueue, &sc->rx_done_task);
992 taskqueue_drain(sc->taskqueue, &sc->tx_done_task);
993 taskqueue_drain_timeout(sc->taskqueue, &sc->periodic_task);
995 taskqueue_cancel_timeout(sc->taskqueue, &sc->periodic_task, NULL);
999 /* disable interrupts */
1000 RT_WRITE(sc, sc->fe_int_enable, 0);
1002 if(sc->rt_chipid != RT_CHIPID_RT5350 &&
1003 sc->rt_chipid != RT_CHIPID_MT7620 &&
1004 sc->rt_chipid != RT_CHIPID_MT7621) {
1006 RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET);
1009 if (sc->gdma1_base != 0)
1010 RT_WRITE(sc, sc->gdma1_base + GDMA_FWD_CFG,
1012 GDM_ICS_EN | /* Enable IP Csum */
1013 GDM_TCS_EN | /* Enable TCP Csum */
1014 GDM_UCS_EN | /* Enable UDP Csum */
1015 GDM_STRPCRC | /* Strip CRC from packet */
1016 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* fwd UCast to CPU */
1017 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* fwd BCast to CPU */
1018 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* fwd MCast to CPU */
1019 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* fwd Other to CPU */
1026 struct rt_softc *sc;
1031 RT_SOFTC_UNLOCK(sc);
1035 * rt_tx_data - transmit packet.
1038 rt_tx_data(struct rt_softc *sc, struct mbuf *m, int qid)
1041 struct rt_softc_tx_ring *ring;
1042 struct rt_softc_tx_data *data;
1043 struct rt_txdesc *desc;
1045 bus_dma_segment_t dma_seg[RT_SOFTC_MAX_SCATTER];
1046 int error, ndmasegs, ndescs, i;
1048 KASSERT(qid >= 0 && qid < RT_SOFTC_TX_RING_COUNT,
1049 ("%s: Tx data: invalid qid=%d\n",
1050 device_get_nameunit(sc->dev), qid));
1052 RT_SOFTC_TX_RING_ASSERT_LOCKED(&sc->tx_ring[qid]);
1055 ring = &sc->tx_ring[qid];
1056 desc = &ring->desc[ring->desc_cur];
1057 data = &ring->data[ring->data_cur];
1059 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag, data->dma_map, m,
1060 dma_seg, &ndmasegs, 0);
1062 /* too many fragments, linearize */
1064 RT_DPRINTF(sc, RT_DEBUG_TX,
1065 "could not load mbuf DMA map, trying to linearize "
1066 "mbuf: ndmasegs=%d, len=%d, error=%d\n",
1067 ndmasegs, m->m_pkthdr.len, error);
1069 m_d = m_collapse(m, M_NOWAIT, 16);
1077 sc->tx_defrag_packets++;
1079 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag,
1080 data->dma_map, m, dma_seg, &ndmasegs, 0);
1082 device_printf(sc->dev, "could not load mbuf DMA map: "
1083 "ndmasegs=%d, len=%d, error=%d\n",
1084 ndmasegs, m->m_pkthdr.len, error);
1090 if (m->m_pkthdr.len == 0)
1093 /* determine how many Tx descs are required */
1094 ndescs = 1 + ndmasegs / 2;
1095 if ((ring->desc_queued + ndescs) >
1096 (RT_SOFTC_TX_RING_DESC_COUNT - 2)) {
1097 RT_DPRINTF(sc, RT_DEBUG_TX,
1098 "there are not enough Tx descs\n");
1100 sc->no_tx_desc_avail++;
1102 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
1109 /* set up Tx descs */
1110 for (i = 0; i < ndmasegs; i += 2) {
1111 /* TODO: this needs to be refined as MT7620 for example has
1112 * a different word3 layout than RT305x and RT5350 (the last
1113 * one doesn't use word3 at all). And so does MT7621...
1116 if (sc->rt_chipid != RT_CHIPID_MT7621) {
1117 /* Set destination */
1118 if (sc->rt_chipid != RT_CHIPID_MT7620)
1119 desc->dst = (TXDSCR_DST_PORT_GDMA1);
1121 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1122 desc->dst |= (TXDSCR_IP_CSUM_GEN |
1123 TXDSCR_UDP_CSUM_GEN | TXDSCR_TCP_CSUM_GEN);
1137 desc->sdp0 = htole32(dma_seg[i].ds_addr);
1138 desc->sdl0 = htole16(dma_seg[i].ds_len |
1139 ( ((i+1) == ndmasegs )?RT_TXDESC_SDL0_LASTSEG:0 ));
1141 if ((i+1) < ndmasegs) {
1142 desc->sdp1 = htole32(dma_seg[i+1].ds_addr);
1143 desc->sdl1 = htole16(dma_seg[i+1].ds_len |
1144 ( ((i+2) == ndmasegs )?RT_TXDESC_SDL1_LASTSEG:0 ));
1150 if ((i+2) < ndmasegs) {
1151 ring->desc_queued++;
1152 ring->desc_cur = (ring->desc_cur + 1) %
1153 RT_SOFTC_TX_RING_DESC_COUNT;
1155 desc = &ring->desc[ring->desc_cur];
1158 RT_DPRINTF(sc, RT_DEBUG_TX, "sending data: len=%d, ndmasegs=%d, "
1159 "DMA ds_len=%d/%d/%d/%d/%d\n",
1160 m->m_pkthdr.len, ndmasegs,
1161 (int) dma_seg[0].ds_len,
1162 (int) dma_seg[1].ds_len,
1163 (int) dma_seg[2].ds_len,
1164 (int) dma_seg[3].ds_len,
1165 (int) dma_seg[4].ds_len);
1167 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map,
1168 BUS_DMASYNC_PREWRITE);
1169 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
1170 BUS_DMASYNC_PREWRITE);
1171 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
1172 BUS_DMASYNC_PREWRITE);
1174 ring->desc_queued++;
1175 ring->desc_cur = (ring->desc_cur + 1) % RT_SOFTC_TX_RING_DESC_COUNT;
1177 ring->data_queued++;
1178 ring->data_cur = (ring->data_cur + 1) % RT_SOFTC_TX_RING_DATA_COUNT;
1181 RT_WRITE(sc, sc->tx_ctx_idx[qid], ring->desc_cur);
1187 * rt_start - start Transmit/Receive
1190 rt_start(struct ifnet *ifp)
1192 struct rt_softc *sc;
1194 int qid = 0 /* XXX must check QoS priority */;
1198 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1202 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1206 m->m_pkthdr.rcvif = NULL;
1208 RT_SOFTC_TX_RING_LOCK(&sc->tx_ring[qid]);
1210 if (sc->tx_ring[qid].data_queued >=
1211 RT_SOFTC_TX_RING_DATA_COUNT) {
1212 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]);
1214 RT_DPRINTF(sc, RT_DEBUG_TX,
1215 "if_start: Tx ring with qid=%d is full\n", qid);
1219 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1220 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1222 sc->tx_data_queue_full[qid]++;
1227 if (rt_tx_data(sc, m, qid) != 0) {
1228 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]);
1230 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1235 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]);
1236 sc->tx_timer = RT_TX_WATCHDOG_TIMEOUT;
1237 callout_reset(&sc->tx_watchdog_ch, hz, rt_tx_watchdog, sc);
1242 * rt_update_promisc - set/clear promiscuous mode. Unused yet, because
1243 * filtering done by attached Ethernet switch.
1246 rt_update_promisc(struct ifnet *ifp)
1248 struct rt_softc *sc;
1251 printf("%s: %s promiscuous mode\n",
1252 device_get_nameunit(sc->dev),
1253 (ifp->if_flags & IFF_PROMISC) ? "entering" : "leaving");
1257 * rt_ioctl - ioctl handler.
1260 rt_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1262 struct rt_softc *sc;
1264 #ifdef IF_RT_PHY_SUPPORT
1265 struct mii_data *mii;
1266 #endif /* IF_RT_PHY_SUPPORT */
1267 int error, startall;
1270 ifr = (struct ifreq *) data;
1278 if (ifp->if_flags & IFF_UP) {
1279 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1280 if ((ifp->if_flags ^ sc->if_flags) &
1282 rt_update_promisc(ifp);
1288 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1291 sc->if_flags = ifp->if_flags;
1292 RT_SOFTC_UNLOCK(sc);
1296 #ifdef IF_RT_PHY_SUPPORT
1297 mii = device_get_softc(sc->rt_miibus);
1298 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1300 error = ifmedia_ioctl(ifp, ifr, &sc->rt_ifmedia, cmd);
1301 #endif /* IF_RT_PHY_SUPPORT */
1304 error = ether_ioctl(ifp, cmd, data);
1311 * rt_tx_watchdog - Handler of TX Watchdog
1314 rt_tx_watchdog(void *arg)
1316 struct rt_softc *sc;
1322 if (sc->tx_timer == 0)
1325 if (--sc->tx_timer == 0) {
1326 device_printf(sc->dev, "Tx watchdog timeout: resetting\n");
1329 * XXX: Commented out, because reset break input.
1334 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1335 sc->tx_watchdog_timeouts++;
1337 callout_reset(&sc->tx_watchdog_ch, hz, rt_tx_watchdog, sc);
1341 * rt_cnt_ppe_af - Handler of PPE Counter Table Almost Full interrupt
1344 rt_cnt_ppe_af(struct rt_softc *sc)
1347 RT_DPRINTF(sc, RT_DEBUG_INTR, "PPE Counter Table Almost Full\n");
1351 * rt_cnt_gdm_af - Handler of GDMA 1 & 2 Counter Table Almost Full interrupt
1354 rt_cnt_gdm_af(struct rt_softc *sc)
1357 RT_DPRINTF(sc, RT_DEBUG_INTR,
1358 "GDMA 1 & 2 Counter Table Almost Full\n");
1362 * rt_pse_p2_fc - Handler of PSE port2 (GDMA 2) flow control interrupt
1365 rt_pse_p2_fc(struct rt_softc *sc)
1368 RT_DPRINTF(sc, RT_DEBUG_INTR,
1369 "PSE port2 (GDMA 2) flow control asserted.\n");
1373 * rt_gdm_crc_drop - Handler of GDMA 1/2 discard a packet due to CRC error
1377 rt_gdm_crc_drop(struct rt_softc *sc)
1380 RT_DPRINTF(sc, RT_DEBUG_INTR,
1381 "GDMA 1 & 2 discard a packet due to CRC error\n");
1385 * rt_pse_buf_drop - Handler of buffer sharing limitation interrupt
1388 rt_pse_buf_drop(struct rt_softc *sc)
1391 RT_DPRINTF(sc, RT_DEBUG_INTR,
1392 "PSE discards a packet due to buffer sharing limitation\n");
1396 * rt_gdm_other_drop - Handler of discard on other reason interrupt
1399 rt_gdm_other_drop(struct rt_softc *sc)
1402 RT_DPRINTF(sc, RT_DEBUG_INTR,
1403 "GDMA 1 & 2 discard a packet due to other reason\n");
1407 * rt_pse_p1_fc - Handler of PSE port1 (GDMA 1) flow control interrupt
1410 rt_pse_p1_fc(struct rt_softc *sc)
1413 RT_DPRINTF(sc, RT_DEBUG_INTR,
1414 "PSE port1 (GDMA 1) flow control asserted.\n");
1418 * rt_pse_p0_fc - Handler of PSE port0 (CDMA) flow control interrupt
1421 rt_pse_p0_fc(struct rt_softc *sc)
1424 RT_DPRINTF(sc, RT_DEBUG_INTR,
1425 "PSE port0 (CDMA) flow control asserted.\n");
1429 * rt_pse_fq_empty - Handler of PSE free Q empty threshold reached interrupt
1432 rt_pse_fq_empty(struct rt_softc *sc)
1435 RT_DPRINTF(sc, RT_DEBUG_INTR,
1436 "PSE free Q empty threshold reached & forced drop "
1437 "condition occurred.\n");
1441 * rt_intr - main ISR
1446 struct rt_softc *sc;
1453 /* acknowledge interrupts */
1454 status = RT_READ(sc, sc->fe_int_status);
1455 RT_WRITE(sc, sc->fe_int_status, status);
1457 RT_DPRINTF(sc, RT_DEBUG_INTR, "interrupt: status=0x%08x\n", status);
1459 if (status == 0xffffffff || /* device likely went away */
1460 status == 0) /* not for us */
1465 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1468 if (status & CNT_PPE_AF)
1471 if (status & CNT_GDM_AF)
1474 if (status & PSE_P2_FC)
1477 if (status & GDM_CRC_DROP)
1478 rt_gdm_crc_drop(sc);
1480 if (status & PSE_BUF_DROP)
1481 rt_pse_buf_drop(sc);
1483 if (status & GDM_OTHER_DROP)
1484 rt_gdm_other_drop(sc);
1486 if (status & PSE_P1_FC)
1489 if (status & PSE_P0_FC)
1492 if (status & PSE_FQ_EMPTY)
1493 rt_pse_fq_empty(sc);
1495 if (status & INT_TX_COHERENT)
1496 rt_tx_coherent_intr(sc);
1498 if (status & INT_RX_COHERENT)
1499 rt_rx_coherent_intr(sc);
1501 if (status & RX_DLY_INT)
1502 rt_rx_delay_intr(sc);
1504 if (status & TX_DLY_INT)
1505 rt_tx_delay_intr(sc);
1507 if (status & INT_RX_DONE)
1510 if (status & INT_TXQ3_DONE)
1513 if (status & INT_TXQ2_DONE)
1516 if (status & INT_TXQ1_DONE)
1519 if (status & INT_TXQ0_DONE)
1524 * rt_rt5350_intr - main ISR for Ralink 5350 SoC
1527 rt_rt5350_intr(void *arg)
1529 struct rt_softc *sc;
1536 /* acknowledge interrupts */
1537 status = RT_READ(sc, sc->fe_int_status);
1538 RT_WRITE(sc, sc->fe_int_status, status);
1540 RT_DPRINTF(sc, RT_DEBUG_INTR, "interrupt: status=0x%08x\n", status);
1542 if (status == 0xffffffff || /* device likely went away */
1543 status == 0) /* not for us */
1548 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1551 if (status & RT5350_INT_TX_COHERENT)
1552 rt_tx_coherent_intr(sc);
1553 if (status & RT5350_INT_RX_COHERENT)
1554 rt_rx_coherent_intr(sc);
1555 if (status & RT5350_RX_DLY_INT)
1556 rt_rx_delay_intr(sc);
1557 if (status & RT5350_TX_DLY_INT)
1558 rt_tx_delay_intr(sc);
1559 if (status & RT5350_INT_RXQ1_DONE)
1561 if (status & RT5350_INT_RXQ0_DONE)
1563 if (status & RT5350_INT_TXQ3_DONE)
1565 if (status & RT5350_INT_TXQ2_DONE)
1567 if (status & RT5350_INT_TXQ1_DONE)
1569 if (status & RT5350_INT_TXQ0_DONE)
1574 rt_tx_coherent_intr(struct rt_softc *sc)
1579 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx coherent interrupt\n");
1581 sc->tx_coherent_interrupts++;
1583 /* restart DMA engine */
1584 tmp = RT_READ(sc, sc->pdma_glo_cfg);
1585 tmp &= ~(FE_TX_WB_DDONE | FE_TX_DMA_EN);
1586 RT_WRITE(sc, sc->pdma_glo_cfg, tmp);
1588 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
1589 rt_reset_tx_ring(sc, &sc->tx_ring[i]);
1591 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
1592 RT_WRITE(sc, sc->tx_base_ptr[i],
1593 sc->tx_ring[i].desc_phys_addr);
1594 RT_WRITE(sc, sc->tx_max_cnt[i],
1595 RT_SOFTC_TX_RING_DESC_COUNT);
1596 RT_WRITE(sc, sc->tx_ctx_idx[i], 0);
1603 * rt_rx_coherent_intr
1606 rt_rx_coherent_intr(struct rt_softc *sc)
1611 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx coherent interrupt\n");
1613 sc->rx_coherent_interrupts++;
1615 /* restart DMA engine */
1616 tmp = RT_READ(sc, sc->pdma_glo_cfg);
1617 tmp &= ~(FE_RX_DMA_EN);
1618 RT_WRITE(sc, sc->pdma_glo_cfg, tmp);
1621 for (i = 0; i < sc->rx_ring_count; i++)
1622 rt_reset_rx_ring(sc, &sc->rx_ring[i]);
1624 for (i = 0; i < sc->rx_ring_count; i++) {
1625 RT_WRITE(sc, sc->rx_base_ptr[i],
1626 sc->rx_ring[i].desc_phys_addr);
1627 RT_WRITE(sc, sc->rx_max_cnt[i],
1628 RT_SOFTC_RX_RING_DATA_COUNT);
1629 RT_WRITE(sc, sc->rx_calc_idx[i],
1630 RT_SOFTC_RX_RING_DATA_COUNT - 1);
1637 * rt_rx_intr - a packet received
1640 rt_rx_intr(struct rt_softc *sc, int qid)
1642 KASSERT(qid >= 0 && qid < sc->rx_ring_count,
1643 ("%s: Rx interrupt: invalid qid=%d\n",
1644 device_get_nameunit(sc->dev), qid));
1646 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx interrupt\n");
1647 sc->rx_interrupts[qid]++;
1650 if (!(sc->intr_disable_mask & (sc->int_rx_done_mask << qid))) {
1651 rt_intr_disable(sc, (sc->int_rx_done_mask << qid));
1652 taskqueue_enqueue(sc->taskqueue, &sc->rx_done_task);
1655 sc->intr_pending_mask |= (sc->int_rx_done_mask << qid);
1656 RT_SOFTC_UNLOCK(sc);
1660 rt_rx_delay_intr(struct rt_softc *sc)
1663 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx delay interrupt\n");
1664 sc->rx_delay_interrupts++;
1668 rt_tx_delay_intr(struct rt_softc *sc)
1671 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx delay interrupt\n");
1672 sc->tx_delay_interrupts++;
1676 * rt_tx_intr - Transsmition of packet done
1679 rt_tx_intr(struct rt_softc *sc, int qid)
1682 KASSERT(qid >= 0 && qid < RT_SOFTC_TX_RING_COUNT,
1683 ("%s: Tx interrupt: invalid qid=%d\n",
1684 device_get_nameunit(sc->dev), qid));
1686 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx interrupt: qid=%d\n", qid);
1688 sc->tx_interrupts[qid]++;
1691 if (!(sc->intr_disable_mask & (sc->int_tx_done_mask << qid))) {
1692 rt_intr_disable(sc, (sc->int_tx_done_mask << qid));
1693 taskqueue_enqueue(sc->taskqueue, &sc->tx_done_task);
1696 sc->intr_pending_mask |= (sc->int_tx_done_mask << qid);
1697 RT_SOFTC_UNLOCK(sc);
1701 * rt_rx_done_task - run RX task
1704 rt_rx_done_task(void *context, int pending)
1706 struct rt_softc *sc;
1713 RT_DPRINTF(sc, RT_DEBUG_RX, "Rx done task\n");
1715 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1718 sc->intr_pending_mask &= ~sc->int_rx_done_mask;
1720 again = rt_rx_eof(sc, &sc->rx_ring[0], sc->rx_process_limit);
1724 if ((sc->intr_pending_mask & sc->int_rx_done_mask) || again) {
1725 RT_DPRINTF(sc, RT_DEBUG_RX,
1726 "Rx done task: scheduling again\n");
1727 taskqueue_enqueue(sc->taskqueue, &sc->rx_done_task);
1729 rt_intr_enable(sc, sc->int_rx_done_mask);
1732 RT_SOFTC_UNLOCK(sc);
1736 * rt_tx_done_task - check for pending TX task in all queues
1739 rt_tx_done_task(void *context, int pending)
1741 struct rt_softc *sc;
1749 RT_DPRINTF(sc, RT_DEBUG_TX, "Tx done task\n");
1751 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1754 for (i = RT_SOFTC_TX_RING_COUNT - 1; i >= 0; i--) {
1755 if (sc->intr_pending_mask & (sc->int_tx_done_mask << i)) {
1756 sc->intr_pending_mask &= ~(sc->int_tx_done_mask << i);
1757 rt_tx_eof(sc, &sc->tx_ring[i]);
1763 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1765 if(sc->rt_chipid == RT_CHIPID_RT5350 ||
1766 sc->rt_chipid == RT_CHIPID_MT7620 ||
1767 sc->rt_chipid == RT_CHIPID_MT7621)
1769 RT5350_INT_TXQ3_DONE |
1770 RT5350_INT_TXQ2_DONE |
1771 RT5350_INT_TXQ1_DONE |
1772 RT5350_INT_TXQ0_DONE);
1782 rt_intr_enable(sc, ~sc->intr_pending_mask &
1783 (sc->intr_disable_mask & intr_mask));
1785 if (sc->intr_pending_mask & intr_mask) {
1786 RT_DPRINTF(sc, RT_DEBUG_TX,
1787 "Tx done task: scheduling again\n");
1788 taskqueue_enqueue(sc->taskqueue, &sc->tx_done_task);
1791 RT_SOFTC_UNLOCK(sc);
1793 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1798 * rt_periodic_task - run periodic task
1801 rt_periodic_task(void *context, int pending)
1803 struct rt_softc *sc;
1809 RT_DPRINTF(sc, RT_DEBUG_PERIODIC, "periodic task: round=%lu\n",
1810 sc->periodic_round);
1812 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1816 sc->periodic_round++;
1817 rt_update_stats(sc);
1819 if ((sc->periodic_round % 10) == 0) {
1820 rt_update_raw_counters(sc);
1824 RT_SOFTC_UNLOCK(sc);
1825 taskqueue_enqueue_timeout(sc->taskqueue, &sc->periodic_task, hz / 10);
1829 * rt_rx_eof - check for frames that done by DMA engine and pass it into
1830 * network subsystem.
1833 rt_rx_eof(struct rt_softc *sc, struct rt_softc_rx_ring *ring, int limit)
1836 /* struct rt_softc_rx_ring *ring; */
1837 struct rt_rxdesc *desc;
1838 struct rt_softc_rx_data *data;
1839 struct mbuf *m, *mnew;
1840 bus_dma_segment_t segs[1];
1841 bus_dmamap_t dma_map;
1842 uint32_t index, desc_flags;
1843 int error, nsegs, len, nframes;
1846 /* ring = &sc->rx_ring[0]; */
1850 while (limit != 0) {
1851 index = RT_READ(sc, sc->rx_drx_idx[0]);
1852 if (ring->cur == index)
1855 desc = &ring->desc[ring->cur];
1856 data = &ring->data[ring->cur];
1858 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
1859 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1862 if ( sc->debug & RT_DEBUG_RX ) {
1863 printf("\nRX Descriptor[%#08x] dump:\n", (u_int)desc);
1864 hexdump(desc, 16, 0, 0);
1865 printf("-----------------------------------\n");
1869 /* XXX Sometime device don`t set DDONE bit */
1871 if (!(desc->sdl0 & htole16(RT_RXDESC_SDL0_DDONE))) {
1872 RT_DPRINTF(sc, RT_DEBUG_RX, "DDONE=0, try next\n");
1877 len = le16toh(desc->sdl0) & 0x3fff;
1878 RT_DPRINTF(sc, RT_DEBUG_RX, "new frame len=%d\n", len);
1882 mnew = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
1885 sc->rx_mbuf_alloc_errors++;
1886 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1890 mnew->m_len = mnew->m_pkthdr.len = MJUMPAGESIZE;
1892 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag,
1893 ring->spare_dma_map, mnew, segs, &nsegs, BUS_DMA_NOWAIT);
1895 RT_DPRINTF(sc, RT_DEBUG_RX,
1896 "could not load Rx mbuf DMA map: "
1897 "error=%d, nsegs=%d\n",
1902 sc->rx_mbuf_dmamap_errors++;
1903 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1908 KASSERT(nsegs == 1, ("%s: too many DMA segments",
1909 device_get_nameunit(sc->dev)));
1911 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
1912 BUS_DMASYNC_POSTREAD);
1913 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
1915 dma_map = data->dma_map;
1916 data->dma_map = ring->spare_dma_map;
1917 ring->spare_dma_map = dma_map;
1919 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
1920 BUS_DMASYNC_PREREAD);
1923 desc_flags = desc->word3;
1926 /* Add 2 for proper align of RX IP header */
1927 desc->sdp0 = htole32(segs[0].ds_addr+2);
1928 desc->sdl0 = htole32(segs[0].ds_len-2);
1931 RT_DPRINTF(sc, RT_DEBUG_RX,
1932 "Rx frame: rxdesc flags=0x%08x\n", desc_flags);
1934 m->m_pkthdr.rcvif = ifp;
1935 /* Add 2 to fix data align, after sdp0 = addr + 2 */
1937 m->m_pkthdr.len = m->m_len = len;
1939 /* check for crc errors */
1940 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1941 /*check for valid checksum*/
1942 if (desc_flags & (sc->csum_fail_ip|sc->csum_fail_l4)) {
1943 RT_DPRINTF(sc, RT_DEBUG_RX,
1944 "rxdesc: crc error\n");
1946 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1948 if (!(ifp->if_flags & IFF_PROMISC)) {
1953 if ((desc_flags & sc->csum_fail_ip) == 0) {
1954 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1955 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1956 m->m_pkthdr.csum_data = 0xffff;
1958 m->m_flags &= ~M_HASFCS;
1961 (*ifp->if_input)(ifp, m);
1963 desc->sdl0 &= ~htole16(RT_RXDESC_SDL0_DDONE);
1965 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
1966 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1968 ring->cur = (ring->cur + 1) % RT_SOFTC_RX_RING_DATA_COUNT;
1974 RT_WRITE(sc, sc->rx_calc_idx[0],
1975 RT_SOFTC_RX_RING_DATA_COUNT - 1);
1977 RT_WRITE(sc, sc->rx_calc_idx[0],
1980 RT_DPRINTF(sc, RT_DEBUG_RX, "Rx eof: nframes=%d\n", nframes);
1982 sc->rx_packets += nframes;
1984 return (limit == 0);
1988 * rt_tx_eof - check for successful transmitted frames and mark their
1989 * descriptor as free.
1992 rt_tx_eof(struct rt_softc *sc, struct rt_softc_tx_ring *ring)
1995 struct rt_txdesc *desc;
1996 struct rt_softc_tx_data *data;
1998 int ndescs, nframes;
2006 index = RT_READ(sc, sc->tx_dtx_idx[ring->qid]);
2007 if (ring->desc_next == index)
2012 desc = &ring->desc[ring->desc_next];
2014 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2015 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2017 if (desc->sdl0 & htole16(RT_TXDESC_SDL0_LASTSEG) ||
2018 desc->sdl1 & htole16(RT_TXDESC_SDL1_LASTSEG)) {
2021 data = &ring->data[ring->data_next];
2023 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
2024 BUS_DMASYNC_POSTWRITE);
2025 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
2031 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2033 RT_SOFTC_TX_RING_LOCK(ring);
2034 ring->data_queued--;
2035 ring->data_next = (ring->data_next + 1) %
2036 RT_SOFTC_TX_RING_DATA_COUNT;
2037 RT_SOFTC_TX_RING_UNLOCK(ring);
2040 desc->sdl0 &= ~htole16(RT_TXDESC_SDL0_DDONE);
2042 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2043 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2045 RT_SOFTC_TX_RING_LOCK(ring);
2046 ring->desc_queued--;
2047 ring->desc_next = (ring->desc_next + 1) %
2048 RT_SOFTC_TX_RING_DESC_COUNT;
2049 RT_SOFTC_TX_RING_UNLOCK(ring);
2052 RT_DPRINTF(sc, RT_DEBUG_TX,
2053 "Tx eof: qid=%d, ndescs=%d, nframes=%d\n", ring->qid, ndescs,
2058 * rt_update_stats - query statistics counters and update related variables.
2061 rt_update_stats(struct rt_softc *sc)
2066 RT_DPRINTF(sc, RT_DEBUG_STATS, "update statistic: \n");
2067 /* XXX do update stats here */
2071 * rt_watchdog - reinit device on watchdog event.
2074 rt_watchdog(struct rt_softc *sc)
2080 if(sc->rt_chipid != RT_CHIPID_RT5350 &&
2081 sc->rt_chipid != RT_CHIPID_MT7620 &&
2082 sc->rt_chipid != RT_CHIPID_MT7621) {
2083 tmp = RT_READ(sc, PSE_BASE + CDMA_OQ_STA);
2085 RT_DPRINTF(sc, RT_DEBUG_WATCHDOG,
2086 "watchdog: PSE_IQ_STA=0x%08x\n", tmp);
2088 /* XXX: do not reset */
2090 if (((tmp >> P0_IQ_PCNT_SHIFT) & 0xff) != 0) {
2091 sc->tx_queue_not_empty[0]++;
2093 for (ntries = 0; ntries < 10; ntries++) {
2094 tmp = RT_READ(sc, PSE_BASE + PSE_IQ_STA);
2095 if (((tmp >> P0_IQ_PCNT_SHIFT) & 0xff) == 0)
2102 if (((tmp >> P1_IQ_PCNT_SHIFT) & 0xff) != 0) {
2103 sc->tx_queue_not_empty[1]++;
2105 for (ntries = 0; ntries < 10; ntries++) {
2106 tmp = RT_READ(sc, PSE_BASE + PSE_IQ_STA);
2107 if (((tmp >> P1_IQ_PCNT_SHIFT) & 0xff) == 0)
2117 * rt_update_raw_counters - update counters.
2120 rt_update_raw_counters(struct rt_softc *sc)
2123 sc->tx_bytes += RT_READ(sc, CNTR_BASE + GDMA_TX_GBCNT0);
2124 sc->tx_packets += RT_READ(sc, CNTR_BASE + GDMA_TX_GPCNT0);
2125 sc->tx_skip += RT_READ(sc, CNTR_BASE + GDMA_TX_SKIPCNT0);
2126 sc->tx_collision+= RT_READ(sc, CNTR_BASE + GDMA_TX_COLCNT0);
2128 sc->rx_bytes += RT_READ(sc, CNTR_BASE + GDMA_RX_GBCNT0);
2129 sc->rx_packets += RT_READ(sc, CNTR_BASE + GDMA_RX_GPCNT0);
2130 sc->rx_crc_err += RT_READ(sc, CNTR_BASE + GDMA_RX_CSUM_ERCNT0);
2131 sc->rx_short_err+= RT_READ(sc, CNTR_BASE + GDMA_RX_SHORT_ERCNT0);
2132 sc->rx_long_err += RT_READ(sc, CNTR_BASE + GDMA_RX_LONG_ERCNT0);
2133 sc->rx_phy_err += RT_READ(sc, CNTR_BASE + GDMA_RX_FERCNT0);
2134 sc->rx_fifo_overflows+= RT_READ(sc, CNTR_BASE + GDMA_RX_OERCNT0);
2138 rt_intr_enable(struct rt_softc *sc, uint32_t intr_mask)
2142 sc->intr_disable_mask &= ~intr_mask;
2143 tmp = sc->intr_enable_mask & ~sc->intr_disable_mask;
2144 RT_WRITE(sc, sc->fe_int_enable, tmp);
2148 rt_intr_disable(struct rt_softc *sc, uint32_t intr_mask)
2152 sc->intr_disable_mask |= intr_mask;
2153 tmp = sc->intr_enable_mask & ~sc->intr_disable_mask;
2154 RT_WRITE(sc, sc->fe_int_enable, tmp);
2158 * rt_txrx_enable - enable TX/RX DMA
2161 rt_txrx_enable(struct rt_softc *sc)
2169 /* enable Tx/Rx DMA engine */
2170 for (ntries = 0; ntries < 200; ntries++) {
2171 tmp = RT_READ(sc, sc->pdma_glo_cfg);
2172 if (!(tmp & (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)))
2178 if (ntries == 200) {
2179 device_printf(sc->dev, "timeout waiting for DMA engine\n");
2185 tmp |= FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
2186 RT_WRITE(sc, sc->pdma_glo_cfg, tmp);
2188 /* XXX set Rx filter */
2193 * rt_alloc_rx_ring - allocate RX DMA ring buffer
2196 rt_alloc_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring, int qid)
2198 struct rt_rxdesc *desc;
2199 struct rt_softc_rx_data *data;
2200 bus_dma_segment_t segs[1];
2201 int i, nsegs, error;
2203 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2204 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2205 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc), 1,
2206 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc),
2207 0, NULL, NULL, &ring->desc_dma_tag);
2209 device_printf(sc->dev,
2210 "could not create Rx desc DMA tag\n");
2214 error = bus_dmamem_alloc(ring->desc_dma_tag, (void **) &ring->desc,
2215 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_dma_map);
2217 device_printf(sc->dev,
2218 "could not allocate Rx desc DMA memory\n");
2222 error = bus_dmamap_load(ring->desc_dma_tag, ring->desc_dma_map,
2224 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc),
2225 rt_dma_map_addr, &ring->desc_phys_addr, 0);
2227 device_printf(sc->dev, "could not load Rx desc DMA map\n");
2231 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2232 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2233 MJUMPAGESIZE, 1, MJUMPAGESIZE, 0, NULL, NULL,
2234 &ring->data_dma_tag);
2236 device_printf(sc->dev,
2237 "could not create Rx data DMA tag\n");
2241 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) {
2242 desc = &ring->desc[i];
2243 data = &ring->data[i];
2245 error = bus_dmamap_create(ring->data_dma_tag, 0,
2248 device_printf(sc->dev, "could not create Rx data DMA "
2253 data->m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
2255 if (data->m == NULL) {
2256 device_printf(sc->dev, "could not allocate Rx mbuf\n");
2261 data->m->m_len = data->m->m_pkthdr.len = MJUMPAGESIZE;
2263 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag,
2264 data->dma_map, data->m, segs, &nsegs, BUS_DMA_NOWAIT);
2266 device_printf(sc->dev,
2267 "could not load Rx mbuf DMA map\n");
2271 KASSERT(nsegs == 1, ("%s: too many DMA segments",
2272 device_get_nameunit(sc->dev)));
2274 /* Add 2 for proper align of RX IP header */
2275 desc->sdp0 = htole32(segs[0].ds_addr+2);
2276 desc->sdl0 = htole32(segs[0].ds_len-2);
2279 error = bus_dmamap_create(ring->data_dma_tag, 0,
2280 &ring->spare_dma_map);
2282 device_printf(sc->dev,
2283 "could not create Rx spare DMA map\n");
2287 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2288 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2293 rt_free_rx_ring(sc, ring);
2298 * rt_reset_rx_ring - reset RX ring buffer
2301 rt_reset_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring)
2303 struct rt_rxdesc *desc;
2306 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) {
2307 desc = &ring->desc[i];
2308 desc->sdl0 &= ~htole16(RT_RXDESC_SDL0_DDONE);
2311 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2312 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2317 * rt_free_rx_ring - free memory used by RX ring buffer
2320 rt_free_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring)
2322 struct rt_softc_rx_data *data;
2325 if (ring->desc != NULL) {
2326 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2327 BUS_DMASYNC_POSTWRITE);
2328 bus_dmamap_unload(ring->desc_dma_tag, ring->desc_dma_map);
2329 bus_dmamem_free(ring->desc_dma_tag, ring->desc,
2330 ring->desc_dma_map);
2333 if (ring->desc_dma_tag != NULL)
2334 bus_dma_tag_destroy(ring->desc_dma_tag);
2336 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) {
2337 data = &ring->data[i];
2339 if (data->m != NULL) {
2340 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
2341 BUS_DMASYNC_POSTREAD);
2342 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
2346 if (data->dma_map != NULL)
2347 bus_dmamap_destroy(ring->data_dma_tag, data->dma_map);
2350 if (ring->spare_dma_map != NULL)
2351 bus_dmamap_destroy(ring->data_dma_tag, ring->spare_dma_map);
2353 if (ring->data_dma_tag != NULL)
2354 bus_dma_tag_destroy(ring->data_dma_tag);
2358 * rt_alloc_tx_ring - allocate TX ring buffer
2361 rt_alloc_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring, int qid)
2363 struct rt_softc_tx_data *data;
2366 mtx_init(&ring->lock, device_get_nameunit(sc->dev), NULL, MTX_DEF);
2368 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2369 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2370 RT_SOFTC_TX_RING_DESC_COUNT * sizeof(struct rt_txdesc), 1,
2371 RT_SOFTC_TX_RING_DESC_COUNT * sizeof(struct rt_txdesc),
2372 0, NULL, NULL, &ring->desc_dma_tag);
2374 device_printf(sc->dev,
2375 "could not create Tx desc DMA tag\n");
2379 error = bus_dmamem_alloc(ring->desc_dma_tag, (void **) &ring->desc,
2380 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_dma_map);
2382 device_printf(sc->dev,
2383 "could not allocate Tx desc DMA memory\n");
2387 error = bus_dmamap_load(ring->desc_dma_tag, ring->desc_dma_map,
2388 ring->desc, (RT_SOFTC_TX_RING_DESC_COUNT *
2389 sizeof(struct rt_txdesc)), rt_dma_map_addr,
2390 &ring->desc_phys_addr, 0);
2392 device_printf(sc->dev, "could not load Tx desc DMA map\n");
2396 ring->desc_queued = 0;
2398 ring->desc_next = 0;
2400 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2401 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2402 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE, 1,
2403 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE,
2404 0, NULL, NULL, &ring->seg0_dma_tag);
2406 device_printf(sc->dev,
2407 "could not create Tx seg0 DMA tag\n");
2411 error = bus_dmamem_alloc(ring->seg0_dma_tag, (void **) &ring->seg0,
2412 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->seg0_dma_map);
2414 device_printf(sc->dev,
2415 "could not allocate Tx seg0 DMA memory\n");
2419 error = bus_dmamap_load(ring->seg0_dma_tag, ring->seg0_dma_map,
2421 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE,
2422 rt_dma_map_addr, &ring->seg0_phys_addr, 0);
2424 device_printf(sc->dev, "could not load Tx seg0 DMA map\n");
2428 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2429 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2430 MJUMPAGESIZE, RT_SOFTC_MAX_SCATTER, MJUMPAGESIZE, 0, NULL, NULL,
2431 &ring->data_dma_tag);
2433 device_printf(sc->dev,
2434 "could not create Tx data DMA tag\n");
2438 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) {
2439 data = &ring->data[i];
2441 error = bus_dmamap_create(ring->data_dma_tag, 0,
2444 device_printf(sc->dev, "could not create Tx data DMA "
2450 ring->data_queued = 0;
2452 ring->data_next = 0;
2458 rt_free_tx_ring(sc, ring);
2463 * rt_reset_tx_ring - reset TX ring buffer to empty state
2466 rt_reset_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring)
2468 struct rt_softc_tx_data *data;
2469 struct rt_txdesc *desc;
2472 for (i = 0; i < RT_SOFTC_TX_RING_DESC_COUNT; i++) {
2473 desc = &ring->desc[i];
2479 ring->desc_queued = 0;
2481 ring->desc_next = 0;
2483 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2484 BUS_DMASYNC_PREWRITE);
2486 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map,
2487 BUS_DMASYNC_PREWRITE);
2489 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) {
2490 data = &ring->data[i];
2492 if (data->m != NULL) {
2493 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
2494 BUS_DMASYNC_POSTWRITE);
2495 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
2501 ring->data_queued = 0;
2503 ring->data_next = 0;
2507 * rt_free_tx_ring - free RX ring buffer
2510 rt_free_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring)
2512 struct rt_softc_tx_data *data;
2515 if (ring->desc != NULL) {
2516 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2517 BUS_DMASYNC_POSTWRITE);
2518 bus_dmamap_unload(ring->desc_dma_tag, ring->desc_dma_map);
2519 bus_dmamem_free(ring->desc_dma_tag, ring->desc,
2520 ring->desc_dma_map);
2523 if (ring->desc_dma_tag != NULL)
2524 bus_dma_tag_destroy(ring->desc_dma_tag);
2526 if (ring->seg0 != NULL) {
2527 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map,
2528 BUS_DMASYNC_POSTWRITE);
2529 bus_dmamap_unload(ring->seg0_dma_tag, ring->seg0_dma_map);
2530 bus_dmamem_free(ring->seg0_dma_tag, ring->seg0,
2531 ring->seg0_dma_map);
2534 if (ring->seg0_dma_tag != NULL)
2535 bus_dma_tag_destroy(ring->seg0_dma_tag);
2537 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) {
2538 data = &ring->data[i];
2540 if (data->m != NULL) {
2541 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
2542 BUS_DMASYNC_POSTWRITE);
2543 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
2547 if (data->dma_map != NULL)
2548 bus_dmamap_destroy(ring->data_dma_tag, data->dma_map);
2551 if (ring->data_dma_tag != NULL)
2552 bus_dma_tag_destroy(ring->data_dma_tag);
2554 mtx_destroy(&ring->lock);
2558 * rt_dma_map_addr - get address of busdma segment
2561 rt_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2566 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
2568 *(bus_addr_t *) arg = segs[0].ds_addr;
2572 * rt_sysctl_attach - attach sysctl nodes for NIC counters.
2575 rt_sysctl_attach(struct rt_softc *sc)
2577 struct sysctl_ctx_list *ctx;
2578 struct sysctl_oid *tree;
2579 struct sysctl_oid *stats;
2581 ctx = device_get_sysctl_ctx(sc->dev);
2582 tree = device_get_sysctl_tree(sc->dev);
2584 /* statistic counters */
2585 stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
2586 "stats", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "statistic");
2588 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2589 "interrupts", CTLFLAG_RD, &sc->interrupts,
2592 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2593 "tx_coherent_interrupts", CTLFLAG_RD, &sc->tx_coherent_interrupts,
2594 "Tx coherent interrupts");
2596 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2597 "rx_coherent_interrupts", CTLFLAG_RD, &sc->rx_coherent_interrupts,
2598 "Rx coherent interrupts");
2600 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2601 "rx_interrupts", CTLFLAG_RD, &sc->rx_interrupts[0],
2604 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2605 "rx_delay_interrupts", CTLFLAG_RD, &sc->rx_delay_interrupts,
2606 "Rx delay interrupts");
2608 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2609 "TXQ3_interrupts", CTLFLAG_RD, &sc->tx_interrupts[3],
2610 "Tx AC3 interrupts");
2612 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2613 "TXQ2_interrupts", CTLFLAG_RD, &sc->tx_interrupts[2],
2614 "Tx AC2 interrupts");
2616 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2617 "TXQ1_interrupts", CTLFLAG_RD, &sc->tx_interrupts[1],
2618 "Tx AC1 interrupts");
2620 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2621 "TXQ0_interrupts", CTLFLAG_RD, &sc->tx_interrupts[0],
2622 "Tx AC0 interrupts");
2624 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2625 "tx_delay_interrupts", CTLFLAG_RD, &sc->tx_delay_interrupts,
2626 "Tx delay interrupts");
2628 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2629 "TXQ3_desc_queued", CTLFLAG_RD, &sc->tx_ring[3].desc_queued,
2630 0, "Tx AC3 descriptors queued");
2632 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2633 "TXQ3_data_queued", CTLFLAG_RD, &sc->tx_ring[3].data_queued,
2634 0, "Tx AC3 data queued");
2636 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2637 "TXQ2_desc_queued", CTLFLAG_RD, &sc->tx_ring[2].desc_queued,
2638 0, "Tx AC2 descriptors queued");
2640 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2641 "TXQ2_data_queued", CTLFLAG_RD, &sc->tx_ring[2].data_queued,
2642 0, "Tx AC2 data queued");
2644 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2645 "TXQ1_desc_queued", CTLFLAG_RD, &sc->tx_ring[1].desc_queued,
2646 0, "Tx AC1 descriptors queued");
2648 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2649 "TXQ1_data_queued", CTLFLAG_RD, &sc->tx_ring[1].data_queued,
2650 0, "Tx AC1 data queued");
2652 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2653 "TXQ0_desc_queued", CTLFLAG_RD, &sc->tx_ring[0].desc_queued,
2654 0, "Tx AC0 descriptors queued");
2656 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2657 "TXQ0_data_queued", CTLFLAG_RD, &sc->tx_ring[0].data_queued,
2658 0, "Tx AC0 data queued");
2660 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2661 "TXQ3_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[3],
2662 "Tx AC3 data queue full");
2664 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2665 "TXQ2_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[2],
2666 "Tx AC2 data queue full");
2668 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2669 "TXQ1_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[1],
2670 "Tx AC1 data queue full");
2672 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2673 "TXQ0_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[0],
2674 "Tx AC0 data queue full");
2676 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2677 "tx_watchdog_timeouts", CTLFLAG_RD, &sc->tx_watchdog_timeouts,
2678 "Tx watchdog timeouts");
2680 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2681 "tx_defrag_packets", CTLFLAG_RD, &sc->tx_defrag_packets,
2682 "Tx defragmented packets");
2684 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2685 "no_tx_desc_avail", CTLFLAG_RD, &sc->no_tx_desc_avail,
2686 "no Tx descriptors available");
2688 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2689 "rx_mbuf_alloc_errors", CTLFLAG_RD, &sc->rx_mbuf_alloc_errors,
2690 "Rx mbuf allocation errors");
2692 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2693 "rx_mbuf_dmamap_errors", CTLFLAG_RD, &sc->rx_mbuf_dmamap_errors,
2694 "Rx mbuf DMA mapping errors");
2696 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2697 "tx_queue_0_not_empty", CTLFLAG_RD, &sc->tx_queue_not_empty[0],
2698 "Tx queue 0 not empty");
2700 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2701 "tx_queue_1_not_empty", CTLFLAG_RD, &sc->tx_queue_not_empty[1],
2702 "Tx queue 1 not empty");
2704 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2705 "rx_packets", CTLFLAG_RD, &sc->rx_packets,
2708 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2709 "rx_crc_errors", CTLFLAG_RD, &sc->rx_crc_err,
2712 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2713 "rx_phy_errors", CTLFLAG_RD, &sc->rx_phy_err,
2716 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2717 "rx_dup_packets", CTLFLAG_RD, &sc->rx_dup_packets,
2718 "Rx duplicate packets");
2720 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2721 "rx_fifo_overflows", CTLFLAG_RD, &sc->rx_fifo_overflows,
2722 "Rx FIFO overflows");
2724 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2725 "rx_bytes", CTLFLAG_RD, &sc->rx_bytes,
2728 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2729 "rx_long_err", CTLFLAG_RD, &sc->rx_long_err,
2730 "Rx too long frame errors");
2732 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2733 "rx_short_err", CTLFLAG_RD, &sc->rx_short_err,
2734 "Rx too short frame errors");
2736 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2737 "tx_bytes", CTLFLAG_RD, &sc->tx_bytes,
2740 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2741 "tx_packets", CTLFLAG_RD, &sc->tx_packets,
2744 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2745 "tx_skip", CTLFLAG_RD, &sc->tx_skip,
2746 "Tx skip count for GDMA ports");
2748 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2749 "tx_collision", CTLFLAG_RD, &sc->tx_collision,
2750 "Tx collision count for GDMA ports");
2753 #if defined(IF_RT_PHY_SUPPORT) || defined(RT_MDIO)
2754 /* This code is only work RT2880 and same chip. */
2755 /* TODO: make RT3052 and later support code. But nobody need it? */
2757 rt_miibus_readreg(device_t dev, int phy, int reg)
2759 struct rt_softc *sc = device_get_softc(dev);
2763 * PSEUDO_PHYAD is a special value for indicate switch attached.
2764 * No one PHY use PSEUDO_PHYAD (0x1e) address.
2768 /* Fake PHY ID for bfeswitch attach */
2771 return (BMSR_EXTSTAT|BMSR_MEDIAMASK);
2773 return (0x40); /* As result of faking */
2774 case MII_PHYIDR2: /* PHY will detect as */
2775 return (0x6250); /* bfeswitch */
2780 /* Wait prev command done if any */
2781 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2782 dat = ((phy << MDIO_PHY_ADDR_SHIFT) & MDIO_PHY_ADDR_MASK) |
2783 ((reg << MDIO_PHYREG_ADDR_SHIFT) & MDIO_PHYREG_ADDR_MASK);
2784 RT_WRITE(sc, MDIO_ACCESS, dat);
2785 RT_WRITE(sc, MDIO_ACCESS, dat | MDIO_CMD_ONGO);
2786 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2788 return (RT_READ(sc, MDIO_ACCESS) & MDIO_PHY_DATA_MASK);
2792 rt_miibus_writereg(device_t dev, int phy, int reg, int val)
2794 struct rt_softc *sc = device_get_softc(dev);
2797 /* Wait prev command done if any */
2798 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2800 ((phy << MDIO_PHY_ADDR_SHIFT) & MDIO_PHY_ADDR_MASK) |
2801 ((reg << MDIO_PHYREG_ADDR_SHIFT) & MDIO_PHYREG_ADDR_MASK) |
2802 (val & MDIO_PHY_DATA_MASK);
2803 RT_WRITE(sc, MDIO_ACCESS, dat);
2804 RT_WRITE(sc, MDIO_ACCESS, dat | MDIO_CMD_ONGO);
2805 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2811 #ifdef IF_RT_PHY_SUPPORT
2813 rt_miibus_statchg(device_t dev)
2815 struct rt_softc *sc = device_get_softc(dev);
2816 struct mii_data *mii;
2818 mii = device_get_softc(sc->rt_miibus);
2820 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
2821 (IFM_ACTIVE | IFM_AVALID)) {
2822 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2825 /* XXX check link here */
2833 #endif /* IF_RT_PHY_SUPPORT */
2835 static device_method_t rt_dev_methods[] =
2837 DEVMETHOD(device_probe, rt_probe),
2838 DEVMETHOD(device_attach, rt_attach),
2839 DEVMETHOD(device_detach, rt_detach),
2840 DEVMETHOD(device_shutdown, rt_shutdown),
2841 DEVMETHOD(device_suspend, rt_suspend),
2842 DEVMETHOD(device_resume, rt_resume),
2844 #ifdef IF_RT_PHY_SUPPORT
2846 DEVMETHOD(miibus_readreg, rt_miibus_readreg),
2847 DEVMETHOD(miibus_writereg, rt_miibus_writereg),
2848 DEVMETHOD(miibus_statchg, rt_miibus_statchg),
2854 static driver_t rt_driver =
2858 sizeof(struct rt_softc)
2861 static devclass_t rt_dev_class;
2863 DRIVER_MODULE(rt, nexus, rt_driver, rt_dev_class, 0, 0);
2865 DRIVER_MODULE(rt, simplebus, rt_driver, rt_dev_class, 0, 0);
2868 MODULE_DEPEND(rt, ether, 1, 1, 1);
2869 MODULE_DEPEND(rt, miibus, 1, 1, 1);
2872 MODULE_DEPEND(rt, mdio, 1, 1, 1);
2874 static int rtmdio_probe(device_t);
2875 static int rtmdio_attach(device_t);
2876 static int rtmdio_detach(device_t);
2878 static struct mtx miibus_mtx;
2880 MTX_SYSINIT(miibus_mtx, &miibus_mtx, "rt mii lock", MTX_DEF);
2883 * Declare an additional, separate driver for accessing the MDIO bus.
2885 static device_method_t rtmdio_methods[] = {
2886 /* Device interface */
2887 DEVMETHOD(device_probe, rtmdio_probe),
2888 DEVMETHOD(device_attach, rtmdio_attach),
2889 DEVMETHOD(device_detach, rtmdio_detach),
2892 DEVMETHOD(bus_add_child, device_add_child_ordered),
2895 DEVMETHOD(mdio_readreg, rt_miibus_readreg),
2896 DEVMETHOD(mdio_writereg, rt_miibus_writereg),
2899 DEFINE_CLASS_0(rtmdio, rtmdio_driver, rtmdio_methods,
2900 sizeof(struct rt_softc));
2901 static devclass_t rtmdio_devclass;
2903 DRIVER_MODULE(miiproxy, rt, miiproxy_driver, miiproxy_devclass, 0, 0);
2904 DRIVER_MODULE(rtmdio, simplebus, rtmdio_driver, rtmdio_devclass, 0, 0);
2905 DRIVER_MODULE(mdio, rtmdio, mdio_driver, mdio_devclass, 0, 0);
2908 rtmdio_probe(device_t dev)
2910 if (!ofw_bus_status_okay(dev))
2913 if (!ofw_bus_is_compatible(dev, "ralink,rt2880-mdio"))
2916 device_set_desc(dev, "RT built-in ethernet interface, MDIO controller");
2921 rtmdio_attach(device_t dev)
2923 struct rt_softc *sc;
2926 sc = device_get_softc(dev);
2929 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
2930 &sc->mem_rid, RF_ACTIVE | RF_SHAREABLE);
2931 if (sc->mem == NULL) {
2932 device_printf(dev, "couldn't map memory\n");
2937 sc->bst = rman_get_bustag(sc->mem);
2938 sc->bsh = rman_get_bushandle(sc->mem);
2940 bus_generic_probe(dev);
2941 bus_enumerate_hinted_children(dev);
2942 error = bus_generic_attach(dev);
2948 rtmdio_detach(device_t dev)