2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2015-2016, Stanislav Galabov
5 * Copyright (c) 2014, Aleksandr A. Mityaev
6 * Copyright (c) 2011, Aleksandr Rybalko
8 * by Alexander Egorenkov <egorenar@gmail.com>
9 * and by Damien Bergamini <damien.bergamini@free.fr>
10 * All rights reserved.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice unmodified, this list of conditions, and the following
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
42 #include <net/if_var.h>
43 #include <net/if_arp.h>
44 #include <net/ethernet.h>
45 #include <net/if_dl.h>
46 #include <net/if_media.h>
47 #include <net/if_types.h>
48 #include <net/if_vlan_var.h>
52 #include <machine/bus.h>
53 #include <machine/cache.h>
54 #include <machine/cpufunc.h>
55 #include <machine/resource.h>
56 #include <vm/vm_param.h>
59 #include <machine/pmap.h>
63 #include "opt_platform.h"
64 #include "opt_rt305x.h"
67 #include <dev/ofw/openfirm.h>
68 #include <dev/ofw/ofw_bus.h>
69 #include <dev/ofw/ofw_bus_subr.h>
72 #include <dev/mii/mii.h>
73 #include <dev/mii/miivar.h>
76 #include <dev/mdio/mdio.h>
77 #include <dev/etherswitch/miiproxy.h>
82 #include <mips/rt305x/rt305x_sysctlvar.h>
83 #include <mips/rt305x/rt305xreg.h>
86 #ifdef IF_RT_PHY_SUPPORT
87 #include "miibus_if.h"
93 #define RT_MAX_AGG_SIZE 3840
95 #define RT_TX_DATA_SEG0_SIZE MJUMPAGESIZE
97 #define RT_MS(_v, _f) (((_v) & _f) >> _f##_S)
98 #define RT_SM(_v, _f) (((_v) << _f##_S) & _f)
100 #define RT_TX_WATCHDOG_TIMEOUT 5
102 #define RT_CHIPID_RT2880 0x2880
103 #define RT_CHIPID_RT3050 0x3050
104 #define RT_CHIPID_RT3883 0x3883
105 #define RT_CHIPID_RT5350 0x5350
106 #define RT_CHIPID_MT7620 0x7620
107 #define RT_CHIPID_MT7621 0x7621
110 /* more specific and new models should go first */
111 static const struct ofw_compat_data rt_compat_data[] = {
112 { "ralink,rt2880-eth", RT_CHIPID_RT2880 },
113 { "ralink,rt3050-eth", RT_CHIPID_RT3050 },
114 { "ralink,rt3352-eth", RT_CHIPID_RT3050 },
115 { "ralink,rt3883-eth", RT_CHIPID_RT3883 },
116 { "ralink,rt5350-eth", RT_CHIPID_RT5350 },
117 { "ralink,mt7620a-eth", RT_CHIPID_MT7620 },
118 { "mediatek,mt7620-eth", RT_CHIPID_MT7620 },
119 { "ralink,mt7621-eth", RT_CHIPID_MT7621 },
120 { "mediatek,mt7621-eth", RT_CHIPID_MT7621 },
126 * Static function prototypes
128 static int rt_probe(device_t dev);
129 static int rt_attach(device_t dev);
130 static int rt_detach(device_t dev);
131 static int rt_shutdown(device_t dev);
132 static int rt_suspend(device_t dev);
133 static int rt_resume(device_t dev);
134 static void rt_init_locked(void *priv);
135 static void rt_init(void *priv);
136 static void rt_stop_locked(void *priv);
137 static void rt_stop(void *priv);
138 static void rt_start(struct ifnet *ifp);
139 static int rt_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
140 static void rt_periodic(void *arg);
141 static void rt_tx_watchdog(void *arg);
142 static void rt_intr(void *arg);
143 static void rt_rt5350_intr(void *arg);
144 static void rt_tx_coherent_intr(struct rt_softc *sc);
145 static void rt_rx_coherent_intr(struct rt_softc *sc);
146 static void rt_rx_delay_intr(struct rt_softc *sc);
147 static void rt_tx_delay_intr(struct rt_softc *sc);
148 static void rt_rx_intr(struct rt_softc *sc, int qid);
149 static void rt_tx_intr(struct rt_softc *sc, int qid);
150 static void rt_rx_done_task(void *context, int pending);
151 static void rt_tx_done_task(void *context, int pending);
152 static void rt_periodic_task(void *context, int pending);
153 static int rt_rx_eof(struct rt_softc *sc,
154 struct rt_softc_rx_ring *ring, int limit);
155 static void rt_tx_eof(struct rt_softc *sc,
156 struct rt_softc_tx_ring *ring);
157 static void rt_update_stats(struct rt_softc *sc);
158 static void rt_watchdog(struct rt_softc *sc);
159 static void rt_update_raw_counters(struct rt_softc *sc);
160 static void rt_intr_enable(struct rt_softc *sc, uint32_t intr_mask);
161 static void rt_intr_disable(struct rt_softc *sc, uint32_t intr_mask);
162 static int rt_txrx_enable(struct rt_softc *sc);
163 static int rt_alloc_rx_ring(struct rt_softc *sc,
164 struct rt_softc_rx_ring *ring, int qid);
165 static void rt_reset_rx_ring(struct rt_softc *sc,
166 struct rt_softc_rx_ring *ring);
167 static void rt_free_rx_ring(struct rt_softc *sc,
168 struct rt_softc_rx_ring *ring);
169 static int rt_alloc_tx_ring(struct rt_softc *sc,
170 struct rt_softc_tx_ring *ring, int qid);
171 static void rt_reset_tx_ring(struct rt_softc *sc,
172 struct rt_softc_tx_ring *ring);
173 static void rt_free_tx_ring(struct rt_softc *sc,
174 struct rt_softc_tx_ring *ring);
175 static void rt_dma_map_addr(void *arg, bus_dma_segment_t *segs,
176 int nseg, int error);
177 static void rt_sysctl_attach(struct rt_softc *sc);
178 #ifdef IF_RT_PHY_SUPPORT
179 void rt_miibus_statchg(device_t);
181 #if defined(IF_RT_PHY_SUPPORT) || defined(RT_MDIO)
182 static int rt_miibus_readreg(device_t, int, int);
183 static int rt_miibus_writereg(device_t, int, int, int);
185 static int rt_ifmedia_upd(struct ifnet *);
186 static void rt_ifmedia_sts(struct ifnet *, struct ifmediareq *);
188 static SYSCTL_NODE(_hw, OID_AUTO, rt, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
189 "RT driver parameters");
191 static int rt_debug = 0;
192 SYSCTL_INT(_hw_rt, OID_AUTO, debug, CTLFLAG_RWTUN, &rt_debug, 0,
197 rt_probe(device_t dev)
199 struct rt_softc *sc = device_get_softc(dev);
202 const struct ofw_compat_data * cd;
204 cd = ofw_bus_search_compatible(dev, rt_compat_data);
205 if (cd->ocd_data == 0)
208 sc->rt_chipid = (unsigned int)(cd->ocd_data);
211 sc->rt_chipid = RT_CHIPID_MT7620;
212 #elif defined(MT7621)
213 sc->rt_chipid = RT_CHIPID_MT7621;
214 #elif defined(RT5350)
215 sc->rt_chipid = RT_CHIPID_RT5350;
217 sc->rt_chipid = RT_CHIPID_RT3050;
220 snprintf(buf, sizeof(buf), "Ralink %cT%x onChip Ethernet driver",
221 sc->rt_chipid >= 0x7600 ? 'M' : 'R', sc->rt_chipid);
222 device_set_desc_copy(dev, buf);
223 return (BUS_PROBE_GENERIC);
227 * macaddr_atoi - translate string MAC address to uint8_t array
230 macaddr_atoi(const char *str, uint8_t *mac)
233 unsigned int amac[ETHER_ADDR_LEN]; /* Aligned version */
235 count = sscanf(str, "%x%*c%x%*c%x%*c%x%*c%x%*c%x",
236 &amac[0], &amac[1], &amac[2],
237 &amac[3], &amac[4], &amac[5]);
238 if (count < ETHER_ADDR_LEN) {
239 memset(mac, 0, ETHER_ADDR_LEN);
243 /* Copy aligned to result */
244 for (i = 0; i < ETHER_ADDR_LEN; i ++)
245 mac[i] = (amac[i] & 0xff);
250 #ifdef USE_GENERATED_MAC_ADDRESS
252 * generate_mac(uin8_t *mac)
253 * This is MAC address generator for cases when real device MAC address
254 * unknown or not yet accessible.
255 * Use 'b','s','d' signature and 3 octets from CRC32 on kenv.
256 * MAC = 'b', 's', 'd', CRC[3]^CRC[2], CRC[1], CRC[0]
258 * Output - MAC address, that do not change between reboots, if hints or
259 * bootloader info unchange.
262 generate_mac(uint8_t *mac)
266 uint32_t crc = 0xffffffff;
268 /* Generate CRC32 on kenv */
269 for (cp = kenvp[0]; cp != NULL; cp = kenvp[++i]) {
270 crc = calculate_crc32c(crc, cp, strlen(cp) + 1);
277 mac[3] = (crc >> 24) ^ ((crc >> 16) & 0xff);
278 mac[4] = (crc >> 8) & 0xff;
284 * ether_request_mac - try to find usable MAC address.
287 ether_request_mac(device_t dev, uint8_t *mac)
292 * "ethaddr" is passed via envp on RedBoot platforms
293 * "kmac" is passed via argv on RouterBOOT platforms
295 #if defined(RT305X_UBOOT) || defined(__REDBOOT__) || defined(__ROUTERBOOT__)
296 if ((var = kern_getenv("ethaddr")) != NULL ||
297 (var = kern_getenv("kmac")) != NULL ) {
298 if(!macaddr_atoi(var, mac)) {
299 printf("%s: use %s macaddr from KENV\n",
300 device_get_nameunit(dev), var);
310 * hint.[dev].[unit].macaddr
312 if (!resource_string_value(device_get_name(dev),
313 device_get_unit(dev), "macaddr", (const char **)&var)) {
314 if(!macaddr_atoi(var, mac)) {
315 printf("%s: use %s macaddr from hints\n",
316 device_get_nameunit(dev), var);
321 #ifdef USE_GENERATED_MAC_ADDRESS
324 device_printf(dev, "use generated %02x:%02x:%02x:%02x:%02x:%02x "
325 "macaddr\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
335 device_printf(dev, "use hardcoded 00:18:e7:d5:83:90 macaddr\n");
345 reset_freng(struct rt_softc *sc)
347 /* XXX hard reset kills everything so skip it ... */
352 rt_attach(device_t dev)
362 sc = device_get_softc(dev);
366 node = ofw_bus_get_node(sc->dev);
369 mtx_init(&sc->lock, device_get_nameunit(dev), MTX_NETWORK_LOCK,
370 MTX_DEF | MTX_RECURSE);
373 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
374 RF_ACTIVE | RF_SHAREABLE);
375 if (sc->mem == NULL) {
376 device_printf(dev, "could not allocate memory resource\n");
381 sc->bst = rman_get_bustag(sc->mem);
382 sc->bsh = rman_get_bushandle(sc->mem);
385 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
387 if (sc->irq == NULL) {
389 "could not allocate interrupt resource\n");
395 sc->debug = rt_debug;
397 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
398 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
399 "debug", CTLFLAG_RW, &sc->debug, 0, "rt debug level");
405 if (sc->rt_chipid == RT_CHIPID_MT7620) {
406 sc->csum_fail_ip = MT7620_RXD_SRC_IP_CSUM_FAIL;
407 sc->csum_fail_l4 = MT7620_RXD_SRC_L4_CSUM_FAIL;
408 } else if (sc->rt_chipid == RT_CHIPID_MT7621) {
409 sc->csum_fail_ip = MT7621_RXD_SRC_IP_CSUM_FAIL;
410 sc->csum_fail_l4 = MT7621_RXD_SRC_L4_CSUM_FAIL;
412 sc->csum_fail_ip = RT305X_RXD_SRC_IP_CSUM_FAIL;
413 sc->csum_fail_l4 = RT305X_RXD_SRC_L4_CSUM_FAIL;
416 /* Fill in soc-specific registers map */
417 switch(sc->rt_chipid) {
418 case RT_CHIPID_MT7620:
419 case RT_CHIPID_MT7621:
420 sc->gdma1_base = MT7620_GDMA1_BASE;
422 case RT_CHIPID_RT5350:
423 device_printf(dev, "%cT%x Ethernet MAC (rev 0x%08x)\n",
424 sc->rt_chipid >= 0x7600 ? 'M' : 'R',
425 sc->rt_chipid, sc->mac_rev);
426 /* RT5350: No GDMA, PSE, CDMA, PPE */
427 RT_WRITE(sc, GE_PORT_BASE + 0x0C00, // UDPCS, TCPCS, IPCS=1
428 RT_READ(sc, GE_PORT_BASE + 0x0C00) | (0x7<<16));
429 sc->delay_int_cfg=RT5350_PDMA_BASE+RT5350_DELAY_INT_CFG;
430 sc->fe_int_status=RT5350_FE_INT_STATUS;
431 sc->fe_int_enable=RT5350_FE_INT_ENABLE;
432 sc->pdma_glo_cfg=RT5350_PDMA_BASE+RT5350_PDMA_GLO_CFG;
433 sc->pdma_rst_idx=RT5350_PDMA_BASE+RT5350_PDMA_RST_IDX;
434 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
435 sc->tx_base_ptr[i]=RT5350_PDMA_BASE+RT5350_TX_BASE_PTR(i);
436 sc->tx_max_cnt[i]=RT5350_PDMA_BASE+RT5350_TX_MAX_CNT(i);
437 sc->tx_ctx_idx[i]=RT5350_PDMA_BASE+RT5350_TX_CTX_IDX(i);
438 sc->tx_dtx_idx[i]=RT5350_PDMA_BASE+RT5350_TX_DTX_IDX(i);
441 sc->rx_base_ptr[0]=RT5350_PDMA_BASE+RT5350_RX_BASE_PTR0;
442 sc->rx_max_cnt[0]=RT5350_PDMA_BASE+RT5350_RX_MAX_CNT0;
443 sc->rx_calc_idx[0]=RT5350_PDMA_BASE+RT5350_RX_CALC_IDX0;
444 sc->rx_drx_idx[0]=RT5350_PDMA_BASE+RT5350_RX_DRX_IDX0;
445 sc->rx_base_ptr[1]=RT5350_PDMA_BASE+RT5350_RX_BASE_PTR1;
446 sc->rx_max_cnt[1]=RT5350_PDMA_BASE+RT5350_RX_MAX_CNT1;
447 sc->rx_calc_idx[1]=RT5350_PDMA_BASE+RT5350_RX_CALC_IDX1;
448 sc->rx_drx_idx[1]=RT5350_PDMA_BASE+RT5350_RX_DRX_IDX1;
449 sc->int_rx_done_mask=RT5350_INT_RXQ0_DONE;
450 sc->int_tx_done_mask=RT5350_INT_TXQ0_DONE;
453 device_printf(dev, "RT305XF Ethernet MAC (rev 0x%08x)\n",
455 sc->gdma1_base = GDMA1_BASE;
456 sc->delay_int_cfg=PDMA_BASE+DELAY_INT_CFG;
457 sc->fe_int_status=GE_PORT_BASE+FE_INT_STATUS;
458 sc->fe_int_enable=GE_PORT_BASE+FE_INT_ENABLE;
459 sc->pdma_glo_cfg=PDMA_BASE+PDMA_GLO_CFG;
460 sc->pdma_rst_idx=PDMA_BASE+PDMA_RST_IDX;
461 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
462 sc->tx_base_ptr[i]=PDMA_BASE+TX_BASE_PTR(i);
463 sc->tx_max_cnt[i]=PDMA_BASE+TX_MAX_CNT(i);
464 sc->tx_ctx_idx[i]=PDMA_BASE+TX_CTX_IDX(i);
465 sc->tx_dtx_idx[i]=PDMA_BASE+TX_DTX_IDX(i);
468 sc->rx_base_ptr[0]=PDMA_BASE+RX_BASE_PTR0;
469 sc->rx_max_cnt[0]=PDMA_BASE+RX_MAX_CNT0;
470 sc->rx_calc_idx[0]=PDMA_BASE+RX_CALC_IDX0;
471 sc->rx_drx_idx[0]=PDMA_BASE+RX_DRX_IDX0;
472 sc->int_rx_done_mask=INT_RX_DONE;
473 sc->int_tx_done_mask=INT_TXQ0_DONE;
476 if (sc->gdma1_base != 0)
477 RT_WRITE(sc, sc->gdma1_base + GDMA_FWD_CFG,
479 GDM_ICS_EN | /* Enable IP Csum */
480 GDM_TCS_EN | /* Enable TCP Csum */
481 GDM_UCS_EN | /* Enable UDP Csum */
482 GDM_STRPCRC | /* Strip CRC from packet */
483 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* fwd UCast to CPU */
484 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* fwd BCast to CPU */
485 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* fwd MCast to CPU */
486 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* fwd Other to CPU */
490 if (sc->rt_chipid == RT_CHIPID_RT2880 ||
491 sc->rt_chipid == RT_CHIPID_RT3883) {
492 if (OF_getprop(node, "port-mode", fdtval, sizeof(fdtval)) > 0 &&
493 strcmp(fdtval, "gigasw") == 0)
494 RT_WRITE(sc, MDIO_CFG, MDIO_2880_GIGA_INIT);
496 RT_WRITE(sc, MDIO_CFG, MDIO_2880_100T_INIT);
500 /* allocate Tx and Rx rings */
501 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
502 error = rt_alloc_tx_ring(sc, &sc->tx_ring[i], i);
504 device_printf(dev, "could not allocate Tx ring #%d\n",
510 sc->tx_ring_mgtqid = 5;
511 for (i = 0; i < sc->rx_ring_count; i++) {
512 error = rt_alloc_rx_ring(sc, &sc->rx_ring[i], i);
514 device_printf(dev, "could not allocate Rx ring\n");
519 callout_init(&sc->periodic_ch, 0);
520 callout_init_mtx(&sc->tx_watchdog_ch, &sc->lock, 0);
522 ifp = sc->ifp = if_alloc(IFT_ETHER);
524 device_printf(dev, "could not if_alloc()\n");
530 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
531 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
532 ifp->if_init = rt_init;
533 ifp->if_ioctl = rt_ioctl;
534 ifp->if_start = rt_start;
535 #define RT_TX_QLEN 256
537 IFQ_SET_MAXLEN(&ifp->if_snd, RT_TX_QLEN);
538 ifp->if_snd.ifq_drv_maxlen = RT_TX_QLEN;
539 IFQ_SET_READY(&ifp->if_snd);
541 #ifdef IF_RT_PHY_SUPPORT
542 error = mii_attach(dev, &sc->rt_miibus, ifp, rt_ifmedia_upd,
543 rt_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
545 device_printf(dev, "attaching PHYs failed\n");
550 ifmedia_init(&sc->rt_ifmedia, 0, rt_ifmedia_upd, rt_ifmedia_sts);
551 ifmedia_add(&sc->rt_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0,
553 ifmedia_set(&sc->rt_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX);
555 #endif /* IF_RT_PHY_SUPPORT */
557 ether_request_mac(dev, sc->mac_addr);
558 ether_ifattach(ifp, sc->mac_addr);
561 * Tell the upper layer(s) we support long frames.
563 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
564 ifp->if_capabilities |= IFCAP_VLAN_MTU;
565 ifp->if_capenable |= IFCAP_VLAN_MTU;
566 ifp->if_capabilities |= IFCAP_RXCSUM|IFCAP_TXCSUM;
567 ifp->if_capenable |= IFCAP_RXCSUM|IFCAP_TXCSUM;
569 /* init task queue */
570 NET_TASK_INIT(&sc->rx_done_task, 0, rt_rx_done_task, sc);
571 TASK_INIT(&sc->tx_done_task, 0, rt_tx_done_task, sc);
572 TASK_INIT(&sc->periodic_task, 0, rt_periodic_task, sc);
574 sc->rx_process_limit = 100;
576 sc->taskqueue = taskqueue_create("rt_taskq", M_NOWAIT,
577 taskqueue_thread_enqueue, &sc->taskqueue);
579 taskqueue_start_threads(&sc->taskqueue, 1, PI_NET, "%s taskq",
580 device_get_nameunit(sc->dev));
582 rt_sysctl_attach(sc);
584 /* set up interrupt */
585 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
586 NULL, (sc->rt_chipid == RT_CHIPID_RT5350 ||
587 sc->rt_chipid == RT_CHIPID_MT7620 ||
588 sc->rt_chipid == RT_CHIPID_MT7621) ? rt_rt5350_intr : rt_intr,
591 printf("%s: could not set up interrupt\n",
592 device_get_nameunit(dev));
596 device_printf(dev, "debug var at %#08x\n", (u_int)&(sc->debug));
602 /* free Tx and Rx rings */
603 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
604 rt_free_tx_ring(sc, &sc->tx_ring[i]);
606 for (i = 0; i < sc->rx_ring_count; i++)
607 rt_free_rx_ring(sc, &sc->rx_ring[i]);
609 mtx_destroy(&sc->lock);
612 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
616 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
626 rt_ifmedia_upd(struct ifnet *ifp)
629 #ifdef IF_RT_PHY_SUPPORT
630 struct mii_data *mii;
631 struct mii_softc *miisc;
637 mii = device_get_softc(sc->rt_miibus);
638 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
640 error = mii_mediachg(mii);
645 #else /* !IF_RT_PHY_SUPPORT */
648 struct ifmedia_entry *ife;
651 ifm = &sc->rt_ifmedia;
654 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
657 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
658 device_printf(sc->dev,
659 "AUTO is not supported for multiphy MAC");
667 #endif /* IF_RT_PHY_SUPPORT */
671 * Report current media status.
674 rt_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
676 #ifdef IF_RT_PHY_SUPPORT
678 struct mii_data *mii;
683 mii = device_get_softc(sc->rt_miibus);
685 ifmr->ifm_active = mii->mii_media_active;
686 ifmr->ifm_status = mii->mii_media_status;
687 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
688 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
690 #else /* !IF_RT_PHY_SUPPORT */
692 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
693 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
694 #endif /* IF_RT_PHY_SUPPORT */
698 rt_detach(device_t dev)
704 sc = device_get_softc(dev);
707 RT_DPRINTF(sc, RT_DEBUG_ANY, "detaching\n");
711 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
713 callout_stop(&sc->periodic_ch);
714 callout_stop(&sc->tx_watchdog_ch);
716 taskqueue_drain(sc->taskqueue, &sc->rx_done_task);
717 taskqueue_drain(sc->taskqueue, &sc->tx_done_task);
718 taskqueue_drain(sc->taskqueue, &sc->periodic_task);
720 /* free Tx and Rx rings */
721 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
722 rt_free_tx_ring(sc, &sc->tx_ring[i]);
723 for (i = 0; i < sc->rx_ring_count; i++)
724 rt_free_rx_ring(sc, &sc->rx_ring[i]);
728 #ifdef IF_RT_PHY_SUPPORT
729 if (sc->rt_miibus != NULL)
730 device_delete_child(dev, sc->rt_miibus);
736 taskqueue_free(sc->taskqueue);
738 mtx_destroy(&sc->lock);
740 bus_generic_detach(dev);
741 bus_teardown_intr(dev, sc->irq, sc->irqh);
742 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq);
743 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem);
749 rt_shutdown(device_t dev)
753 sc = device_get_softc(dev);
754 RT_DPRINTF(sc, RT_DEBUG_ANY, "shutting down\n");
761 rt_suspend(device_t dev)
765 sc = device_get_softc(dev);
766 RT_DPRINTF(sc, RT_DEBUG_ANY, "suspending\n");
773 rt_resume(device_t dev)
778 sc = device_get_softc(dev);
781 RT_DPRINTF(sc, RT_DEBUG_ANY, "resuming\n");
783 if (ifp->if_flags & IFF_UP)
790 * rt_init_locked - Run initialization process having locked mtx.
793 rt_init_locked(void *priv)
797 #ifdef IF_RT_PHY_SUPPORT
798 struct mii_data *mii;
805 #ifdef IF_RT_PHY_SUPPORT
806 mii = device_get_softc(sc->rt_miibus);
809 RT_DPRINTF(sc, RT_DEBUG_ANY, "initializing\n");
811 RT_SOFTC_ASSERT_LOCKED(sc);
814 //RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET);
815 //rt305x_sysctl_set(SYSCTL_RSTCTRL, SYSCTL_RSTCTRL_FRENG);
817 /* Fwd to CPU (uni|broad|multi)cast and Unknown */
818 if (sc->gdma1_base != 0)
819 RT_WRITE(sc, sc->gdma1_base + GDMA_FWD_CFG,
821 GDM_ICS_EN | /* Enable IP Csum */
822 GDM_TCS_EN | /* Enable TCP Csum */
823 GDM_UCS_EN | /* Enable UDP Csum */
824 GDM_STRPCRC | /* Strip CRC from packet */
825 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* fwd UCast to CPU */
826 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* fwd BCast to CPU */
827 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* fwd MCast to CPU */
828 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* fwd Other to CPU */
831 /* disable DMA engine */
832 RT_WRITE(sc, sc->pdma_glo_cfg, 0);
833 RT_WRITE(sc, sc->pdma_rst_idx, 0xffffffff);
835 /* wait while DMA engine is busy */
836 for (ntries = 0; ntries < 100; ntries++) {
837 tmp = RT_READ(sc, sc->pdma_glo_cfg);
838 if (!(tmp & (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)))
844 device_printf(sc->dev, "timeout waiting for DMA engine\n");
848 /* reset Rx and Tx rings */
849 tmp = FE_RST_DRX_IDX0 |
855 RT_WRITE(sc, sc->pdma_rst_idx, tmp);
857 /* XXX switch set mac address */
858 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
859 rt_reset_tx_ring(sc, &sc->tx_ring[i]);
861 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
862 /* update TX_BASE_PTRx */
863 RT_WRITE(sc, sc->tx_base_ptr[i],
864 sc->tx_ring[i].desc_phys_addr);
865 RT_WRITE(sc, sc->tx_max_cnt[i],
866 RT_SOFTC_TX_RING_DESC_COUNT);
867 RT_WRITE(sc, sc->tx_ctx_idx[i], 0);
871 for (i = 0; i < sc->rx_ring_count; i++)
872 rt_reset_rx_ring(sc, &sc->rx_ring[i]);
874 /* update RX_BASE_PTRx */
875 for (i = 0; i < sc->rx_ring_count; i++) {
876 RT_WRITE(sc, sc->rx_base_ptr[i],
877 sc->rx_ring[i].desc_phys_addr);
878 RT_WRITE(sc, sc->rx_max_cnt[i],
879 RT_SOFTC_RX_RING_DATA_COUNT);
880 RT_WRITE(sc, sc->rx_calc_idx[i],
881 RT_SOFTC_RX_RING_DATA_COUNT - 1);
884 /* write back DDONE, 16byte burst enable RX/TX DMA */
885 tmp = FE_TX_WB_DDONE | FE_DMA_BT_SIZE16 | FE_RX_DMA_EN | FE_TX_DMA_EN;
886 if (sc->rt_chipid == RT_CHIPID_MT7620 ||
887 sc->rt_chipid == RT_CHIPID_MT7621)
889 RT_WRITE(sc, sc->pdma_glo_cfg, tmp);
891 /* disable interrupts mitigation */
892 RT_WRITE(sc, sc->delay_int_cfg, 0);
894 /* clear pending interrupts */
895 RT_WRITE(sc, sc->fe_int_status, 0xffffffff);
897 /* enable interrupts */
898 if (sc->rt_chipid == RT_CHIPID_RT5350 ||
899 sc->rt_chipid == RT_CHIPID_MT7620 ||
900 sc->rt_chipid == RT_CHIPID_MT7621)
901 tmp = RT5350_INT_TX_COHERENT |
902 RT5350_INT_RX_COHERENT |
903 RT5350_INT_TXQ3_DONE |
904 RT5350_INT_TXQ2_DONE |
905 RT5350_INT_TXQ1_DONE |
906 RT5350_INT_TXQ0_DONE |
907 RT5350_INT_RXQ1_DONE |
908 RT5350_INT_RXQ0_DONE;
927 sc->intr_enable_mask = tmp;
929 RT_WRITE(sc, sc->fe_int_enable, tmp);
931 if (rt_txrx_enable(sc) != 0)
934 #ifdef IF_RT_PHY_SUPPORT
935 if (mii) mii_mediachg(mii);
936 #endif /* IF_RT_PHY_SUPPORT */
938 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
939 ifp->if_drv_flags |= IFF_DRV_RUNNING;
941 sc->periodic_round = 0;
943 callout_reset(&sc->periodic_ch, hz / 10, rt_periodic, sc);
952 * rt_init - lock and initialize device.
966 * rt_stop_locked - stop TX/RX w/ lock
969 rt_stop_locked(void *priv)
977 RT_DPRINTF(sc, RT_DEBUG_ANY, "stopping\n");
979 RT_SOFTC_ASSERT_LOCKED(sc);
981 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
982 callout_stop(&sc->periodic_ch);
983 callout_stop(&sc->tx_watchdog_ch);
985 taskqueue_block(sc->taskqueue);
988 * Sometime rt_stop_locked called from isr and we get panic
989 * When found, I fix it
992 taskqueue_drain(sc->taskqueue, &sc->rx_done_task);
993 taskqueue_drain(sc->taskqueue, &sc->tx_done_task);
994 taskqueue_drain(sc->taskqueue, &sc->periodic_task);
998 /* disable interrupts */
999 RT_WRITE(sc, sc->fe_int_enable, 0);
1001 if(sc->rt_chipid != RT_CHIPID_RT5350 &&
1002 sc->rt_chipid != RT_CHIPID_MT7620 &&
1003 sc->rt_chipid != RT_CHIPID_MT7621) {
1005 RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET);
1008 if (sc->gdma1_base != 0)
1009 RT_WRITE(sc, sc->gdma1_base + GDMA_FWD_CFG,
1011 GDM_ICS_EN | /* Enable IP Csum */
1012 GDM_TCS_EN | /* Enable TCP Csum */
1013 GDM_UCS_EN | /* Enable UDP Csum */
1014 GDM_STRPCRC | /* Strip CRC from packet */
1015 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* fwd UCast to CPU */
1016 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* fwd BCast to CPU */
1017 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* fwd MCast to CPU */
1018 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* fwd Other to CPU */
1025 struct rt_softc *sc;
1030 RT_SOFTC_UNLOCK(sc);
1034 * rt_tx_data - transmit packet.
1037 rt_tx_data(struct rt_softc *sc, struct mbuf *m, int qid)
1040 struct rt_softc_tx_ring *ring;
1041 struct rt_softc_tx_data *data;
1042 struct rt_txdesc *desc;
1044 bus_dma_segment_t dma_seg[RT_SOFTC_MAX_SCATTER];
1045 int error, ndmasegs, ndescs, i;
1047 KASSERT(qid >= 0 && qid < RT_SOFTC_TX_RING_COUNT,
1048 ("%s: Tx data: invalid qid=%d\n",
1049 device_get_nameunit(sc->dev), qid));
1051 RT_SOFTC_TX_RING_ASSERT_LOCKED(&sc->tx_ring[qid]);
1054 ring = &sc->tx_ring[qid];
1055 desc = &ring->desc[ring->desc_cur];
1056 data = &ring->data[ring->data_cur];
1058 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag, data->dma_map, m,
1059 dma_seg, &ndmasegs, 0);
1061 /* too many fragments, linearize */
1063 RT_DPRINTF(sc, RT_DEBUG_TX,
1064 "could not load mbuf DMA map, trying to linearize "
1065 "mbuf: ndmasegs=%d, len=%d, error=%d\n",
1066 ndmasegs, m->m_pkthdr.len, error);
1068 m_d = m_collapse(m, M_NOWAIT, 16);
1076 sc->tx_defrag_packets++;
1078 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag,
1079 data->dma_map, m, dma_seg, &ndmasegs, 0);
1081 device_printf(sc->dev, "could not load mbuf DMA map: "
1082 "ndmasegs=%d, len=%d, error=%d\n",
1083 ndmasegs, m->m_pkthdr.len, error);
1089 if (m->m_pkthdr.len == 0)
1092 /* determine how many Tx descs are required */
1093 ndescs = 1 + ndmasegs / 2;
1094 if ((ring->desc_queued + ndescs) >
1095 (RT_SOFTC_TX_RING_DESC_COUNT - 2)) {
1096 RT_DPRINTF(sc, RT_DEBUG_TX,
1097 "there are not enough Tx descs\n");
1099 sc->no_tx_desc_avail++;
1101 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
1108 /* set up Tx descs */
1109 for (i = 0; i < ndmasegs; i += 2) {
1110 /* TODO: this needs to be refined as MT7620 for example has
1111 * a different word3 layout than RT305x and RT5350 (the last
1112 * one doesn't use word3 at all). And so does MT7621...
1115 if (sc->rt_chipid != RT_CHIPID_MT7621) {
1116 /* Set destination */
1117 if (sc->rt_chipid != RT_CHIPID_MT7620)
1118 desc->dst = (TXDSCR_DST_PORT_GDMA1);
1120 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1121 desc->dst |= (TXDSCR_IP_CSUM_GEN |
1122 TXDSCR_UDP_CSUM_GEN | TXDSCR_TCP_CSUM_GEN);
1136 desc->sdp0 = htole32(dma_seg[i].ds_addr);
1137 desc->sdl0 = htole16(dma_seg[i].ds_len |
1138 ( ((i+1) == ndmasegs )?RT_TXDESC_SDL0_LASTSEG:0 ));
1140 if ((i+1) < ndmasegs) {
1141 desc->sdp1 = htole32(dma_seg[i+1].ds_addr);
1142 desc->sdl1 = htole16(dma_seg[i+1].ds_len |
1143 ( ((i+2) == ndmasegs )?RT_TXDESC_SDL1_LASTSEG:0 ));
1149 if ((i+2) < ndmasegs) {
1150 ring->desc_queued++;
1151 ring->desc_cur = (ring->desc_cur + 1) %
1152 RT_SOFTC_TX_RING_DESC_COUNT;
1154 desc = &ring->desc[ring->desc_cur];
1157 RT_DPRINTF(sc, RT_DEBUG_TX, "sending data: len=%d, ndmasegs=%d, "
1158 "DMA ds_len=%d/%d/%d/%d/%d\n",
1159 m->m_pkthdr.len, ndmasegs,
1160 (int) dma_seg[0].ds_len,
1161 (int) dma_seg[1].ds_len,
1162 (int) dma_seg[2].ds_len,
1163 (int) dma_seg[3].ds_len,
1164 (int) dma_seg[4].ds_len);
1166 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map,
1167 BUS_DMASYNC_PREWRITE);
1168 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
1169 BUS_DMASYNC_PREWRITE);
1170 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
1171 BUS_DMASYNC_PREWRITE);
1173 ring->desc_queued++;
1174 ring->desc_cur = (ring->desc_cur + 1) % RT_SOFTC_TX_RING_DESC_COUNT;
1176 ring->data_queued++;
1177 ring->data_cur = (ring->data_cur + 1) % RT_SOFTC_TX_RING_DATA_COUNT;
1180 RT_WRITE(sc, sc->tx_ctx_idx[qid], ring->desc_cur);
1186 * rt_start - start Transmit/Receive
1189 rt_start(struct ifnet *ifp)
1191 struct rt_softc *sc;
1193 int qid = 0 /* XXX must check QoS priority */;
1197 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1201 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1205 m->m_pkthdr.rcvif = NULL;
1207 RT_SOFTC_TX_RING_LOCK(&sc->tx_ring[qid]);
1209 if (sc->tx_ring[qid].data_queued >=
1210 RT_SOFTC_TX_RING_DATA_COUNT) {
1211 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]);
1213 RT_DPRINTF(sc, RT_DEBUG_TX,
1214 "if_start: Tx ring with qid=%d is full\n", qid);
1218 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1219 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1221 sc->tx_data_queue_full[qid]++;
1226 if (rt_tx_data(sc, m, qid) != 0) {
1227 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]);
1229 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1234 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]);
1235 sc->tx_timer = RT_TX_WATCHDOG_TIMEOUT;
1236 callout_reset(&sc->tx_watchdog_ch, hz, rt_tx_watchdog, sc);
1241 * rt_update_promisc - set/clear promiscuous mode. Unused yet, because
1242 * filtering done by attached Ethernet switch.
1245 rt_update_promisc(struct ifnet *ifp)
1247 struct rt_softc *sc;
1250 printf("%s: %s promiscuous mode\n",
1251 device_get_nameunit(sc->dev),
1252 (ifp->if_flags & IFF_PROMISC) ? "entering" : "leaving");
1256 * rt_ioctl - ioctl handler.
1259 rt_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1261 struct rt_softc *sc;
1263 #ifdef IF_RT_PHY_SUPPORT
1264 struct mii_data *mii;
1265 #endif /* IF_RT_PHY_SUPPORT */
1266 int error, startall;
1269 ifr = (struct ifreq *) data;
1277 if (ifp->if_flags & IFF_UP) {
1278 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1279 if ((ifp->if_flags ^ sc->if_flags) &
1281 rt_update_promisc(ifp);
1287 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1290 sc->if_flags = ifp->if_flags;
1291 RT_SOFTC_UNLOCK(sc);
1295 #ifdef IF_RT_PHY_SUPPORT
1296 mii = device_get_softc(sc->rt_miibus);
1297 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1299 error = ifmedia_ioctl(ifp, ifr, &sc->rt_ifmedia, cmd);
1300 #endif /* IF_RT_PHY_SUPPORT */
1303 error = ether_ioctl(ifp, cmd, data);
1310 * rt_periodic - Handler of PERIODIC interrupt
1313 rt_periodic(void *arg)
1315 struct rt_softc *sc;
1318 RT_DPRINTF(sc, RT_DEBUG_PERIODIC, "periodic\n");
1319 taskqueue_enqueue(sc->taskqueue, &sc->periodic_task);
1323 * rt_tx_watchdog - Handler of TX Watchdog
1326 rt_tx_watchdog(void *arg)
1328 struct rt_softc *sc;
1334 if (sc->tx_timer == 0)
1337 if (--sc->tx_timer == 0) {
1338 device_printf(sc->dev, "Tx watchdog timeout: resetting\n");
1341 * XXX: Commented out, because reset break input.
1346 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1347 sc->tx_watchdog_timeouts++;
1349 callout_reset(&sc->tx_watchdog_ch, hz, rt_tx_watchdog, sc);
1353 * rt_cnt_ppe_af - Handler of PPE Counter Table Almost Full interrupt
1356 rt_cnt_ppe_af(struct rt_softc *sc)
1359 RT_DPRINTF(sc, RT_DEBUG_INTR, "PPE Counter Table Almost Full\n");
1363 * rt_cnt_gdm_af - Handler of GDMA 1 & 2 Counter Table Almost Full interrupt
1366 rt_cnt_gdm_af(struct rt_softc *sc)
1369 RT_DPRINTF(sc, RT_DEBUG_INTR,
1370 "GDMA 1 & 2 Counter Table Almost Full\n");
1374 * rt_pse_p2_fc - Handler of PSE port2 (GDMA 2) flow control interrupt
1377 rt_pse_p2_fc(struct rt_softc *sc)
1380 RT_DPRINTF(sc, RT_DEBUG_INTR,
1381 "PSE port2 (GDMA 2) flow control asserted.\n");
1385 * rt_gdm_crc_drop - Handler of GDMA 1/2 discard a packet due to CRC error
1389 rt_gdm_crc_drop(struct rt_softc *sc)
1392 RT_DPRINTF(sc, RT_DEBUG_INTR,
1393 "GDMA 1 & 2 discard a packet due to CRC error\n");
1397 * rt_pse_buf_drop - Handler of buffer sharing limitation interrupt
1400 rt_pse_buf_drop(struct rt_softc *sc)
1403 RT_DPRINTF(sc, RT_DEBUG_INTR,
1404 "PSE discards a packet due to buffer sharing limitation\n");
1408 * rt_gdm_other_drop - Handler of discard on other reason interrupt
1411 rt_gdm_other_drop(struct rt_softc *sc)
1414 RT_DPRINTF(sc, RT_DEBUG_INTR,
1415 "GDMA 1 & 2 discard a packet due to other reason\n");
1419 * rt_pse_p1_fc - Handler of PSE port1 (GDMA 1) flow control interrupt
1422 rt_pse_p1_fc(struct rt_softc *sc)
1425 RT_DPRINTF(sc, RT_DEBUG_INTR,
1426 "PSE port1 (GDMA 1) flow control asserted.\n");
1430 * rt_pse_p0_fc - Handler of PSE port0 (CDMA) flow control interrupt
1433 rt_pse_p0_fc(struct rt_softc *sc)
1436 RT_DPRINTF(sc, RT_DEBUG_INTR,
1437 "PSE port0 (CDMA) flow control asserted.\n");
1441 * rt_pse_fq_empty - Handler of PSE free Q empty threshold reached interrupt
1444 rt_pse_fq_empty(struct rt_softc *sc)
1447 RT_DPRINTF(sc, RT_DEBUG_INTR,
1448 "PSE free Q empty threshold reached & forced drop "
1449 "condition occurred.\n");
1453 * rt_intr - main ISR
1458 struct rt_softc *sc;
1465 /* acknowledge interrupts */
1466 status = RT_READ(sc, sc->fe_int_status);
1467 RT_WRITE(sc, sc->fe_int_status, status);
1469 RT_DPRINTF(sc, RT_DEBUG_INTR, "interrupt: status=0x%08x\n", status);
1471 if (status == 0xffffffff || /* device likely went away */
1472 status == 0) /* not for us */
1477 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1480 if (status & CNT_PPE_AF)
1483 if (status & CNT_GDM_AF)
1486 if (status & PSE_P2_FC)
1489 if (status & GDM_CRC_DROP)
1490 rt_gdm_crc_drop(sc);
1492 if (status & PSE_BUF_DROP)
1493 rt_pse_buf_drop(sc);
1495 if (status & GDM_OTHER_DROP)
1496 rt_gdm_other_drop(sc);
1498 if (status & PSE_P1_FC)
1501 if (status & PSE_P0_FC)
1504 if (status & PSE_FQ_EMPTY)
1505 rt_pse_fq_empty(sc);
1507 if (status & INT_TX_COHERENT)
1508 rt_tx_coherent_intr(sc);
1510 if (status & INT_RX_COHERENT)
1511 rt_rx_coherent_intr(sc);
1513 if (status & RX_DLY_INT)
1514 rt_rx_delay_intr(sc);
1516 if (status & TX_DLY_INT)
1517 rt_tx_delay_intr(sc);
1519 if (status & INT_RX_DONE)
1522 if (status & INT_TXQ3_DONE)
1525 if (status & INT_TXQ2_DONE)
1528 if (status & INT_TXQ1_DONE)
1531 if (status & INT_TXQ0_DONE)
1536 * rt_rt5350_intr - main ISR for Ralink 5350 SoC
1539 rt_rt5350_intr(void *arg)
1541 struct rt_softc *sc;
1548 /* acknowledge interrupts */
1549 status = RT_READ(sc, sc->fe_int_status);
1550 RT_WRITE(sc, sc->fe_int_status, status);
1552 RT_DPRINTF(sc, RT_DEBUG_INTR, "interrupt: status=0x%08x\n", status);
1554 if (status == 0xffffffff || /* device likely went away */
1555 status == 0) /* not for us */
1560 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1563 if (status & RT5350_INT_TX_COHERENT)
1564 rt_tx_coherent_intr(sc);
1565 if (status & RT5350_INT_RX_COHERENT)
1566 rt_rx_coherent_intr(sc);
1567 if (status & RT5350_RX_DLY_INT)
1568 rt_rx_delay_intr(sc);
1569 if (status & RT5350_TX_DLY_INT)
1570 rt_tx_delay_intr(sc);
1571 if (status & RT5350_INT_RXQ1_DONE)
1573 if (status & RT5350_INT_RXQ0_DONE)
1575 if (status & RT5350_INT_TXQ3_DONE)
1577 if (status & RT5350_INT_TXQ2_DONE)
1579 if (status & RT5350_INT_TXQ1_DONE)
1581 if (status & RT5350_INT_TXQ0_DONE)
1586 rt_tx_coherent_intr(struct rt_softc *sc)
1591 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx coherent interrupt\n");
1593 sc->tx_coherent_interrupts++;
1595 /* restart DMA engine */
1596 tmp = RT_READ(sc, sc->pdma_glo_cfg);
1597 tmp &= ~(FE_TX_WB_DDONE | FE_TX_DMA_EN);
1598 RT_WRITE(sc, sc->pdma_glo_cfg, tmp);
1600 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
1601 rt_reset_tx_ring(sc, &sc->tx_ring[i]);
1603 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
1604 RT_WRITE(sc, sc->tx_base_ptr[i],
1605 sc->tx_ring[i].desc_phys_addr);
1606 RT_WRITE(sc, sc->tx_max_cnt[i],
1607 RT_SOFTC_TX_RING_DESC_COUNT);
1608 RT_WRITE(sc, sc->tx_ctx_idx[i], 0);
1615 * rt_rx_coherent_intr
1618 rt_rx_coherent_intr(struct rt_softc *sc)
1623 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx coherent interrupt\n");
1625 sc->rx_coherent_interrupts++;
1627 /* restart DMA engine */
1628 tmp = RT_READ(sc, sc->pdma_glo_cfg);
1629 tmp &= ~(FE_RX_DMA_EN);
1630 RT_WRITE(sc, sc->pdma_glo_cfg, tmp);
1633 for (i = 0; i < sc->rx_ring_count; i++)
1634 rt_reset_rx_ring(sc, &sc->rx_ring[i]);
1636 for (i = 0; i < sc->rx_ring_count; i++) {
1637 RT_WRITE(sc, sc->rx_base_ptr[i],
1638 sc->rx_ring[i].desc_phys_addr);
1639 RT_WRITE(sc, sc->rx_max_cnt[i],
1640 RT_SOFTC_RX_RING_DATA_COUNT);
1641 RT_WRITE(sc, sc->rx_calc_idx[i],
1642 RT_SOFTC_RX_RING_DATA_COUNT - 1);
1649 * rt_rx_intr - a packet received
1652 rt_rx_intr(struct rt_softc *sc, int qid)
1654 KASSERT(qid >= 0 && qid < sc->rx_ring_count,
1655 ("%s: Rx interrupt: invalid qid=%d\n",
1656 device_get_nameunit(sc->dev), qid));
1658 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx interrupt\n");
1659 sc->rx_interrupts[qid]++;
1662 if (!(sc->intr_disable_mask & (sc->int_rx_done_mask << qid))) {
1663 rt_intr_disable(sc, (sc->int_rx_done_mask << qid));
1664 taskqueue_enqueue(sc->taskqueue, &sc->rx_done_task);
1667 sc->intr_pending_mask |= (sc->int_rx_done_mask << qid);
1668 RT_SOFTC_UNLOCK(sc);
1672 rt_rx_delay_intr(struct rt_softc *sc)
1675 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx delay interrupt\n");
1676 sc->rx_delay_interrupts++;
1680 rt_tx_delay_intr(struct rt_softc *sc)
1683 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx delay interrupt\n");
1684 sc->tx_delay_interrupts++;
1688 * rt_tx_intr - Transsmition of packet done
1691 rt_tx_intr(struct rt_softc *sc, int qid)
1694 KASSERT(qid >= 0 && qid < RT_SOFTC_TX_RING_COUNT,
1695 ("%s: Tx interrupt: invalid qid=%d\n",
1696 device_get_nameunit(sc->dev), qid));
1698 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx interrupt: qid=%d\n", qid);
1700 sc->tx_interrupts[qid]++;
1703 if (!(sc->intr_disable_mask & (sc->int_tx_done_mask << qid))) {
1704 rt_intr_disable(sc, (sc->int_tx_done_mask << qid));
1705 taskqueue_enqueue(sc->taskqueue, &sc->tx_done_task);
1708 sc->intr_pending_mask |= (sc->int_tx_done_mask << qid);
1709 RT_SOFTC_UNLOCK(sc);
1713 * rt_rx_done_task - run RX task
1716 rt_rx_done_task(void *context, int pending)
1718 struct rt_softc *sc;
1725 RT_DPRINTF(sc, RT_DEBUG_RX, "Rx done task\n");
1727 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1730 sc->intr_pending_mask &= ~sc->int_rx_done_mask;
1732 again = rt_rx_eof(sc, &sc->rx_ring[0], sc->rx_process_limit);
1736 if ((sc->intr_pending_mask & sc->int_rx_done_mask) || again) {
1737 RT_DPRINTF(sc, RT_DEBUG_RX,
1738 "Rx done task: scheduling again\n");
1739 taskqueue_enqueue(sc->taskqueue, &sc->rx_done_task);
1741 rt_intr_enable(sc, sc->int_rx_done_mask);
1744 RT_SOFTC_UNLOCK(sc);
1748 * rt_tx_done_task - check for pending TX task in all queues
1751 rt_tx_done_task(void *context, int pending)
1753 struct rt_softc *sc;
1761 RT_DPRINTF(sc, RT_DEBUG_TX, "Tx done task\n");
1763 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1766 for (i = RT_SOFTC_TX_RING_COUNT - 1; i >= 0; i--) {
1767 if (sc->intr_pending_mask & (sc->int_tx_done_mask << i)) {
1768 sc->intr_pending_mask &= ~(sc->int_tx_done_mask << i);
1769 rt_tx_eof(sc, &sc->tx_ring[i]);
1775 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1777 if(sc->rt_chipid == RT_CHIPID_RT5350 ||
1778 sc->rt_chipid == RT_CHIPID_MT7620 ||
1779 sc->rt_chipid == RT_CHIPID_MT7621)
1781 RT5350_INT_TXQ3_DONE |
1782 RT5350_INT_TXQ2_DONE |
1783 RT5350_INT_TXQ1_DONE |
1784 RT5350_INT_TXQ0_DONE);
1794 rt_intr_enable(sc, ~sc->intr_pending_mask &
1795 (sc->intr_disable_mask & intr_mask));
1797 if (sc->intr_pending_mask & intr_mask) {
1798 RT_DPRINTF(sc, RT_DEBUG_TX,
1799 "Tx done task: scheduling again\n");
1800 taskqueue_enqueue(sc->taskqueue, &sc->tx_done_task);
1803 RT_SOFTC_UNLOCK(sc);
1805 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1810 * rt_periodic_task - run periodic task
1813 rt_periodic_task(void *context, int pending)
1815 struct rt_softc *sc;
1821 RT_DPRINTF(sc, RT_DEBUG_PERIODIC, "periodic task: round=%lu\n",
1822 sc->periodic_round);
1824 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1828 sc->periodic_round++;
1829 rt_update_stats(sc);
1831 if ((sc->periodic_round % 10) == 0) {
1832 rt_update_raw_counters(sc);
1836 RT_SOFTC_UNLOCK(sc);
1837 callout_reset(&sc->periodic_ch, hz / 10, rt_periodic, sc);
1841 * rt_rx_eof - check for frames that done by DMA engine and pass it into
1842 * network subsystem.
1845 rt_rx_eof(struct rt_softc *sc, struct rt_softc_rx_ring *ring, int limit)
1848 /* struct rt_softc_rx_ring *ring; */
1849 struct rt_rxdesc *desc;
1850 struct rt_softc_rx_data *data;
1851 struct mbuf *m, *mnew;
1852 bus_dma_segment_t segs[1];
1853 bus_dmamap_t dma_map;
1854 uint32_t index, desc_flags;
1855 int error, nsegs, len, nframes;
1858 /* ring = &sc->rx_ring[0]; */
1862 while (limit != 0) {
1863 index = RT_READ(sc, sc->rx_drx_idx[0]);
1864 if (ring->cur == index)
1867 desc = &ring->desc[ring->cur];
1868 data = &ring->data[ring->cur];
1870 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
1871 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1874 if ( sc->debug & RT_DEBUG_RX ) {
1875 printf("\nRX Descriptor[%#08x] dump:\n", (u_int)desc);
1876 hexdump(desc, 16, 0, 0);
1877 printf("-----------------------------------\n");
1881 /* XXX Sometime device don`t set DDONE bit */
1883 if (!(desc->sdl0 & htole16(RT_RXDESC_SDL0_DDONE))) {
1884 RT_DPRINTF(sc, RT_DEBUG_RX, "DDONE=0, try next\n");
1889 len = le16toh(desc->sdl0) & 0x3fff;
1890 RT_DPRINTF(sc, RT_DEBUG_RX, "new frame len=%d\n", len);
1894 mnew = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
1897 sc->rx_mbuf_alloc_errors++;
1898 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1902 mnew->m_len = mnew->m_pkthdr.len = MJUMPAGESIZE;
1904 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag,
1905 ring->spare_dma_map, mnew, segs, &nsegs, BUS_DMA_NOWAIT);
1907 RT_DPRINTF(sc, RT_DEBUG_RX,
1908 "could not load Rx mbuf DMA map: "
1909 "error=%d, nsegs=%d\n",
1914 sc->rx_mbuf_dmamap_errors++;
1915 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1920 KASSERT(nsegs == 1, ("%s: too many DMA segments",
1921 device_get_nameunit(sc->dev)));
1923 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
1924 BUS_DMASYNC_POSTREAD);
1925 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
1927 dma_map = data->dma_map;
1928 data->dma_map = ring->spare_dma_map;
1929 ring->spare_dma_map = dma_map;
1931 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
1932 BUS_DMASYNC_PREREAD);
1935 desc_flags = desc->word3;
1938 /* Add 2 for proper align of RX IP header */
1939 desc->sdp0 = htole32(segs[0].ds_addr+2);
1940 desc->sdl0 = htole32(segs[0].ds_len-2);
1943 RT_DPRINTF(sc, RT_DEBUG_RX,
1944 "Rx frame: rxdesc flags=0x%08x\n", desc_flags);
1946 m->m_pkthdr.rcvif = ifp;
1947 /* Add 2 to fix data align, after sdp0 = addr + 2 */
1949 m->m_pkthdr.len = m->m_len = len;
1951 /* check for crc errors */
1952 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1953 /*check for valid checksum*/
1954 if (desc_flags & (sc->csum_fail_ip|sc->csum_fail_l4)) {
1955 RT_DPRINTF(sc, RT_DEBUG_RX,
1956 "rxdesc: crc error\n");
1958 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1960 if (!(ifp->if_flags & IFF_PROMISC)) {
1965 if ((desc_flags & sc->csum_fail_ip) == 0) {
1966 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1967 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1968 m->m_pkthdr.csum_data = 0xffff;
1970 m->m_flags &= ~M_HASFCS;
1973 (*ifp->if_input)(ifp, m);
1975 desc->sdl0 &= ~htole16(RT_RXDESC_SDL0_DDONE);
1977 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
1978 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1980 ring->cur = (ring->cur + 1) % RT_SOFTC_RX_RING_DATA_COUNT;
1986 RT_WRITE(sc, sc->rx_calc_idx[0],
1987 RT_SOFTC_RX_RING_DATA_COUNT - 1);
1989 RT_WRITE(sc, sc->rx_calc_idx[0],
1992 RT_DPRINTF(sc, RT_DEBUG_RX, "Rx eof: nframes=%d\n", nframes);
1994 sc->rx_packets += nframes;
1996 return (limit == 0);
2000 * rt_tx_eof - check for successful transmitted frames and mark their
2001 * descriptor as free.
2004 rt_tx_eof(struct rt_softc *sc, struct rt_softc_tx_ring *ring)
2007 struct rt_txdesc *desc;
2008 struct rt_softc_tx_data *data;
2010 int ndescs, nframes;
2018 index = RT_READ(sc, sc->tx_dtx_idx[ring->qid]);
2019 if (ring->desc_next == index)
2024 desc = &ring->desc[ring->desc_next];
2026 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2027 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2029 if (desc->sdl0 & htole16(RT_TXDESC_SDL0_LASTSEG) ||
2030 desc->sdl1 & htole16(RT_TXDESC_SDL1_LASTSEG)) {
2033 data = &ring->data[ring->data_next];
2035 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
2036 BUS_DMASYNC_POSTWRITE);
2037 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
2043 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2045 RT_SOFTC_TX_RING_LOCK(ring);
2046 ring->data_queued--;
2047 ring->data_next = (ring->data_next + 1) %
2048 RT_SOFTC_TX_RING_DATA_COUNT;
2049 RT_SOFTC_TX_RING_UNLOCK(ring);
2052 desc->sdl0 &= ~htole16(RT_TXDESC_SDL0_DDONE);
2054 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2055 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2057 RT_SOFTC_TX_RING_LOCK(ring);
2058 ring->desc_queued--;
2059 ring->desc_next = (ring->desc_next + 1) %
2060 RT_SOFTC_TX_RING_DESC_COUNT;
2061 RT_SOFTC_TX_RING_UNLOCK(ring);
2064 RT_DPRINTF(sc, RT_DEBUG_TX,
2065 "Tx eof: qid=%d, ndescs=%d, nframes=%d\n", ring->qid, ndescs,
2070 * rt_update_stats - query statistics counters and update related variables.
2073 rt_update_stats(struct rt_softc *sc)
2078 RT_DPRINTF(sc, RT_DEBUG_STATS, "update statistic: \n");
2079 /* XXX do update stats here */
2083 * rt_watchdog - reinit device on watchdog event.
2086 rt_watchdog(struct rt_softc *sc)
2092 if(sc->rt_chipid != RT_CHIPID_RT5350 &&
2093 sc->rt_chipid != RT_CHIPID_MT7620 &&
2094 sc->rt_chipid != RT_CHIPID_MT7621) {
2095 tmp = RT_READ(sc, PSE_BASE + CDMA_OQ_STA);
2097 RT_DPRINTF(sc, RT_DEBUG_WATCHDOG,
2098 "watchdog: PSE_IQ_STA=0x%08x\n", tmp);
2100 /* XXX: do not reset */
2102 if (((tmp >> P0_IQ_PCNT_SHIFT) & 0xff) != 0) {
2103 sc->tx_queue_not_empty[0]++;
2105 for (ntries = 0; ntries < 10; ntries++) {
2106 tmp = RT_READ(sc, PSE_BASE + PSE_IQ_STA);
2107 if (((tmp >> P0_IQ_PCNT_SHIFT) & 0xff) == 0)
2114 if (((tmp >> P1_IQ_PCNT_SHIFT) & 0xff) != 0) {
2115 sc->tx_queue_not_empty[1]++;
2117 for (ntries = 0; ntries < 10; ntries++) {
2118 tmp = RT_READ(sc, PSE_BASE + PSE_IQ_STA);
2119 if (((tmp >> P1_IQ_PCNT_SHIFT) & 0xff) == 0)
2129 * rt_update_raw_counters - update counters.
2132 rt_update_raw_counters(struct rt_softc *sc)
2135 sc->tx_bytes += RT_READ(sc, CNTR_BASE + GDMA_TX_GBCNT0);
2136 sc->tx_packets += RT_READ(sc, CNTR_BASE + GDMA_TX_GPCNT0);
2137 sc->tx_skip += RT_READ(sc, CNTR_BASE + GDMA_TX_SKIPCNT0);
2138 sc->tx_collision+= RT_READ(sc, CNTR_BASE + GDMA_TX_COLCNT0);
2140 sc->rx_bytes += RT_READ(sc, CNTR_BASE + GDMA_RX_GBCNT0);
2141 sc->rx_packets += RT_READ(sc, CNTR_BASE + GDMA_RX_GPCNT0);
2142 sc->rx_crc_err += RT_READ(sc, CNTR_BASE + GDMA_RX_CSUM_ERCNT0);
2143 sc->rx_short_err+= RT_READ(sc, CNTR_BASE + GDMA_RX_SHORT_ERCNT0);
2144 sc->rx_long_err += RT_READ(sc, CNTR_BASE + GDMA_RX_LONG_ERCNT0);
2145 sc->rx_phy_err += RT_READ(sc, CNTR_BASE + GDMA_RX_FERCNT0);
2146 sc->rx_fifo_overflows+= RT_READ(sc, CNTR_BASE + GDMA_RX_OERCNT0);
2150 rt_intr_enable(struct rt_softc *sc, uint32_t intr_mask)
2154 sc->intr_disable_mask &= ~intr_mask;
2155 tmp = sc->intr_enable_mask & ~sc->intr_disable_mask;
2156 RT_WRITE(sc, sc->fe_int_enable, tmp);
2160 rt_intr_disable(struct rt_softc *sc, uint32_t intr_mask)
2164 sc->intr_disable_mask |= intr_mask;
2165 tmp = sc->intr_enable_mask & ~sc->intr_disable_mask;
2166 RT_WRITE(sc, sc->fe_int_enable, tmp);
2170 * rt_txrx_enable - enable TX/RX DMA
2173 rt_txrx_enable(struct rt_softc *sc)
2181 /* enable Tx/Rx DMA engine */
2182 for (ntries = 0; ntries < 200; ntries++) {
2183 tmp = RT_READ(sc, sc->pdma_glo_cfg);
2184 if (!(tmp & (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)))
2190 if (ntries == 200) {
2191 device_printf(sc->dev, "timeout waiting for DMA engine\n");
2197 tmp |= FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
2198 RT_WRITE(sc, sc->pdma_glo_cfg, tmp);
2200 /* XXX set Rx filter */
2205 * rt_alloc_rx_ring - allocate RX DMA ring buffer
2208 rt_alloc_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring, int qid)
2210 struct rt_rxdesc *desc;
2211 struct rt_softc_rx_data *data;
2212 bus_dma_segment_t segs[1];
2213 int i, nsegs, error;
2215 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2216 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2217 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc), 1,
2218 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc),
2219 0, NULL, NULL, &ring->desc_dma_tag);
2221 device_printf(sc->dev,
2222 "could not create Rx desc DMA tag\n");
2226 error = bus_dmamem_alloc(ring->desc_dma_tag, (void **) &ring->desc,
2227 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_dma_map);
2229 device_printf(sc->dev,
2230 "could not allocate Rx desc DMA memory\n");
2234 error = bus_dmamap_load(ring->desc_dma_tag, ring->desc_dma_map,
2236 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc),
2237 rt_dma_map_addr, &ring->desc_phys_addr, 0);
2239 device_printf(sc->dev, "could not load Rx desc DMA map\n");
2243 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2244 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2245 MJUMPAGESIZE, 1, MJUMPAGESIZE, 0, NULL, NULL,
2246 &ring->data_dma_tag);
2248 device_printf(sc->dev,
2249 "could not create Rx data DMA tag\n");
2253 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) {
2254 desc = &ring->desc[i];
2255 data = &ring->data[i];
2257 error = bus_dmamap_create(ring->data_dma_tag, 0,
2260 device_printf(sc->dev, "could not create Rx data DMA "
2265 data->m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
2267 if (data->m == NULL) {
2268 device_printf(sc->dev, "could not allocate Rx mbuf\n");
2273 data->m->m_len = data->m->m_pkthdr.len = MJUMPAGESIZE;
2275 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag,
2276 data->dma_map, data->m, segs, &nsegs, BUS_DMA_NOWAIT);
2278 device_printf(sc->dev,
2279 "could not load Rx mbuf DMA map\n");
2283 KASSERT(nsegs == 1, ("%s: too many DMA segments",
2284 device_get_nameunit(sc->dev)));
2286 /* Add 2 for proper align of RX IP header */
2287 desc->sdp0 = htole32(segs[0].ds_addr+2);
2288 desc->sdl0 = htole32(segs[0].ds_len-2);
2291 error = bus_dmamap_create(ring->data_dma_tag, 0,
2292 &ring->spare_dma_map);
2294 device_printf(sc->dev,
2295 "could not create Rx spare DMA map\n");
2299 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2300 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2305 rt_free_rx_ring(sc, ring);
2310 * rt_reset_rx_ring - reset RX ring buffer
2313 rt_reset_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring)
2315 struct rt_rxdesc *desc;
2318 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) {
2319 desc = &ring->desc[i];
2320 desc->sdl0 &= ~htole16(RT_RXDESC_SDL0_DDONE);
2323 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2324 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2329 * rt_free_rx_ring - free memory used by RX ring buffer
2332 rt_free_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring)
2334 struct rt_softc_rx_data *data;
2337 if (ring->desc != NULL) {
2338 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2339 BUS_DMASYNC_POSTWRITE);
2340 bus_dmamap_unload(ring->desc_dma_tag, ring->desc_dma_map);
2341 bus_dmamem_free(ring->desc_dma_tag, ring->desc,
2342 ring->desc_dma_map);
2345 if (ring->desc_dma_tag != NULL)
2346 bus_dma_tag_destroy(ring->desc_dma_tag);
2348 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) {
2349 data = &ring->data[i];
2351 if (data->m != NULL) {
2352 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
2353 BUS_DMASYNC_POSTREAD);
2354 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
2358 if (data->dma_map != NULL)
2359 bus_dmamap_destroy(ring->data_dma_tag, data->dma_map);
2362 if (ring->spare_dma_map != NULL)
2363 bus_dmamap_destroy(ring->data_dma_tag, ring->spare_dma_map);
2365 if (ring->data_dma_tag != NULL)
2366 bus_dma_tag_destroy(ring->data_dma_tag);
2370 * rt_alloc_tx_ring - allocate TX ring buffer
2373 rt_alloc_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring, int qid)
2375 struct rt_softc_tx_data *data;
2378 mtx_init(&ring->lock, device_get_nameunit(sc->dev), NULL, MTX_DEF);
2380 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2381 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2382 RT_SOFTC_TX_RING_DESC_COUNT * sizeof(struct rt_txdesc), 1,
2383 RT_SOFTC_TX_RING_DESC_COUNT * sizeof(struct rt_txdesc),
2384 0, NULL, NULL, &ring->desc_dma_tag);
2386 device_printf(sc->dev,
2387 "could not create Tx desc DMA tag\n");
2391 error = bus_dmamem_alloc(ring->desc_dma_tag, (void **) &ring->desc,
2392 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_dma_map);
2394 device_printf(sc->dev,
2395 "could not allocate Tx desc DMA memory\n");
2399 error = bus_dmamap_load(ring->desc_dma_tag, ring->desc_dma_map,
2400 ring->desc, (RT_SOFTC_TX_RING_DESC_COUNT *
2401 sizeof(struct rt_txdesc)), rt_dma_map_addr,
2402 &ring->desc_phys_addr, 0);
2404 device_printf(sc->dev, "could not load Tx desc DMA map\n");
2408 ring->desc_queued = 0;
2410 ring->desc_next = 0;
2412 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2413 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2414 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE, 1,
2415 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE,
2416 0, NULL, NULL, &ring->seg0_dma_tag);
2418 device_printf(sc->dev,
2419 "could not create Tx seg0 DMA tag\n");
2423 error = bus_dmamem_alloc(ring->seg0_dma_tag, (void **) &ring->seg0,
2424 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->seg0_dma_map);
2426 device_printf(sc->dev,
2427 "could not allocate Tx seg0 DMA memory\n");
2431 error = bus_dmamap_load(ring->seg0_dma_tag, ring->seg0_dma_map,
2433 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE,
2434 rt_dma_map_addr, &ring->seg0_phys_addr, 0);
2436 device_printf(sc->dev, "could not load Tx seg0 DMA map\n");
2440 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2441 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2442 MJUMPAGESIZE, RT_SOFTC_MAX_SCATTER, MJUMPAGESIZE, 0, NULL, NULL,
2443 &ring->data_dma_tag);
2445 device_printf(sc->dev,
2446 "could not create Tx data DMA tag\n");
2450 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) {
2451 data = &ring->data[i];
2453 error = bus_dmamap_create(ring->data_dma_tag, 0,
2456 device_printf(sc->dev, "could not create Tx data DMA "
2462 ring->data_queued = 0;
2464 ring->data_next = 0;
2470 rt_free_tx_ring(sc, ring);
2475 * rt_reset_tx_ring - reset TX ring buffer to empty state
2478 rt_reset_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring)
2480 struct rt_softc_tx_data *data;
2481 struct rt_txdesc *desc;
2484 for (i = 0; i < RT_SOFTC_TX_RING_DESC_COUNT; i++) {
2485 desc = &ring->desc[i];
2491 ring->desc_queued = 0;
2493 ring->desc_next = 0;
2495 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2496 BUS_DMASYNC_PREWRITE);
2498 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map,
2499 BUS_DMASYNC_PREWRITE);
2501 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) {
2502 data = &ring->data[i];
2504 if (data->m != NULL) {
2505 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
2506 BUS_DMASYNC_POSTWRITE);
2507 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
2513 ring->data_queued = 0;
2515 ring->data_next = 0;
2519 * rt_free_tx_ring - free RX ring buffer
2522 rt_free_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring)
2524 struct rt_softc_tx_data *data;
2527 if (ring->desc != NULL) {
2528 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2529 BUS_DMASYNC_POSTWRITE);
2530 bus_dmamap_unload(ring->desc_dma_tag, ring->desc_dma_map);
2531 bus_dmamem_free(ring->desc_dma_tag, ring->desc,
2532 ring->desc_dma_map);
2535 if (ring->desc_dma_tag != NULL)
2536 bus_dma_tag_destroy(ring->desc_dma_tag);
2538 if (ring->seg0 != NULL) {
2539 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map,
2540 BUS_DMASYNC_POSTWRITE);
2541 bus_dmamap_unload(ring->seg0_dma_tag, ring->seg0_dma_map);
2542 bus_dmamem_free(ring->seg0_dma_tag, ring->seg0,
2543 ring->seg0_dma_map);
2546 if (ring->seg0_dma_tag != NULL)
2547 bus_dma_tag_destroy(ring->seg0_dma_tag);
2549 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) {
2550 data = &ring->data[i];
2552 if (data->m != NULL) {
2553 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
2554 BUS_DMASYNC_POSTWRITE);
2555 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
2559 if (data->dma_map != NULL)
2560 bus_dmamap_destroy(ring->data_dma_tag, data->dma_map);
2563 if (ring->data_dma_tag != NULL)
2564 bus_dma_tag_destroy(ring->data_dma_tag);
2566 mtx_destroy(&ring->lock);
2570 * rt_dma_map_addr - get address of busdma segment
2573 rt_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2578 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
2580 *(bus_addr_t *) arg = segs[0].ds_addr;
2584 * rt_sysctl_attach - attach sysctl nodes for NIC counters.
2587 rt_sysctl_attach(struct rt_softc *sc)
2589 struct sysctl_ctx_list *ctx;
2590 struct sysctl_oid *tree;
2591 struct sysctl_oid *stats;
2593 ctx = device_get_sysctl_ctx(sc->dev);
2594 tree = device_get_sysctl_tree(sc->dev);
2596 /* statistic counters */
2597 stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
2598 "stats", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "statistic");
2600 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2601 "interrupts", CTLFLAG_RD, &sc->interrupts,
2604 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2605 "tx_coherent_interrupts", CTLFLAG_RD, &sc->tx_coherent_interrupts,
2606 "Tx coherent interrupts");
2608 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2609 "rx_coherent_interrupts", CTLFLAG_RD, &sc->rx_coherent_interrupts,
2610 "Rx coherent interrupts");
2612 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2613 "rx_interrupts", CTLFLAG_RD, &sc->rx_interrupts[0],
2616 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2617 "rx_delay_interrupts", CTLFLAG_RD, &sc->rx_delay_interrupts,
2618 "Rx delay interrupts");
2620 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2621 "TXQ3_interrupts", CTLFLAG_RD, &sc->tx_interrupts[3],
2622 "Tx AC3 interrupts");
2624 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2625 "TXQ2_interrupts", CTLFLAG_RD, &sc->tx_interrupts[2],
2626 "Tx AC2 interrupts");
2628 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2629 "TXQ1_interrupts", CTLFLAG_RD, &sc->tx_interrupts[1],
2630 "Tx AC1 interrupts");
2632 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2633 "TXQ0_interrupts", CTLFLAG_RD, &sc->tx_interrupts[0],
2634 "Tx AC0 interrupts");
2636 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2637 "tx_delay_interrupts", CTLFLAG_RD, &sc->tx_delay_interrupts,
2638 "Tx delay interrupts");
2640 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2641 "TXQ3_desc_queued", CTLFLAG_RD, &sc->tx_ring[3].desc_queued,
2642 0, "Tx AC3 descriptors queued");
2644 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2645 "TXQ3_data_queued", CTLFLAG_RD, &sc->tx_ring[3].data_queued,
2646 0, "Tx AC3 data queued");
2648 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2649 "TXQ2_desc_queued", CTLFLAG_RD, &sc->tx_ring[2].desc_queued,
2650 0, "Tx AC2 descriptors queued");
2652 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2653 "TXQ2_data_queued", CTLFLAG_RD, &sc->tx_ring[2].data_queued,
2654 0, "Tx AC2 data queued");
2656 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2657 "TXQ1_desc_queued", CTLFLAG_RD, &sc->tx_ring[1].desc_queued,
2658 0, "Tx AC1 descriptors queued");
2660 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2661 "TXQ1_data_queued", CTLFLAG_RD, &sc->tx_ring[1].data_queued,
2662 0, "Tx AC1 data queued");
2664 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2665 "TXQ0_desc_queued", CTLFLAG_RD, &sc->tx_ring[0].desc_queued,
2666 0, "Tx AC0 descriptors queued");
2668 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2669 "TXQ0_data_queued", CTLFLAG_RD, &sc->tx_ring[0].data_queued,
2670 0, "Tx AC0 data queued");
2672 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2673 "TXQ3_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[3],
2674 "Tx AC3 data queue full");
2676 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2677 "TXQ2_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[2],
2678 "Tx AC2 data queue full");
2680 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2681 "TXQ1_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[1],
2682 "Tx AC1 data queue full");
2684 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2685 "TXQ0_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[0],
2686 "Tx AC0 data queue full");
2688 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2689 "tx_watchdog_timeouts", CTLFLAG_RD, &sc->tx_watchdog_timeouts,
2690 "Tx watchdog timeouts");
2692 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2693 "tx_defrag_packets", CTLFLAG_RD, &sc->tx_defrag_packets,
2694 "Tx defragmented packets");
2696 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2697 "no_tx_desc_avail", CTLFLAG_RD, &sc->no_tx_desc_avail,
2698 "no Tx descriptors available");
2700 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2701 "rx_mbuf_alloc_errors", CTLFLAG_RD, &sc->rx_mbuf_alloc_errors,
2702 "Rx mbuf allocation errors");
2704 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2705 "rx_mbuf_dmamap_errors", CTLFLAG_RD, &sc->rx_mbuf_dmamap_errors,
2706 "Rx mbuf DMA mapping errors");
2708 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2709 "tx_queue_0_not_empty", CTLFLAG_RD, &sc->tx_queue_not_empty[0],
2710 "Tx queue 0 not empty");
2712 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2713 "tx_queue_1_not_empty", CTLFLAG_RD, &sc->tx_queue_not_empty[1],
2714 "Tx queue 1 not empty");
2716 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2717 "rx_packets", CTLFLAG_RD, &sc->rx_packets,
2720 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2721 "rx_crc_errors", CTLFLAG_RD, &sc->rx_crc_err,
2724 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2725 "rx_phy_errors", CTLFLAG_RD, &sc->rx_phy_err,
2728 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2729 "rx_dup_packets", CTLFLAG_RD, &sc->rx_dup_packets,
2730 "Rx duplicate packets");
2732 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2733 "rx_fifo_overflows", CTLFLAG_RD, &sc->rx_fifo_overflows,
2734 "Rx FIFO overflows");
2736 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2737 "rx_bytes", CTLFLAG_RD, &sc->rx_bytes,
2740 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2741 "rx_long_err", CTLFLAG_RD, &sc->rx_long_err,
2742 "Rx too long frame errors");
2744 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2745 "rx_short_err", CTLFLAG_RD, &sc->rx_short_err,
2746 "Rx too short frame errors");
2748 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2749 "tx_bytes", CTLFLAG_RD, &sc->tx_bytes,
2752 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2753 "tx_packets", CTLFLAG_RD, &sc->tx_packets,
2756 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2757 "tx_skip", CTLFLAG_RD, &sc->tx_skip,
2758 "Tx skip count for GDMA ports");
2760 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2761 "tx_collision", CTLFLAG_RD, &sc->tx_collision,
2762 "Tx collision count for GDMA ports");
2765 #if defined(IF_RT_PHY_SUPPORT) || defined(RT_MDIO)
2766 /* This code is only work RT2880 and same chip. */
2767 /* TODO: make RT3052 and later support code. But nobody need it? */
2769 rt_miibus_readreg(device_t dev, int phy, int reg)
2771 struct rt_softc *sc = device_get_softc(dev);
2775 * PSEUDO_PHYAD is a special value for indicate switch attached.
2776 * No one PHY use PSEUDO_PHYAD (0x1e) address.
2780 /* Fake PHY ID for bfeswitch attach */
2783 return (BMSR_EXTSTAT|BMSR_MEDIAMASK);
2785 return (0x40); /* As result of faking */
2786 case MII_PHYIDR2: /* PHY will detect as */
2787 return (0x6250); /* bfeswitch */
2792 /* Wait prev command done if any */
2793 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2794 dat = ((phy << MDIO_PHY_ADDR_SHIFT) & MDIO_PHY_ADDR_MASK) |
2795 ((reg << MDIO_PHYREG_ADDR_SHIFT) & MDIO_PHYREG_ADDR_MASK);
2796 RT_WRITE(sc, MDIO_ACCESS, dat);
2797 RT_WRITE(sc, MDIO_ACCESS, dat | MDIO_CMD_ONGO);
2798 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2800 return (RT_READ(sc, MDIO_ACCESS) & MDIO_PHY_DATA_MASK);
2804 rt_miibus_writereg(device_t dev, int phy, int reg, int val)
2806 struct rt_softc *sc = device_get_softc(dev);
2809 /* Wait prev command done if any */
2810 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2812 ((phy << MDIO_PHY_ADDR_SHIFT) & MDIO_PHY_ADDR_MASK) |
2813 ((reg << MDIO_PHYREG_ADDR_SHIFT) & MDIO_PHYREG_ADDR_MASK) |
2814 (val & MDIO_PHY_DATA_MASK);
2815 RT_WRITE(sc, MDIO_ACCESS, dat);
2816 RT_WRITE(sc, MDIO_ACCESS, dat | MDIO_CMD_ONGO);
2817 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2823 #ifdef IF_RT_PHY_SUPPORT
2825 rt_miibus_statchg(device_t dev)
2827 struct rt_softc *sc = device_get_softc(dev);
2828 struct mii_data *mii;
2830 mii = device_get_softc(sc->rt_miibus);
2832 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
2833 (IFM_ACTIVE | IFM_AVALID)) {
2834 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2837 /* XXX check link here */
2845 #endif /* IF_RT_PHY_SUPPORT */
2847 static device_method_t rt_dev_methods[] =
2849 DEVMETHOD(device_probe, rt_probe),
2850 DEVMETHOD(device_attach, rt_attach),
2851 DEVMETHOD(device_detach, rt_detach),
2852 DEVMETHOD(device_shutdown, rt_shutdown),
2853 DEVMETHOD(device_suspend, rt_suspend),
2854 DEVMETHOD(device_resume, rt_resume),
2856 #ifdef IF_RT_PHY_SUPPORT
2858 DEVMETHOD(miibus_readreg, rt_miibus_readreg),
2859 DEVMETHOD(miibus_writereg, rt_miibus_writereg),
2860 DEVMETHOD(miibus_statchg, rt_miibus_statchg),
2866 static driver_t rt_driver =
2870 sizeof(struct rt_softc)
2873 static devclass_t rt_dev_class;
2875 DRIVER_MODULE(rt, nexus, rt_driver, rt_dev_class, 0, 0);
2877 DRIVER_MODULE(rt, simplebus, rt_driver, rt_dev_class, 0, 0);
2880 MODULE_DEPEND(rt, ether, 1, 1, 1);
2881 MODULE_DEPEND(rt, miibus, 1, 1, 1);
2884 MODULE_DEPEND(rt, mdio, 1, 1, 1);
2886 static int rtmdio_probe(device_t);
2887 static int rtmdio_attach(device_t);
2888 static int rtmdio_detach(device_t);
2890 static struct mtx miibus_mtx;
2892 MTX_SYSINIT(miibus_mtx, &miibus_mtx, "rt mii lock", MTX_DEF);
2895 * Declare an additional, separate driver for accessing the MDIO bus.
2897 static device_method_t rtmdio_methods[] = {
2898 /* Device interface */
2899 DEVMETHOD(device_probe, rtmdio_probe),
2900 DEVMETHOD(device_attach, rtmdio_attach),
2901 DEVMETHOD(device_detach, rtmdio_detach),
2904 DEVMETHOD(bus_add_child, device_add_child_ordered),
2907 DEVMETHOD(mdio_readreg, rt_miibus_readreg),
2908 DEVMETHOD(mdio_writereg, rt_miibus_writereg),
2911 DEFINE_CLASS_0(rtmdio, rtmdio_driver, rtmdio_methods,
2912 sizeof(struct rt_softc));
2913 static devclass_t rtmdio_devclass;
2915 DRIVER_MODULE(miiproxy, rt, miiproxy_driver, miiproxy_devclass, 0, 0);
2916 DRIVER_MODULE(rtmdio, simplebus, rtmdio_driver, rtmdio_devclass, 0, 0);
2917 DRIVER_MODULE(mdio, rtmdio, mdio_driver, mdio_devclass, 0, 0);
2920 rtmdio_probe(device_t dev)
2922 if (!ofw_bus_status_okay(dev))
2925 if (!ofw_bus_is_compatible(dev, "ralink,rt2880-mdio"))
2928 device_set_desc(dev, "RT built-in ethernet interface, MDIO controller");
2933 rtmdio_attach(device_t dev)
2935 struct rt_softc *sc;
2938 sc = device_get_softc(dev);
2941 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
2942 &sc->mem_rid, RF_ACTIVE | RF_SHAREABLE);
2943 if (sc->mem == NULL) {
2944 device_printf(dev, "couldn't map memory\n");
2949 sc->bst = rman_get_bustag(sc->mem);
2950 sc->bsh = rman_get_bushandle(sc->mem);
2952 bus_generic_probe(dev);
2953 bus_enumerate_hinted_children(dev);
2954 error = bus_generic_attach(dev);
2960 rtmdio_detach(device_t dev)