2 * Copyright (c) 2015-2016, Stanislav Galabov
3 * Copyright (c) 2014, Aleksandr A. Mityaev
4 * Copyright (c) 2011, Aleksandr Rybalko
6 * by Alexander Egorenkov <egorenar@gmail.com>
7 * and by Damien Bergamini <damien.bergamini@free.fr>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice unmodified, this list of conditions, and the following
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
40 #include <net/if_var.h>
41 #include <net/if_arp.h>
42 #include <net/ethernet.h>
43 #include <net/if_dl.h>
44 #include <net/if_media.h>
45 #include <net/if_types.h>
46 #include <net/if_vlan_var.h>
50 #include <machine/bus.h>
51 #include <machine/cache.h>
52 #include <machine/cpufunc.h>
53 #include <machine/resource.h>
54 #include <vm/vm_param.h>
57 #include <machine/pmap.h>
61 #include "opt_platform.h"
62 #include "opt_rt305x.h"
65 #include <dev/ofw/openfirm.h>
66 #include <dev/ofw/ofw_bus.h>
67 #include <dev/ofw/ofw_bus_subr.h>
70 #include <dev/mii/mii.h>
71 #include <dev/mii/miivar.h>
74 #include <mips/rt305x/rt305x_sysctlvar.h>
75 #include <mips/rt305x/rt305xreg.h>
78 #ifdef IF_RT_PHY_SUPPORT
79 #include "miibus_if.h"
85 #define RT_MAX_AGG_SIZE 3840
87 #define RT_TX_DATA_SEG0_SIZE MJUMPAGESIZE
89 #define RT_MS(_v, _f) (((_v) & _f) >> _f##_S)
90 #define RT_SM(_v, _f) (((_v) << _f##_S) & _f)
92 #define RT_TX_WATCHDOG_TIMEOUT 5
94 #define RT_CHIPID_RT3050 0x3050
95 #define RT_CHIPID_RT5350 0x5350
96 #define RT_CHIPID_MT7620 0x7620
97 #define RT_CHIPID_MT7621 0x7621
100 /* more specific and new models should go first */
101 static const struct ofw_compat_data rt_compat_data[] = {
102 { "ralink,rt3050-eth", RT_CHIPID_RT3050 },
103 { "ralink,rt3352-eth", RT_CHIPID_RT3050 },
104 { "ralink,rt3883-eth", RT_CHIPID_RT3050 },
105 { "ralink,rt5350-eth", RT_CHIPID_RT5350 },
106 { "ralink,mt7620a-eth", RT_CHIPID_MT7620 },
107 { "mediatek,mt7620-eth", RT_CHIPID_MT7620 },
108 { "ralink,mt7621-eth", RT_CHIPID_MT7621 },
109 { "mediatek,mt7621-eth", RT_CHIPID_MT7621 },
115 * Static function prototypes
117 static int rt_probe(device_t dev);
118 static int rt_attach(device_t dev);
119 static int rt_detach(device_t dev);
120 static int rt_shutdown(device_t dev);
121 static int rt_suspend(device_t dev);
122 static int rt_resume(device_t dev);
123 static void rt_init_locked(void *priv);
124 static void rt_init(void *priv);
125 static void rt_stop_locked(void *priv);
126 static void rt_stop(void *priv);
127 static void rt_start(struct ifnet *ifp);
128 static int rt_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
129 static void rt_periodic(void *arg);
130 static void rt_tx_watchdog(void *arg);
131 static void rt_intr(void *arg);
132 static void rt_rt5350_intr(void *arg);
133 static void rt_tx_coherent_intr(struct rt_softc *sc);
134 static void rt_rx_coherent_intr(struct rt_softc *sc);
135 static void rt_rx_delay_intr(struct rt_softc *sc);
136 static void rt_tx_delay_intr(struct rt_softc *sc);
137 static void rt_rx_intr(struct rt_softc *sc, int qid);
138 static void rt_tx_intr(struct rt_softc *sc, int qid);
139 static void rt_rx_done_task(void *context, int pending);
140 static void rt_tx_done_task(void *context, int pending);
141 static void rt_periodic_task(void *context, int pending);
142 static int rt_rx_eof(struct rt_softc *sc,
143 struct rt_softc_rx_ring *ring, int limit);
144 static void rt_tx_eof(struct rt_softc *sc,
145 struct rt_softc_tx_ring *ring);
146 static void rt_update_stats(struct rt_softc *sc);
147 static void rt_watchdog(struct rt_softc *sc);
148 static void rt_update_raw_counters(struct rt_softc *sc);
149 static void rt_intr_enable(struct rt_softc *sc, uint32_t intr_mask);
150 static void rt_intr_disable(struct rt_softc *sc, uint32_t intr_mask);
151 static int rt_txrx_enable(struct rt_softc *sc);
152 static int rt_alloc_rx_ring(struct rt_softc *sc,
153 struct rt_softc_rx_ring *ring, int qid);
154 static void rt_reset_rx_ring(struct rt_softc *sc,
155 struct rt_softc_rx_ring *ring);
156 static void rt_free_rx_ring(struct rt_softc *sc,
157 struct rt_softc_rx_ring *ring);
158 static int rt_alloc_tx_ring(struct rt_softc *sc,
159 struct rt_softc_tx_ring *ring, int qid);
160 static void rt_reset_tx_ring(struct rt_softc *sc,
161 struct rt_softc_tx_ring *ring);
162 static void rt_free_tx_ring(struct rt_softc *sc,
163 struct rt_softc_tx_ring *ring);
164 static void rt_dma_map_addr(void *arg, bus_dma_segment_t *segs,
165 int nseg, int error);
166 static void rt_sysctl_attach(struct rt_softc *sc);
167 #ifdef IF_RT_PHY_SUPPORT
168 void rt_miibus_statchg(device_t);
169 static int rt_miibus_readreg(device_t, int, int);
170 static int rt_miibus_writereg(device_t, int, int, int);
172 static int rt_ifmedia_upd(struct ifnet *);
173 static void rt_ifmedia_sts(struct ifnet *, struct ifmediareq *);
175 static SYSCTL_NODE(_hw, OID_AUTO, rt, CTLFLAG_RD, 0, "RT driver parameters");
177 static int rt_debug = 0;
178 SYSCTL_INT(_hw_rt, OID_AUTO, debug, CTLFLAG_RWTUN, &rt_debug, 0,
183 rt_probe(device_t dev)
185 struct rt_softc *sc = device_get_softc(dev);
188 const struct ofw_compat_data * cd;
190 cd = ofw_bus_search_compatible(dev, rt_compat_data);
191 if (cd->ocd_data == 0)
194 sc->rt_chipid = (unsigned int)(cd->ocd_data);
197 sc->rt_chipid = RT_CHIPID_MT7620;
198 #elif defined(MT7621)
199 sc->rt_chipid = RT_CHIPID_MT7621;
200 #elif defined(RT5350)
201 sc->rt_chipid = RT_CHIPID_RT5350;
203 sc->rt_chipid = RT_CHIPID_RT3050;
206 snprintf(buf, sizeof(buf), "Ralink %cT%x onChip Ethernet driver",
207 sc->rt_chipid >= 0x7600 ? 'M' : 'R', sc->rt_chipid);
208 device_set_desc_copy(dev, buf);
209 return (BUS_PROBE_GENERIC);
213 * macaddr_atoi - translate string MAC address to uint8_t array
216 macaddr_atoi(const char *str, uint8_t *mac)
219 unsigned int amac[ETHER_ADDR_LEN]; /* Aligned version */
221 count = sscanf(str, "%x%*c%x%*c%x%*c%x%*c%x%*c%x",
222 &amac[0], &amac[1], &amac[2],
223 &amac[3], &amac[4], &amac[5]);
224 if (count < ETHER_ADDR_LEN) {
225 memset(mac, 0, ETHER_ADDR_LEN);
229 /* Copy aligned to result */
230 for (i = 0; i < ETHER_ADDR_LEN; i ++)
231 mac[i] = (amac[i] & 0xff);
236 #ifdef USE_GENERATED_MAC_ADDRESS
238 * generate_mac(uin8_t *mac)
239 * This is MAC address generator for cases when real device MAC address
240 * unknown or not yet accessible.
241 * Use 'b','s','d' signature and 3 octets from CRC32 on kenv.
242 * MAC = 'b', 's', 'd', CRC[3]^CRC[2], CRC[1], CRC[0]
244 * Output - MAC address, that do not change between reboots, if hints or
245 * bootloader info unchange.
248 generate_mac(uint8_t *mac)
252 uint32_t crc = 0xffffffff;
254 /* Generate CRC32 on kenv */
255 for (cp = kenvp[0]; cp != NULL; cp = kenvp[++i]) {
256 crc = calculate_crc32c(crc, cp, strlen(cp) + 1);
263 mac[3] = (crc >> 24) ^ ((crc >> 16) & 0xff);
264 mac[4] = (crc >> 8) & 0xff;
270 * ether_request_mac - try to find usable MAC address.
273 ether_request_mac(device_t dev, uint8_t *mac)
278 * "ethaddr" is passed via envp on RedBoot platforms
279 * "kmac" is passed via argv on RouterBOOT platforms
281 #if defined(RT305X_UBOOT) || defined(__REDBOOT__) || defined(__ROUTERBOOT__)
282 if ((var = kern_getenv("ethaddr")) != NULL ||
283 (var = kern_getenv("kmac")) != NULL ) {
285 if(!macaddr_atoi(var, mac)) {
286 printf("%s: use %s macaddr from KENV\n",
287 device_get_nameunit(dev), var);
297 * hint.[dev].[unit].macaddr
299 if (!resource_string_value(device_get_name(dev),
300 device_get_unit(dev), "macaddr", (const char **)&var)) {
302 if(!macaddr_atoi(var, mac)) {
303 printf("%s: use %s macaddr from hints\n",
304 device_get_nameunit(dev), var);
309 #ifdef USE_GENERATED_MAC_ADDRESS
312 device_printf(dev, "use generated %02x:%02x:%02x:%02x:%02x:%02x "
313 "macaddr\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
323 device_printf(dev, "use hardcoded 00:18:e7:d5:83:90 macaddr\n");
333 reset_freng(struct rt_softc *sc)
335 /* XXX hard reset kills everything so skip it ... */
340 rt_attach(device_t dev)
346 sc = device_get_softc(dev);
349 mtx_init(&sc->lock, device_get_nameunit(dev), MTX_NETWORK_LOCK,
350 MTX_DEF | MTX_RECURSE);
353 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
355 if (sc->mem == NULL) {
356 device_printf(dev, "could not allocate memory resource\n");
361 sc->bst = rman_get_bustag(sc->mem);
362 sc->bsh = rman_get_bushandle(sc->mem);
365 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
367 if (sc->irq == NULL) {
369 "could not allocate interrupt resource\n");
375 sc->debug = rt_debug;
377 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
378 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
379 "debug", CTLFLAG_RW, &sc->debug, 0, "rt debug level");
386 if (sc->rt_chipid == RT_CHIPID_MT7620) {
387 sc->csum_fail_ip = MT7620_RXD_SRC_IP_CSUM_FAIL;
388 sc->csum_fail_l4 = MT7620_RXD_SRC_L4_CSUM_FAIL;
389 } else if (sc->rt_chipid == RT_CHIPID_MT7621) {
390 sc->csum_fail_ip = MT7621_RXD_SRC_IP_CSUM_FAIL;
391 sc->csum_fail_l4 = MT7621_RXD_SRC_L4_CSUM_FAIL;
393 sc->csum_fail_ip = RT305X_RXD_SRC_IP_CSUM_FAIL;
394 sc->csum_fail_l4 = RT305X_RXD_SRC_L4_CSUM_FAIL;
397 /* Fill in soc-specific registers map */
398 switch(sc->rt_chipid) {
399 case RT_CHIPID_MT7620:
400 case RT_CHIPID_MT7621:
401 case RT_CHIPID_RT5350:
402 device_printf(dev, "%cT%x Ethernet MAC (rev 0x%08x)\n",
403 sc->rt_chipid >= 0x7600 ? 'M' : 'R',
404 sc->rt_chipid, sc->mac_rev);
405 /* RT5350: No GDMA, PSE, CDMA, PPE */
406 RT_WRITE(sc, GE_PORT_BASE + 0x0C00, // UDPCS, TCPCS, IPCS=1
407 RT_READ(sc, GE_PORT_BASE + 0x0C00) | (0x7<<16));
408 sc->delay_int_cfg=RT5350_PDMA_BASE+RT5350_DELAY_INT_CFG;
409 sc->fe_int_status=RT5350_FE_INT_STATUS;
410 sc->fe_int_enable=RT5350_FE_INT_ENABLE;
411 sc->pdma_glo_cfg=RT5350_PDMA_BASE+RT5350_PDMA_GLO_CFG;
412 sc->pdma_rst_idx=RT5350_PDMA_BASE+RT5350_PDMA_RST_IDX;
413 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
414 sc->tx_base_ptr[i]=RT5350_PDMA_BASE+RT5350_TX_BASE_PTR(i);
415 sc->tx_max_cnt[i]=RT5350_PDMA_BASE+RT5350_TX_MAX_CNT(i);
416 sc->tx_ctx_idx[i]=RT5350_PDMA_BASE+RT5350_TX_CTX_IDX(i);
417 sc->tx_dtx_idx[i]=RT5350_PDMA_BASE+RT5350_TX_DTX_IDX(i);
420 sc->rx_base_ptr[0]=RT5350_PDMA_BASE+RT5350_RX_BASE_PTR0;
421 sc->rx_max_cnt[0]=RT5350_PDMA_BASE+RT5350_RX_MAX_CNT0;
422 sc->rx_calc_idx[0]=RT5350_PDMA_BASE+RT5350_RX_CALC_IDX0;
423 sc->rx_drx_idx[0]=RT5350_PDMA_BASE+RT5350_RX_DRX_IDX0;
424 sc->rx_base_ptr[1]=RT5350_PDMA_BASE+RT5350_RX_BASE_PTR1;
425 sc->rx_max_cnt[1]=RT5350_PDMA_BASE+RT5350_RX_MAX_CNT1;
426 sc->rx_calc_idx[1]=RT5350_PDMA_BASE+RT5350_RX_CALC_IDX1;
427 sc->rx_drx_idx[1]=RT5350_PDMA_BASE+RT5350_RX_DRX_IDX1;
428 sc->int_rx_done_mask=RT5350_INT_RXQ0_DONE;
429 sc->int_tx_done_mask=RT5350_INT_TXQ0_DONE;
432 device_printf(dev, "RT305XF Ethernet MAC (rev 0x%08x)\n",
434 RT_WRITE(sc, GDMA1_BASE + GDMA_FWD_CFG,
436 GDM_ICS_EN | /* Enable IP Csum */
437 GDM_TCS_EN | /* Enable TCP Csum */
438 GDM_UCS_EN | /* Enable UDP Csum */
439 GDM_STRPCRC | /* Strip CRC from packet */
440 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* fwd UCast to CPU */
441 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* fwd BCast to CPU */
442 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* fwd MCast to CPU */
443 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* fwd Other to CPU */
446 sc->delay_int_cfg=PDMA_BASE+DELAY_INT_CFG;
447 sc->fe_int_status=GE_PORT_BASE+FE_INT_STATUS;
448 sc->fe_int_enable=GE_PORT_BASE+FE_INT_ENABLE;
449 sc->pdma_glo_cfg=PDMA_BASE+PDMA_GLO_CFG;
450 sc->pdma_glo_cfg=PDMA_BASE+PDMA_GLO_CFG;
451 sc->pdma_rst_idx=PDMA_BASE+PDMA_RST_IDX;
452 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
453 sc->tx_base_ptr[i]=PDMA_BASE+TX_BASE_PTR(i);
454 sc->tx_max_cnt[i]=PDMA_BASE+TX_MAX_CNT(i);
455 sc->tx_ctx_idx[i]=PDMA_BASE+TX_CTX_IDX(i);
456 sc->tx_dtx_idx[i]=PDMA_BASE+TX_DTX_IDX(i);
459 sc->rx_base_ptr[0]=PDMA_BASE+RX_BASE_PTR0;
460 sc->rx_max_cnt[0]=PDMA_BASE+RX_MAX_CNT0;
461 sc->rx_calc_idx[0]=PDMA_BASE+RX_CALC_IDX0;
462 sc->rx_drx_idx[0]=PDMA_BASE+RX_DRX_IDX0;
463 sc->int_rx_done_mask=INT_RX_DONE;
464 sc->int_tx_done_mask=INT_TXQ0_DONE;
467 /* allocate Tx and Rx rings */
468 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
469 error = rt_alloc_tx_ring(sc, &sc->tx_ring[i], i);
471 device_printf(dev, "could not allocate Tx ring #%d\n",
477 sc->tx_ring_mgtqid = 5;
478 for (i = 0; i < sc->rx_ring_count; i++) {
479 error = rt_alloc_rx_ring(sc, &sc->rx_ring[i], i);
481 device_printf(dev, "could not allocate Rx ring\n");
486 callout_init(&sc->periodic_ch, 0);
487 callout_init_mtx(&sc->tx_watchdog_ch, &sc->lock, 0);
489 ifp = sc->ifp = if_alloc(IFT_ETHER);
491 device_printf(dev, "could not if_alloc()\n");
497 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
498 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
499 ifp->if_init = rt_init;
500 ifp->if_ioctl = rt_ioctl;
501 ifp->if_start = rt_start;
502 #define RT_TX_QLEN 256
504 IFQ_SET_MAXLEN(&ifp->if_snd, RT_TX_QLEN);
505 ifp->if_snd.ifq_drv_maxlen = RT_TX_QLEN;
506 IFQ_SET_READY(&ifp->if_snd);
508 #ifdef IF_RT_PHY_SUPPORT
509 error = mii_attach(dev, &sc->rt_miibus, ifp, rt_ifmedia_upd,
510 rt_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
512 device_printf(dev, "attaching PHYs failed\n");
517 ifmedia_init(&sc->rt_ifmedia, 0, rt_ifmedia_upd, rt_ifmedia_sts);
518 ifmedia_add(&sc->rt_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0,
520 ifmedia_set(&sc->rt_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX);
522 #endif /* IF_RT_PHY_SUPPORT */
524 ether_request_mac(dev, sc->mac_addr);
525 ether_ifattach(ifp, sc->mac_addr);
528 * Tell the upper layer(s) we support long frames.
530 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
531 ifp->if_capabilities |= IFCAP_VLAN_MTU;
532 ifp->if_capenable |= IFCAP_VLAN_MTU;
533 ifp->if_capabilities |= IFCAP_RXCSUM|IFCAP_TXCSUM;
534 ifp->if_capenable |= IFCAP_RXCSUM|IFCAP_TXCSUM;
536 /* init task queue */
537 TASK_INIT(&sc->rx_done_task, 0, rt_rx_done_task, sc);
538 TASK_INIT(&sc->tx_done_task, 0, rt_tx_done_task, sc);
539 TASK_INIT(&sc->periodic_task, 0, rt_periodic_task, sc);
541 sc->rx_process_limit = 100;
543 sc->taskqueue = taskqueue_create("rt_taskq", M_NOWAIT,
544 taskqueue_thread_enqueue, &sc->taskqueue);
546 taskqueue_start_threads(&sc->taskqueue, 1, PI_NET, "%s taskq",
547 device_get_nameunit(sc->dev));
549 rt_sysctl_attach(sc);
551 /* set up interrupt */
552 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
553 NULL, (sc->rt_chipid == RT_CHIPID_RT5350 ||
554 sc->rt_chipid == RT_CHIPID_MT7620 ||
555 sc->rt_chipid == RT_CHIPID_MT7621) ? rt_rt5350_intr : rt_intr,
558 printf("%s: could not set up interrupt\n",
559 device_get_nameunit(dev));
563 device_printf(dev, "debug var at %#08x\n", (u_int)&(sc->debug));
569 /* free Tx and Rx rings */
570 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
571 rt_free_tx_ring(sc, &sc->tx_ring[i]);
573 for (i = 0; i < sc->rx_ring_count; i++)
574 rt_free_rx_ring(sc, &sc->rx_ring[i]);
576 mtx_destroy(&sc->lock);
579 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
583 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
593 rt_ifmedia_upd(struct ifnet *ifp)
596 #ifdef IF_RT_PHY_SUPPORT
597 struct mii_data *mii;
598 struct mii_softc *miisc;
604 mii = device_get_softc(sc->rt_miibus);
605 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
607 error = mii_mediachg(mii);
612 #else /* !IF_RT_PHY_SUPPORT */
615 struct ifmedia_entry *ife;
618 ifm = &sc->rt_ifmedia;
621 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
624 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
625 device_printf(sc->dev,
626 "AUTO is not supported for multiphy MAC");
634 #endif /* IF_RT_PHY_SUPPORT */
638 * Report current media status.
641 rt_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
643 #ifdef IF_RT_PHY_SUPPORT
645 struct mii_data *mii;
650 mii = device_get_softc(sc->rt_miibus);
652 ifmr->ifm_active = mii->mii_media_active;
653 ifmr->ifm_status = mii->mii_media_status;
654 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
655 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
657 #else /* !IF_RT_PHY_SUPPORT */
659 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
660 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
661 #endif /* IF_RT_PHY_SUPPORT */
665 rt_detach(device_t dev)
671 sc = device_get_softc(dev);
674 RT_DPRINTF(sc, RT_DEBUG_ANY, "detaching\n");
678 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
680 callout_stop(&sc->periodic_ch);
681 callout_stop(&sc->tx_watchdog_ch);
683 taskqueue_drain(sc->taskqueue, &sc->rx_done_task);
684 taskqueue_drain(sc->taskqueue, &sc->tx_done_task);
685 taskqueue_drain(sc->taskqueue, &sc->periodic_task);
687 /* free Tx and Rx rings */
688 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
689 rt_free_tx_ring(sc, &sc->tx_ring[i]);
690 for (i = 0; i < sc->rx_ring_count; i++)
691 rt_free_rx_ring(sc, &sc->rx_ring[i]);
695 #ifdef IF_RT_PHY_SUPPORT
696 if (sc->rt_miibus != NULL)
697 device_delete_child(dev, sc->rt_miibus);
703 taskqueue_free(sc->taskqueue);
705 mtx_destroy(&sc->lock);
707 bus_generic_detach(dev);
708 bus_teardown_intr(dev, sc->irq, sc->irqh);
709 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq);
710 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem);
716 rt_shutdown(device_t dev)
720 sc = device_get_softc(dev);
721 RT_DPRINTF(sc, RT_DEBUG_ANY, "shutting down\n");
728 rt_suspend(device_t dev)
732 sc = device_get_softc(dev);
733 RT_DPRINTF(sc, RT_DEBUG_ANY, "suspending\n");
740 rt_resume(device_t dev)
745 sc = device_get_softc(dev);
748 RT_DPRINTF(sc, RT_DEBUG_ANY, "resuming\n");
750 if (ifp->if_flags & IFF_UP)
757 * rt_init_locked - Run initialization process having locked mtx.
760 rt_init_locked(void *priv)
764 #ifdef IF_RT_PHY_SUPPORT
765 struct mii_data *mii;
772 #ifdef IF_RT_PHY_SUPPORT
773 mii = device_get_softc(sc->rt_miibus);
776 RT_DPRINTF(sc, RT_DEBUG_ANY, "initializing\n");
778 RT_SOFTC_ASSERT_LOCKED(sc);
781 //RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET);
782 //rt305x_sysctl_set(SYSCTL_RSTCTRL, SYSCTL_RSTCTRL_FRENG);
784 /* Fwd to CPU (uni|broad|multi)cast and Unknown */
785 if(sc->rt_chipid == RT_CHIPID_RT3050)
786 RT_WRITE(sc, GDMA1_BASE + GDMA_FWD_CFG,
788 GDM_ICS_EN | /* Enable IP Csum */
789 GDM_TCS_EN | /* Enable TCP Csum */
790 GDM_UCS_EN | /* Enable UDP Csum */
791 GDM_STRPCRC | /* Strip CRC from packet */
792 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* Forward UCast to CPU */
793 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* Forward BCast to CPU */
794 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* Forward MCast to CPU */
795 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* Forward Other to CPU */
798 /* disable DMA engine */
799 RT_WRITE(sc, sc->pdma_glo_cfg, 0);
800 RT_WRITE(sc, sc->pdma_rst_idx, 0xffffffff);
802 /* wait while DMA engine is busy */
803 for (ntries = 0; ntries < 100; ntries++) {
804 tmp = RT_READ(sc, sc->pdma_glo_cfg);
805 if (!(tmp & (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)))
811 device_printf(sc->dev, "timeout waiting for DMA engine\n");
815 /* reset Rx and Tx rings */
816 tmp = FE_RST_DRX_IDX0 |
822 RT_WRITE(sc, sc->pdma_rst_idx, tmp);
824 /* XXX switch set mac address */
825 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
826 rt_reset_tx_ring(sc, &sc->tx_ring[i]);
828 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
829 /* update TX_BASE_PTRx */
830 RT_WRITE(sc, sc->tx_base_ptr[i],
831 sc->tx_ring[i].desc_phys_addr);
832 RT_WRITE(sc, sc->tx_max_cnt[i],
833 RT_SOFTC_TX_RING_DESC_COUNT);
834 RT_WRITE(sc, sc->tx_ctx_idx[i], 0);
838 for (i = 0; i < sc->rx_ring_count; i++)
839 rt_reset_rx_ring(sc, &sc->rx_ring[i]);
841 /* update RX_BASE_PTRx */
842 for (i = 0; i < sc->rx_ring_count; i++) {
843 RT_WRITE(sc, sc->rx_base_ptr[i],
844 sc->rx_ring[i].desc_phys_addr);
845 RT_WRITE(sc, sc->rx_max_cnt[i],
846 RT_SOFTC_RX_RING_DATA_COUNT);
847 RT_WRITE(sc, sc->rx_calc_idx[i],
848 RT_SOFTC_RX_RING_DATA_COUNT - 1);
851 /* write back DDONE, 16byte burst enable RX/TX DMA */
852 tmp = FE_TX_WB_DDONE | FE_DMA_BT_SIZE16 | FE_RX_DMA_EN | FE_TX_DMA_EN;
853 if (sc->rt_chipid == RT_CHIPID_MT7620 ||
854 sc->rt_chipid == RT_CHIPID_MT7621)
856 RT_WRITE(sc, sc->pdma_glo_cfg, tmp);
858 /* disable interrupts mitigation */
859 RT_WRITE(sc, sc->delay_int_cfg, 0);
861 /* clear pending interrupts */
862 RT_WRITE(sc, sc->fe_int_status, 0xffffffff);
864 /* enable interrupts */
865 if (sc->rt_chipid == RT_CHIPID_RT5350 ||
866 sc->rt_chipid == RT_CHIPID_MT7620 ||
867 sc->rt_chipid == RT_CHIPID_MT7621)
868 tmp = RT5350_INT_TX_COHERENT |
869 RT5350_INT_RX_COHERENT |
870 RT5350_INT_TXQ3_DONE |
871 RT5350_INT_TXQ2_DONE |
872 RT5350_INT_TXQ1_DONE |
873 RT5350_INT_TXQ0_DONE |
874 RT5350_INT_RXQ1_DONE |
875 RT5350_INT_RXQ0_DONE;
894 sc->intr_enable_mask = tmp;
896 RT_WRITE(sc, sc->fe_int_enable, tmp);
898 if (rt_txrx_enable(sc) != 0)
901 #ifdef IF_RT_PHY_SUPPORT
902 if (mii) mii_mediachg(mii);
903 #endif /* IF_RT_PHY_SUPPORT */
905 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
906 ifp->if_drv_flags |= IFF_DRV_RUNNING;
908 sc->periodic_round = 0;
910 callout_reset(&sc->periodic_ch, hz / 10, rt_periodic, sc);
919 * rt_init - lock and initialize device.
933 * rt_stop_locked - stop TX/RX w/ lock
936 rt_stop_locked(void *priv)
944 RT_DPRINTF(sc, RT_DEBUG_ANY, "stopping\n");
946 RT_SOFTC_ASSERT_LOCKED(sc);
948 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
949 callout_stop(&sc->periodic_ch);
950 callout_stop(&sc->tx_watchdog_ch);
952 taskqueue_block(sc->taskqueue);
955 * Sometime rt_stop_locked called from isr and we get panic
956 * When found, I fix it
959 taskqueue_drain(sc->taskqueue, &sc->rx_done_task);
960 taskqueue_drain(sc->taskqueue, &sc->tx_done_task);
961 taskqueue_drain(sc->taskqueue, &sc->periodic_task);
965 /* disable interrupts */
966 RT_WRITE(sc, sc->fe_int_enable, 0);
968 if(sc->rt_chipid == RT_CHIPID_RT5350 ||
969 sc->rt_chipid == RT_CHIPID_MT7620 ||
970 sc->rt_chipid == RT_CHIPID_MT7621) {
973 RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET);
975 RT_WRITE(sc, GDMA1_BASE + GDMA_FWD_CFG,
977 GDM_ICS_EN | /* Enable IP Csum */
978 GDM_TCS_EN | /* Enable TCP Csum */
979 GDM_UCS_EN | /* Enable UDP Csum */
980 GDM_STRPCRC | /* Strip CRC from packet */
981 GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | /* Forward UCast to CPU */
982 GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | /* Forward BCast to CPU */
983 GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | /* Forward MCast to CPU */
984 GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT /* Forward Other to CPU */
1001 * rt_tx_data - transmit packet.
1004 rt_tx_data(struct rt_softc *sc, struct mbuf *m, int qid)
1007 struct rt_softc_tx_ring *ring;
1008 struct rt_softc_tx_data *data;
1009 struct rt_txdesc *desc;
1011 bus_dma_segment_t dma_seg[RT_SOFTC_MAX_SCATTER];
1012 int error, ndmasegs, ndescs, i;
1014 KASSERT(qid >= 0 && qid < RT_SOFTC_TX_RING_COUNT,
1015 ("%s: Tx data: invalid qid=%d\n",
1016 device_get_nameunit(sc->dev), qid));
1018 RT_SOFTC_TX_RING_ASSERT_LOCKED(&sc->tx_ring[qid]);
1021 ring = &sc->tx_ring[qid];
1022 desc = &ring->desc[ring->desc_cur];
1023 data = &ring->data[ring->data_cur];
1025 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag, data->dma_map, m,
1026 dma_seg, &ndmasegs, 0);
1028 /* too many fragments, linearize */
1030 RT_DPRINTF(sc, RT_DEBUG_TX,
1031 "could not load mbuf DMA map, trying to linearize "
1032 "mbuf: ndmasegs=%d, len=%d, error=%d\n",
1033 ndmasegs, m->m_pkthdr.len, error);
1035 m_d = m_collapse(m, M_NOWAIT, 16);
1043 sc->tx_defrag_packets++;
1045 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag,
1046 data->dma_map, m, dma_seg, &ndmasegs, 0);
1048 device_printf(sc->dev, "could not load mbuf DMA map: "
1049 "ndmasegs=%d, len=%d, error=%d\n",
1050 ndmasegs, m->m_pkthdr.len, error);
1056 if (m->m_pkthdr.len == 0)
1059 /* determine how many Tx descs are required */
1060 ndescs = 1 + ndmasegs / 2;
1061 if ((ring->desc_queued + ndescs) >
1062 (RT_SOFTC_TX_RING_DESC_COUNT - 2)) {
1063 RT_DPRINTF(sc, RT_DEBUG_TX,
1064 "there are not enough Tx descs\n");
1066 sc->no_tx_desc_avail++;
1068 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
1075 /* set up Tx descs */
1076 for (i = 0; i < ndmasegs; i += 2) {
1078 /* TODO: this needs to be refined as MT7620 for example has
1079 * a different word3 layout than RT305x and RT5350 (the last
1080 * one doesn't use word3 at all). And so does MT7621...
1083 if (sc->rt_chipid != RT_CHIPID_MT7621) {
1084 /* Set destination */
1085 if (sc->rt_chipid != RT_CHIPID_MT7620)
1086 desc->dst = (TXDSCR_DST_PORT_GDMA1);
1088 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1089 desc->dst |= (TXDSCR_IP_CSUM_GEN |
1090 TXDSCR_UDP_CSUM_GEN | TXDSCR_TCP_CSUM_GEN);
1104 desc->sdp0 = htole32(dma_seg[i].ds_addr);
1105 desc->sdl0 = htole16(dma_seg[i].ds_len |
1106 ( ((i+1) == ndmasegs )?RT_TXDESC_SDL0_LASTSEG:0 ));
1108 if ((i+1) < ndmasegs) {
1109 desc->sdp1 = htole32(dma_seg[i+1].ds_addr);
1110 desc->sdl1 = htole16(dma_seg[i+1].ds_len |
1111 ( ((i+2) == ndmasegs )?RT_TXDESC_SDL1_LASTSEG:0 ));
1117 if ((i+2) < ndmasegs) {
1118 ring->desc_queued++;
1119 ring->desc_cur = (ring->desc_cur + 1) %
1120 RT_SOFTC_TX_RING_DESC_COUNT;
1122 desc = &ring->desc[ring->desc_cur];
1125 RT_DPRINTF(sc, RT_DEBUG_TX, "sending data: len=%d, ndmasegs=%d, "
1126 "DMA ds_len=%d/%d/%d/%d/%d\n",
1127 m->m_pkthdr.len, ndmasegs,
1128 (int) dma_seg[0].ds_len,
1129 (int) dma_seg[1].ds_len,
1130 (int) dma_seg[2].ds_len,
1131 (int) dma_seg[3].ds_len,
1132 (int) dma_seg[4].ds_len);
1134 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map,
1135 BUS_DMASYNC_PREWRITE);
1136 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
1137 BUS_DMASYNC_PREWRITE);
1138 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
1139 BUS_DMASYNC_PREWRITE);
1141 ring->desc_queued++;
1142 ring->desc_cur = (ring->desc_cur + 1) % RT_SOFTC_TX_RING_DESC_COUNT;
1144 ring->data_queued++;
1145 ring->data_cur = (ring->data_cur + 1) % RT_SOFTC_TX_RING_DATA_COUNT;
1148 RT_WRITE(sc, sc->tx_ctx_idx[qid], ring->desc_cur);
1154 * rt_start - start Transmit/Receive
1157 rt_start(struct ifnet *ifp)
1159 struct rt_softc *sc;
1161 int qid = 0 /* XXX must check QoS priority */;
1165 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1169 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1173 m->m_pkthdr.rcvif = NULL;
1175 RT_SOFTC_TX_RING_LOCK(&sc->tx_ring[qid]);
1177 if (sc->tx_ring[qid].data_queued >=
1178 RT_SOFTC_TX_RING_DATA_COUNT) {
1179 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]);
1181 RT_DPRINTF(sc, RT_DEBUG_TX,
1182 "if_start: Tx ring with qid=%d is full\n", qid);
1186 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1187 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1189 sc->tx_data_queue_full[qid]++;
1194 if (rt_tx_data(sc, m, qid) != 0) {
1195 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]);
1197 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1202 RT_SOFTC_TX_RING_UNLOCK(&sc->tx_ring[qid]);
1203 sc->tx_timer = RT_TX_WATCHDOG_TIMEOUT;
1204 callout_reset(&sc->tx_watchdog_ch, hz, rt_tx_watchdog, sc);
1209 * rt_update_promisc - set/clear promiscuous mode. Unused yet, because
1210 * filtering done by attached Ethernet switch.
1213 rt_update_promisc(struct ifnet *ifp)
1215 struct rt_softc *sc;
1218 printf("%s: %s promiscuous mode\n",
1219 device_get_nameunit(sc->dev),
1220 (ifp->if_flags & IFF_PROMISC) ? "entering" : "leaving");
1224 * rt_ioctl - ioctl handler.
1227 rt_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1229 struct rt_softc *sc;
1231 #ifdef IF_RT_PHY_SUPPORT
1232 struct mii_data *mii;
1233 #endif /* IF_RT_PHY_SUPPORT */
1234 int error, startall;
1237 ifr = (struct ifreq *) data;
1245 if (ifp->if_flags & IFF_UP) {
1246 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1247 if ((ifp->if_flags ^ sc->if_flags) &
1249 rt_update_promisc(ifp);
1255 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1258 sc->if_flags = ifp->if_flags;
1259 RT_SOFTC_UNLOCK(sc);
1263 #ifdef IF_RT_PHY_SUPPORT
1264 mii = device_get_softc(sc->rt_miibus);
1265 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1267 error = ifmedia_ioctl(ifp, ifr, &sc->rt_ifmedia, cmd);
1268 #endif /* IF_RT_PHY_SUPPORT */
1271 error = ether_ioctl(ifp, cmd, data);
1278 * rt_periodic - Handler of PERIODIC interrupt
1281 rt_periodic(void *arg)
1283 struct rt_softc *sc;
1286 RT_DPRINTF(sc, RT_DEBUG_PERIODIC, "periodic\n");
1287 taskqueue_enqueue(sc->taskqueue, &sc->periodic_task);
1291 * rt_tx_watchdog - Handler of TX Watchdog
1294 rt_tx_watchdog(void *arg)
1296 struct rt_softc *sc;
1302 if (sc->tx_timer == 0)
1305 if (--sc->tx_timer == 0) {
1306 device_printf(sc->dev, "Tx watchdog timeout: resetting\n");
1309 * XXX: Commented out, because reset break input.
1314 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1315 sc->tx_watchdog_timeouts++;
1317 callout_reset(&sc->tx_watchdog_ch, hz, rt_tx_watchdog, sc);
1321 * rt_cnt_ppe_af - Handler of PPE Counter Table Almost Full interrupt
1324 rt_cnt_ppe_af(struct rt_softc *sc)
1327 RT_DPRINTF(sc, RT_DEBUG_INTR, "PPE Counter Table Almost Full\n");
1331 * rt_cnt_gdm_af - Handler of GDMA 1 & 2 Counter Table Almost Full interrupt
1334 rt_cnt_gdm_af(struct rt_softc *sc)
1337 RT_DPRINTF(sc, RT_DEBUG_INTR,
1338 "GDMA 1 & 2 Counter Table Almost Full\n");
1342 * rt_pse_p2_fc - Handler of PSE port2 (GDMA 2) flow control interrupt
1345 rt_pse_p2_fc(struct rt_softc *sc)
1348 RT_DPRINTF(sc, RT_DEBUG_INTR,
1349 "PSE port2 (GDMA 2) flow control asserted.\n");
1353 * rt_gdm_crc_drop - Handler of GDMA 1/2 discard a packet due to CRC error
1357 rt_gdm_crc_drop(struct rt_softc *sc)
1360 RT_DPRINTF(sc, RT_DEBUG_INTR,
1361 "GDMA 1 & 2 discard a packet due to CRC error\n");
1365 * rt_pse_buf_drop - Handler of buffer sharing limitation interrupt
1368 rt_pse_buf_drop(struct rt_softc *sc)
1371 RT_DPRINTF(sc, RT_DEBUG_INTR,
1372 "PSE discards a packet due to buffer sharing limitation\n");
1376 * rt_gdm_other_drop - Handler of discard on other reason interrupt
1379 rt_gdm_other_drop(struct rt_softc *sc)
1382 RT_DPRINTF(sc, RT_DEBUG_INTR,
1383 "GDMA 1 & 2 discard a packet due to other reason\n");
1387 * rt_pse_p1_fc - Handler of PSE port1 (GDMA 1) flow control interrupt
1390 rt_pse_p1_fc(struct rt_softc *sc)
1393 RT_DPRINTF(sc, RT_DEBUG_INTR,
1394 "PSE port1 (GDMA 1) flow control asserted.\n");
1398 * rt_pse_p0_fc - Handler of PSE port0 (CDMA) flow control interrupt
1401 rt_pse_p0_fc(struct rt_softc *sc)
1404 RT_DPRINTF(sc, RT_DEBUG_INTR,
1405 "PSE port0 (CDMA) flow control asserted.\n");
1409 * rt_pse_fq_empty - Handler of PSE free Q empty threshold reached interrupt
1412 rt_pse_fq_empty(struct rt_softc *sc)
1415 RT_DPRINTF(sc, RT_DEBUG_INTR,
1416 "PSE free Q empty threshold reached & forced drop "
1417 "condition occurred.\n");
1421 * rt_intr - main ISR
1426 struct rt_softc *sc;
1433 /* acknowledge interrupts */
1434 status = RT_READ(sc, sc->fe_int_status);
1435 RT_WRITE(sc, sc->fe_int_status, status);
1437 RT_DPRINTF(sc, RT_DEBUG_INTR, "interrupt: status=0x%08x\n", status);
1439 if (status == 0xffffffff || /* device likely went away */
1440 status == 0) /* not for us */
1445 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1448 if (status & CNT_PPE_AF)
1451 if (status & CNT_GDM_AF)
1454 if (status & PSE_P2_FC)
1457 if (status & GDM_CRC_DROP)
1458 rt_gdm_crc_drop(sc);
1460 if (status & PSE_BUF_DROP)
1461 rt_pse_buf_drop(sc);
1463 if (status & GDM_OTHER_DROP)
1464 rt_gdm_other_drop(sc);
1466 if (status & PSE_P1_FC)
1469 if (status & PSE_P0_FC)
1472 if (status & PSE_FQ_EMPTY)
1473 rt_pse_fq_empty(sc);
1475 if (status & INT_TX_COHERENT)
1476 rt_tx_coherent_intr(sc);
1478 if (status & INT_RX_COHERENT)
1479 rt_rx_coherent_intr(sc);
1481 if (status & RX_DLY_INT)
1482 rt_rx_delay_intr(sc);
1484 if (status & TX_DLY_INT)
1485 rt_tx_delay_intr(sc);
1487 if (status & INT_RX_DONE)
1490 if (status & INT_TXQ3_DONE)
1493 if (status & INT_TXQ2_DONE)
1496 if (status & INT_TXQ1_DONE)
1499 if (status & INT_TXQ0_DONE)
1504 * rt_rt5350_intr - main ISR for Ralink 5350 SoC
1507 rt_rt5350_intr(void *arg)
1509 struct rt_softc *sc;
1516 /* acknowledge interrupts */
1517 status = RT_READ(sc, sc->fe_int_status);
1518 RT_WRITE(sc, sc->fe_int_status, status);
1520 RT_DPRINTF(sc, RT_DEBUG_INTR, "interrupt: status=0x%08x\n", status);
1522 if (status == 0xffffffff || /* device likely went away */
1523 status == 0) /* not for us */
1528 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1531 if (status & RT5350_INT_TX_COHERENT)
1532 rt_tx_coherent_intr(sc);
1533 if (status & RT5350_INT_RX_COHERENT)
1534 rt_rx_coherent_intr(sc);
1535 if (status & RT5350_RX_DLY_INT)
1536 rt_rx_delay_intr(sc);
1537 if (status & RT5350_TX_DLY_INT)
1538 rt_tx_delay_intr(sc);
1539 if (status & RT5350_INT_RXQ1_DONE)
1541 if (status & RT5350_INT_RXQ0_DONE)
1543 if (status & RT5350_INT_TXQ3_DONE)
1545 if (status & RT5350_INT_TXQ2_DONE)
1547 if (status & RT5350_INT_TXQ1_DONE)
1549 if (status & RT5350_INT_TXQ0_DONE)
1554 rt_tx_coherent_intr(struct rt_softc *sc)
1559 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx coherent interrupt\n");
1561 sc->tx_coherent_interrupts++;
1563 /* restart DMA engine */
1564 tmp = RT_READ(sc, sc->pdma_glo_cfg);
1565 tmp &= ~(FE_TX_WB_DDONE | FE_TX_DMA_EN);
1566 RT_WRITE(sc, sc->pdma_glo_cfg, tmp);
1568 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
1569 rt_reset_tx_ring(sc, &sc->tx_ring[i]);
1571 for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
1572 RT_WRITE(sc, sc->tx_base_ptr[i],
1573 sc->tx_ring[i].desc_phys_addr);
1574 RT_WRITE(sc, sc->tx_max_cnt[i],
1575 RT_SOFTC_TX_RING_DESC_COUNT);
1576 RT_WRITE(sc, sc->tx_ctx_idx[i], 0);
1583 * rt_rx_coherent_intr
1586 rt_rx_coherent_intr(struct rt_softc *sc)
1591 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx coherent interrupt\n");
1593 sc->rx_coherent_interrupts++;
1595 /* restart DMA engine */
1596 tmp = RT_READ(sc, sc->pdma_glo_cfg);
1597 tmp &= ~(FE_RX_DMA_EN);
1598 RT_WRITE(sc, sc->pdma_glo_cfg, tmp);
1601 for (i = 0; i < sc->rx_ring_count; i++)
1602 rt_reset_rx_ring(sc, &sc->rx_ring[i]);
1604 for (i = 0; i < sc->rx_ring_count; i++) {
1605 RT_WRITE(sc, sc->rx_base_ptr[i],
1606 sc->rx_ring[i].desc_phys_addr);
1607 RT_WRITE(sc, sc->rx_max_cnt[i],
1608 RT_SOFTC_RX_RING_DATA_COUNT);
1609 RT_WRITE(sc, sc->rx_calc_idx[i],
1610 RT_SOFTC_RX_RING_DATA_COUNT - 1);
1617 * rt_rx_intr - a packet received
1620 rt_rx_intr(struct rt_softc *sc, int qid)
1622 KASSERT(qid >= 0 && qid < sc->rx_ring_count,
1623 ("%s: Rx interrupt: invalid qid=%d\n",
1624 device_get_nameunit(sc->dev), qid));
1626 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx interrupt\n");
1627 sc->rx_interrupts[qid]++;
1630 if (!(sc->intr_disable_mask & (sc->int_rx_done_mask << qid))) {
1631 rt_intr_disable(sc, (sc->int_rx_done_mask << qid));
1632 taskqueue_enqueue(sc->taskqueue, &sc->rx_done_task);
1635 sc->intr_pending_mask |= (sc->int_rx_done_mask << qid);
1636 RT_SOFTC_UNLOCK(sc);
1640 rt_rx_delay_intr(struct rt_softc *sc)
1643 RT_DPRINTF(sc, RT_DEBUG_INTR, "Rx delay interrupt\n");
1644 sc->rx_delay_interrupts++;
1648 rt_tx_delay_intr(struct rt_softc *sc)
1651 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx delay interrupt\n");
1652 sc->tx_delay_interrupts++;
1656 * rt_tx_intr - Transsmition of packet done
1659 rt_tx_intr(struct rt_softc *sc, int qid)
1662 KASSERT(qid >= 0 && qid < RT_SOFTC_TX_RING_COUNT,
1663 ("%s: Tx interrupt: invalid qid=%d\n",
1664 device_get_nameunit(sc->dev), qid));
1666 RT_DPRINTF(sc, RT_DEBUG_INTR, "Tx interrupt: qid=%d\n", qid);
1668 sc->tx_interrupts[qid]++;
1671 if (!(sc->intr_disable_mask & (sc->int_tx_done_mask << qid))) {
1672 rt_intr_disable(sc, (sc->int_tx_done_mask << qid));
1673 taskqueue_enqueue(sc->taskqueue, &sc->tx_done_task);
1676 sc->intr_pending_mask |= (sc->int_tx_done_mask << qid);
1677 RT_SOFTC_UNLOCK(sc);
1681 * rt_rx_done_task - run RX task
1684 rt_rx_done_task(void *context, int pending)
1686 struct rt_softc *sc;
1693 RT_DPRINTF(sc, RT_DEBUG_RX, "Rx done task\n");
1695 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1698 sc->intr_pending_mask &= ~sc->int_rx_done_mask;
1700 again = rt_rx_eof(sc, &sc->rx_ring[0], sc->rx_process_limit);
1704 if ((sc->intr_pending_mask & sc->int_rx_done_mask) || again) {
1705 RT_DPRINTF(sc, RT_DEBUG_RX,
1706 "Rx done task: scheduling again\n");
1707 taskqueue_enqueue(sc->taskqueue, &sc->rx_done_task);
1709 rt_intr_enable(sc, sc->int_rx_done_mask);
1712 RT_SOFTC_UNLOCK(sc);
1716 * rt_tx_done_task - check for pending TX task in all queues
1719 rt_tx_done_task(void *context, int pending)
1721 struct rt_softc *sc;
1729 RT_DPRINTF(sc, RT_DEBUG_TX, "Tx done task\n");
1731 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1734 for (i = RT_SOFTC_TX_RING_COUNT - 1; i >= 0; i--) {
1735 if (sc->intr_pending_mask & (sc->int_tx_done_mask << i)) {
1736 sc->intr_pending_mask &= ~(sc->int_tx_done_mask << i);
1737 rt_tx_eof(sc, &sc->tx_ring[i]);
1743 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1745 if(sc->rt_chipid == RT_CHIPID_RT5350 ||
1746 sc->rt_chipid == RT_CHIPID_MT7620 ||
1747 sc->rt_chipid == RT_CHIPID_MT7621)
1749 RT5350_INT_TXQ3_DONE |
1750 RT5350_INT_TXQ2_DONE |
1751 RT5350_INT_TXQ1_DONE |
1752 RT5350_INT_TXQ0_DONE);
1762 rt_intr_enable(sc, ~sc->intr_pending_mask &
1763 (sc->intr_disable_mask & intr_mask));
1765 if (sc->intr_pending_mask & intr_mask) {
1766 RT_DPRINTF(sc, RT_DEBUG_TX,
1767 "Tx done task: scheduling again\n");
1768 taskqueue_enqueue(sc->taskqueue, &sc->tx_done_task);
1771 RT_SOFTC_UNLOCK(sc);
1773 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1778 * rt_periodic_task - run periodic task
1781 rt_periodic_task(void *context, int pending)
1783 struct rt_softc *sc;
1789 RT_DPRINTF(sc, RT_DEBUG_PERIODIC, "periodic task: round=%lu\n",
1790 sc->periodic_round);
1792 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1796 sc->periodic_round++;
1797 rt_update_stats(sc);
1799 if ((sc->periodic_round % 10) == 0) {
1800 rt_update_raw_counters(sc);
1804 RT_SOFTC_UNLOCK(sc);
1805 callout_reset(&sc->periodic_ch, hz / 10, rt_periodic, sc);
1809 * rt_rx_eof - check for frames that done by DMA engine and pass it into
1810 * network subsystem.
1813 rt_rx_eof(struct rt_softc *sc, struct rt_softc_rx_ring *ring, int limit)
1816 /* struct rt_softc_rx_ring *ring; */
1817 struct rt_rxdesc *desc;
1818 struct rt_softc_rx_data *data;
1819 struct mbuf *m, *mnew;
1820 bus_dma_segment_t segs[1];
1821 bus_dmamap_t dma_map;
1822 uint32_t index, desc_flags;
1823 int error, nsegs, len, nframes;
1826 /* ring = &sc->rx_ring[0]; */
1830 while (limit != 0) {
1831 index = RT_READ(sc, sc->rx_drx_idx[0]);
1832 if (ring->cur == index)
1835 desc = &ring->desc[ring->cur];
1836 data = &ring->data[ring->cur];
1838 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
1839 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1842 if ( sc->debug & RT_DEBUG_RX ) {
1843 printf("\nRX Descriptor[%#08x] dump:\n", (u_int)desc);
1844 hexdump(desc, 16, 0, 0);
1845 printf("-----------------------------------\n");
1849 /* XXX Sometime device don`t set DDONE bit */
1851 if (!(desc->sdl0 & htole16(RT_RXDESC_SDL0_DDONE))) {
1852 RT_DPRINTF(sc, RT_DEBUG_RX, "DDONE=0, try next\n");
1857 len = le16toh(desc->sdl0) & 0x3fff;
1858 RT_DPRINTF(sc, RT_DEBUG_RX, "new frame len=%d\n", len);
1862 mnew = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
1865 sc->rx_mbuf_alloc_errors++;
1866 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1870 mnew->m_len = mnew->m_pkthdr.len = MJUMPAGESIZE;
1872 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag,
1873 ring->spare_dma_map, mnew, segs, &nsegs, BUS_DMA_NOWAIT);
1875 RT_DPRINTF(sc, RT_DEBUG_RX,
1876 "could not load Rx mbuf DMA map: "
1877 "error=%d, nsegs=%d\n",
1882 sc->rx_mbuf_dmamap_errors++;
1883 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1888 KASSERT(nsegs == 1, ("%s: too many DMA segments",
1889 device_get_nameunit(sc->dev)));
1891 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
1892 BUS_DMASYNC_POSTREAD);
1893 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
1895 dma_map = data->dma_map;
1896 data->dma_map = ring->spare_dma_map;
1897 ring->spare_dma_map = dma_map;
1899 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
1900 BUS_DMASYNC_PREREAD);
1903 desc_flags = desc->word3;
1906 /* Add 2 for proper align of RX IP header */
1907 desc->sdp0 = htole32(segs[0].ds_addr+2);
1908 desc->sdl0 = htole32(segs[0].ds_len-2);
1911 RT_DPRINTF(sc, RT_DEBUG_RX,
1912 "Rx frame: rxdesc flags=0x%08x\n", desc_flags);
1914 m->m_pkthdr.rcvif = ifp;
1915 /* Add 2 to fix data align, after sdp0 = addr + 2 */
1917 m->m_pkthdr.len = m->m_len = len;
1919 /* check for crc errors */
1920 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1921 /*check for valid checksum*/
1922 if (desc_flags & (sc->csum_fail_ip|sc->csum_fail_l4)) {
1923 RT_DPRINTF(sc, RT_DEBUG_RX,
1924 "rxdesc: crc error\n");
1926 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1928 if (!(ifp->if_flags & IFF_PROMISC)) {
1933 if ((desc_flags & sc->csum_fail_ip) == 0) {
1934 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1935 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1936 m->m_pkthdr.csum_data = 0xffff;
1938 m->m_flags &= ~M_HASFCS;
1941 (*ifp->if_input)(ifp, m);
1943 desc->sdl0 &= ~htole16(RT_RXDESC_SDL0_DDONE);
1945 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
1946 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1948 ring->cur = (ring->cur + 1) % RT_SOFTC_RX_RING_DATA_COUNT;
1954 RT_WRITE(sc, sc->rx_calc_idx[0],
1955 RT_SOFTC_RX_RING_DATA_COUNT - 1);
1957 RT_WRITE(sc, sc->rx_calc_idx[0],
1960 RT_DPRINTF(sc, RT_DEBUG_RX, "Rx eof: nframes=%d\n", nframes);
1962 sc->rx_packets += nframes;
1964 return (limit == 0);
1968 * rt_tx_eof - check for successful transmitted frames and mark their
1969 * descriptor as free.
1972 rt_tx_eof(struct rt_softc *sc, struct rt_softc_tx_ring *ring)
1975 struct rt_txdesc *desc;
1976 struct rt_softc_tx_data *data;
1978 int ndescs, nframes;
1986 index = RT_READ(sc, sc->tx_dtx_idx[ring->qid]);
1987 if (ring->desc_next == index)
1992 desc = &ring->desc[ring->desc_next];
1994 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
1995 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1997 if (desc->sdl0 & htole16(RT_TXDESC_SDL0_LASTSEG) ||
1998 desc->sdl1 & htole16(RT_TXDESC_SDL1_LASTSEG)) {
2001 data = &ring->data[ring->data_next];
2003 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
2004 BUS_DMASYNC_POSTWRITE);
2005 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
2011 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2013 RT_SOFTC_TX_RING_LOCK(ring);
2014 ring->data_queued--;
2015 ring->data_next = (ring->data_next + 1) %
2016 RT_SOFTC_TX_RING_DATA_COUNT;
2017 RT_SOFTC_TX_RING_UNLOCK(ring);
2020 desc->sdl0 &= ~htole16(RT_TXDESC_SDL0_DDONE);
2022 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2023 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2025 RT_SOFTC_TX_RING_LOCK(ring);
2026 ring->desc_queued--;
2027 ring->desc_next = (ring->desc_next + 1) %
2028 RT_SOFTC_TX_RING_DESC_COUNT;
2029 RT_SOFTC_TX_RING_UNLOCK(ring);
2032 RT_DPRINTF(sc, RT_DEBUG_TX,
2033 "Tx eof: qid=%d, ndescs=%d, nframes=%d\n", ring->qid, ndescs,
2038 * rt_update_stats - query statistics counters and update related variables.
2041 rt_update_stats(struct rt_softc *sc)
2046 RT_DPRINTF(sc, RT_DEBUG_STATS, "update statistic: \n");
2047 /* XXX do update stats here */
2051 * rt_watchdog - reinit device on watchdog event.
2054 rt_watchdog(struct rt_softc *sc)
2060 if(sc->rt_chipid != RT_CHIPID_RT5350 &&
2061 sc->rt_chipid != RT_CHIPID_MT7620 &&
2062 sc->rt_chipid != RT_CHIPID_MT7621) {
2063 tmp = RT_READ(sc, PSE_BASE + CDMA_OQ_STA);
2065 RT_DPRINTF(sc, RT_DEBUG_WATCHDOG,
2066 "watchdog: PSE_IQ_STA=0x%08x\n", tmp);
2068 /* XXX: do not reset */
2070 if (((tmp >> P0_IQ_PCNT_SHIFT) & 0xff) != 0) {
2071 sc->tx_queue_not_empty[0]++;
2073 for (ntries = 0; ntries < 10; ntries++) {
2074 tmp = RT_READ(sc, PSE_BASE + PSE_IQ_STA);
2075 if (((tmp >> P0_IQ_PCNT_SHIFT) & 0xff) == 0)
2082 if (((tmp >> P1_IQ_PCNT_SHIFT) & 0xff) != 0) {
2083 sc->tx_queue_not_empty[1]++;
2085 for (ntries = 0; ntries < 10; ntries++) {
2086 tmp = RT_READ(sc, PSE_BASE + PSE_IQ_STA);
2087 if (((tmp >> P1_IQ_PCNT_SHIFT) & 0xff) == 0)
2097 * rt_update_raw_counters - update counters.
2100 rt_update_raw_counters(struct rt_softc *sc)
2103 sc->tx_bytes += RT_READ(sc, CNTR_BASE + GDMA_TX_GBCNT0);
2104 sc->tx_packets += RT_READ(sc, CNTR_BASE + GDMA_TX_GPCNT0);
2105 sc->tx_skip += RT_READ(sc, CNTR_BASE + GDMA_TX_SKIPCNT0);
2106 sc->tx_collision+= RT_READ(sc, CNTR_BASE + GDMA_TX_COLCNT0);
2108 sc->rx_bytes += RT_READ(sc, CNTR_BASE + GDMA_RX_GBCNT0);
2109 sc->rx_packets += RT_READ(sc, CNTR_BASE + GDMA_RX_GPCNT0);
2110 sc->rx_crc_err += RT_READ(sc, CNTR_BASE + GDMA_RX_CSUM_ERCNT0);
2111 sc->rx_short_err+= RT_READ(sc, CNTR_BASE + GDMA_RX_SHORT_ERCNT0);
2112 sc->rx_long_err += RT_READ(sc, CNTR_BASE + GDMA_RX_LONG_ERCNT0);
2113 sc->rx_phy_err += RT_READ(sc, CNTR_BASE + GDMA_RX_FERCNT0);
2114 sc->rx_fifo_overflows+= RT_READ(sc, CNTR_BASE + GDMA_RX_OERCNT0);
2118 rt_intr_enable(struct rt_softc *sc, uint32_t intr_mask)
2122 sc->intr_disable_mask &= ~intr_mask;
2123 tmp = sc->intr_enable_mask & ~sc->intr_disable_mask;
2124 RT_WRITE(sc, sc->fe_int_enable, tmp);
2128 rt_intr_disable(struct rt_softc *sc, uint32_t intr_mask)
2132 sc->intr_disable_mask |= intr_mask;
2133 tmp = sc->intr_enable_mask & ~sc->intr_disable_mask;
2134 RT_WRITE(sc, sc->fe_int_enable, tmp);
2138 * rt_txrx_enable - enable TX/RX DMA
2141 rt_txrx_enable(struct rt_softc *sc)
2149 /* enable Tx/Rx DMA engine */
2150 for (ntries = 0; ntries < 200; ntries++) {
2151 tmp = RT_READ(sc, sc->pdma_glo_cfg);
2152 if (!(tmp & (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)))
2158 if (ntries == 200) {
2159 device_printf(sc->dev, "timeout waiting for DMA engine\n");
2165 tmp |= FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
2166 RT_WRITE(sc, sc->pdma_glo_cfg, tmp);
2168 /* XXX set Rx filter */
2173 * rt_alloc_rx_ring - allocate RX DMA ring buffer
2176 rt_alloc_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring, int qid)
2178 struct rt_rxdesc *desc;
2179 struct rt_softc_rx_data *data;
2180 bus_dma_segment_t segs[1];
2181 int i, nsegs, error;
2183 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2184 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2185 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc), 1,
2186 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc),
2187 0, NULL, NULL, &ring->desc_dma_tag);
2189 device_printf(sc->dev,
2190 "could not create Rx desc DMA tag\n");
2194 error = bus_dmamem_alloc(ring->desc_dma_tag, (void **) &ring->desc,
2195 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_dma_map);
2197 device_printf(sc->dev,
2198 "could not allocate Rx desc DMA memory\n");
2202 error = bus_dmamap_load(ring->desc_dma_tag, ring->desc_dma_map,
2204 RT_SOFTC_RX_RING_DATA_COUNT * sizeof(struct rt_rxdesc),
2205 rt_dma_map_addr, &ring->desc_phys_addr, 0);
2207 device_printf(sc->dev, "could not load Rx desc DMA map\n");
2211 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2212 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2213 MJUMPAGESIZE, 1, MJUMPAGESIZE, 0, NULL, NULL,
2214 &ring->data_dma_tag);
2216 device_printf(sc->dev,
2217 "could not create Rx data DMA tag\n");
2221 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) {
2222 desc = &ring->desc[i];
2223 data = &ring->data[i];
2225 error = bus_dmamap_create(ring->data_dma_tag, 0,
2228 device_printf(sc->dev, "could not create Rx data DMA "
2233 data->m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
2235 if (data->m == NULL) {
2236 device_printf(sc->dev, "could not allocate Rx mbuf\n");
2241 data->m->m_len = data->m->m_pkthdr.len = MJUMPAGESIZE;
2243 error = bus_dmamap_load_mbuf_sg(ring->data_dma_tag,
2244 data->dma_map, data->m, segs, &nsegs, BUS_DMA_NOWAIT);
2246 device_printf(sc->dev,
2247 "could not load Rx mbuf DMA map\n");
2251 KASSERT(nsegs == 1, ("%s: too many DMA segments",
2252 device_get_nameunit(sc->dev)));
2254 /* Add 2 for proper align of RX IP header */
2255 desc->sdp0 = htole32(segs[0].ds_addr+2);
2256 desc->sdl0 = htole32(segs[0].ds_len-2);
2259 error = bus_dmamap_create(ring->data_dma_tag, 0,
2260 &ring->spare_dma_map);
2262 device_printf(sc->dev,
2263 "could not create Rx spare DMA map\n");
2267 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2268 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2273 rt_free_rx_ring(sc, ring);
2278 * rt_reset_rx_ring - reset RX ring buffer
2281 rt_reset_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring)
2283 struct rt_rxdesc *desc;
2286 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) {
2287 desc = &ring->desc[i];
2288 desc->sdl0 &= ~htole16(RT_RXDESC_SDL0_DDONE);
2291 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2292 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2297 * rt_free_rx_ring - free memory used by RX ring buffer
2300 rt_free_rx_ring(struct rt_softc *sc, struct rt_softc_rx_ring *ring)
2302 struct rt_softc_rx_data *data;
2305 if (ring->desc != NULL) {
2306 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2307 BUS_DMASYNC_POSTWRITE);
2308 bus_dmamap_unload(ring->desc_dma_tag, ring->desc_dma_map);
2309 bus_dmamem_free(ring->desc_dma_tag, ring->desc,
2310 ring->desc_dma_map);
2313 if (ring->desc_dma_tag != NULL)
2314 bus_dma_tag_destroy(ring->desc_dma_tag);
2316 for (i = 0; i < RT_SOFTC_RX_RING_DATA_COUNT; i++) {
2317 data = &ring->data[i];
2319 if (data->m != NULL) {
2320 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
2321 BUS_DMASYNC_POSTREAD);
2322 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
2326 if (data->dma_map != NULL)
2327 bus_dmamap_destroy(ring->data_dma_tag, data->dma_map);
2330 if (ring->spare_dma_map != NULL)
2331 bus_dmamap_destroy(ring->data_dma_tag, ring->spare_dma_map);
2333 if (ring->data_dma_tag != NULL)
2334 bus_dma_tag_destroy(ring->data_dma_tag);
2338 * rt_alloc_tx_ring - allocate TX ring buffer
2341 rt_alloc_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring, int qid)
2343 struct rt_softc_tx_data *data;
2346 mtx_init(&ring->lock, device_get_nameunit(sc->dev), NULL, MTX_DEF);
2348 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2349 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2350 RT_SOFTC_TX_RING_DESC_COUNT * sizeof(struct rt_txdesc), 1,
2351 RT_SOFTC_TX_RING_DESC_COUNT * sizeof(struct rt_txdesc),
2352 0, NULL, NULL, &ring->desc_dma_tag);
2354 device_printf(sc->dev,
2355 "could not create Tx desc DMA tag\n");
2359 error = bus_dmamem_alloc(ring->desc_dma_tag, (void **) &ring->desc,
2360 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_dma_map);
2362 device_printf(sc->dev,
2363 "could not allocate Tx desc DMA memory\n");
2367 error = bus_dmamap_load(ring->desc_dma_tag, ring->desc_dma_map,
2368 ring->desc, (RT_SOFTC_TX_RING_DESC_COUNT *
2369 sizeof(struct rt_txdesc)), rt_dma_map_addr,
2370 &ring->desc_phys_addr, 0);
2372 device_printf(sc->dev, "could not load Tx desc DMA map\n");
2376 ring->desc_queued = 0;
2378 ring->desc_next = 0;
2380 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2381 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2382 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE, 1,
2383 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE,
2384 0, NULL, NULL, &ring->seg0_dma_tag);
2386 device_printf(sc->dev,
2387 "could not create Tx seg0 DMA tag\n");
2391 error = bus_dmamem_alloc(ring->seg0_dma_tag, (void **) &ring->seg0,
2392 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->seg0_dma_map);
2394 device_printf(sc->dev,
2395 "could not allocate Tx seg0 DMA memory\n");
2399 error = bus_dmamap_load(ring->seg0_dma_tag, ring->seg0_dma_map,
2401 RT_SOFTC_TX_RING_DATA_COUNT * RT_TX_DATA_SEG0_SIZE,
2402 rt_dma_map_addr, &ring->seg0_phys_addr, 0);
2404 device_printf(sc->dev, "could not load Tx seg0 DMA map\n");
2408 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), PAGE_SIZE, 0,
2409 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
2410 MJUMPAGESIZE, RT_SOFTC_MAX_SCATTER, MJUMPAGESIZE, 0, NULL, NULL,
2411 &ring->data_dma_tag);
2413 device_printf(sc->dev,
2414 "could not create Tx data DMA tag\n");
2418 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) {
2419 data = &ring->data[i];
2421 error = bus_dmamap_create(ring->data_dma_tag, 0,
2424 device_printf(sc->dev, "could not create Tx data DMA "
2430 ring->data_queued = 0;
2432 ring->data_next = 0;
2438 rt_free_tx_ring(sc, ring);
2443 * rt_reset_tx_ring - reset TX ring buffer to empty state
2446 rt_reset_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring)
2448 struct rt_softc_tx_data *data;
2449 struct rt_txdesc *desc;
2452 for (i = 0; i < RT_SOFTC_TX_RING_DESC_COUNT; i++) {
2453 desc = &ring->desc[i];
2459 ring->desc_queued = 0;
2461 ring->desc_next = 0;
2463 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2464 BUS_DMASYNC_PREWRITE);
2466 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map,
2467 BUS_DMASYNC_PREWRITE);
2469 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) {
2470 data = &ring->data[i];
2472 if (data->m != NULL) {
2473 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
2474 BUS_DMASYNC_POSTWRITE);
2475 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
2481 ring->data_queued = 0;
2483 ring->data_next = 0;
2487 * rt_free_tx_ring - free RX ring buffer
2490 rt_free_tx_ring(struct rt_softc *sc, struct rt_softc_tx_ring *ring)
2492 struct rt_softc_tx_data *data;
2495 if (ring->desc != NULL) {
2496 bus_dmamap_sync(ring->desc_dma_tag, ring->desc_dma_map,
2497 BUS_DMASYNC_POSTWRITE);
2498 bus_dmamap_unload(ring->desc_dma_tag, ring->desc_dma_map);
2499 bus_dmamem_free(ring->desc_dma_tag, ring->desc,
2500 ring->desc_dma_map);
2503 if (ring->desc_dma_tag != NULL)
2504 bus_dma_tag_destroy(ring->desc_dma_tag);
2506 if (ring->seg0 != NULL) {
2507 bus_dmamap_sync(ring->seg0_dma_tag, ring->seg0_dma_map,
2508 BUS_DMASYNC_POSTWRITE);
2509 bus_dmamap_unload(ring->seg0_dma_tag, ring->seg0_dma_map);
2510 bus_dmamem_free(ring->seg0_dma_tag, ring->seg0,
2511 ring->seg0_dma_map);
2514 if (ring->seg0_dma_tag != NULL)
2515 bus_dma_tag_destroy(ring->seg0_dma_tag);
2517 for (i = 0; i < RT_SOFTC_TX_RING_DATA_COUNT; i++) {
2518 data = &ring->data[i];
2520 if (data->m != NULL) {
2521 bus_dmamap_sync(ring->data_dma_tag, data->dma_map,
2522 BUS_DMASYNC_POSTWRITE);
2523 bus_dmamap_unload(ring->data_dma_tag, data->dma_map);
2527 if (data->dma_map != NULL)
2528 bus_dmamap_destroy(ring->data_dma_tag, data->dma_map);
2531 if (ring->data_dma_tag != NULL)
2532 bus_dma_tag_destroy(ring->data_dma_tag);
2534 mtx_destroy(&ring->lock);
2538 * rt_dma_map_addr - get address of busdma segment
2541 rt_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2546 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
2548 *(bus_addr_t *) arg = segs[0].ds_addr;
2552 * rt_sysctl_attach - attach sysctl nodes for NIC counters.
2555 rt_sysctl_attach(struct rt_softc *sc)
2557 struct sysctl_ctx_list *ctx;
2558 struct sysctl_oid *tree;
2559 struct sysctl_oid *stats;
2561 ctx = device_get_sysctl_ctx(sc->dev);
2562 tree = device_get_sysctl_tree(sc->dev);
2564 /* statistic counters */
2565 stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
2566 "stats", CTLFLAG_RD, 0, "statistic");
2568 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2569 "interrupts", CTLFLAG_RD, &sc->interrupts,
2572 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2573 "tx_coherent_interrupts", CTLFLAG_RD, &sc->tx_coherent_interrupts,
2574 "Tx coherent interrupts");
2576 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2577 "rx_coherent_interrupts", CTLFLAG_RD, &sc->rx_coherent_interrupts,
2578 "Rx coherent interrupts");
2580 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2581 "rx_interrupts", CTLFLAG_RD, &sc->rx_interrupts[0],
2584 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2585 "rx_delay_interrupts", CTLFLAG_RD, &sc->rx_delay_interrupts,
2586 "Rx delay interrupts");
2588 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2589 "TXQ3_interrupts", CTLFLAG_RD, &sc->tx_interrupts[3],
2590 "Tx AC3 interrupts");
2592 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2593 "TXQ2_interrupts", CTLFLAG_RD, &sc->tx_interrupts[2],
2594 "Tx AC2 interrupts");
2596 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2597 "TXQ1_interrupts", CTLFLAG_RD, &sc->tx_interrupts[1],
2598 "Tx AC1 interrupts");
2600 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2601 "TXQ0_interrupts", CTLFLAG_RD, &sc->tx_interrupts[0],
2602 "Tx AC0 interrupts");
2604 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2605 "tx_delay_interrupts", CTLFLAG_RD, &sc->tx_delay_interrupts,
2606 "Tx delay interrupts");
2608 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2609 "TXQ3_desc_queued", CTLFLAG_RD, &sc->tx_ring[3].desc_queued,
2610 0, "Tx AC3 descriptors queued");
2612 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2613 "TXQ3_data_queued", CTLFLAG_RD, &sc->tx_ring[3].data_queued,
2614 0, "Tx AC3 data queued");
2616 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2617 "TXQ2_desc_queued", CTLFLAG_RD, &sc->tx_ring[2].desc_queued,
2618 0, "Tx AC2 descriptors queued");
2620 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2621 "TXQ2_data_queued", CTLFLAG_RD, &sc->tx_ring[2].data_queued,
2622 0, "Tx AC2 data queued");
2624 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2625 "TXQ1_desc_queued", CTLFLAG_RD, &sc->tx_ring[1].desc_queued,
2626 0, "Tx AC1 descriptors queued");
2628 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2629 "TXQ1_data_queued", CTLFLAG_RD, &sc->tx_ring[1].data_queued,
2630 0, "Tx AC1 data queued");
2632 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2633 "TXQ0_desc_queued", CTLFLAG_RD, &sc->tx_ring[0].desc_queued,
2634 0, "Tx AC0 descriptors queued");
2636 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2637 "TXQ0_data_queued", CTLFLAG_RD, &sc->tx_ring[0].data_queued,
2638 0, "Tx AC0 data queued");
2640 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2641 "TXQ3_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[3],
2642 "Tx AC3 data queue full");
2644 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2645 "TXQ2_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[2],
2646 "Tx AC2 data queue full");
2648 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2649 "TXQ1_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[1],
2650 "Tx AC1 data queue full");
2652 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2653 "TXQ0_data_queue_full", CTLFLAG_RD, &sc->tx_data_queue_full[0],
2654 "Tx AC0 data queue full");
2656 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2657 "tx_watchdog_timeouts", CTLFLAG_RD, &sc->tx_watchdog_timeouts,
2658 "Tx watchdog timeouts");
2660 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2661 "tx_defrag_packets", CTLFLAG_RD, &sc->tx_defrag_packets,
2662 "Tx defragmented packets");
2664 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2665 "no_tx_desc_avail", CTLFLAG_RD, &sc->no_tx_desc_avail,
2666 "no Tx descriptors available");
2668 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2669 "rx_mbuf_alloc_errors", CTLFLAG_RD, &sc->rx_mbuf_alloc_errors,
2670 "Rx mbuf allocation errors");
2672 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2673 "rx_mbuf_dmamap_errors", CTLFLAG_RD, &sc->rx_mbuf_dmamap_errors,
2674 "Rx mbuf DMA mapping errors");
2676 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2677 "tx_queue_0_not_empty", CTLFLAG_RD, &sc->tx_queue_not_empty[0],
2678 "Tx queue 0 not empty");
2680 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2681 "tx_queue_1_not_empty", CTLFLAG_RD, &sc->tx_queue_not_empty[1],
2682 "Tx queue 1 not empty");
2684 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2685 "rx_packets", CTLFLAG_RD, &sc->rx_packets,
2688 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2689 "rx_crc_errors", CTLFLAG_RD, &sc->rx_crc_err,
2692 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2693 "rx_phy_errors", CTLFLAG_RD, &sc->rx_phy_err,
2696 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2697 "rx_dup_packets", CTLFLAG_RD, &sc->rx_dup_packets,
2698 "Rx duplicate packets");
2700 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2701 "rx_fifo_overflows", CTLFLAG_RD, &sc->rx_fifo_overflows,
2702 "Rx FIFO overflows");
2704 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2705 "rx_bytes", CTLFLAG_RD, &sc->rx_bytes,
2708 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2709 "rx_long_err", CTLFLAG_RD, &sc->rx_long_err,
2710 "Rx too long frame errors");
2712 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2713 "rx_short_err", CTLFLAG_RD, &sc->rx_short_err,
2714 "Rx too short frame errors");
2716 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2717 "tx_bytes", CTLFLAG_RD, &sc->tx_bytes,
2720 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2721 "tx_packets", CTLFLAG_RD, &sc->tx_packets,
2724 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2725 "tx_skip", CTLFLAG_RD, &sc->tx_skip,
2726 "Tx skip count for GDMA ports");
2728 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(stats), OID_AUTO,
2729 "tx_collision", CTLFLAG_RD, &sc->tx_collision,
2730 "Tx collision count for GDMA ports");
2733 #ifdef IF_RT_PHY_SUPPORT
2735 rt_miibus_readreg(device_t dev, int phy, int reg)
2737 struct rt_softc *sc = device_get_softc(dev);
2740 * PSEUDO_PHYAD is a special value for indicate switch attached.
2741 * No one PHY use PSEUDO_PHYAD (0x1e) address.
2744 /* Fake PHY ID for bfeswitch attach */
2747 return (BMSR_EXTSTAT|BMSR_MEDIAMASK);
2749 return (0x40); /* As result of faking */
2750 case MII_PHYIDR2: /* PHY will detect as */
2751 return (0x6250); /* bfeswitch */
2755 /* Wait prev command done if any */
2756 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2757 RT_WRITE(sc, MDIO_ACCESS,
2759 ((phy << MDIO_PHY_ADDR_SHIFT) & MDIO_PHY_ADDR_MASK) ||
2760 ((reg << MDIO_PHYREG_ADDR_SHIFT) & MDIO_PHYREG_ADDR_MASK));
2761 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2763 return (RT_READ(sc, MDIO_ACCESS) & MDIO_PHY_DATA_MASK);
2767 rt_miibus_writereg(device_t dev, int phy, int reg, int val)
2769 struct rt_softc *sc = device_get_softc(dev);
2771 /* Wait prev command done if any */
2772 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2773 RT_WRITE(sc, MDIO_ACCESS,
2774 MDIO_CMD_ONGO || MDIO_CMD_WR ||
2775 ((phy << MDIO_PHY_ADDR_SHIFT) & MDIO_PHY_ADDR_MASK) ||
2776 ((reg << MDIO_PHYREG_ADDR_SHIFT) & MDIO_PHYREG_ADDR_MASK) ||
2777 (val & MDIO_PHY_DATA_MASK));
2778 while (RT_READ(sc, MDIO_ACCESS) & MDIO_CMD_ONGO);
2784 rt_miibus_statchg(device_t dev)
2786 struct rt_softc *sc = device_get_softc(dev);
2787 struct mii_data *mii;
2789 mii = device_get_softc(sc->rt_miibus);
2791 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
2792 (IFM_ACTIVE | IFM_AVALID)) {
2793 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2796 /* XXX check link here */
2804 #endif /* IF_RT_PHY_SUPPORT */
2806 static device_method_t rt_dev_methods[] =
2808 DEVMETHOD(device_probe, rt_probe),
2809 DEVMETHOD(device_attach, rt_attach),
2810 DEVMETHOD(device_detach, rt_detach),
2811 DEVMETHOD(device_shutdown, rt_shutdown),
2812 DEVMETHOD(device_suspend, rt_suspend),
2813 DEVMETHOD(device_resume, rt_resume),
2815 #ifdef IF_RT_PHY_SUPPORT
2817 DEVMETHOD(miibus_readreg, rt_miibus_readreg),
2818 DEVMETHOD(miibus_writereg, rt_miibus_writereg),
2819 DEVMETHOD(miibus_statchg, rt_miibus_statchg),
2825 static driver_t rt_driver =
2829 sizeof(struct rt_softc)
2832 static devclass_t rt_dev_class;
2834 DRIVER_MODULE(rt, nexus, rt_driver, rt_dev_class, 0, 0);
2836 DRIVER_MODULE(rt, simplebus, rt_driver, rt_dev_class, 0, 0);
2839 MODULE_DEPEND(rt, ether, 1, 1, 1);
2840 MODULE_DEPEND(rt, miibus, 1, 1, 1);