2 * Copyright (c) 2009, Aleksandr Rybalko
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #define RT_READ(sc, reg) \
34 bus_space_read_4((sc)->bst, (sc)->bsh, reg)
36 #define RT_WRITE(sc, reg, val) \
37 bus_space_write_4((sc)->bst, (sc)->bsh, reg, val)
39 #define GE_PORT_BASE 0x0000
41 #define MDIO_ACCESS 0x00
42 #define MDIO_CMD_ONGO (1<<31)
43 #define MDIO_CMD_WR (1<<30)
44 #define MDIO_PHY_ADDR_MASK 0x1f000000
45 #define MDIO_PHY_ADDR_SHIFT 24
46 #define MDIO_PHYREG_ADDR_MASK 0x001f0000
47 #define MDIO_PHYREG_ADDR_SHIFT 16
48 #define MDIO_PHY_DATA_MASK 0x0000ffff
49 #define MDIO_PHY_DATA_SHIFT 0
51 #define FE_GLO_CFG 0x08 /*Frame Engine Global Configuration */
52 #define EXT_VLAN_TYPE_MASK 0xffff0000
53 #define EXT_VLAN_TYPE_SHIFT 16
54 #define EXT_VLAN_TYPE_DFLT 0x81000000
55 #define US_CYC_CNT_MASK 0x0000ff00
56 #define US_CYC_CNT_SHIFT 8
57 #define US_CYC_CNT_DFLT (132<<8) /* sys clocks per 1uS */
58 #define L2_SPACE (8<<4) /* L2 space. Unit is 8 bytes */
60 #define FE_RST_GLO 0x0C /*Frame Engine Global Reset*/
61 #define FC_DROP_CNT_MASK 0xffff0000 /*Flow cntrl drop count */
62 #define FC_DROP_CNT_SHIFT 16
63 #define PSE_RESET (1<<0)
65 /* RT305x interrupt registers */
66 #define FE_INT_STATUS 0x10
67 #define CNT_PPE_AF (1<<31)
68 #define CNT_GDM_AF (1<<29)
69 #define PSE_P2_FC (1<<26)
70 #define GDM_CRC_DROP (1<<25)
71 #define PSE_BUF_DROP (1<<24)
72 #define GDM_OTHER_DROP (1<<23)
73 #define PSE_P1_FC (1<<22)
74 #define PSE_P0_FC (1<<21)
75 #define PSE_FQ_EMPTY (1<<20)
76 #define INT_TX_COHERENT (1<<17)
77 #define INT_RX_COHERENT (1<<16)
78 #define INT_TXQ3_DONE (1<<11)
79 #define INT_TXQ2_DONE (1<<10)
80 #define INT_TXQ1_DONE (1<<9)
81 #define INT_TXQ0_DONE (1<<8)
82 #define INT_RX_DONE (1<<2)
83 #define TX_DLY_INT (1<<1) /* TXQ[0|1]_DONE with delay */
84 #define RX_DLY_INT (1<<0) /* RX_DONE with delay */
85 #define FE_INT_ENABLE 0x14
87 /* RT5350 interrupt registers */
88 #define RT5350_FE_INT_STATUS (RT5350_PDMA_BASE + 0x220)
89 #define RT5350_INT_RX_COHERENT (1<<31)
90 #define RT5350_RX_DLY_INT (1<<30)
91 #define RT5350_INT_TX_COHERENT (1<<29)
92 #define RT5350_TX_DLY_INT (1<<28)
93 #define RT5350_INT_RXQ1_DONE (1<<17)
94 #define RT5350_INT_RXQ0_DONE (1<<16)
95 #define RT5350_INT_TXQ3_DONE (1<<3)
96 #define RT5350_INT_TXQ2_DONE (1<<2)
97 #define RT5350_INT_TXQ1_DONE (1<<1)
98 #define RT5350_INT_TXQ0_DONE (1<<0)
99 #define RT5350_FE_INT_ENABLE (RT5350_PDMA_BASE + 0x228)
101 #define MDIO_CFG2 0x18
102 #define FOE_TS_T 0x1c
103 #define PSE_FQ_PCNT_MASK 0xff000000
104 #define PSE_FQ_PCNT_SHIFT 24
105 #define FOE_TS_TIMESTAMP_MASK 0x0000ffff
106 #define FOE_TS_TIMESTAMP_SHIFT 0
108 #define GDMA1_BASE 0x0020
109 #define GDMA2_BASE 0x0060
110 #define CDMA_BASE 0x0080
112 #define GDMA_FWD_CFG 0x00 /* Only GDMA */
113 #define GDM_DROP_256B (1<<23)
114 #define GDM_ICS_EN (1<<22)
115 #define GDM_TCS_EN (1<<21)
116 #define GDM_UCS_EN (1<<20)
117 #define GDM_DISPAD (1<<18)
118 #define GDM_DISCRC (1<<17)
119 #define GDM_STRPCRC (1<<16)
120 #define GDM_UFRC_P_SHIFT 12
121 #define GDM_BFRC_P_SHIFT 8
122 #define GDM_MFRC_P_SHIFT 4
123 #define GDM_OFRC_P_SHIFT 0
124 #define GDM_XFRC_P_MASK 0x07
125 #define GDM_DST_PORT_CPU 0
126 #define GDM_DST_PORT_GDMA1 1
127 #define GDM_DST_PORT_GDMA2 2
128 #define GDM_DST_PORT_PPE 6
129 #define GDM_DST_PORT_DISCARD 7
131 #define CDMA_CSG_CFG 0x00 /* Only CDMA */
132 #define INS_VLAN_TAG (0x8100<<16)
133 #define ICS_GEN_EN (1<<2)
134 #define TCS_GEN_EN (1<<1)
135 #define UCS_GEN_EN (1<<0)
137 #define GDMA_SCH_CFG 0x04
138 #define GDM1_SCH_MOD_MASK 0x03000000
139 #define GDM1_SCH_MOD_SHIFT 24
140 #define GDM1_SCH_MOD_WRR 0
141 #define GDM1_SCH_MOD_STRICT 1
142 #define GDM1_SCH_MOD_MIXED 2
148 #define GDM1_WT_Q3_SHIFT 12
149 #define GDM1_WT_Q2_SHIFT 8
150 #define GDM1_WT_Q1_SHIFT 4
151 #define GDM1_WT_Q0_SHIFT 0
153 #define GDMA_SHPR_CFG 0x08
154 #define GDM1_SHPR_EN (1<<24)
155 #define GDM1_BK_SIZE_MASK 0x00ff0000 /* Bucket size 1kB units */
156 #define GDM1_BK_SIZE_SHIFT 16
157 #define GDM1_TK_RATE_MASK 0x00003fff /* Shaper token rate 8B/ms units */
158 #define GDM1_TK_RATE_SHIFT 0
160 #define GDMA_MAC_ADRL 0x0C
161 #define GDMA_MAC_ADRH 0x10
163 #define PPPOE_SID_0001 0x08 /* 0..15 SID0, 15..31 SID1 */
164 #define PPPOE_SID_0203 0x0c
165 #define PPPOE_SID_0405 0x10
166 #define PPPOE_SID_0607 0x14
167 #define PPPOE_SID_0809 0x18
168 #define PPPOE_SID_1011 0x1c
169 #define PPPOE_SID_1213 0x20
170 #define PPPOE_SID_1415 0x24
171 #define VLAN_ID_0001 0x28 /* 0..11 VID0, 15..26 VID1 */
172 #define VLAN_ID_0203 0x2c
173 #define VLAN_ID_0405 0x30
174 #define VLAN_ID_0607 0x34
175 #define VLAN_ID_0809 0x38
176 #define VLAN_ID_1011 0x3c
177 #define VLAN_ID_1213 0x40
178 #define VLAN_ID_1415 0x44
180 #define PSE_BASE 0x0040
181 #define PSE_FQFC_CFG 0x00
182 #define FQ_MAX_PCNT_MASK 0xff000000
183 #define FQ_MAX_PCNT_SHIFT 24
184 #define FQ_FC_RLS_MASK 0x00ff0000
185 #define FQ_FC_RLS_SHIFT 16
186 #define FQ_FC_ASRT_MASK 0x0000ff00
187 #define FQ_FC_ASRT_SHIFT 8
188 #define FQ_FC_DROP_MASK 0x000000ff
189 #define FQ_FC_DROP_SHIFT 0
191 #define CDMA_FC_CFG 0x04
192 #define GDMA1_FC_CFG 0x08
193 #define GDMA2_FC_CFG 0x0C
194 #define P_SHARING (1<<28)
195 #define P_HQ_DEF_MASK 0x0f000000
196 #define P_HQ_DEF_SHIFT 24
197 #define P_HQ_RESV_MASK 0x00ff0000
198 #define P_HQ_RESV_SHIFT 16
199 #define P_LQ_RESV_MASK 0x0000ff00
200 #define P_LQ_RESV_SHIFT 8
201 #define P_IQ_ASRT_MASK 0x000000ff
202 #define P_IQ_ASRT_SHIFT 0
204 #define CDMA_OQ_STA 0x10
205 #define GDMA1_OQ_STA 0x14
206 #define GDMA2_OQ_STA 0x18
207 #define P_OQ3_PCNT_MASK 0xff000000
208 #define P_OQ3_PCNT_SHIFT 24
209 #define P_OQ2_PCNT_MASK 0x00ff0000
210 #define P_OQ2_PCNT_SHIFT 16
211 #define P_OQ1_PCNT_MASK 0x0000ff00
212 #define P_OQ1_PCNT_SHIFT 8
213 #define P_OQ0_PCNT_MASK 0x000000ff
214 #define P_OQ0_PCNT_SHIFT 0
216 #define PSE_IQ_STA 0x1C
217 #define P6_OQ0_PCNT_MASK 0xff000000
218 #define P6_OQ0_PCNT_SHIFT 24
219 #define P2_IQ_PCNT_MASK 0x00ff0000
220 #define P2_IQ_PCNT_SHIFT 16
221 #define P1_IQ_PCNT_MASK 0x0000ff00
222 #define P1_IQ_PCNT_SHIFT 8
223 #define P0_IQ_PCNT_MASK 0x000000ff
224 #define P0_IQ_PCNT_SHIFT 0
226 #define PDMA_BASE 0x0100
227 #define RT5350_PDMA_BASE 0x0800
228 #define PDMA_GLO_CFG 0x00
229 #define RT5350_PDMA_GLO_CFG 0x204
230 #define FE_TX_WB_DDONE (1<<6)
231 #define FE_DMA_BT_SIZE4 (0<<4)
232 #define FE_DMA_BT_SIZE8 (1<<4)
233 #define FE_DMA_BT_SIZE16 (2<<4)
234 #define FE_RX_DMA_BUSY (1<<3)
235 #define FE_RX_DMA_EN (1<<2)
236 #define FE_TX_DMA_BUSY (1<<1)
237 #define FE_TX_DMA_EN (1<<0)
238 #define PDMA_RST_IDX 0x04
239 #define RT5350_PDMA_RST_IDX 0x208
240 #define FE_RST_DRX_IDX0 (1<<16)
241 #define FE_RST_DTX_IDX3 (1<<3)
242 #define FE_RST_DTX_IDX2 (1<<2)
243 #define FE_RST_DTX_IDX1 (1<<1)
244 #define FE_RST_DTX_IDX0 (1<<0)
246 #define PDMA_SCH_CFG 0x08
247 #define RT5350_PDMA_SCH_CFG 0x280
248 #define DELAY_INT_CFG 0x0C
249 #define RT5350_DELAY_INT_CFG 0x20C
250 #define TXDLY_INT_EN (1<<31)
251 #define TXMAX_PINT_SHIFT 24
252 #define TXMAX_PTIME_SHIFT 16
253 #define RXDLY_INT_EN (1<<15)
254 #define RXMAX_PINT_SHIFT 8
255 #define RXMAX_PTIME_SHIFT 0
257 #define TX_BASE_PTR0 0x10
258 #define TX_MAX_CNT0 0x14
259 #define TX_CTX_IDX0 0x18
260 #define TX_DTX_IDX0 0x1C
262 #define TX_BASE_PTR1 0x20
263 #define TX_MAX_CNT1 0x24
264 #define TX_CTX_IDX1 0x28
265 #define TX_DTX_IDX1 0x2C
267 #define RX_BASE_PTR0 0x30
268 #define RX_MAX_CNT0 0x34
269 #define RX_CALC_IDX0 0x38
270 #define RX_DRX_IDX0 0x3C
272 #define TX_BASE_PTR2 0x40
273 #define TX_MAX_CNT2 0x44
274 #define TX_CTX_IDX2 0x48
275 #define TX_DTX_IDX2 0x4C
277 #define TX_BASE_PTR3 0x50
278 #define TX_MAX_CNT3 0x54
279 #define TX_CTX_IDX3 0x58
280 #define TX_DTX_IDX3 0x5C
282 #define TX_BASE_PTR(qid) (((qid>1)?(0x20):(0x10)) + (qid) * 16)
283 #define TX_MAX_CNT(qid) (((qid>1)?(0x24):(0x14)) + (qid) * 16)
284 #define TX_CTX_IDX(qid) (((qid>1)?(0x28):(0x18)) + (qid) * 16)
285 #define TX_DTX_IDX(qid) (((qid>1)?(0x2c):(0x1c)) + (qid) * 16)
287 #define RT5350_TX_BASE_PTR0 0x000
288 #define RT5350_TX_MAX_CNT0 0x004
289 #define RT5350_TX_CTX_IDX0 0x008
290 #define RT5350_TX_DTX_IDX0 0x00C
292 #define RT5350_TX_BASE_PTR1 0x010
293 #define RT5350_TX_MAX_CNT1 0x014
294 #define RT5350_TX_CTX_IDX1 0x018
295 #define RT5350_TX_DTX_IDX1 0x01C
297 #define RT5350_TX_BASE_PTR2 0x020
298 #define RT5350_TX_MAX_CNT2 0x024
299 #define RT5350_TX_CTX_IDX2 0x028
300 #define RT5350_TX_DTX_IDX2 0x02C
302 #define RT5350_TX_BASE_PTR3 0x030
303 #define RT5350_TX_MAX_CNT3 0x034
304 #define RT5350_TX_CTX_IDX3 0x038
305 #define RT5350_TX_DTX_IDX3 0x03C
307 #define RT5350_RX_BASE_PTR0 0x100
308 #define RT5350_RX_MAX_CNT0 0x104
309 #define RT5350_RX_CALC_IDX0 0x108
310 #define RT5350_RX_DRX_IDX0 0x10C
312 #define RT5350_RX_BASE_PTR1 0x110
313 #define RT5350_RX_MAX_CNT1 0x114
314 #define RT5350_RX_CALC_IDX1 0x118
315 #define RT5350_RX_DRX_IDX1 0x11C
317 #define RT5350_TX_BASE_PTR(qid) ((qid) * 0x10 + 0x000)
318 #define RT5350_TX_MAX_CNT(qid) ((qid) * 0x10 + 0x004)
319 #define RT5350_TX_CTX_IDX(qid) ((qid) * 0x10 + 0x008)
320 #define RT5350_TX_DTX_IDX(qid) ((qid) * 0x10 + 0x00C)
322 #define PPE_BASE 0x0200
324 #define CNTR_BASE 0x0400
325 #define PPE_AC_BCNT0 0x000
326 #define PPE_AC_PCNT0 0x004
327 #define PPE_AC_BCNT63 0x1F8
328 #define PPE_AC_PCNT63 0x1FC
329 #define PPE_MTR_CNT0 0x200
330 #define PPE_MTR_CNT63 0x2FC
331 #define GDMA_TX_GBCNT0 0x300
332 #define GDMA_TX_GPCNT0 0x304
333 #define GDMA_TX_SKIPCNT0 0x308
334 #define GDMA_TX_COLCNT0 0x30C
335 #define GDMA_RX_GBCNT0 0x320
336 #define GDMA_RX_GPCNT0 0x324
337 #define GDMA_RX_OERCNT0 0x328
338 #define GDMA_RX_FERCNT0 0x32C
339 #define GDMA_RX_SHORT_ERCNT0 0x330
340 #define GDMA_RX_LONG_ERCNT0 0x334
341 #define GDMA_RX_CSUM_ERCNT0 0x338
343 #define POLICYTABLE_BASE 0x1000
345 #endif /* _IF_RTREG_H_ */