2 * Copyright (c) 2009, Aleksandr Rybalko
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #define RT_READ(sc, reg) \
34 bus_space_read_4((sc)->bst, (sc)->bsh, reg)
36 #define RT_WRITE(sc, reg, val) \
37 bus_space_write_4((sc)->bst, (sc)->bsh, reg, val)
39 #define GE_PORT_BASE 0x0000
41 #define MDIO_ACCESS 0x00
42 #define MDIO_CMD_ONGO (1<<31)
43 #define MDIO_CMD_WR (1<<30)
44 #define MDIO_PHY_ADDR_MASK 0x1f000000
45 #define MDIO_PHY_ADDR_SHIFT 24
46 #define MDIO_PHYREG_ADDR_MASK 0x001f0000
47 #define MDIO_PHYREG_ADDR_SHIFT 16
48 #define MDIO_PHY_DATA_MASK 0x0000ffff
49 #define MDIO_PHY_DATA_SHIFT 0
52 #define MDIO_2880_100T_INIT 0x1001BC01
53 #define MDIO_2880_GIGA_INIT 0x1F01DC01
55 #define FE_GLO_CFG 0x08 /*Frame Engine Global Configuration */
56 #define EXT_VLAN_TYPE_MASK 0xffff0000
57 #define EXT_VLAN_TYPE_SHIFT 16
58 #define EXT_VLAN_TYPE_DFLT 0x81000000
59 #define US_CYC_CNT_MASK 0x0000ff00
60 #define US_CYC_CNT_SHIFT 8
61 #define US_CYC_CNT_DFLT (132<<8) /* sys clocks per 1uS */
62 #define L2_SPACE (8<<4) /* L2 space. Unit is 8 bytes */
64 #define FE_RST_GLO 0x0C /*Frame Engine Global Reset*/
65 #define FC_DROP_CNT_MASK 0xffff0000 /*Flow cntrl drop count */
66 #define FC_DROP_CNT_SHIFT 16
67 #define PSE_RESET (1<<0)
69 /* RT305x interrupt registers */
70 #define FE_INT_STATUS 0x10
71 #define CNT_PPE_AF (1<<31)
72 #define CNT_GDM_AF (1<<29)
73 #define PSE_P2_FC (1<<26)
74 #define GDM_CRC_DROP (1<<25)
75 #define PSE_BUF_DROP (1<<24)
76 #define GDM_OTHER_DROP (1<<23)
77 #define PSE_P1_FC (1<<22)
78 #define PSE_P0_FC (1<<21)
79 #define PSE_FQ_EMPTY (1<<20)
80 #define INT_TX_COHERENT (1<<17)
81 #define INT_RX_COHERENT (1<<16)
82 #define INT_TXQ3_DONE (1<<11)
83 #define INT_TXQ2_DONE (1<<10)
84 #define INT_TXQ1_DONE (1<<9)
85 #define INT_TXQ0_DONE (1<<8)
86 #define INT_RX_DONE (1<<2)
87 #define TX_DLY_INT (1<<1) /* TXQ[0|1]_DONE with delay */
88 #define RX_DLY_INT (1<<0) /* RX_DONE with delay */
89 #define FE_INT_ENABLE 0x14
91 /* RT5350 interrupt registers */
92 #define RT5350_FE_INT_STATUS (RT5350_PDMA_BASE + 0x220)
93 #define RT5350_INT_RX_COHERENT (1<<31)
94 #define RT5350_RX_DLY_INT (1<<30)
95 #define RT5350_INT_TX_COHERENT (1<<29)
96 #define RT5350_TX_DLY_INT (1<<28)
97 #define RT5350_INT_RXQ1_DONE (1<<17)
98 #define RT5350_INT_RXQ0_DONE (1<<16)
99 #define RT5350_INT_TXQ3_DONE (1<<3)
100 #define RT5350_INT_TXQ2_DONE (1<<2)
101 #define RT5350_INT_TXQ1_DONE (1<<1)
102 #define RT5350_INT_TXQ0_DONE (1<<0)
103 #define RT5350_FE_INT_ENABLE (RT5350_PDMA_BASE + 0x228)
105 #define MDIO_CFG2 0x18
106 #define FOE_TS_T 0x1c
107 #define PSE_FQ_PCNT_MASK 0xff000000
108 #define PSE_FQ_PCNT_SHIFT 24
109 #define FOE_TS_TIMESTAMP_MASK 0x0000ffff
110 #define FOE_TS_TIMESTAMP_SHIFT 0
112 #define GDMA1_BASE 0x0020
113 #define GDMA2_BASE 0x0060
114 #define CDMA_BASE 0x0080
115 #define MT7620_GDMA1_BASE 0x600
117 #define GDMA_FWD_CFG 0x00 /* Only GDMA */
118 #define GDM_DROP_256B (1<<23)
119 #define GDM_ICS_EN (1<<22)
120 #define GDM_TCS_EN (1<<21)
121 #define GDM_UCS_EN (1<<20)
122 #define GDM_DISPAD (1<<18)
123 #define GDM_DISCRC (1<<17)
124 #define GDM_STRPCRC (1<<16)
125 #define GDM_UFRC_P_SHIFT 12
126 #define GDM_BFRC_P_SHIFT 8
127 #define GDM_MFRC_P_SHIFT 4
128 #define GDM_OFRC_P_SHIFT 0
129 #define GDM_XFRC_P_MASK 0x07
130 #define GDM_DST_PORT_CPU 0
131 #define GDM_DST_PORT_GDMA1 1
132 #define GDM_DST_PORT_GDMA2 2
133 #define GDM_DST_PORT_PPE 6
134 #define GDM_DST_PORT_DISCARD 7
136 #define CDMA_CSG_CFG 0x00 /* Only CDMA */
137 #define INS_VLAN_TAG (0x8100<<16)
138 #define ICS_GEN_EN (1<<2)
139 #define TCS_GEN_EN (1<<1)
140 #define UCS_GEN_EN (1<<0)
142 #define GDMA_SCH_CFG 0x04
143 #define GDM1_SCH_MOD_MASK 0x03000000
144 #define GDM1_SCH_MOD_SHIFT 24
145 #define GDM1_SCH_MOD_WRR 0
146 #define GDM1_SCH_MOD_STRICT 1
147 #define GDM1_SCH_MOD_MIXED 2
153 #define GDM1_WT_Q3_SHIFT 12
154 #define GDM1_WT_Q2_SHIFT 8
155 #define GDM1_WT_Q1_SHIFT 4
156 #define GDM1_WT_Q0_SHIFT 0
158 #define GDMA_SHPR_CFG 0x08
159 #define GDM1_SHPR_EN (1<<24)
160 #define GDM1_BK_SIZE_MASK 0x00ff0000 /* Bucket size 1kB units */
161 #define GDM1_BK_SIZE_SHIFT 16
162 #define GDM1_TK_RATE_MASK 0x00003fff /* Shaper token rate 8B/ms units */
163 #define GDM1_TK_RATE_SHIFT 0
165 #define GDMA_MAC_ADRL 0x0C
166 #define GDMA_MAC_ADRH 0x10
168 #define PPPOE_SID_0001 0x08 /* 0..15 SID0, 15..31 SID1 */
169 #define PPPOE_SID_0203 0x0c
170 #define PPPOE_SID_0405 0x10
171 #define PPPOE_SID_0607 0x14
172 #define PPPOE_SID_0809 0x18
173 #define PPPOE_SID_1011 0x1c
174 #define PPPOE_SID_1213 0x20
175 #define PPPOE_SID_1415 0x24
176 #define VLAN_ID_0001 0x28 /* 0..11 VID0, 15..26 VID1 */
177 #define VLAN_ID_0203 0x2c
178 #define VLAN_ID_0405 0x30
179 #define VLAN_ID_0607 0x34
180 #define VLAN_ID_0809 0x38
181 #define VLAN_ID_1011 0x3c
182 #define VLAN_ID_1213 0x40
183 #define VLAN_ID_1415 0x44
185 #define PSE_BASE 0x0040
186 #define PSE_FQFC_CFG 0x00
187 #define FQ_MAX_PCNT_MASK 0xff000000
188 #define FQ_MAX_PCNT_SHIFT 24
189 #define FQ_FC_RLS_MASK 0x00ff0000
190 #define FQ_FC_RLS_SHIFT 16
191 #define FQ_FC_ASRT_MASK 0x0000ff00
192 #define FQ_FC_ASRT_SHIFT 8
193 #define FQ_FC_DROP_MASK 0x000000ff
194 #define FQ_FC_DROP_SHIFT 0
196 #define CDMA_FC_CFG 0x04
197 #define GDMA1_FC_CFG 0x08
198 #define GDMA2_FC_CFG 0x0C
199 #define P_SHARING (1<<28)
200 #define P_HQ_DEF_MASK 0x0f000000
201 #define P_HQ_DEF_SHIFT 24
202 #define P_HQ_RESV_MASK 0x00ff0000
203 #define P_HQ_RESV_SHIFT 16
204 #define P_LQ_RESV_MASK 0x0000ff00
205 #define P_LQ_RESV_SHIFT 8
206 #define P_IQ_ASRT_MASK 0x000000ff
207 #define P_IQ_ASRT_SHIFT 0
209 #define CDMA_OQ_STA 0x10
210 #define GDMA1_OQ_STA 0x14
211 #define GDMA2_OQ_STA 0x18
212 #define P_OQ3_PCNT_MASK 0xff000000
213 #define P_OQ3_PCNT_SHIFT 24
214 #define P_OQ2_PCNT_MASK 0x00ff0000
215 #define P_OQ2_PCNT_SHIFT 16
216 #define P_OQ1_PCNT_MASK 0x0000ff00
217 #define P_OQ1_PCNT_SHIFT 8
218 #define P_OQ0_PCNT_MASK 0x000000ff
219 #define P_OQ0_PCNT_SHIFT 0
221 #define PSE_IQ_STA 0x1C
222 #define P6_OQ0_PCNT_MASK 0xff000000
223 #define P6_OQ0_PCNT_SHIFT 24
224 #define P2_IQ_PCNT_MASK 0x00ff0000
225 #define P2_IQ_PCNT_SHIFT 16
226 #define P1_IQ_PCNT_MASK 0x0000ff00
227 #define P1_IQ_PCNT_SHIFT 8
228 #define P0_IQ_PCNT_MASK 0x000000ff
229 #define P0_IQ_PCNT_SHIFT 0
231 #define PDMA_BASE 0x0100
232 #define RT5350_PDMA_BASE 0x0800
233 #define PDMA_GLO_CFG 0x00
234 #define RT5350_PDMA_GLO_CFG 0x204
235 #define FE_TX_WB_DDONE (1<<6)
236 #define FE_DMA_BT_SIZE4 (0<<4)
237 #define FE_DMA_BT_SIZE8 (1<<4)
238 #define FE_DMA_BT_SIZE16 (2<<4)
239 #define FE_RX_DMA_BUSY (1<<3)
240 #define FE_RX_DMA_EN (1<<2)
241 #define FE_TX_DMA_BUSY (1<<1)
242 #define FE_TX_DMA_EN (1<<0)
243 #define PDMA_RST_IDX 0x04
244 #define RT5350_PDMA_RST_IDX 0x208
245 #define FE_RST_DRX_IDX0 (1<<16)
246 #define FE_RST_DTX_IDX3 (1<<3)
247 #define FE_RST_DTX_IDX2 (1<<2)
248 #define FE_RST_DTX_IDX1 (1<<1)
249 #define FE_RST_DTX_IDX0 (1<<0)
251 #define PDMA_SCH_CFG 0x08
252 #define RT5350_PDMA_SCH_CFG 0x280
253 #define DELAY_INT_CFG 0x0C
254 #define RT5350_DELAY_INT_CFG 0x20C
255 #define TXDLY_INT_EN (1<<31)
256 #define TXMAX_PINT_SHIFT 24
257 #define TXMAX_PTIME_SHIFT 16
258 #define RXDLY_INT_EN (1<<15)
259 #define RXMAX_PINT_SHIFT 8
260 #define RXMAX_PTIME_SHIFT 0
262 #define TX_BASE_PTR0 0x10
263 #define TX_MAX_CNT0 0x14
264 #define TX_CTX_IDX0 0x18
265 #define TX_DTX_IDX0 0x1C
267 #define TX_BASE_PTR1 0x20
268 #define TX_MAX_CNT1 0x24
269 #define TX_CTX_IDX1 0x28
270 #define TX_DTX_IDX1 0x2C
272 #define RX_BASE_PTR0 0x30
273 #define RX_MAX_CNT0 0x34
274 #define RX_CALC_IDX0 0x38
275 #define RX_DRX_IDX0 0x3C
277 #define TX_BASE_PTR2 0x40
278 #define TX_MAX_CNT2 0x44
279 #define TX_CTX_IDX2 0x48
280 #define TX_DTX_IDX2 0x4C
282 #define TX_BASE_PTR3 0x50
283 #define TX_MAX_CNT3 0x54
284 #define TX_CTX_IDX3 0x58
285 #define TX_DTX_IDX3 0x5C
287 #define TX_BASE_PTR(qid) (((qid>1)?(0x20):(0x10)) + (qid) * 16)
288 #define TX_MAX_CNT(qid) (((qid>1)?(0x24):(0x14)) + (qid) * 16)
289 #define TX_CTX_IDX(qid) (((qid>1)?(0x28):(0x18)) + (qid) * 16)
290 #define TX_DTX_IDX(qid) (((qid>1)?(0x2c):(0x1c)) + (qid) * 16)
292 #define RT5350_TX_BASE_PTR0 0x000
293 #define RT5350_TX_MAX_CNT0 0x004
294 #define RT5350_TX_CTX_IDX0 0x008
295 #define RT5350_TX_DTX_IDX0 0x00C
297 #define RT5350_TX_BASE_PTR1 0x010
298 #define RT5350_TX_MAX_CNT1 0x014
299 #define RT5350_TX_CTX_IDX1 0x018
300 #define RT5350_TX_DTX_IDX1 0x01C
302 #define RT5350_TX_BASE_PTR2 0x020
303 #define RT5350_TX_MAX_CNT2 0x024
304 #define RT5350_TX_CTX_IDX2 0x028
305 #define RT5350_TX_DTX_IDX2 0x02C
307 #define RT5350_TX_BASE_PTR3 0x030
308 #define RT5350_TX_MAX_CNT3 0x034
309 #define RT5350_TX_CTX_IDX3 0x038
310 #define RT5350_TX_DTX_IDX3 0x03C
312 #define RT5350_RX_BASE_PTR0 0x100
313 #define RT5350_RX_MAX_CNT0 0x104
314 #define RT5350_RX_CALC_IDX0 0x108
315 #define RT5350_RX_DRX_IDX0 0x10C
317 #define RT5350_RX_BASE_PTR1 0x110
318 #define RT5350_RX_MAX_CNT1 0x114
319 #define RT5350_RX_CALC_IDX1 0x118
320 #define RT5350_RX_DRX_IDX1 0x11C
322 #define RT5350_TX_BASE_PTR(qid) ((qid) * 0x10 + 0x000)
323 #define RT5350_TX_MAX_CNT(qid) ((qid) * 0x10 + 0x004)
324 #define RT5350_TX_CTX_IDX(qid) ((qid) * 0x10 + 0x008)
325 #define RT5350_TX_DTX_IDX(qid) ((qid) * 0x10 + 0x00C)
327 #define PPE_BASE 0x0200
329 #define CNTR_BASE 0x0400
330 #define PPE_AC_BCNT0 0x000
331 #define PPE_AC_PCNT0 0x004
332 #define PPE_AC_BCNT63 0x1F8
333 #define PPE_AC_PCNT63 0x1FC
334 #define PPE_MTR_CNT0 0x200
335 #define PPE_MTR_CNT63 0x2FC
336 #define GDMA_TX_GBCNT0 0x300
337 #define GDMA_TX_GPCNT0 0x304
338 #define GDMA_TX_SKIPCNT0 0x308
339 #define GDMA_TX_COLCNT0 0x30C
340 #define GDMA_RX_GBCNT0 0x320
341 #define GDMA_RX_GPCNT0 0x324
342 #define GDMA_RX_OERCNT0 0x328
343 #define GDMA_RX_FERCNT0 0x32C
344 #define GDMA_RX_SHORT_ERCNT0 0x330
345 #define GDMA_RX_LONG_ERCNT0 0x334
346 #define GDMA_RX_CSUM_ERCNT0 0x338
348 #define POLICYTABLE_BASE 0x1000
350 #endif /* _IF_RTREG_H_ */