2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2009, Aleksandr Rybalko
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #define RT_READ(sc, reg) \
36 bus_space_read_4((sc)->bst, (sc)->bsh, reg)
38 #define RT_WRITE(sc, reg, val) \
39 bus_space_write_4((sc)->bst, (sc)->bsh, reg, val)
41 #define GE_PORT_BASE 0x0000
43 #define MDIO_ACCESS 0x00
44 #define MDIO_CMD_ONGO (1<<31)
45 #define MDIO_CMD_WR (1<<30)
46 #define MDIO_PHY_ADDR_MASK 0x1f000000
47 #define MDIO_PHY_ADDR_SHIFT 24
48 #define MDIO_PHYREG_ADDR_MASK 0x001f0000
49 #define MDIO_PHYREG_ADDR_SHIFT 16
50 #define MDIO_PHY_DATA_MASK 0x0000ffff
51 #define MDIO_PHY_DATA_SHIFT 0
54 #define MDIO_2880_100T_INIT 0x1001BC01
55 #define MDIO_2880_GIGA_INIT 0x1F01DC01
57 #define FE_GLO_CFG 0x08 /*Frame Engine Global Configuration */
58 #define EXT_VLAN_TYPE_MASK 0xffff0000
59 #define EXT_VLAN_TYPE_SHIFT 16
60 #define EXT_VLAN_TYPE_DFLT 0x81000000
61 #define US_CYC_CNT_MASK 0x0000ff00
62 #define US_CYC_CNT_SHIFT 8
63 #define US_CYC_CNT_DFLT (132<<8) /* sys clocks per 1uS */
64 #define L2_SPACE (8<<4) /* L2 space. Unit is 8 bytes */
66 #define FE_RST_GLO 0x0C /*Frame Engine Global Reset*/
67 #define FC_DROP_CNT_MASK 0xffff0000 /*Flow cntrl drop count */
68 #define FC_DROP_CNT_SHIFT 16
69 #define PSE_RESET (1<<0)
71 /* RT305x interrupt registers */
72 #define FE_INT_STATUS 0x10
73 #define CNT_PPE_AF (1<<31)
74 #define CNT_GDM_AF (1<<29)
75 #define PSE_P2_FC (1<<26)
76 #define GDM_CRC_DROP (1<<25)
77 #define PSE_BUF_DROP (1<<24)
78 #define GDM_OTHER_DROP (1<<23)
79 #define PSE_P1_FC (1<<22)
80 #define PSE_P0_FC (1<<21)
81 #define PSE_FQ_EMPTY (1<<20)
82 #define INT_TX_COHERENT (1<<17)
83 #define INT_RX_COHERENT (1<<16)
84 #define INT_TXQ3_DONE (1<<11)
85 #define INT_TXQ2_DONE (1<<10)
86 #define INT_TXQ1_DONE (1<<9)
87 #define INT_TXQ0_DONE (1<<8)
88 #define INT_RX_DONE (1<<2)
89 #define TX_DLY_INT (1<<1) /* TXQ[0|1]_DONE with delay */
90 #define RX_DLY_INT (1<<0) /* RX_DONE with delay */
91 #define FE_INT_ENABLE 0x14
93 /* RT5350 interrupt registers */
94 #define RT5350_FE_INT_STATUS (RT5350_PDMA_BASE + 0x220)
95 #define RT5350_INT_RX_COHERENT (1<<31)
96 #define RT5350_RX_DLY_INT (1<<30)
97 #define RT5350_INT_TX_COHERENT (1<<29)
98 #define RT5350_TX_DLY_INT (1<<28)
99 #define RT5350_INT_RXQ1_DONE (1<<17)
100 #define RT5350_INT_RXQ0_DONE (1<<16)
101 #define RT5350_INT_TXQ3_DONE (1<<3)
102 #define RT5350_INT_TXQ2_DONE (1<<2)
103 #define RT5350_INT_TXQ1_DONE (1<<1)
104 #define RT5350_INT_TXQ0_DONE (1<<0)
105 #define RT5350_FE_INT_ENABLE (RT5350_PDMA_BASE + 0x228)
107 #define MDIO_CFG2 0x18
108 #define FOE_TS_T 0x1c
109 #define PSE_FQ_PCNT_MASK 0xff000000
110 #define PSE_FQ_PCNT_SHIFT 24
111 #define FOE_TS_TIMESTAMP_MASK 0x0000ffff
112 #define FOE_TS_TIMESTAMP_SHIFT 0
114 #define GDMA1_BASE 0x0020
115 #define GDMA2_BASE 0x0060
116 #define CDMA_BASE 0x0080
117 #define MT7620_GDMA1_BASE 0x600
119 #define GDMA_FWD_CFG 0x00 /* Only GDMA */
120 #define GDM_DROP_256B (1<<23)
121 #define GDM_ICS_EN (1<<22)
122 #define GDM_TCS_EN (1<<21)
123 #define GDM_UCS_EN (1<<20)
124 #define GDM_DISPAD (1<<18)
125 #define GDM_DISCRC (1<<17)
126 #define GDM_STRPCRC (1<<16)
127 #define GDM_UFRC_P_SHIFT 12
128 #define GDM_BFRC_P_SHIFT 8
129 #define GDM_MFRC_P_SHIFT 4
130 #define GDM_OFRC_P_SHIFT 0
131 #define GDM_XFRC_P_MASK 0x07
132 #define GDM_DST_PORT_CPU 0
133 #define GDM_DST_PORT_GDMA1 1
134 #define GDM_DST_PORT_GDMA2 2
135 #define GDM_DST_PORT_PPE 6
136 #define GDM_DST_PORT_DISCARD 7
138 #define CDMA_CSG_CFG 0x00 /* Only CDMA */
139 #define INS_VLAN_TAG (0x8100<<16)
140 #define ICS_GEN_EN (1<<2)
141 #define TCS_GEN_EN (1<<1)
142 #define UCS_GEN_EN (1<<0)
144 #define GDMA_SCH_CFG 0x04
145 #define GDM1_SCH_MOD_MASK 0x03000000
146 #define GDM1_SCH_MOD_SHIFT 24
147 #define GDM1_SCH_MOD_WRR 0
148 #define GDM1_SCH_MOD_STRICT 1
149 #define GDM1_SCH_MOD_MIXED 2
155 #define GDM1_WT_Q3_SHIFT 12
156 #define GDM1_WT_Q2_SHIFT 8
157 #define GDM1_WT_Q1_SHIFT 4
158 #define GDM1_WT_Q0_SHIFT 0
160 #define GDMA_SHPR_CFG 0x08
161 #define GDM1_SHPR_EN (1<<24)
162 #define GDM1_BK_SIZE_MASK 0x00ff0000 /* Bucket size 1kB units */
163 #define GDM1_BK_SIZE_SHIFT 16
164 #define GDM1_TK_RATE_MASK 0x00003fff /* Shaper token rate 8B/ms units */
165 #define GDM1_TK_RATE_SHIFT 0
167 #define GDMA_MAC_ADRL 0x0C
168 #define GDMA_MAC_ADRH 0x10
170 #define PPPOE_SID_0001 0x08 /* 0..15 SID0, 15..31 SID1 */
171 #define PPPOE_SID_0203 0x0c
172 #define PPPOE_SID_0405 0x10
173 #define PPPOE_SID_0607 0x14
174 #define PPPOE_SID_0809 0x18
175 #define PPPOE_SID_1011 0x1c
176 #define PPPOE_SID_1213 0x20
177 #define PPPOE_SID_1415 0x24
178 #define VLAN_ID_0001 0x28 /* 0..11 VID0, 15..26 VID1 */
179 #define VLAN_ID_0203 0x2c
180 #define VLAN_ID_0405 0x30
181 #define VLAN_ID_0607 0x34
182 #define VLAN_ID_0809 0x38
183 #define VLAN_ID_1011 0x3c
184 #define VLAN_ID_1213 0x40
185 #define VLAN_ID_1415 0x44
187 #define PSE_BASE 0x0040
188 #define PSE_FQFC_CFG 0x00
189 #define FQ_MAX_PCNT_MASK 0xff000000
190 #define FQ_MAX_PCNT_SHIFT 24
191 #define FQ_FC_RLS_MASK 0x00ff0000
192 #define FQ_FC_RLS_SHIFT 16
193 #define FQ_FC_ASRT_MASK 0x0000ff00
194 #define FQ_FC_ASRT_SHIFT 8
195 #define FQ_FC_DROP_MASK 0x000000ff
196 #define FQ_FC_DROP_SHIFT 0
198 #define CDMA_FC_CFG 0x04
199 #define GDMA1_FC_CFG 0x08
200 #define GDMA2_FC_CFG 0x0C
201 #define P_SHARING (1<<28)
202 #define P_HQ_DEF_MASK 0x0f000000
203 #define P_HQ_DEF_SHIFT 24
204 #define P_HQ_RESV_MASK 0x00ff0000
205 #define P_HQ_RESV_SHIFT 16
206 #define P_LQ_RESV_MASK 0x0000ff00
207 #define P_LQ_RESV_SHIFT 8
208 #define P_IQ_ASRT_MASK 0x000000ff
209 #define P_IQ_ASRT_SHIFT 0
211 #define CDMA_OQ_STA 0x10
212 #define GDMA1_OQ_STA 0x14
213 #define GDMA2_OQ_STA 0x18
214 #define P_OQ3_PCNT_MASK 0xff000000
215 #define P_OQ3_PCNT_SHIFT 24
216 #define P_OQ2_PCNT_MASK 0x00ff0000
217 #define P_OQ2_PCNT_SHIFT 16
218 #define P_OQ1_PCNT_MASK 0x0000ff00
219 #define P_OQ1_PCNT_SHIFT 8
220 #define P_OQ0_PCNT_MASK 0x000000ff
221 #define P_OQ0_PCNT_SHIFT 0
223 #define PSE_IQ_STA 0x1C
224 #define P6_OQ0_PCNT_MASK 0xff000000
225 #define P6_OQ0_PCNT_SHIFT 24
226 #define P2_IQ_PCNT_MASK 0x00ff0000
227 #define P2_IQ_PCNT_SHIFT 16
228 #define P1_IQ_PCNT_MASK 0x0000ff00
229 #define P1_IQ_PCNT_SHIFT 8
230 #define P0_IQ_PCNT_MASK 0x000000ff
231 #define P0_IQ_PCNT_SHIFT 0
233 #define PDMA_BASE 0x0100
234 #define RT5350_PDMA_BASE 0x0800
235 #define PDMA_GLO_CFG 0x00
236 #define RT5350_PDMA_GLO_CFG 0x204
237 #define FE_TX_WB_DDONE (1<<6)
238 #define FE_DMA_BT_SIZE4 (0<<4)
239 #define FE_DMA_BT_SIZE8 (1<<4)
240 #define FE_DMA_BT_SIZE16 (2<<4)
241 #define FE_RX_DMA_BUSY (1<<3)
242 #define FE_RX_DMA_EN (1<<2)
243 #define FE_TX_DMA_BUSY (1<<1)
244 #define FE_TX_DMA_EN (1<<0)
245 #define PDMA_RST_IDX 0x04
246 #define RT5350_PDMA_RST_IDX 0x208
247 #define FE_RST_DRX_IDX0 (1<<16)
248 #define FE_RST_DTX_IDX3 (1<<3)
249 #define FE_RST_DTX_IDX2 (1<<2)
250 #define FE_RST_DTX_IDX1 (1<<1)
251 #define FE_RST_DTX_IDX0 (1<<0)
253 #define PDMA_SCH_CFG 0x08
254 #define RT5350_PDMA_SCH_CFG 0x280
255 #define DELAY_INT_CFG 0x0C
256 #define RT5350_DELAY_INT_CFG 0x20C
257 #define TXDLY_INT_EN (1<<31)
258 #define TXMAX_PINT_SHIFT 24
259 #define TXMAX_PTIME_SHIFT 16
260 #define RXDLY_INT_EN (1<<15)
261 #define RXMAX_PINT_SHIFT 8
262 #define RXMAX_PTIME_SHIFT 0
264 #define TX_BASE_PTR0 0x10
265 #define TX_MAX_CNT0 0x14
266 #define TX_CTX_IDX0 0x18
267 #define TX_DTX_IDX0 0x1C
269 #define TX_BASE_PTR1 0x20
270 #define TX_MAX_CNT1 0x24
271 #define TX_CTX_IDX1 0x28
272 #define TX_DTX_IDX1 0x2C
274 #define RX_BASE_PTR0 0x30
275 #define RX_MAX_CNT0 0x34
276 #define RX_CALC_IDX0 0x38
277 #define RX_DRX_IDX0 0x3C
279 #define TX_BASE_PTR2 0x40
280 #define TX_MAX_CNT2 0x44
281 #define TX_CTX_IDX2 0x48
282 #define TX_DTX_IDX2 0x4C
284 #define TX_BASE_PTR3 0x50
285 #define TX_MAX_CNT3 0x54
286 #define TX_CTX_IDX3 0x58
287 #define TX_DTX_IDX3 0x5C
289 #define TX_BASE_PTR(qid) (((qid>1)?(0x20):(0x10)) + (qid) * 16)
290 #define TX_MAX_CNT(qid) (((qid>1)?(0x24):(0x14)) + (qid) * 16)
291 #define TX_CTX_IDX(qid) (((qid>1)?(0x28):(0x18)) + (qid) * 16)
292 #define TX_DTX_IDX(qid) (((qid>1)?(0x2c):(0x1c)) + (qid) * 16)
294 #define RT5350_TX_BASE_PTR0 0x000
295 #define RT5350_TX_MAX_CNT0 0x004
296 #define RT5350_TX_CTX_IDX0 0x008
297 #define RT5350_TX_DTX_IDX0 0x00C
299 #define RT5350_TX_BASE_PTR1 0x010
300 #define RT5350_TX_MAX_CNT1 0x014
301 #define RT5350_TX_CTX_IDX1 0x018
302 #define RT5350_TX_DTX_IDX1 0x01C
304 #define RT5350_TX_BASE_PTR2 0x020
305 #define RT5350_TX_MAX_CNT2 0x024
306 #define RT5350_TX_CTX_IDX2 0x028
307 #define RT5350_TX_DTX_IDX2 0x02C
309 #define RT5350_TX_BASE_PTR3 0x030
310 #define RT5350_TX_MAX_CNT3 0x034
311 #define RT5350_TX_CTX_IDX3 0x038
312 #define RT5350_TX_DTX_IDX3 0x03C
314 #define RT5350_RX_BASE_PTR0 0x100
315 #define RT5350_RX_MAX_CNT0 0x104
316 #define RT5350_RX_CALC_IDX0 0x108
317 #define RT5350_RX_DRX_IDX0 0x10C
319 #define RT5350_RX_BASE_PTR1 0x110
320 #define RT5350_RX_MAX_CNT1 0x114
321 #define RT5350_RX_CALC_IDX1 0x118
322 #define RT5350_RX_DRX_IDX1 0x11C
324 #define RT5350_TX_BASE_PTR(qid) ((qid) * 0x10 + 0x000)
325 #define RT5350_TX_MAX_CNT(qid) ((qid) * 0x10 + 0x004)
326 #define RT5350_TX_CTX_IDX(qid) ((qid) * 0x10 + 0x008)
327 #define RT5350_TX_DTX_IDX(qid) ((qid) * 0x10 + 0x00C)
329 #define PPE_BASE 0x0200
331 #define CNTR_BASE 0x0400
332 #define PPE_AC_BCNT0 0x000
333 #define PPE_AC_PCNT0 0x004
334 #define PPE_AC_BCNT63 0x1F8
335 #define PPE_AC_PCNT63 0x1FC
336 #define PPE_MTR_CNT0 0x200
337 #define PPE_MTR_CNT63 0x2FC
338 #define GDMA_TX_GBCNT0 0x300
339 #define GDMA_TX_GPCNT0 0x304
340 #define GDMA_TX_SKIPCNT0 0x308
341 #define GDMA_TX_COLCNT0 0x30C
342 #define GDMA_RX_GBCNT0 0x320
343 #define GDMA_RX_GPCNT0 0x324
344 #define GDMA_RX_OERCNT0 0x328
345 #define GDMA_RX_FERCNT0 0x32C
346 #define GDMA_RX_SHORT_ERCNT0 0x330
347 #define GDMA_RX_LONG_ERCNT0 0x334
348 #define GDMA_RX_CSUM_ERCNT0 0x338
350 #define POLICYTABLE_BASE 0x1000
352 #endif /* _IF_RTREG_H_ */