2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2010-2011 Aleksandr Rybalko <ray@ddteam.net>
5 * Copyright (c) 2009-2010 Alexander Egorenkov <egorenar@gmail.com>
6 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 #include <sys/param.h>
37 #include <sys/sysctl.h>
38 #include <sys/sockio.h>
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
42 #include <sys/systm.h>
43 #include <sys/malloc.h>
44 #include <sys/taskqueue.h>
45 #include <sys/module.h>
47 #include <sys/endian.h>
49 #include <machine/bus.h>
50 #include <machine/resource.h>
55 #include <net/if_arp.h>
56 #include <net/ethernet.h>
57 #include <net/if_dl.h>
58 #include <net/if_media.h>
59 #include <net/if_types.h>
61 #include "opt_if_rt.h"
63 #define RT_SOFTC_LOCK(sc) mtx_lock(&(sc)->lock)
64 #define RT_SOFTC_UNLOCK(sc) mtx_unlock(&(sc)->lock)
65 #define RT_SOFTC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->lock, MA_OWNED)
67 #define RT_SOFTC_TX_RING_LOCK(ring) mtx_lock(&(ring)->lock)
68 #define RT_SOFTC_TX_RING_UNLOCK(ring) mtx_unlock(&(ring)->lock)
69 #define RT_SOFTC_TX_RING_ASSERT_LOCKED(ring) \
70 mtx_assert(&(ring)->lock, MA_OWNED)
72 #define RT_SOFTC_TX_RING_COUNT 4
73 #define RT_SOFTC_RX_RING_COUNT 4
75 #ifndef IF_RT_RING_DATA_COUNT
76 #define IF_RT_RING_DATA_COUNT 128
79 #define RT_SOFTC_RX_RING_DATA_COUNT IF_RT_RING_DATA_COUNT
81 #define RT_SOFTC_MAX_SCATTER 10
83 #define RT_SOFTC_TX_RING_DATA_COUNT (IF_RT_RING_DATA_COUNT/4)
84 #define RT_SOFTC_TX_RING_DESC_COUNT \
85 (RT_SOFTC_TX_RING_DATA_COUNT * RT_SOFTC_MAX_SCATTER)
87 #define RT_TXDESC_SDL1_BURST (1 << 15)
88 #define RT_TXDESC_SDL1_LASTSEG (1 << 14)
89 #define RT_TXDESC_SDL0_DDONE (1 << 15)
90 #define RT_TXDESC_SDL0_LASTSEG (1 << 14)
98 #define TXDSCR_INS_VLAN_TAG 0x80
99 #define TXDSCR_VLAN_PRIO_MASK 0x70
100 #define TXDSCR_VLAN_IDX_MASK 0x0f
102 #define TXDSCR_USR_DEF_FLD 0x80
103 #define TXDSCR_INS_PPPOE_HDR 0x10
104 #define TXDSCR_PPPOE_SID_MASK 0x0f
106 #define TXDSCR_QUEUE_MASK 0x07
108 #define TXDSCR_IP_CSUM_GEN 0x80
109 #define TXDSCR_UDP_CSUM_GEN 0x40
110 #define TXDSCR_TCP_CSUM_GEN 0x20
111 #define TXDSCR_DST_PORT_MASK 0x07
112 #define TXDSCR_DST_PORT_CPU 0x00
113 #define TXDSCR_DST_PORT_GDMA1 0x01
114 #define TXDSCR_DST_PORT_GDMA2 0x02
115 #define TXDSCR_DST_PORT_PPE 0x06
116 #define TXDSCR_DST_PORT_DISC 0x07
119 #define RT_RXDESC_SDL0_DDONE (1 << 15)
121 #define RT305X_RXD_SRC_L4_CSUM_FAIL (1 << 28)
122 #define RT305X_RXD_SRC_IP_CSUM_FAIL (1 << 29)
123 #define MT7620_RXD_SRC_L4_CSUM_FAIL (1 << 22)
124 #define MT7620_RXD_SRC_IP_CSUM_FAIL (1 << 25)
125 #define MT7621_RXD_SRC_L4_CSUM_FAIL (1 << 23)
126 #define MT7621_RXD_SRC_IP_CSUM_FAIL (1 << 26)
136 #define RXDSXR_FOE_ENTRY_VALID 0x40
137 #define RXDSXR_FOE_ENTRY_MASK 0x3f
139 #define RXDSXR_AI_COU_REASON 0xff
140 #define RXDSXR_AI_PARSER_RSLT_MASK 0xff
142 #define RXDSXR_SRC_IPFVLD 0x80
143 #define RXDSXR_SRC_L4FVLD 0x40
144 #define RXDSXR_SRC_IP_CSUM_FAIL 0x20
145 #define RXDSXR_SRC_L4_CSUM_FAIL 0x10
146 #define RXDSXR_SRC_AIS 0x08
147 #define RXDSXR_SRC_PORT_MASK 0x07
152 struct rt_softc_rx_data
154 bus_dmamap_t dma_map;
158 struct rt_softc_rx_ring
160 bus_dma_tag_t desc_dma_tag;
161 bus_dmamap_t desc_dma_map;
162 bus_addr_t desc_phys_addr;
163 struct rt_rxdesc *desc;
164 bus_dma_tag_t data_dma_tag;
165 bus_dmamap_t spare_dma_map;
166 struct rt_softc_rx_data data[RT_SOFTC_RX_RING_DATA_COUNT];
171 struct rt_softc_tx_data
173 bus_dmamap_t dma_map;
177 struct rt_softc_tx_ring
180 bus_dma_tag_t desc_dma_tag;
181 bus_dmamap_t desc_dma_map;
182 bus_addr_t desc_phys_addr;
183 struct rt_txdesc *desc;
187 bus_dma_tag_t seg0_dma_tag;
188 bus_dmamap_t seg0_dma_map;
189 bus_addr_t seg0_phys_addr;
191 bus_dma_tag_t data_dma_tag;
192 struct rt_softc_tx_data data[RT_SOFTC_TX_RING_DATA_COUNT];
206 struct resource *mem;
208 struct resource *irq;
212 bus_space_handle_t bsh;
216 struct ifmedia rt_ifmedia;
219 uint8_t mac_addr[ETHER_ADDR_LEN];
222 uint32_t intr_enable_mask;
223 uint32_t intr_disable_mask;
224 uint32_t intr_pending_mask;
226 struct task rx_done_task;
227 int rx_process_limit;
228 struct task tx_done_task;
229 struct task periodic_task;
230 struct callout periodic_ch;
231 unsigned long periodic_round;
232 struct taskqueue *taskqueue;
234 struct rt_softc_rx_ring rx_ring[RT_SOFTC_RX_RING_COUNT];
235 struct rt_softc_tx_ring tx_ring[RT_SOFTC_TX_RING_COUNT];
238 struct callout tx_watchdog_ch;
241 /* statistic counters */
242 unsigned long interrupts;
243 unsigned long tx_coherent_interrupts;
244 unsigned long rx_coherent_interrupts;
245 unsigned long rx_interrupts[RT_SOFTC_RX_RING_COUNT];
246 unsigned long rx_delay_interrupts;
247 unsigned long tx_interrupts[RT_SOFTC_TX_RING_COUNT];
248 unsigned long tx_delay_interrupts;
249 unsigned long tx_data_queue_full[RT_SOFTC_TX_RING_COUNT];
250 unsigned long tx_watchdog_timeouts;
251 unsigned long tx_defrag_packets;
252 unsigned long no_tx_desc_avail;
253 unsigned long rx_mbuf_alloc_errors;
254 unsigned long rx_mbuf_dmamap_errors;
255 unsigned long tx_queue_not_empty[2];
257 unsigned long rx_bytes;
258 unsigned long rx_packets;
259 unsigned long rx_crc_err;
260 unsigned long rx_phy_err;
261 unsigned long rx_dup_packets;
262 unsigned long rx_fifo_overflows;
263 unsigned long rx_short_err;
264 unsigned long rx_long_err;
265 unsigned long tx_bytes;
266 unsigned long tx_packets;
267 unsigned long tx_skip;
268 unsigned long tx_collision;
277 /* chip specific registers config */
279 uint32_t csum_fail_l4;
280 uint32_t csum_fail_ip;
281 uint32_t int_rx_done_mask;
282 uint32_t int_tx_done_mask;
283 uint32_t delay_int_cfg;
284 uint32_t fe_int_status;
285 uint32_t fe_int_enable;
286 uint32_t pdma_glo_cfg;
287 uint32_t pdma_rst_idx;
289 uint32_t tx_base_ptr[RT_SOFTC_TX_RING_COUNT];
290 uint32_t tx_max_cnt[RT_SOFTC_TX_RING_COUNT];
291 uint32_t tx_ctx_idx[RT_SOFTC_TX_RING_COUNT];
292 uint32_t tx_dtx_idx[RT_SOFTC_TX_RING_COUNT];
293 uint32_t rx_base_ptr[RT_SOFTC_RX_RING_COUNT];
294 uint32_t rx_max_cnt[RT_SOFTC_RX_RING_COUNT];
295 uint32_t rx_calc_idx[RT_SOFTC_RX_RING_COUNT];
296 uint32_t rx_drx_idx[RT_SOFTC_RX_RING_COUNT];
302 RT_DEBUG_RX = 0x00000001,
303 RT_DEBUG_TX = 0x00000002,
304 RT_DEBUG_INTR = 0x00000004,
305 RT_DEBUG_STATE = 0x00000008,
306 RT_DEBUG_STATS = 0x00000010,
307 RT_DEBUG_PERIODIC = 0x00000020,
308 RT_DEBUG_WATCHDOG = 0x00000040,
309 RT_DEBUG_ANY = 0xffffffff
312 #define RT_DPRINTF(sc, m, fmt, ...) \
313 do { if ((sc)->debug & (m)) \
314 device_printf(sc->dev, fmt, ## __VA_ARGS__); } while (0)
316 #define RT_DPRINTF(sc, m, fmt, ...)
317 #endif /* #ifdef IF_RT_DEBUG */
319 #endif /* #ifndef _IF_RTVAR_H_ */