sys/dev/rtwn/rtl8188e/r88e_init.c

   1 /*      $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $   */
   2
   3 /*-
   4  * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
   5  * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org>
   6  * Copyright (c) 2015-2016 Andriy Voskoboinyk <avos@FreeBSD.org>
   7  *
   8  * Permission to use, copy, modify, and distribute this software for any
   9  * purpose with or without fee is hereby granted, provided that the above
  10  * copyright notice and this permission notice appear in all copies.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  13  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  14  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  15  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  16  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  17  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  18  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  19  */
  20
  21 #include <sys/cdefs.h>
  22 __FBSDID("$FreeBSD$");
  23
  24 #include "opt_wlan.h"
  25
  26 #include <sys/param.h>
  27 #include <sys/lock.h>
  28 #include <sys/mutex.h>
  29 #include <sys/mbuf.h>
  30 #include <sys/kernel.h>
  31 #include <sys/socket.h>
  32 #include <sys/systm.h>
  33 #include <sys/malloc.h>
  34 #include <sys/queue.h>
  35 #include <sys/taskqueue.h>
  36 #include <sys/bus.h>
  37 #include <sys/endian.h>
  38 #include <sys/linker.h>
  39
  40 #include <net/if.h>
  41 #include <net/ethernet.h>
  42 #include <net/if_media.h>
  43
  44 #include <net80211/ieee80211_var.h>
  45 #include <net80211/ieee80211_radiotap.h>
  46
  47 #include <dev/rtwn/if_rtwnreg.h>
  48 #include <dev/rtwn/if_rtwnvar.h>
  49
  50 #include <dev/rtwn/if_rtwn_debug.h>
  51
  52 #include <dev/rtwn/rtl8192c/r92c.h>
  53 #include <dev/rtwn/rtl8192c/r92c_var.h>
  54
  55 #include <dev/rtwn/rtl8188e/r88e.h>
  56 #include <dev/rtwn/rtl8188e/r88e_reg.h>
  57
  58
  59 static void
  60 r88e_crystalcap_write(struct rtwn_softc *sc)
  61 {
  62         struct r92c_softc *rs = sc->sc_priv;
  63         uint32_t reg;
  64         uint8_t val;
  65
  66         val = rs->crystalcap & 0x3f;
  67         reg = rtwn_bb_read(sc, R92C_AFE_XTAL_CTRL);
  68         rtwn_bb_write(sc, R92C_AFE_XTAL_CTRL,
  69             RW(reg, R92C_AFE_XTAL_CTRL_ADDR, val | val << 6));
  70 }
  71
  72 void
  73 r88e_init_bb(struct rtwn_softc *sc)
  74 {
  75
  76         /* Enable BB and RF. */
  77         rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
  78             R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
  79             R92C_SYS_FUNC_EN_DIO_RF);
  80
  81         rtwn_write_1(sc, R92C_RF_CTRL,
  82             R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
  83         rtwn_write_1(sc, R92C_SYS_FUNC_EN,
  84             R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD |
  85             R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB);
  86
  87         r92c_init_bb_common(sc);
  88
  89         rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422);
  90         rtwn_delay(sc, 1);
  91         rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420);
  92         rtwn_delay(sc, 1);
  93
  94         r88e_crystalcap_write(sc);
  95 }
  96
  97 int
  98 r88e_power_on(struct rtwn_softc *sc)
  99 {
 100 #define RTWN_CHK(res) do {      \
 101         if (res != 0)           \
 102                 return (EIO);   \
 103 } while(0)
 104         int ntries;
 105
 106         /* Wait for power ready bit. */
 107         for (ntries = 0; ntries < 5000; ntries++) {
 108                 if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
 109                         break;
 110                 rtwn_delay(sc, 10);
 111         }
 112         if (ntries == 5000) {
 113                 device_printf(sc->sc_dev,
 114                     "timeout waiting for chip power up\n");
 115                 return (ETIMEDOUT);
 116         }
 117
 118         /* Reset BB. */
 119         RTWN_CHK(rtwn_setbits_1(sc, R92C_SYS_FUNC_EN,
 120             R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST, 0));
 121
 122         RTWN_CHK(rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80));
 123
 124         /* Disable HWPDN. */
 125         RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
 126             R92C_APS_FSMCO_APDM_HPDN, 0, 1));
 127
 128         /* Disable WL suspend. */
 129         RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
 130             R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE, 0, 1));
 131
 132         RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
 133             0, R92C_APS_FSMCO_APFM_ONMAC, 1));
 134         for (ntries = 0; ntries < 5000; ntries++) {
 135                 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
 136                     R92C_APS_FSMCO_APFM_ONMAC))
 137                         break;
 138                 rtwn_delay(sc, 10);
 139         }
 140         if (ntries == 5000)
 141                 return (ETIMEDOUT);
 142
 143         /* Enable LDO normal mode. */
 144         RTWN_CHK(rtwn_setbits_1(sc, R92C_LPLDO_CTRL,
 145             R92C_LPLDO_CTRL_SLEEP, 0));
 146
 147         /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
 148         RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0));
 149         RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
 150             R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN |
 151             R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN |
 152             R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN |
 153             ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
 154             R92C_CR_CALTMR_EN));
 155
 156         return (0);
 157 #undef RTWN_CHK
 158 }