sys/dev/rtwn/rtl8192c/pci/r92ce_init.c

   1 /*      $OpenBSD: if_rtwn.c,v 1.6 2015/08/28 00:03:53 deraadt Exp $     */
   2
   3 /*-
   4  * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
   5  * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org>
   6  * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org>
   7  *
   8  * Permission to use, copy, modify, and distribute this software for any
   9  * purpose with or without fee is hereby granted, provided that the above
  10  * copyright notice and this permission notice appear in all copies.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  13  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  14  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  15  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  16  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  17  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  18  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  19  */
  20
  21 #include <sys/cdefs.h>
  22 __FBSDID("$FreeBSD$");
  23
  24 #include "opt_wlan.h"
  25
  26 #include <sys/param.h>
  27 #include <sys/lock.h>
  28 #include <sys/mutex.h>
  29 #include <sys/mbuf.h>
  30 #include <sys/kernel.h>
  31 #include <sys/socket.h>
  32 #include <sys/systm.h>
  33 #include <sys/malloc.h>
  34 #include <sys/queue.h>
  35 #include <sys/taskqueue.h>
  36 #include <sys/bus.h>
  37 #include <sys/endian.h>
  38 #include <sys/linker.h>
  39
  40 #include <machine/bus.h>
  41 #include <machine/resource.h>
  42 #include <sys/rman.h>
  43
  44 #include <net/if.h>
  45 #include <net/ethernet.h>
  46 #include <net/if_media.h>
  47
  48 #include <net80211/ieee80211_var.h>
  49 #include <net80211/ieee80211_radiotap.h>
  50
  51 #include <dev/rtwn/if_rtwnvar.h>
  52
  53 #include <dev/rtwn/pci/rtwn_pci_var.h>
  54
  55 #include <dev/rtwn/rtl8192c/r92c_var.h>
  56
  57 #include <dev/rtwn/rtl8192c/pci/r92ce.h>
  58 #include <dev/rtwn/rtl8192c/pci/r92ce_reg.h>
  59
  60
  61 void
  62 r92ce_init_intr(struct rtwn_softc *sc)
  63 {
  64         /* Disable interrupts. */
  65         rtwn_write_4(sc, R92C_HISR, 0x00000000);
  66         rtwn_write_4(sc, R92C_HIMR, 0x00000000);
  67 }
  68
  69 void
  70 r92ce_init_edca(struct rtwn_softc *sc)
  71 {
  72         /* SIFS */
  73         rtwn_write_2(sc, R92C_SPEC_SIFS, 0x1010);
  74         rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x1010);
  75         rtwn_write_2(sc, R92C_SIFS_CCK, 0x1010);
  76         rtwn_write_2(sc, R92C_SIFS_OFDM, 0x0e0e);
  77         /* TXOP */
  78         rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b);
  79         rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f);
  80         rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4322);
  81         rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3222);
  82 }
  83
  84 void
  85 r92ce_init_bb(struct rtwn_softc *sc)
  86 {
  87
  88         /* Enable BB and RF. */
  89         rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
  90             R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
  91             R92C_SYS_FUNC_EN_DIO_RF);
  92
  93         rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83);
  94
  95         rtwn_write_1(sc, R92C_RF_CTRL,
  96             R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
  97
  98         rtwn_write_1(sc, R92C_SYS_FUNC_EN,
  99             R92C_SYS_FUNC_EN_DIO_PCIE | R92C_SYS_FUNC_EN_PCIEA |
 100             R92C_SYS_FUNC_EN_PPLL | R92C_SYS_FUNC_EN_BB_GLB_RST |
 101             R92C_SYS_FUNC_EN_BBRSTB);
 102
 103         rtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80);
 104
 105         rtwn_setbits_4(sc, R92C_LEDCFG0, 0, 0x00800000);
 106
 107         r92c_init_bb_common(sc);
 108 }
 109
 110 int
 111 r92ce_power_on(struct rtwn_softc *sc)
 112 {
 113         struct r92c_softc *rs = sc->sc_priv;
 114         uint32_t reg;
 115         int ntries;
 116
 117         /* Wait for autoload done bit. */
 118         for (ntries = 0; ntries < 1000; ntries++) {
 119                 if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN)
 120                         break;
 121                 DELAY(5);
 122         }
 123         if (ntries == 1000) {
 124                 device_printf(sc->sc_dev,
 125                     "timeout waiting for chip autoload\n");
 126                 return (ETIMEDOUT);
 127         }
 128
 129         /* Unlock ISO/CLK/Power control register. */
 130         rtwn_write_1(sc, R92C_RSV_CTRL, 0);
 131
 132         if (rs->board_type != R92C_BOARD_TYPE_DONGLE) {
 133                 /* bt coex */
 134                 rtwn_setbits_4(sc, R92C_APS_FSMCO, 0,
 135                     R92C_APS_FSMCO_SOP_ABG |
 136                     R92C_APS_FSMCO_SOP_AMB |
 137                     R92C_APS_FSMCO_XOP_BTCK);
 138         }
 139
 140         /* Move SPS into PWM mode. */
 141         rtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b);
 142
 143         /* Set low byte to 0x0f, leave others unchanged. */
 144         rtwn_write_1(sc, R92C_AFE_XTAL_CTRL, 0x0f);
 145
 146         /* TODO: check if we need this for 8188CE */
 147         if (rs->board_type != R92C_BOARD_TYPE_DONGLE) {
 148                 /* bt coex */
 149                 /* XXX magic from linux */
 150                 rtwn_setbits_4(sc, R92C_AFE_XTAL_CTRL, 0x024800, 0);
 151         }
 152
 153         rtwn_setbits_2(sc, R92C_SYS_ISO_CTRL, 0xff00,
 154             R92C_SYS_ISO_CTRL_PWC_EV12V | R92C_SYS_ISO_CTRL_DIOR);
 155
 156         DELAY(200);
 157
 158         /* TODO: linux does additional btcoex stuff here */
 159
 160         /* Auto enable WLAN. */
 161         rtwn_setbits_2(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_ONMAC);
 162         for (ntries = 0; ntries < 1000; ntries++) {
 163                 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
 164                     R92C_APS_FSMCO_APFM_ONMAC))
 165                         break;
 166                 DELAY(5);
 167         }
 168         if (ntries == 1000) {
 169                 device_printf(sc->sc_dev, "timeout waiting for MAC auto ON\n");
 170                 return (ETIMEDOUT);
 171         }
 172
 173         /* Enable radio, GPIO and LED functions. */
 174         rtwn_write_2(sc, R92C_APS_FSMCO,
 175             R92C_APS_FSMCO_AFSM_PCIE |
 176             R92C_APS_FSMCO_PDN_EN |
 177             R92C_APS_FSMCO_PFM_ALDN);
 178         /* Release RF digital isolation. */
 179         rtwn_setbits_2(sc, R92C_SYS_ISO_CTRL, R92C_SYS_ISO_CTRL_DIOR, 0);
 180
 181         if (rs->chip & R92C_CHIP_92C)
 182                 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x77);
 183         else
 184                 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x22);
 185
 186         rtwn_write_4(sc, R92C_INT_MIG, 0);
 187
 188         if (rs->board_type != R92C_BOARD_TYPE_DONGLE) {
 189                 /* bt coex */
 190                 /* XXX magic from linux */
 191                 rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0x02, 0);
 192         }
 193
 194         rtwn_setbits_1(sc, R92C_GPIO_MUXCFG, R92C_GPIO_MUXCFG_RFKILL, 0);
 195
 196         reg = rtwn_read_1(sc, R92C_GPIO_IO_SEL);
 197         if (!(reg & R92C_GPIO_IO_SEL_RFKILL)) {
 198                 device_printf(sc->sc_dev,
 199                     "radio is disabled by hardware switch\n");
 200                 /* XXX how driver will know when radio will be enabled? */
 201                 return (EPERM);
 202         }
 203
 204         /* Initialize MAC. */
 205         rtwn_setbits_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF, 0);
 206         for (ntries = 0; ntries < 200; ntries++) {
 207                 if (!(rtwn_read_1(sc, R92C_APSD_CTRL) &
 208                     R92C_APSD_CTRL_OFF_STATUS))
 209                         break;
 210                 DELAY(500);
 211         }
 212         if (ntries == 200) {
 213                 device_printf(sc->sc_dev,
 214                     "timeout waiting for MAC initialization\n");
 215                 return (ETIMEDOUT);
 216         }
 217
 218         /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
 219         rtwn_setbits_2(sc, R92C_CR, 0,
 220             R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
 221             R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN |
 222             R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN |
 223             ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0));
 224
 225         rtwn_write_4(sc, R92C_MCUTST_1, 0x0);
 226
 227         return (0);
 228 }
 229
 230 void
 231 r92ce_power_off(struct rtwn_softc *sc)
 232 {
 233 #ifndef RTWN_WITHOUT_UCODE
 234         struct r92c_softc *rs = sc->sc_priv;
 235
 236         /* Deinit C2H event handler. */
 237         callout_stop(&rs->rs_c2h_report);
 238         rs->rs_c2h_paused = 0;
 239         rs->rs_c2h_pending = 0;
 240         rs->rs_c2h_timeout = hz;
 241 #endif
 242
 243         /* Stop hardware. */
 244         /* Disable interrupts. */
 245         rtwn_write_4(sc, R92C_HISR, 0);
 246         rtwn_write_4(sc, R92C_HIMR, 0);
 247
 248         /* Stop hardware. */
 249         rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
 250
 251         /* Turn off RF. */
 252         rtwn_write_1(sc, R92C_RF_CTRL, 0);
 253
 254         /* Reset BB state machine */
 255         rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, 0, R92C_SYS_FUNC_EN_BB_GLB_RST);
 256         rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
 257
 258         /* Disable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
 259         rtwn_setbits_2(sc, R92C_CR,
 260             R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
 261             R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN |
 262             R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN |
 263             R92C_CR_ENSEC,
 264             0);
 265
 266         /* If firmware in ram code, do reset. */
 267 #ifndef RTWN_WITHOUT_UCODE
 268         if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL)
 269                 r92ce_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN);
 270 #endif
 271
 272         /* TODO: linux does additional btcoex stuff here */
 273         rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0x80); /* linux magic number */
 274         rtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); /* ditto */
 275         rtwn_write_1(sc, R92C_AFE_XTAL_CTRL, 0x0e); /* different with btcoex */
 276         rtwn_write_1(sc, R92C_RSV_CTRL, 0x0e);
 277         rtwn_write_1(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_PDN_EN);
 278 }
 279
 280 void
 281 r92ce_init_ampdu(struct rtwn_softc *sc)
 282 {
 283
 284         /* Setup AMPDU aggregation. */
 285         rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631);  /* MCS7~0 */
 286         rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16);
 287 }
 288
 289 void
 290 r92ce_post_init(struct rtwn_softc *sc)
 291 {
 292         rtwn_write_2(sc, R92C_FWHW_TXQ_CTRL,
 293             0x1f00 | R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW);
 294
 295         rtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff);
 296
 297         /* Perform LO and IQ calibrations. */
 298         r92ce_iq_calib(sc);
 299         /* Perform LC calibration. */
 300         r92c_lc_calib(sc);
 301
 302         r92c_pa_bias_init(sc);
 303
 304         /* Fix for lower temperature. */
 305         rtwn_write_1(sc, 0x15, 0xe9);
 306
 307 #ifndef RTWN_WITHOUT_UCODE
 308         if (sc->sc_flags & RTWN_FW_LOADED) {
 309                 struct r92c_softc *rs = sc->sc_priv;
 310
 311                 if (sc->sc_ratectl_sysctl == RTWN_RATECTL_FW) {
 312                         /* XXX TODO: fix (see comment in r92cu_init.c) */
 313                         sc->sc_ratectl = RTWN_RATECTL_NET80211;
 314                 } else
 315                         sc->sc_ratectl = sc->sc_ratectl_sysctl;
 316
 317                 /* Start C2H event handling. */
 318                 callout_reset(&rs->rs_c2h_report, rs->rs_c2h_timeout,
 319                     r92c_handle_c2h_report, sc);
 320         } else
 321 #endif
 322                 sc->sc_ratectl = RTWN_RATECTL_NONE;
 323 }