sys/dev/rtwn/rtl8192c/r92c_calib.c

   1 /*      $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $   */
   2
   3 /*-
   4  * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
   5  * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org>
   6  * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org>
   7  *
   8  * Permission to use, copy, modify, and distribute this software for any
   9  * purpose with or without fee is hereby granted, provided that the above
  10  * copyright notice and this permission notice appear in all copies.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  13  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  14  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  15  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  16  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  17  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  18  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  19  */
  20
  21 #include <sys/cdefs.h>
  22 __FBSDID("$FreeBSD$");
  23
  24 #include "opt_wlan.h"
  25
  26 #include <sys/param.h>
  27 #include <sys/lock.h>
  28 #include <sys/mutex.h>
  29 #include <sys/mbuf.h>
  30 #include <sys/kernel.h>
  31 #include <sys/socket.h>
  32 #include <sys/systm.h>
  33 #include <sys/malloc.h>
  34 #include <sys/queue.h>
  35 #include <sys/taskqueue.h>
  36 #include <sys/bus.h>
  37 #include <sys/endian.h>
  38 #include <sys/linker.h>
  39
  40 #include <net/if.h>
  41 #include <net/ethernet.h>
  42 #include <net/if_media.h>
  43
  44 #include <net80211/ieee80211_var.h>
  45 #include <net80211/ieee80211_radiotap.h>
  46
  47 #include <dev/rtwn/if_rtwnreg.h>
  48 #include <dev/rtwn/if_rtwnvar.h>
  49 #include <dev/rtwn/if_rtwn_debug.h>
  50
  51 #include <dev/rtwn/rtl8192c/r92c.h>
  52 #include <dev/rtwn/rtl8192c/r92c_reg.h>
  53
  54
  55 /* Registers to save and restore during IQ calibration. */
  56 struct r92c_iq_cal_reg_vals {
  57         uint32_t        adda[16];
  58         uint8_t         txpause;
  59         uint8_t         bcn_ctrl[2];
  60         uint32_t        gpio_muxcfg;
  61         uint32_t        cck0_afesetting;
  62         uint32_t        ofdm0_trxpathena;
  63         uint32_t        ofdm0_trmuxpar;
  64         uint32_t        fpga0_rfifacesw0;
  65         uint32_t        fpga0_rfifacesw1;
  66         uint32_t        fpga0_rfifaceoe0;
  67         uint32_t        fpga0_rfifaceoe1;
  68         uint32_t        config_ant0;
  69         uint32_t        config_ant1;
  70 };
  71
  72 /* XXX TODO: merge */
  73 static int
  74 r92c_iq_calib_chain(struct rtwn_softc *sc, int chain, uint16_t tx[2],
  75     uint16_t rx[2])
  76 {
  77         uint32_t status;
  78
  79         if (chain == 0) {       /* IQ calibration for chain 0. */
  80                 /* IQ calibration settings for chain 0. */
  81                 rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x10008c1f);
  82                 rtwn_bb_write(sc, R92C_RX_IQK_TONE(0), 0x10008c1f);
  83                 rtwn_bb_write(sc, R92C_TX_IQK_PI(0), 0x82140102);
  84
  85                 if (sc->ntxchains > 1) {
  86                         rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160202);
  87                         /* IQ calibration settings for chain 1. */
  88                         rtwn_bb_write(sc, R92C_TX_IQK_TONE(1), 0x10008c22);
  89                         rtwn_bb_write(sc, R92C_RX_IQK_TONE(1), 0x10008c22);
  90                         rtwn_bb_write(sc, R92C_TX_IQK_PI(1), 0x82140102);
  91                         rtwn_bb_write(sc, R92C_RX_IQK_PI(1), 0x28160202);
  92                 } else
  93                         rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160502);
  94
  95                 /* LO calibration settings. */
  96                 rtwn_bb_write(sc, R92C_IQK_AGC_RSP, 0x001028d1);
  97                 /* We're doing LO and IQ calibration in one shot. */
  98                 rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf9000000);
  99                 rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf8000000);
 100
 101         } else {                /* IQ calibration for chain 1. */
 102                 /* We're doing LO and IQ calibration in one shot. */
 103                 rtwn_bb_write(sc, R92C_IQK_AGC_CONT, 2);
 104                 rtwn_bb_write(sc, R92C_IQK_AGC_CONT, 0);
 105         }
 106
 107         /* Give LO and IQ calibrations the time to complete. */
 108         rtwn_delay(sc, 10000);
 109
 110         /* Read IQ calibration status. */
 111         status = rtwn_bb_read(sc, R92C_RX_POWER_IQK_AFTER(0));
 112
 113         if (status & (1 << (28 + chain * 3)))
 114                 return (0);     /* Tx failed. */
 115         /* Read Tx IQ calibration results. */
 116         tx[0] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_BEFORE(chain)),
 117             R92C_POWER_IQK_RESULT);
 118         tx[1] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_AFTER(chain)),
 119             R92C_POWER_IQK_RESULT);
 120         if (tx[0] == 0x142 || tx[1] == 0x042)
 121                 return (0);     /* Tx failed. */
 122
 123         if (status & (1 << (27 + chain * 3)))
 124                 return (1);     /* Rx failed. */
 125         /* Read Rx IQ calibration results. */
 126         rx[0] = MS(rtwn_bb_read(sc, R92C_RX_POWER_IQK_BEFORE(chain)),
 127             R92C_POWER_IQK_RESULT);
 128         rx[1] = MS(rtwn_bb_read(sc, R92C_RX_POWER_IQK_AFTER(chain)),
 129             R92C_POWER_IQK_RESULT);
 130         if (rx[0] == 0x132 || rx[1] == 0x036)
 131                 return (1);     /* Rx failed. */
 132
 133         return (3);     /* Both Tx and Rx succeeded. */
 134 }
 135
 136 static void
 137 r92c_iq_calib_run(struct rtwn_softc *sc, int n, uint16_t tx[2][2],
 138     uint16_t rx[2][2], struct r92c_iq_cal_reg_vals *vals)
 139 {
 140         /* Registers to save and restore during IQ calibration. */
 141         static const uint16_t reg_adda[16] = {
 142                 0x85c, 0xe6c, 0xe70, 0xe74,
 143                 0xe78, 0xe7c, 0xe80, 0xe84,
 144                 0xe88, 0xe8c, 0xed0, 0xed4,
 145                 0xed8, 0xedc, 0xee0, 0xeec
 146         };
 147         int i, chain;
 148         uint32_t hssi_param1;
 149
 150         if (n == 0) {
 151                 for (i = 0; i < nitems(reg_adda); i++)
 152                         vals->adda[i] = rtwn_bb_read(sc, reg_adda[i]);
 153
 154                 vals->txpause = rtwn_read_1(sc, R92C_TXPAUSE);
 155                 vals->bcn_ctrl[0] = rtwn_read_1(sc, R92C_BCN_CTRL(0));
 156                 vals->bcn_ctrl[1] = rtwn_read_1(sc, R92C_BCN_CTRL(1));
 157                 vals->gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG);
 158         }
 159
 160         if (sc->ntxchains == 1) {
 161                 rtwn_bb_write(sc, reg_adda[0], 0x0b1b25a0);
 162                 for (i = 1; i < nitems(reg_adda); i++)
 163                         rtwn_bb_write(sc, reg_adda[i], 0x0bdb25a0);
 164         } else {
 165                 for (i = 0; i < nitems(reg_adda); i++)
 166                         rtwn_bb_write(sc, reg_adda[i], 0x04db25a4);
 167         }
 168
 169         hssi_param1 = rtwn_bb_read(sc, R92C_HSSI_PARAM1(0));
 170         if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) {
 171                 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0),
 172                     hssi_param1 | R92C_HSSI_PARAM1_PI);
 173                 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1),
 174                     hssi_param1 | R92C_HSSI_PARAM1_PI);
 175         }
 176
 177         if (n == 0) {
 178                 vals->cck0_afesetting = rtwn_bb_read(sc, R92C_CCK0_AFESETTING);
 179                 vals->ofdm0_trxpathena =
 180                     rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
 181                 vals->ofdm0_trmuxpar = rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR);
 182                 vals->fpga0_rfifacesw0 =
 183                     rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(0));
 184                 vals->fpga0_rfifacesw1 =
 185                     rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1));
 186                 vals->fpga0_rfifaceoe0 =
 187                     rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0));
 188                 vals->fpga0_rfifaceoe1 =
 189                     rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(1));
 190                 vals->config_ant0 = rtwn_bb_read(sc, R92C_CONFIG_ANT(0));
 191                 vals->config_ant1 = rtwn_bb_read(sc, R92C_CONFIG_ANT(1));
 192         }
 193
 194         rtwn_bb_setbits(sc, R92C_CCK0_AFESETTING, 0, 0x0f000000);
 195         rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 0x03a05600);
 196         rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, 0x000800e4);
 197         rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000);
 198         rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACESW(0), 0, 0x04000400);
 199         rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(0), 0x400, 0);
 200         rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(1), 0x400, 0);
 201
 202         if (sc->ntxchains > 1) {
 203                 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000);
 204                 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00010000);
 205         }
 206
 207         rtwn_write_1(sc, R92C_TXPAUSE,
 208             R92C_TX_QUEUE_AC | R92C_TX_QUEUE_MGT | R92C_TX_QUEUE_HIGH);
 209         rtwn_write_1(sc, R92C_BCN_CTRL(0),
 210             vals->bcn_ctrl[0] & ~R92C_BCN_CTRL_EN_BCN);
 211         rtwn_write_1(sc, R92C_BCN_CTRL(1),
 212             vals->bcn_ctrl[1] & ~R92C_BCN_CTRL_EN_BCN);
 213         rtwn_write_1(sc, R92C_GPIO_MUXCFG,
 214             vals->gpio_muxcfg & ~R92C_GPIO_MUXCFG_ENBT);
 215
 216         rtwn_bb_write(sc, R92C_CONFIG_ANT(0), 0x00080000);
 217         if (sc->ntxchains > 1)
 218                 rtwn_bb_write(sc, R92C_CONFIG_ANT(1), 0x00080000);
 219
 220         rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000);
 221         rtwn_bb_write(sc, R92C_TX_IQK, 0x01007c00);
 222         rtwn_bb_write(sc, R92C_RX_IQK, 0x01004800);
 223
 224         for (chain = 0; chain < sc->ntxchains; chain++) {
 225                 if (chain > 0) {
 226                         /* Put chain 0 on standby. */
 227                         rtwn_bb_write(sc, R92C_FPGA0_IQK, 0);
 228                         rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000);
 229                         rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000);
 230
 231                         /* Enable chain 1. */
 232                         for (i = 0; i < nitems(reg_adda); i++)
 233                                 rtwn_bb_write(sc, reg_adda[i], 0x0b1b25a4);
 234                 }
 235
 236                 /* Run IQ calibration twice. */
 237                 for (i = 0; i < 2; i++) {
 238                         int ret;
 239
 240                         ret = r92c_iq_calib_chain(sc, chain,
 241                             tx[chain], rx[chain]);
 242                         if (ret == 0) {
 243                                 RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB,
 244                                     "%s: chain %d: Tx failed.\n",
 245                                     __func__, chain);
 246                                 tx[chain][0] = 0xff;
 247                                 tx[chain][1] = 0xff;
 248                                 rx[chain][0] = 0xff;
 249                                 rx[chain][1] = 0xff;
 250                         } else if (ret == 1) {
 251                                 RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB,
 252                                     "%s: chain %d: Rx failed.\n",
 253                                     __func__, chain);
 254                                 rx[chain][0] = 0xff;
 255                                 rx[chain][1] = 0xff;
 256                         } else if (ret == 3) {
 257                                 RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB,
 258                                     "%s: chain %d: Both Tx and Rx "
 259                                     "succeeded.\n", __func__, chain);
 260                         }
 261                 }
 262
 263                 RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB,
 264                     "%s: results for run %d chain %d: tx[0] 0x%x, "
 265                     "tx[1] 0x%x, rx[0] 0x%x, rx[1] 0x%x\n", __func__, n, chain,
 266                     tx[chain][0], tx[chain][1], rx[chain][0], rx[chain][1]);
 267         }
 268
 269         rtwn_bb_write(sc, R92C_CCK0_AFESETTING, vals->cck0_afesetting);
 270         rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, vals->ofdm0_trxpathena);
 271         rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(0), vals->fpga0_rfifacesw0);
 272         rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), vals->fpga0_rfifacesw1);
 273         rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, vals->ofdm0_trmuxpar);
 274         rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0), vals->fpga0_rfifaceoe0);
 275         rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1), vals->fpga0_rfifaceoe1);
 276         rtwn_bb_write(sc, R92C_CONFIG_ANT(0), vals->config_ant0);
 277         rtwn_bb_write(sc, R92C_CONFIG_ANT(1), vals->config_ant1);
 278
 279         rtwn_bb_write(sc, R92C_FPGA0_IQK, 0);
 280         rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00032ed3);
 281         if (sc->ntxchains > 1)
 282                 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00032ed3);
 283
 284         if (n != 0) {
 285                 if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) {
 286                         rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), hssi_param1);
 287                         rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), hssi_param1);
 288                 }
 289
 290                 for (i = 0; i < nitems(reg_adda); i++)
 291                         rtwn_bb_write(sc, reg_adda[i], vals->adda[i]);
 292
 293                 rtwn_write_1(sc, R92C_TXPAUSE, vals->txpause);
 294                 rtwn_write_1(sc, R92C_BCN_CTRL(0), vals->bcn_ctrl[0]);
 295                 rtwn_write_1(sc, R92C_BCN_CTRL(1), vals->bcn_ctrl[1]);
 296                 rtwn_write_4(sc, R92C_GPIO_MUXCFG, vals->gpio_muxcfg);
 297
 298                 rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x01008c00);
 299                 rtwn_bb_write(sc, R92C_RX_IQK_TONE(0), 0x01008c00);
 300         }
 301 }
 302
 303 #define RTWN_IQ_CAL_MAX_TOLERANCE 5
 304 static int
 305 r92c_iq_calib_compare_results(struct rtwn_softc *sc, uint16_t tx1[2][2],
 306     uint16_t rx1[2][2], uint16_t tx2[2][2], uint16_t rx2[2][2])
 307 {
 308         int chain, i, tx_ok[2], rx_ok[2];
 309
 310         tx_ok[0] = tx_ok[1] = rx_ok[0] = rx_ok[1] = 0;
 311         for (chain = 0; chain < sc->ntxchains; chain++) {
 312                 for (i = 0; i < 2; i++) {
 313                         if (tx1[chain][i] == 0xff || tx2[chain][i] == 0xff ||
 314                             rx1[chain][i] == 0xff || rx2[chain][i] == 0xff)
 315                                 continue;
 316
 317                         tx_ok[chain] = (abs(tx1[chain][i] - tx2[chain][i]) <=
 318                             RTWN_IQ_CAL_MAX_TOLERANCE);
 319
 320                         rx_ok[chain] = (abs(rx1[chain][i] - rx2[chain][i]) <=
 321                             RTWN_IQ_CAL_MAX_TOLERANCE);
 322                 }
 323         }
 324
 325         if (sc->ntxchains > 1)
 326                 return (tx_ok[0] && tx_ok[1] && rx_ok[0] && rx_ok[1]);
 327         else
 328                 return (tx_ok[0] && rx_ok[0]);
 329 }
 330 #undef RTWN_IQ_CAL_MAX_TOLERANCE
 331
 332 static void
 333 r92c_iq_calib_write_results(struct rtwn_softc *sc, uint16_t tx[2],
 334     uint16_t rx[2], int chain)
 335 {
 336         uint32_t reg, val, x;
 337         long y, tx_c;
 338
 339         if (tx[0] == 0xff || tx[1] == 0xff)
 340                 return;
 341
 342         reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain));
 343         val = ((reg >> 22) & 0x3ff);
 344         x = tx[0];
 345         if (x & 0x00000200)
 346                 x |= 0xfffffc00;
 347         reg = (((x * val) >> 8) & 0x3ff);
 348         rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(chain), 0x3ff, reg);
 349         rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x80000000,
 350             ((x * val) & 0x80) << 24);
 351
 352         y = tx[1];
 353         if (y & 0x00000200)
 354                 y |= 0xfffffc00;
 355         tx_c = (y * val) >> 8;
 356         rtwn_bb_setbits(sc, R92C_OFDM0_TXAFE(chain), 0xf0000000,
 357             (tx_c & 0x3c0) << 22);
 358         rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(chain), 0x003f0000,
 359             (tx_c & 0x3f) << 16);
 360         rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x20000000,
 361             ((y * val) & 0x80) << 22);
 362
 363         if (rx[0] == 0xff || rx[1] == 0xff)
 364                 return;
 365
 366         rtwn_bb_setbits(sc, R92C_OFDM0_RXIQIMBALANCE(chain), 0x3ff,
 367             rx[0] & 0x3ff);
 368         rtwn_bb_setbits(sc, R92C_OFDM0_RXIQIMBALANCE(chain), 0xfc00,
 369             (rx[1] & 0x3f) << 10);
 370
 371         if (chain == 0) {
 372                 rtwn_bb_setbits(sc, R92C_OFDM0_RXIQEXTANTA, 0xf0000000,
 373                     (rx[1] & 0x3c0) << 22);
 374         } else {
 375                 rtwn_bb_setbits(sc, R92C_OFDM0_AGCRSSITABLE, 0xf000,
 376                     (rx[1] & 0x3c0) << 6);
 377         }
 378 }
 379
 380 #define RTWN_IQ_CAL_NRUN        3
 381 void
 382 r92c_iq_calib(struct rtwn_softc *sc)
 383 {
 384         struct r92c_iq_cal_reg_vals vals;
 385         uint16_t tx[RTWN_IQ_CAL_NRUN][2][2], rx[RTWN_IQ_CAL_NRUN][2][2];
 386         int n, valid;
 387
 388         valid = 0;
 389         for (n = 0; n < RTWN_IQ_CAL_NRUN; n++) {
 390                 r92c_iq_calib_run(sc, n, tx[n], rx[n], &vals);
 391
 392                 if (n == 0)
 393                         continue;
 394
 395                 /* Valid results remain stable after consecutive runs. */
 396                 valid = r92c_iq_calib_compare_results(sc, tx[n - 1],
 397                     rx[n - 1], tx[n], rx[n]);
 398                 if (valid)
 399                         break;
 400         }
 401
 402         if (valid) {
 403                 r92c_iq_calib_write_results(sc, tx[n][0], rx[n][0], 0);
 404                 if (sc->ntxchains > 1)
 405                         r92c_iq_calib_write_results(sc, tx[n][1], rx[n][1], 1);
 406         }
 407 }
 408 #undef RTWN_IQ_CAL_NRUN
 409
 410 void
 411 r92c_lc_calib(struct rtwn_softc *sc)
 412 {
 413         uint32_t rf_ac[2];
 414         uint8_t txmode;
 415         int i;
 416
 417         txmode = rtwn_read_1(sc, R92C_OFDM1_LSTF + 3);
 418         if ((txmode & 0x70) != 0) {
 419                 /* Disable all continuous Tx. */
 420                 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70);
 421
 422                 /* Set RF mode to standby mode. */
 423                 for (i = 0; i < sc->nrxchains; i++) {
 424                         rf_ac[i] = rtwn_rf_read(sc, i, R92C_RF_AC);
 425                         rtwn_rf_write(sc, i, R92C_RF_AC,
 426                             RW(rf_ac[i], R92C_RF_AC_MODE,
 427                                 R92C_RF_AC_MODE_STANDBY));
 428                 }
 429         } else {
 430                 /* Block all Tx queues. */
 431                 rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
 432         }
 433         /* Start calibration. */
 434         rtwn_rf_setbits(sc, 0, R92C_RF_CHNLBW, 0, R92C_RF_CHNLBW_LCSTART);
 435
 436         /* Give calibration the time to complete. */
 437         rtwn_delay(sc, 100000); /* 100ms */
 438
 439         /* Restore configuration. */
 440         if ((txmode & 0x70) != 0) {
 441                 /* Restore Tx mode. */
 442                 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode);
 443                 /* Restore RF mode. */
 444                 for (i = 0; i < sc->nrxchains; i++)
 445                         rtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]);
 446         } else {
 447                 /* Unblock all Tx queues. */
 448                 rtwn_write_1(sc, R92C_TXPAUSE, 0x00);
 449         }
 450 }
 451
 452 void
 453 r92c_temp_measure(struct rtwn_softc *sc)
 454 {
 455         rtwn_rf_write(sc, 0, R92C_RF_T_METER, R92C_RF_T_METER_START);
 456 }
 457
 458 uint8_t
 459 r92c_temp_read(struct rtwn_softc *sc)
 460 {
 461         return (MS(rtwn_rf_read(sc, 0, R92C_RF_T_METER),
 462             R92C_RF_T_METER_VAL));
 463 }