1 /* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */
4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org>
6 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org>
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #include <sys/cdefs.h>
22 __FBSDID("$FreeBSD$");
26 #include <sys/param.h>
28 #include <sys/mutex.h>
30 #include <sys/kernel.h>
31 #include <sys/socket.h>
32 #include <sys/systm.h>
33 #include <sys/malloc.h>
34 #include <sys/queue.h>
35 #include <sys/taskqueue.h>
37 #include <sys/endian.h>
38 #include <sys/linker.h>
41 #include <net/ethernet.h>
42 #include <net/if_media.h>
44 #include <net80211/ieee80211_var.h>
45 #include <net80211/ieee80211_radiotap.h>
47 #include <dev/rtwn/if_rtwnreg.h>
48 #include <dev/rtwn/if_rtwnvar.h>
49 #include <dev/rtwn/if_rtwn_debug.h>
51 #include <dev/rtwn/rtl8192c/r92c.h>
52 #include <dev/rtwn/rtl8192c/r92c_reg.h>
55 /* Registers to save and restore during IQ calibration. */
56 struct r92c_iq_cal_reg_vals {
61 uint32_t cck0_afesetting;
62 uint32_t ofdm0_trxpathena;
63 uint32_t ofdm0_trmuxpar;
64 uint32_t fpga0_rfifacesw0;
65 uint32_t fpga0_rfifacesw1;
66 uint32_t fpga0_rfifaceoe0;
67 uint32_t fpga0_rfifaceoe1;
74 r92c_iq_calib_chain(struct rtwn_softc *sc, int chain, uint16_t tx[2],
79 if (chain == 0) { /* IQ calibration for chain 0. */
80 /* IQ calibration settings for chain 0. */
81 rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x10008c1f);
82 rtwn_bb_write(sc, R92C_RX_IQK_TONE(0), 0x10008c1f);
83 rtwn_bb_write(sc, R92C_TX_IQK_PI(0), 0x82140102);
85 if (sc->ntxchains > 1) {
86 rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160202);
87 /* IQ calibration settings for chain 1. */
88 rtwn_bb_write(sc, R92C_TX_IQK_TONE(1), 0x10008c22);
89 rtwn_bb_write(sc, R92C_RX_IQK_TONE(1), 0x10008c22);
90 rtwn_bb_write(sc, R92C_TX_IQK_PI(1), 0x82140102);
91 rtwn_bb_write(sc, R92C_RX_IQK_PI(1), 0x28160202);
93 rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160502);
95 /* LO calibration settings. */
96 rtwn_bb_write(sc, R92C_IQK_AGC_RSP, 0x001028d1);
97 /* We're doing LO and IQ calibration in one shot. */
98 rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf9000000);
99 rtwn_bb_write(sc, R92C_IQK_AGC_PTS, 0xf8000000);
101 } else { /* IQ calibration for chain 1. */
102 /* We're doing LO and IQ calibration in one shot. */
103 rtwn_bb_write(sc, R92C_IQK_AGC_CONT, 2);
104 rtwn_bb_write(sc, R92C_IQK_AGC_CONT, 0);
107 /* Give LO and IQ calibrations the time to complete. */
108 rtwn_delay(sc, 10000);
110 /* Read IQ calibration status. */
111 status = rtwn_bb_read(sc, R92C_RX_POWER_IQK_AFTER(0));
113 if (status & (1 << (28 + chain * 3)))
114 return (0); /* Tx failed. */
115 /* Read Tx IQ calibration results. */
116 tx[0] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_BEFORE(chain)),
117 R92C_POWER_IQK_RESULT);
118 tx[1] = MS(rtwn_bb_read(sc, R92C_TX_POWER_IQK_AFTER(chain)),
119 R92C_POWER_IQK_RESULT);
120 if (tx[0] == 0x142 || tx[1] == 0x042)
121 return (0); /* Tx failed. */
123 if (status & (1 << (27 + chain * 3)))
124 return (1); /* Rx failed. */
125 /* Read Rx IQ calibration results. */
126 rx[0] = MS(rtwn_bb_read(sc, R92C_RX_POWER_IQK_BEFORE(chain)),
127 R92C_POWER_IQK_RESULT);
128 rx[1] = MS(rtwn_bb_read(sc, R92C_RX_POWER_IQK_AFTER(chain)),
129 R92C_POWER_IQK_RESULT);
130 if (rx[0] == 0x132 || rx[1] == 0x036)
131 return (1); /* Rx failed. */
133 return (3); /* Both Tx and Rx succeeded. */
137 r92c_iq_calib_run(struct rtwn_softc *sc, int n, uint16_t tx[2][2],
138 uint16_t rx[2][2], struct r92c_iq_cal_reg_vals *vals)
140 /* Registers to save and restore during IQ calibration. */
141 static const uint16_t reg_adda[16] = {
142 0x85c, 0xe6c, 0xe70, 0xe74,
143 0xe78, 0xe7c, 0xe80, 0xe84,
144 0xe88, 0xe8c, 0xed0, 0xed4,
145 0xed8, 0xedc, 0xee0, 0xeec
148 uint32_t hssi_param1;
151 for (i = 0; i < nitems(reg_adda); i++)
152 vals->adda[i] = rtwn_bb_read(sc, reg_adda[i]);
154 vals->txpause = rtwn_read_1(sc, R92C_TXPAUSE);
155 vals->bcn_ctrl[0] = rtwn_read_1(sc, R92C_BCN_CTRL(0));
156 vals->bcn_ctrl[1] = rtwn_read_1(sc, R92C_BCN_CTRL(1));
157 vals->gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG);
160 if (sc->ntxchains == 1) {
161 rtwn_bb_write(sc, reg_adda[0], 0x0b1b25a0);
162 for (i = 1; i < nitems(reg_adda); i++)
163 rtwn_bb_write(sc, reg_adda[i], 0x0bdb25a0);
165 for (i = 0; i < nitems(reg_adda); i++)
166 rtwn_bb_write(sc, reg_adda[i], 0x04db25a4);
169 hssi_param1 = rtwn_bb_read(sc, R92C_HSSI_PARAM1(0));
170 if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) {
171 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0),
172 hssi_param1 | R92C_HSSI_PARAM1_PI);
173 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1),
174 hssi_param1 | R92C_HSSI_PARAM1_PI);
178 vals->cck0_afesetting = rtwn_bb_read(sc, R92C_CCK0_AFESETTING);
179 vals->ofdm0_trxpathena =
180 rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
181 vals->ofdm0_trmuxpar = rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR);
182 vals->fpga0_rfifacesw0 =
183 rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(0));
184 vals->fpga0_rfifacesw1 =
185 rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1));
186 vals->fpga0_rfifaceoe0 =
187 rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0));
188 vals->fpga0_rfifaceoe1 =
189 rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(1));
190 vals->config_ant0 = rtwn_bb_read(sc, R92C_CONFIG_ANT(0));
191 vals->config_ant1 = rtwn_bb_read(sc, R92C_CONFIG_ANT(1));
194 rtwn_bb_setbits(sc, R92C_CCK0_AFESETTING, 0, 0x0f000000);
195 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 0x03a05600);
196 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, 0x000800e4);
197 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000);
198 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACESW(0), 0, 0x04000400);
199 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(0), 0x400, 0);
200 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(1), 0x400, 0);
202 if (sc->ntxchains > 1) {
203 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000);
204 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00010000);
207 rtwn_write_1(sc, R92C_TXPAUSE,
208 R92C_TX_QUEUE_AC | R92C_TX_QUEUE_MGT | R92C_TX_QUEUE_HIGH);
209 rtwn_write_1(sc, R92C_BCN_CTRL(0),
210 vals->bcn_ctrl[0] & ~R92C_BCN_CTRL_EN_BCN);
211 rtwn_write_1(sc, R92C_BCN_CTRL(1),
212 vals->bcn_ctrl[1] & ~R92C_BCN_CTRL_EN_BCN);
213 rtwn_write_1(sc, R92C_GPIO_MUXCFG,
214 vals->gpio_muxcfg & ~R92C_GPIO_MUXCFG_ENBT);
216 rtwn_bb_write(sc, R92C_CONFIG_ANT(0), 0x00080000);
217 if (sc->ntxchains > 1)
218 rtwn_bb_write(sc, R92C_CONFIG_ANT(1), 0x00080000);
220 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000);
221 rtwn_bb_write(sc, R92C_TX_IQK, 0x01007c00);
222 rtwn_bb_write(sc, R92C_RX_IQK, 0x01004800);
224 for (chain = 0; chain < sc->ntxchains; chain++) {
226 /* Put chain 0 on standby. */
227 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0);
228 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000);
229 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000);
231 /* Enable chain 1. */
232 for (i = 0; i < nitems(reg_adda); i++)
233 rtwn_bb_write(sc, reg_adda[i], 0x0b1b25a4);
236 /* Run IQ calibration twice. */
237 for (i = 0; i < 2; i++) {
240 ret = r92c_iq_calib_chain(sc, chain,
241 tx[chain], rx[chain]);
243 RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB,
244 "%s: chain %d: Tx failed.\n",
250 } else if (ret == 1) {
251 RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB,
252 "%s: chain %d: Rx failed.\n",
256 } else if (ret == 3) {
257 RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB,
258 "%s: chain %d: Both Tx and Rx "
259 "succeeded.\n", __func__, chain);
263 RTWN_DPRINTF(sc, RTWN_DEBUG_CALIB,
264 "%s: results for run %d chain %d: tx[0] 0x%x, "
265 "tx[1] 0x%x, rx[0] 0x%x, rx[1] 0x%x\n", __func__, n, chain,
266 tx[chain][0], tx[chain][1], rx[chain][0], rx[chain][1]);
269 rtwn_bb_write(sc, R92C_CCK0_AFESETTING, vals->cck0_afesetting);
270 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, vals->ofdm0_trxpathena);
271 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(0), vals->fpga0_rfifacesw0);
272 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), vals->fpga0_rfifacesw1);
273 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, vals->ofdm0_trmuxpar);
274 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0), vals->fpga0_rfifaceoe0);
275 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1), vals->fpga0_rfifaceoe1);
276 rtwn_bb_write(sc, R92C_CONFIG_ANT(0), vals->config_ant0);
277 rtwn_bb_write(sc, R92C_CONFIG_ANT(1), vals->config_ant1);
279 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0);
280 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00032ed3);
281 if (sc->ntxchains > 1)
282 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00032ed3);
285 if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) {
286 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), hssi_param1);
287 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), hssi_param1);
290 for (i = 0; i < nitems(reg_adda); i++)
291 rtwn_bb_write(sc, reg_adda[i], vals->adda[i]);
293 rtwn_write_1(sc, R92C_TXPAUSE, vals->txpause);
294 rtwn_write_1(sc, R92C_BCN_CTRL(0), vals->bcn_ctrl[0]);
295 rtwn_write_1(sc, R92C_BCN_CTRL(1), vals->bcn_ctrl[1]);
296 rtwn_write_4(sc, R92C_GPIO_MUXCFG, vals->gpio_muxcfg);
298 rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x01008c00);
299 rtwn_bb_write(sc, R92C_RX_IQK_TONE(0), 0x01008c00);
303 #define RTWN_IQ_CAL_MAX_TOLERANCE 5
305 r92c_iq_calib_compare_results(struct rtwn_softc *sc, uint16_t tx1[2][2],
306 uint16_t rx1[2][2], uint16_t tx2[2][2], uint16_t rx2[2][2])
308 int chain, i, tx_ok[2], rx_ok[2];
310 tx_ok[0] = tx_ok[1] = rx_ok[0] = rx_ok[1] = 0;
311 for (chain = 0; chain < sc->ntxchains; chain++) {
312 for (i = 0; i < 2; i++) {
313 if (tx1[chain][i] == 0xff || tx2[chain][i] == 0xff ||
314 rx1[chain][i] == 0xff || rx2[chain][i] == 0xff)
317 tx_ok[chain] = (abs(tx1[chain][i] - tx2[chain][i]) <=
318 RTWN_IQ_CAL_MAX_TOLERANCE);
320 rx_ok[chain] = (abs(rx1[chain][i] - rx2[chain][i]) <=
321 RTWN_IQ_CAL_MAX_TOLERANCE);
325 if (sc->ntxchains > 1)
326 return (tx_ok[0] && tx_ok[1] && rx_ok[0] && rx_ok[1]);
328 return (tx_ok[0] && rx_ok[0]);
330 #undef RTWN_IQ_CAL_MAX_TOLERANCE
333 r92c_iq_calib_write_results(struct rtwn_softc *sc, uint16_t tx[2],
334 uint16_t rx[2], int chain)
336 uint32_t reg, val, x;
339 if (tx[0] == 0xff || tx[1] == 0xff)
342 reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain));
343 val = ((reg >> 22) & 0x3ff);
347 reg = (((x * val) >> 8) & 0x3ff);
348 rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(chain), 0x3ff, reg);
349 rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x80000000,
350 ((x * val) & 0x80) << 24);
355 tx_c = (y * val) >> 8;
356 rtwn_bb_setbits(sc, R92C_OFDM0_TXAFE(chain), 0xf0000000,
357 (tx_c & 0x3c0) << 22);
358 rtwn_bb_setbits(sc, R92C_OFDM0_TXIQIMBALANCE(chain), 0x003f0000,
359 (tx_c & 0x3f) << 16);
360 rtwn_bb_setbits(sc, R92C_OFDM0_ECCATHRESHOLD, 0x20000000,
361 ((y * val) & 0x80) << 22);
363 if (rx[0] == 0xff || rx[1] == 0xff)
366 rtwn_bb_setbits(sc, R92C_OFDM0_RXIQIMBALANCE(chain), 0x3ff,
368 rtwn_bb_setbits(sc, R92C_OFDM0_RXIQIMBALANCE(chain), 0xfc00,
369 (rx[1] & 0x3f) << 10);
372 rtwn_bb_setbits(sc, R92C_OFDM0_RXIQEXTANTA, 0xf0000000,
373 (rx[1] & 0x3c0) << 22);
375 rtwn_bb_setbits(sc, R92C_OFDM0_AGCRSSITABLE, 0xf000,
376 (rx[1] & 0x3c0) << 6);
380 #define RTWN_IQ_CAL_NRUN 3
382 r92c_iq_calib(struct rtwn_softc *sc)
384 struct r92c_iq_cal_reg_vals vals;
385 uint16_t tx[RTWN_IQ_CAL_NRUN][2][2], rx[RTWN_IQ_CAL_NRUN][2][2];
389 for (n = 0; n < RTWN_IQ_CAL_NRUN; n++) {
390 r92c_iq_calib_run(sc, n, tx[n], rx[n], &vals);
395 /* Valid results remain stable after consecutive runs. */
396 valid = r92c_iq_calib_compare_results(sc, tx[n - 1],
397 rx[n - 1], tx[n], rx[n]);
403 r92c_iq_calib_write_results(sc, tx[n][0], rx[n][0], 0);
404 if (sc->ntxchains > 1)
405 r92c_iq_calib_write_results(sc, tx[n][1], rx[n][1], 1);
408 #undef RTWN_IQ_CAL_NRUN
411 r92c_lc_calib(struct rtwn_softc *sc)
417 txmode = rtwn_read_1(sc, R92C_OFDM1_LSTF + 3);
418 if ((txmode & 0x70) != 0) {
419 /* Disable all continuous Tx. */
420 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70);
422 /* Set RF mode to standby mode. */
423 for (i = 0; i < sc->nrxchains; i++) {
424 rf_ac[i] = rtwn_rf_read(sc, i, R92C_RF_AC);
425 rtwn_rf_write(sc, i, R92C_RF_AC,
426 RW(rf_ac[i], R92C_RF_AC_MODE,
427 R92C_RF_AC_MODE_STANDBY));
430 /* Block all Tx queues. */
431 rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
433 /* Start calibration. */
434 rtwn_rf_setbits(sc, 0, R92C_RF_CHNLBW, 0, R92C_RF_CHNLBW_LCSTART);
436 /* Give calibration the time to complete. */
437 rtwn_delay(sc, 100000); /* 100ms */
439 /* Restore configuration. */
440 if ((txmode & 0x70) != 0) {
441 /* Restore Tx mode. */
442 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode);
443 /* Restore RF mode. */
444 for (i = 0; i < sc->nrxchains; i++)
445 rtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]);
447 /* Unblock all Tx queues. */
448 rtwn_write_1(sc, R92C_TXPAUSE, 0x00);
453 r92c_temp_measure(struct rtwn_softc *sc)
455 rtwn_rf_write(sc, 0, R92C_RF_T_METER, R92C_RF_T_METER_START);
459 r92c_temp_read(struct rtwn_softc *sc)
461 return (MS(rtwn_rf_read(sc, 0, R92C_RF_T_METER),
462 R92C_RF_T_METER_VAL));