1 /* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */
4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org>
6 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org>
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #include <sys/cdefs.h>
22 __FBSDID("$FreeBSD$");
26 #include <sys/param.h>
28 #include <sys/mutex.h>
30 #include <sys/kernel.h>
31 #include <sys/socket.h>
32 #include <sys/systm.h>
33 #include <sys/malloc.h>
34 #include <sys/queue.h>
35 #include <sys/taskqueue.h>
37 #include <sys/endian.h>
38 #include <sys/linker.h>
41 #include <net/ethernet.h>
42 #include <net/if_media.h>
44 #include <net80211/ieee80211_var.h>
45 #include <net80211/ieee80211_radiotap.h>
47 #include <dev/rtwn/if_rtwnreg.h>
48 #include <dev/rtwn/if_rtwnvar.h>
50 #include <dev/rtwn/if_rtwn_debug.h>
51 #include <dev/rtwn/if_rtwn_ridx.h>
53 #include <dev/rtwn/rtl8192c/r92c.h>
54 #include <dev/rtwn/rtl8192c/r92c_priv.h>
55 #include <dev/rtwn/rtl8192c/r92c_reg.h>
56 #include <dev/rtwn/rtl8192c/r92c_var.h>
60 r92c_get_power_group(struct rtwn_softc *sc, struct ieee80211_channel *c)
65 chan = rtwn_chan2centieee(c);
66 if (IEEE80211_IS_CHAN_2GHZ(c)) {
67 if (chan <= 3) group = 0;
68 else if (chan <= 9) group = 1;
69 else if (chan <= 14) group = 2;
71 KASSERT(0, ("wrong 2GHz channel %d!\n", chan));
75 KASSERT(0, ("wrong channel band (flags %08X)\n", c->ic_flags));
84 r92c_get_txpower(struct rtwn_softc *sc, int chain,
85 struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT])
87 struct r92c_softc *rs = sc->sc_priv;
88 struct rtwn_r92c_txpwr *rt = rs->rs_txpwr;
89 const struct rtwn_r92c_txagc *base = rs->rs_txagc;
90 uint8_t ofdmpow, htpow, diff, max;
91 int max_mcs, ridx, group;
93 /* Determine channel group. */
94 group = r92c_get_power_group(sc, c);
95 if (group == -1) { /* shouldn't happen */
96 device_printf(sc->sc_dev, "%s: incorrect channel\n", __func__);
100 /* XXX net80211 regulatory */
102 max_mcs = RTWN_RIDX_HT_MCS(sc->ntxchains * 8 - 1);
103 KASSERT(max_mcs <= RTWN_RIDX_COUNT, ("increase ridx limit\n"));
105 if (rs->regulatory == 0) {
106 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++)
107 power[ridx] = base[chain].pwr[0][ridx];
109 for (ridx = RTWN_RIDX_OFDM6; ridx < RTWN_RIDX_COUNT; ridx++) {
110 if (rs->regulatory == 3) {
111 power[ridx] = base[chain].pwr[0][ridx];
112 /* Apply vendor limits. */
113 if (IEEE80211_IS_CHAN_HT40(c))
114 max = rt->ht40_max_pwr[chain][group];
116 max = rt->ht20_max_pwr[chain][group];
117 if (power[ridx] > max)
119 } else if (rs->regulatory == 1) {
120 if (!IEEE80211_IS_CHAN_HT40(c))
121 power[ridx] = base[chain].pwr[group][ridx];
122 } else if (rs->regulatory != 2)
123 power[ridx] = base[chain].pwr[0][ridx];
126 /* Compute per-CCK rate Tx power. */
127 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++)
128 power[ridx] += rt->cck_tx_pwr[chain][group];
130 htpow = rt->ht40_1s_tx_pwr[chain][group];
131 if (sc->ntxchains > 1) {
132 /* Apply reduction for 2 spatial streams. */
133 diff = rt->ht40_2s_tx_pwr_diff[chain][group];
134 htpow = (htpow > diff) ? htpow - diff : 0;
137 /* Compute per-OFDM rate Tx power. */
138 diff = rt->ofdm_tx_pwr_diff[chain][group];
139 ofdmpow = htpow + diff; /* HT->OFDM correction. */
140 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++)
141 power[ridx] += ofdmpow;
143 /* Compute per-MCS Tx power. */
144 if (!IEEE80211_IS_CHAN_HT40(c)) {
145 diff = rt->ht20_tx_pwr_diff[chain][group];
146 htpow += diff; /* HT40->HT20 correction. */
148 for (ridx = RTWN_RIDX_HT_MCS(0); ridx <= max_mcs; ridx++)
149 power[ridx] += htpow;
151 /* Apply max limit. */
152 for (ridx = RTWN_RIDX_CCK1; ridx <= max_mcs; ridx++) {
153 if (power[ridx] > R92C_MAX_TX_PWR)
154 power[ridx] = R92C_MAX_TX_PWR;
159 r92c_write_txpower(struct rtwn_softc *sc, int chain,
160 uint8_t power[RTWN_RIDX_COUNT])
164 /* Write per-CCK rate Tx power. */
166 reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);
167 reg = RW(reg, R92C_TXAGC_A_CCK1, power[RTWN_RIDX_CCK1]);
168 rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg);
169 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
170 reg = RW(reg, R92C_TXAGC_A_CCK2, power[RTWN_RIDX_CCK2]);
171 reg = RW(reg, R92C_TXAGC_A_CCK55, power[RTWN_RIDX_CCK55]);
172 reg = RW(reg, R92C_TXAGC_A_CCK11, power[RTWN_RIDX_CCK11]);
173 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
175 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);
176 reg = RW(reg, R92C_TXAGC_B_CCK1, power[RTWN_RIDX_CCK1]);
177 reg = RW(reg, R92C_TXAGC_B_CCK2, power[RTWN_RIDX_CCK2]);
178 reg = RW(reg, R92C_TXAGC_B_CCK55, power[RTWN_RIDX_CCK55]);
179 rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg);
180 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
181 reg = RW(reg, R92C_TXAGC_B_CCK11, power[RTWN_RIDX_CCK11]);
182 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
184 /* Write per-OFDM rate Tx power. */
185 rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain),
186 SM(R92C_TXAGC_RATE06, power[RTWN_RIDX_OFDM6]) |
187 SM(R92C_TXAGC_RATE09, power[RTWN_RIDX_OFDM9]) |
188 SM(R92C_TXAGC_RATE12, power[RTWN_RIDX_OFDM12]) |
189 SM(R92C_TXAGC_RATE18, power[RTWN_RIDX_OFDM18]));
190 rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain),
191 SM(R92C_TXAGC_RATE24, power[RTWN_RIDX_OFDM24]) |
192 SM(R92C_TXAGC_RATE36, power[RTWN_RIDX_OFDM36]) |
193 SM(R92C_TXAGC_RATE48, power[RTWN_RIDX_OFDM48]) |
194 SM(R92C_TXAGC_RATE54, power[RTWN_RIDX_OFDM54]));
195 /* Write per-MCS Tx power. */
196 rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain),
197 SM(R92C_TXAGC_MCS00, power[RTWN_RIDX_HT_MCS(0)]) |
198 SM(R92C_TXAGC_MCS01, power[RTWN_RIDX_HT_MCS(1)]) |
199 SM(R92C_TXAGC_MCS02, power[RTWN_RIDX_HT_MCS(2)]) |
200 SM(R92C_TXAGC_MCS03, power[RTWN_RIDX_HT_MCS(3)]));
201 rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain),
202 SM(R92C_TXAGC_MCS04, power[RTWN_RIDX_HT_MCS(4)]) |
203 SM(R92C_TXAGC_MCS05, power[RTWN_RIDX_HT_MCS(5)]) |
204 SM(R92C_TXAGC_MCS06, power[RTWN_RIDX_HT_MCS(6)]) |
205 SM(R92C_TXAGC_MCS07, power[RTWN_RIDX_HT_MCS(7)]));
206 if (sc->ntxchains >= 2) {
207 rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain),
208 SM(R92C_TXAGC_MCS08, power[RTWN_RIDX_HT_MCS(8)]) |
209 SM(R92C_TXAGC_MCS09, power[RTWN_RIDX_HT_MCS(9)]) |
210 SM(R92C_TXAGC_MCS10, power[RTWN_RIDX_HT_MCS(10)]) |
211 SM(R92C_TXAGC_MCS11, power[RTWN_RIDX_HT_MCS(11)]));
212 rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain),
213 SM(R92C_TXAGC_MCS12, power[RTWN_RIDX_HT_MCS(12)]) |
214 SM(R92C_TXAGC_MCS13, power[RTWN_RIDX_HT_MCS(13)]) |
215 SM(R92C_TXAGC_MCS14, power[RTWN_RIDX_HT_MCS(14)]) |
216 SM(R92C_TXAGC_MCS15, power[RTWN_RIDX_HT_MCS(15)]));
221 r92c_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c)
223 uint8_t power[RTWN_RIDX_COUNT];
226 for (i = 0; i < sc->ntxchains; i++) {
227 memset(power, 0, sizeof(power));
228 /* Compute per-rate Tx power values. */
229 rtwn_r92c_get_txpower(sc, i, c, power);
231 if (sc->sc_debug & RTWN_DEBUG_TXPWR) {
234 max_mcs = RTWN_RIDX_HT_MCS(sc->ntxchains * 8 - 1);
236 /* Dump per-rate Tx power values. */
237 printf("Tx power for chain %d:\n", i);
238 for (ridx = RTWN_RIDX_CCK1; ridx <= max_mcs; ridx++)
239 printf("Rate %d = %u\n", ridx, power[ridx]);
242 /* Write per-rate Tx power values to hardware. */
243 r92c_write_txpower(sc, i, power);
248 r92c_set_bw40(struct rtwn_softc *sc, uint8_t chan, int prichlo)
250 struct r92c_softc *rs = sc->sc_priv;
252 rtwn_setbits_1(sc, R92C_BWOPMODE, R92C_BWOPMODE_20MHZ, 0);
253 rtwn_setbits_1(sc, R92C_RRSR + 2, 0x6f, (prichlo ? 1 : 2) << 5);
255 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_40MHZ);
256 rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, 0, R92C_RFMOD_40MHZ);
258 /* Set CCK side band. */
259 rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 0x10,
260 (prichlo ? 0 : 1) << 4);
262 rtwn_bb_setbits(sc, R92C_OFDM1_LSTF, 0x0c00,
263 (prichlo ? 1 : 2) << 10);
265 rtwn_bb_setbits(sc, R92C_FPGA0_ANAPARAM2,
266 R92C_FPGA0_ANAPARAM2_CBW20, 0);
268 rtwn_bb_setbits(sc, 0x818, 0x0c000000, (prichlo ? 2 : 1) << 26);
270 /* Select 40MHz bandwidth. */
271 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
272 (rs->rf_chnlbw[0] & ~0xfff) | chan);
276 r92c_set_bw20(struct rtwn_softc *sc, uint8_t chan)
278 struct r92c_softc *rs = sc->sc_priv;
280 rtwn_setbits_1(sc, R92C_BWOPMODE, 0, R92C_BWOPMODE_20MHZ);
282 rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, R92C_RFMOD_40MHZ, 0);
283 rtwn_bb_setbits(sc, R92C_FPGA1_RFMOD, R92C_RFMOD_40MHZ, 0);
285 rtwn_bb_setbits(sc, R92C_FPGA0_ANAPARAM2, 0,
286 R92C_FPGA0_ANAPARAM2_CBW20);
288 /* Select 20MHz bandwidth. */
289 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
290 (rs->rf_chnlbw[0] & ~0xfff) | chan | R92C_RF_CHNLBW_BW20);
294 r92c_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c)
296 struct r92c_softc *rs = sc->sc_priv;
300 chan = rtwn_chan2centieee(c);
302 /* Set Tx power for this new channel. */
303 r92c_set_txpower(sc, c);
305 for (i = 0; i < sc->nrxchains; i++) {
306 rtwn_rf_write(sc, i, R92C_RF_CHNLBW,
307 RW(rs->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan));
309 if (IEEE80211_IS_CHAN_HT40(c))
310 r92c_set_bw40(sc, chan, IEEE80211_IS_CHAN_HT40U(c));
312 rtwn_r92c_set_bw20(sc, chan);
316 r92c_set_gain(struct rtwn_softc *sc, uint8_t gain)
319 rtwn_bb_setbits(sc, R92C_OFDM0_AGCCORE1(0),
320 R92C_OFDM0_AGCCORE1_GAIN_M, gain);
321 rtwn_bb_setbits(sc, R92C_OFDM0_AGCCORE1(1),
322 R92C_OFDM0_AGCCORE1_GAIN_M, gain);
326 r92c_scan_start(struct ieee80211com *ic)
328 struct rtwn_softc *sc = ic->ic_softc;
329 struct r92c_softc *rs = sc->sc_priv;
332 /* Set gain for scanning. */
333 rtwn_r92c_set_gain(sc, 0x20);
336 rs->rs_scan_start(ic);
340 r92c_scan_end(struct ieee80211com *ic)
342 struct rtwn_softc *sc = ic->ic_softc;
343 struct r92c_softc *rs = sc->sc_priv;
346 /* Set gain under link. */
347 rtwn_r92c_set_gain(sc, 0x32);