2 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
3 * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org>
4 * Copyright (c) 2015-2016 Andriy Voskoboinyk <avos@FreeBSD.org>
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 * $OpenBSD: if_urtwnreg.h,v 1.3 2010/11/16 18:02:59 damien Exp $
28 /* System Configuration. */
29 #define R92C_SYS_ISO_CTRL 0x000
30 #define R92C_SYS_FUNC_EN 0x002
31 #define R92C_APS_FSMCO 0x004
32 #define R92C_SYS_CLKR 0x008
33 #define R92C_AFE_MISC 0x010
34 #define R92C_SPS0_CTRL 0x011
35 #define R92C_SPS_OCP_CFG 0x018
36 #define R92C_RSV_CTRL 0x01c
37 #define R92C_RF_CTRL 0x01f
38 #define R92C_LDOA15_CTRL 0x020
39 #define R92C_LDOV12D_CTRL 0x021
40 #define R92C_LDOHCI12_CTRL 0x022
41 #define R92C_LPLDO_CTRL 0x023
42 #define R92C_AFE_XTAL_CTRL 0x024
43 #define R92C_AFE_PLL_CTRL 0x028
44 #define R92C_APE_PLL_CTRL_EXT 0x02c
45 #define R92C_MAC_PHY_CTRL R92C_APE_PLL_CTRL_EXT
46 #define R92C_EFUSE_CTRL 0x030
47 #define R92C_EFUSE_TEST 0x034
48 #define R92C_PWR_DATA 0x038
49 #define R92C_CAL_TIMER 0x03c
50 #define R92C_ACLK_MON 0x03e
51 #define R92C_GPIO_MUXCFG 0x040
52 #define R92C_GPIO_IO_SEL 0x042
53 #define R92C_MAC_PINMUX_CFG 0x043
54 #define R92C_GPIO_PIN_CTRL 0x044
55 #define R92C_GPIO_IN 0x044
56 #define R92C_GPIO_OUT 0x045
57 #define R92C_GPIO_IOSEL 0x046
58 #define R92C_GPIO_MOD 0x047
59 #define R92C_GPIO_INTM 0x048
60 #define R92C_LEDCFG0 0x04c
61 #define R92C_LEDCFG1 0x04d
62 #define R92C_LEDCFG2 0x04e
63 #define R92C_LEDCFG3 0x04f
64 #define R92C_FSIMR 0x050
65 #define R92C_FSISR 0x054
66 #define R92C_HSIMR 0x058
67 #define R92C_HSISR 0x05c
68 #define R92C_MULTI_FUNC_CTRL 0x068
69 #define R92C_LDO_SWR_CTRL 0x07c
70 #define R92C_MCUFWDL 0x080
71 #define R92C_HMEBOX_EXT(idx) (0x088 + (idx) * 2)
72 #define R92C_EFUSE_ACCESS 0x0cf
73 #define R92C_BIST_SCAN 0x0d0
74 #define R92C_BIST_RPT 0x0d4
75 #define R92C_BIST_ROM_RPT 0x0d8
76 #define R92C_HPON_FSM 0x0ec
77 #define R92C_SYS_CFG 0x0f0
78 #define R92C_TYPE_ID 0x0fc
79 /* MAC General Configuration. */
81 #define R92C_MSR 0x102
82 #define R92C_PBP 0x104
83 #define R92C_TRXDMA_CTRL 0x10c
84 #define R92C_TRXFF_BNDY 0x114
85 #define R92C_TRXFF_STATUS 0x118
86 #define R92C_RXFF_PTR 0x11c
87 #define R92C_HIMR 0x120
88 #define R92C_HISR 0x124
89 #define R92C_HIMRE 0x128
90 #define R92C_HISRE 0x12c
91 #define R92C_CPWM 0x12f
92 #define R92C_FWIMR 0x130
93 #define R92C_FWISR 0x134
94 #define R92C_PKTBUF_DBG_CTRL 0x140
95 #define R92C_PKTBUF_DBG_DATA_L 0x144
96 #define R92C_PKTBUF_DBG_DATA_H 0x148
97 #define R92C_TC0_CTRL(i) (0x150 + (i) * 4)
98 #define R92C_TCUNIT_BASE 0x164
99 #define R92C_MBIST_START 0x174
100 #define R92C_MBIST_DONE 0x178
101 #define R92C_MBIST_FAIL 0x17c
102 #define R92C_C2H_EVT_MSG 0x1a0
103 #define R92C_C2H_EVT_CLEAR 0x1af
104 #define R92C_C2H_EVT_MSG_TEST 0x1b8
105 #define R92C_MCUTST_1 0x1c0
106 #define R92C_FMETHR 0x1c8
107 #define R92C_HMETFR 0x1cc
108 #define R92C_HMEBOX(idx) (0x1d0 + (idx) * 4)
109 #define R92C_LLT_INIT 0x1e0
110 #define R92C_BB_ACCESS_CTRL 0x1e8
111 #define R92C_BB_ACCESS_DATA 0x1ec
112 /* Tx DMA Configuration. */
113 #define R92C_RQPN 0x200
114 #define R92C_FIFOPAGE 0x204
115 #define R92C_TDECTRL 0x208
116 #define R92C_TXDMA_OFFSET_CHK 0x20c
117 #define R92C_TXDMA_STATUS 0x210
118 #define R92C_RQPN_NPQ 0x214
119 #define R92C_AUTO_LLT 0x224
120 /* Rx DMA Configuration. */
121 #define R92C_RXDMA_AGG_PG_TH 0x280
122 #define R92C_RXPKT_NUM 0x284
123 #define R92C_RXDMA_STATUS 0x288
124 /* Protocol Configuration. */
125 #define R92C_VOQ_INFORMATION 0x400
126 #define R92C_VIQ_INFORMATION 0x404
127 #define R92C_BEQ_INFORMATION 0x408
128 #define R92C_BKQ_INFORMATION 0x40c
129 #define R92C_MGQ_INFORMATION 0x410
130 #define R92C_HGQ_INFORMATION 0x414
131 #define R92C_BCNQ_INFORMATION 0x418
132 #define R92C_CPU_MGQ_INFORMATION 0x41c
133 #define R92C_FWHW_TXQ_CTRL 0x420
134 #define R92C_HWSEQ_CTRL 0x423
135 #define R92C_TXPKTBUF_BCNQ_BDNY 0x424
136 #define R92C_TXPKTBUF_MGQ_BDNY 0x425
137 #define R92C_SPEC_SIFS 0x428
138 #define R92C_RL 0x42a
139 #define R92C_DARFRC 0x430
140 #define R92C_RARFRC 0x438
141 #define R92C_RRSR 0x440
142 #define R92C_ARFR(i) (0x444 + (i) * 4)
143 #define R92C_AGGLEN_LMT 0x458
144 #define R92C_AMPDU_MIN_SPACE 0x45c
145 #define R92C_TXPKTBUF_WMAC_LBK_BF_HD 0x45d
146 #define R92C_FAST_EDCA_CTRL 0x460
147 #define R92C_RD_RESP_PKT_TH 0x463
148 #define R92C_INIRTS_RATE_SEL 0x480
149 #define R92C_INIDATA_RATE_SEL(macid) (0x484 + (macid))
150 #define R92C_QUEUE_CTRL 0x4c6
151 #define R92C_MAX_AGGR_NUM 0x4ca
152 #define R92C_BAR_MODE_CTRL 0x4cc
153 /* EDCA Configuration. */
154 #define R92C_EDCA_VO_PARAM 0x500
155 #define R92C_EDCA_VI_PARAM 0x504
156 #define R92C_EDCA_BE_PARAM 0x508
157 #define R92C_EDCA_BK_PARAM 0x50c
158 #define R92C_BCNTCFG 0x510
159 #define R92C_PIFS 0x512
160 #define R92C_RDG_PIFS 0x513
161 #define R92C_SIFS_CCK 0x514
162 #define R92C_SIFS_OFDM 0x516
163 #define R92C_AGGR_BREAK_TIME 0x51a
164 #define R92C_SLOT 0x51b
165 #define R92C_TX_PTCL_CTRL 0x520
166 #define R92C_TXPAUSE 0x522
167 #define R92C_DIS_TXREQ_CLR 0x523
168 #define R92C_RD_CTRL 0x524
169 #define R92C_TBTT_PROHIBIT 0x540
170 #define R92C_RD_NAV_NXT 0x544
171 #define R92C_NAV_PROT_LEN 0x546
172 #define R92C_BCN_CTRL(id) ((id) + 0x550)
173 /* WARNING: R92C_USTIME_TSF == 0x55c, not 0x551 */
174 #define R92C_MBID_NUM 0x552
175 #define R92C_DUAL_TSF_RST 0x553
176 #define R92C_BCN_INTERVAL(id) (0x554 + (id) * 2)
177 #define R92C_DRVERLYINT 0x558
178 #define R92C_BCNDMATIM 0x559
179 #define R92C_ATIMWND 0x55a
180 #define R92C_USTIME_TSF 0x55c
181 #define R92C_BCN_MAX_ERR 0x55d
182 #define R92C_RXTSF_OFFSET_CCK 0x55e
183 #define R92C_RXTSF_OFFSET_OFDM 0x55f
184 #define R92C_TSFTR(i) (0x560 + (i) * 8)
185 #define R92C_PSTIMER 0x580
186 #define R92C_TIMER0 0x584
187 #define R92C_TIMER1 0x588
188 #define R92C_ACMHWCTRL 0x5c0
189 #define R92C_ACMRSTCTRL 0x5c1
190 #define R92C_ACMAVG 0x5c2
191 #define R92C_VO_ADMTIME 0x5c4
192 #define R92C_VI_ADMTIME 0x5c6
193 #define R92C_BE_ADMTIME 0x5c8
194 #define R92C_EDCA_RANDOM_GEN 0x5cc
195 #define R92C_SCH_TXCMD 0x5d0
196 /* WMAC Configuration. */
197 #define R92C_APSD_CTRL 0x600
198 #define R92C_BWOPMODE 0x603
199 #define R92C_TCR 0x604
200 #define R92C_RCR 0x608
201 #define R92C_RX_PKT_LIMIT 0x60c
202 #define R92C_RX_DRVINFO_SZ 0x60f
203 #define R92C_MACID0 0x610
204 #define R92C_BSSID0 0x618
205 #define R92C_MAR 0x620
206 #define R92C_USTIME_EDCA 0x638
207 #define R92C_MAC_SPEC_SIFS 0x63a
208 #define R92C_R2T_SIFS 0x63c
209 #define R92C_T2T_SIFS 0x63e
210 #define R92C_ACKTO 0x640
211 #define R92C_NAV_UPPER 0x652
212 #define R92C_WMAC_TRXPTCL_CTL 0x668
213 #define R92C_CAMCMD 0x670
214 #define R92C_CAMWRITE 0x674
215 #define R92C_CAMREAD 0x678
216 #define R92C_CAMDBG 0x67c
217 #define R92C_SECCFG 0x680
218 #define R92C_RXFLTMAP0 0x6a0
219 #define R92C_RXFLTMAP1 0x6a2
220 #define R92C_RXFLTMAP2 0x6a4
221 #define R92C_BCN_PSR_RPT 0x6a8
222 #define R92C_MACID1 0x700
223 #define R92C_BSSID1 0x708
226 #define R92C_MACID(id) ((id) == 0 ? R92C_MACID0 : R92C_MACID1)
227 #define R92C_BSSID(id) ((id) == 0 ? R92C_BSSID0 : R92C_BSSID1)
229 /* Bits for R92C_SYS_ISO_CTRL. */
230 #define R92C_SYS_ISO_CTRL_MD2PP 0x0001
231 #define R92C_SYS_ISO_CTRL_UA2USB 0x0002
232 #define R92C_SYS_ISO_CTRL_UD2CORE 0x0004
233 #define R92C_SYS_ISO_CTRL_PA2PCIE 0x0008
234 #define R92C_SYS_ISO_CTRL_PD2CORE 0x0010
235 #define R92C_SYS_ISO_CTRL_IP2MAC 0x0020
236 #define R92C_SYS_ISO_CTRL_DIOP 0x0040
237 #define R92C_SYS_ISO_CTRL_DIOE 0x0080
238 #define R92C_SYS_ISO_CTRL_EB2CORE 0x0100
239 #define R92C_SYS_ISO_CTRL_DIOR 0x0200
240 #define R92C_SYS_ISO_CTRL_PWC_EV25V 0x4000
241 #define R92C_SYS_ISO_CTRL_PWC_EV12V 0x8000
243 /* Bits for R92C_SYS_FUNC_EN. */
244 #define R92C_SYS_FUNC_EN_BBRSTB 0x0001
245 #define R92C_SYS_FUNC_EN_BB_GLB_RST 0x0002
246 #define R92C_SYS_FUNC_EN_USBA 0x0004
247 #define R92C_SYS_FUNC_EN_UPLL 0x0008
248 #define R92C_SYS_FUNC_EN_USBD 0x0010
249 #define R92C_SYS_FUNC_EN_DIO_PCIE 0x0020
250 #define R92C_SYS_FUNC_EN_PCIEA 0x0040
251 #define R92C_SYS_FUNC_EN_PPLL 0x0080
252 #define R92C_SYS_FUNC_EN_PCIED 0x0100
253 #define R92C_SYS_FUNC_EN_DIOE 0x0200
254 #define R92C_SYS_FUNC_EN_CPUEN 0x0400
255 #define R92C_SYS_FUNC_EN_DCORE 0x0800
256 #define R92C_SYS_FUNC_EN_ELDR 0x1000
257 #define R92C_SYS_FUNC_EN_DIO_RF 0x2000
258 #define R92C_SYS_FUNC_EN_HWPDN 0x4000
259 #define R92C_SYS_FUNC_EN_MREGEN 0x8000
261 /* Bits for R92C_APS_FSMCO. */
262 #define R92C_APS_FSMCO_PFM_LDALL 0x00000001
263 #define R92C_APS_FSMCO_PFM_ALDN 0x00000002
264 #define R92C_APS_FSMCO_PFM_LDKP 0x00000004
265 #define R92C_APS_FSMCO_PFM_WOWL 0x00000008
266 #define R92C_APS_FSMCO_PDN_EN 0x00000010
267 #define R92C_APS_FSMCO_PDN_PL 0x00000020
268 #define R92C_APS_FSMCO_APFM_ONMAC 0x00000100
269 #define R92C_APS_FSMCO_APFM_OFF 0x00000200
270 #define R92C_APS_FSMCO_APFM_RSM 0x00000400
271 #define R92C_APS_FSMCO_AFSM_HSUS 0x00000800
272 #define R92C_APS_FSMCO_AFSM_PCIE 0x00001000
273 #define R92C_APS_FSMCO_APDM_MAC 0x00002000
274 #define R92C_APS_FSMCO_APDM_HOST 0x00004000
275 #define R92C_APS_FSMCO_APDM_HPDN 0x00008000
276 #define R92C_APS_FSMCO_RDY_MACON 0x00010000
277 #define R92C_APS_FSMCO_SUS_HOST 0x00020000
278 #define R92C_APS_FSMCO_ROP_ALD 0x00100000
279 #define R92C_APS_FSMCO_ROP_PWR 0x00200000
280 #define R92C_APS_FSMCO_ROP_SPS 0x00400000
281 #define R92C_APS_FSMCO_SOP_MRST 0x02000000
282 #define R92C_APS_FSMCO_SOP_FUSE 0x04000000
283 #define R92C_APS_FSMCO_SOP_ABG 0x08000000
284 #define R92C_APS_FSMCO_SOP_AMB 0x10000000
285 #define R92C_APS_FSMCO_SOP_RCK 0x20000000
286 #define R92C_APS_FSMCO_SOP_A8M 0x40000000
287 #define R92C_APS_FSMCO_XOP_BTCK 0x80000000
289 /* Bits for R92C_SYS_CLKR. */
290 #define R92C_SYS_CLKR_ANAD16V_EN 0x00000001
291 #define R92C_SYS_CLKR_ANA8M 0x00000002
292 #define R92C_SYS_CLKR_MACSLP 0x00000010
293 #define R92C_SYS_CLKR_LOADER_EN 0x00000020
294 #define R92C_SYS_CLKR_80M_SSC_DIS 0x00000080
295 #define R92C_SYS_CLKR_80M_SSC_EN_HO 0x00000100
296 #define R92C_SYS_CLKR_PHY_SSC_RSTB 0x00000200
297 #define R92C_SYS_CLKR_SEC_EN 0x00000400
298 #define R92C_SYS_CLKR_MAC_EN 0x00000800
299 #define R92C_SYS_CLKR_SYS_EN 0x00001000
300 #define R92C_SYS_CLKR_RING_EN 0x00002000
302 /* Bits for R92C_RSV_CTRL. */
303 #define R92C_RSV_CTRL_WLOCK_ALL 0x01
304 #define R92C_RSV_CTRL_WLOCK_00 0x02
305 #define R92C_RSV_CTRL_WLOCK_04 0x04
306 #define R92C_RSV_CTRL_WLOCK_08 0x08
307 #define R92C_RSV_CTRL_WLOCK_40 0x10
308 #define R92C_RSV_CTRL_R_DIS_PRST_0 0x20
309 #define R92C_RSV_CTRL_R_DIS_PRST_1 0x40
310 #define R92C_RSV_CTRL_LOCK_ALL_EN 0x80
312 /* Bits for R92C_RF_CTRL. */
313 #define R92C_RF_CTRL_EN 0x01
314 #define R92C_RF_CTRL_RSTB 0x02
315 #define R92C_RF_CTRL_SDMRSTB 0x04
317 /* Bits for R92C_LDOA15_CTRL. */
318 #define R92C_LDOA15_CTRL_EN 0x01
319 #define R92C_LDOA15_CTRL_STBY 0x02
320 #define R92C_LDOA15_CTRL_OBUF 0x04
321 #define R92C_LDOA15_CTRL_REG_VOS 0x08
323 /* Bits for R92C_LDOV12D_CTRL. */
324 #define R92C_LDOV12D_CTRL_LDV12_EN 0x01
326 /* Bits for R92C_LPLDO_CTRL. */
327 #define R92C_LPLDO_CTRL_SLEEP 0x10
329 /* Bits for R92C_AFE_XTAL_CTRL. */
330 #define R92C_AFE_XTAL_CTRL_ADDR_M 0x007ff800
331 #define R92C_AFE_XTAL_CTRL_ADDR_S 11
333 /* Bits for R92C_AFE_PLL_CTRL. */
334 #define R92C_AFE_PLL_CTRL_EN 0x0001
335 #define R92C_AFE_PLL_CTRL_320_EN 0x0002
336 #define R92C_AFE_PLL_CTRL_FREF_SEL 0x0004
337 #define R92C_AFE_PLL_CTRL_EDGE_SEL 0x0008
338 #define R92C_AFE_PLL_CTRL_WDOGB 0x0010
339 #define R92C_AFE_PLL_CTRL_LPFEN 0x0020
341 /* Bits for R92C_EFUSE_CTRL. */
342 #define R92C_EFUSE_CTRL_DATA_M 0x000000ff
343 #define R92C_EFUSE_CTRL_DATA_S 0
344 #define R92C_EFUSE_CTRL_ADDR_M 0x0003ff00
345 #define R92C_EFUSE_CTRL_ADDR_S 8
346 #define R92C_EFUSE_CTRL_VALID 0x80000000
348 /* Bits for R92C_GPIO_MUXCFG. */
349 #define R92C_GPIO_MUXCFG_ENBT 0x0020
351 /* Bits for R92C_LEDCFG0. */
352 #define R92C_LEDCFG0_DIS 0x08
354 /* Bits for R92C_LEDCFG1. */
355 #define R92C_LEDCFG1_DIS 0x80
357 /* Bits for R92C_MULTI_FUNC_CTRL. */
358 #define R92C_MULTI_BT_FUNC_EN 0x00040000
360 /* Bits for R92C_MCUFWDL. */
361 #define R92C_MCUFWDL_EN 0x00000001
362 #define R92C_MCUFWDL_RDY 0x00000002
363 #define R92C_MCUFWDL_CHKSUM_RPT 0x00000004
364 #define R92C_MCUFWDL_MACINI_RDY 0x00000008
365 #define R92C_MCUFWDL_BBINI_RDY 0x00000010
366 #define R92C_MCUFWDL_RFINI_RDY 0x00000020
367 #define R92C_MCUFWDL_WINTINI_RDY 0x00000040
368 #define R92C_MCUFWDL_RAM_DL_SEL 0x00000080 /* 1: RAM, 0: ROM */
369 #define R92C_MCUFWDL_PAGE_M 0x00070000
370 #define R92C_MCUFWDL_PAGE_S 16
371 #define R92C_MCUFWDL_ROM_DLEN 0x00080000
372 #define R92C_MCUFWDL_CPRST 0x00800000
374 /* Bits for R92C_EFUSE_ACCESS. */
375 #define R92C_EFUSE_ACCESS_OFF 0x00
376 #define R92C_EFUSE_ACCESS_ON 0x69
378 /* Bits for R92C_HPON_FSM. */
379 #define R92C_HPON_FSM_CHIP_BONDING_ID_S 22
380 #define R92C_HPON_FSM_CHIP_BONDING_ID_M 0x00c00000
381 #define R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R 1
383 /* Bits for R92C_SYS_CFG. */
384 #define R92C_SYS_CFG_XCLK_VLD 0x00000001
385 #define R92C_SYS_CFG_ACLK_VLD 0x00000002
386 #define R92C_SYS_CFG_UCLK_VLD 0x00000004
387 #define R92C_SYS_CFG_PCLK_VLD 0x00000008
388 #define R92C_SYS_CFG_PCIRSTB 0x00000010
389 #define R92C_SYS_CFG_V15_VLD 0x00000020
390 #define R92C_SYS_CFG_TRP_B15V_EN 0x00000080
391 #define R92C_SYS_CFG_SIC_IDLE 0x00000100
392 #define R92C_SYS_CFG_BD_MAC2 0x00000200
393 #define R92C_SYS_CFG_BD_MAC1 0x00000400
394 #define R92C_SYS_CFG_IC_MACPHY_MODE 0x00000800
395 #define R92C_SYS_CFG_CHIP_VER_RTL_M 0x0000f000
396 #define R92C_SYS_CFG_CHIP_VER_RTL_S 12
397 #define R92C_SYS_CFG_BT_FUNC 0x00010000
398 #define R92C_SYS_CFG_VENDOR_UMC 0x00080000
399 #define R92C_SYS_CFG_PAD_HWPD_IDN 0x00400000
400 #define R92C_SYS_CFG_TRP_VAUX_EN 0x00800000
401 #define R92C_SYS_CFG_TRP_BT_EN 0x01000000
402 #define R92C_SYS_CFG_BD_PKG_SEL 0x02000000
403 #define R92C_SYS_CFG_BD_HCI_SEL 0x04000000
404 #define R92C_SYS_CFG_TYPE_92C 0x08000000
406 /* Bits for R92C_CR. */
407 #define R92C_CR_HCI_TXDMA_EN 0x0001
408 #define R92C_CR_HCI_RXDMA_EN 0x0002
409 #define R92C_CR_TXDMA_EN 0x0004
410 #define R92C_CR_RXDMA_EN 0x0008
411 #define R92C_CR_PROTOCOL_EN 0x0010
412 #define R92C_CR_SCHEDULE_EN 0x0020
413 #define R92C_CR_MACTXEN 0x0040
414 #define R92C_CR_MACRXEN 0x0080
415 #define R92C_CR_ENSWBCN 0x0100
416 #define R92C_CR_ENSEC 0x0200
417 #define R92C_CR_CALTMR_EN 0x0400
419 /* Bits for R92C_MSR. */
420 #define R92C_MSR_NOLINK 0x00
421 #define R92C_MSR_ADHOC 0x01
422 #define R92C_MSR_INFRA 0x02
423 #define R92C_MSR_AP 0x03
424 #define R92C_MSR_MASK (R92C_MSR_AP)
426 /* Bits for R92C_PBP. */
427 #define R92C_PBP_PSRX_M 0x0f
428 #define R92C_PBP_PSRX_S 0
429 #define R92C_PBP_PSTX_M 0xf0
430 #define R92C_PBP_PSTX_S 4
431 #define R92C_PBP_64 0
432 #define R92C_PBP_128 1
433 #define R92C_PBP_256 2
434 #define R92C_PBP_512 3
435 #define R92C_PBP_1024 4
437 /* Bits for R92C_TRXDMA_CTRL. */
438 #define R92C_TRXDMA_CTRL_RX_SHIFT_EN 0x0002
439 #define R92C_TRXDMA_CTRL_RXDMA_AGG_EN 0x0004
440 #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_M 0x0030
441 #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_S 4
442 #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_M 0x00c0
443 #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_S 6
444 #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_M 0x0300
445 #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_S 8
446 #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_M 0x0c00
447 #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_S 10
448 #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_M 0x3000
449 #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_S 12
450 #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_M 0xc000
451 #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_S 14
452 #define R92C_TRXDMA_CTRL_QUEUE_LOW 1
453 #define R92C_TRXDMA_CTRL_QUEUE_NORMAL 2
454 #define R92C_TRXDMA_CTRL_QUEUE_HIGH 3
455 #define R92C_TRXDMA_CTRL_QMAP_M 0xfff0
457 #define R92C_TRXDMA_CTRL_QMAP_3EP 0xf5b0
458 #define R92C_TRXDMA_CTRL_QMAP_HQ_LQ 0xf5f0
459 #define R92C_TRXDMA_CTRL_QMAP_HQ_NQ 0xfaf0
460 #define R92C_TRXDMA_CTRL_QMAP_LQ 0x5550
461 #define R92C_TRXDMA_CTRL_QMAP_NQ 0xaaa0
462 #define R92C_TRXDMA_CTRL_QMAP_HQ 0xfff0
464 /* Bits for R92C_C2H_EVT_CLEAR. */
465 #define R92C_C2H_EVT_HOST_CLOSE 0x00
466 #define R92C_C2H_EVT_FW_CLOSE 0xff
468 /* Bits for R92C_LLT_INIT. */
469 #define R92C_LLT_INIT_DATA_M 0x000000ff
470 #define R92C_LLT_INIT_DATA_S 0
471 #define R92C_LLT_INIT_ADDR_M 0x0000ff00
472 #define R92C_LLT_INIT_ADDR_S 8
473 #define R92C_LLT_INIT_OP_M 0xc0000000
474 #define R92C_LLT_INIT_OP_S 30
475 #define R92C_LLT_INIT_OP_NO_ACTIVE 0
476 #define R92C_LLT_INIT_OP_WRITE 1
478 /* Bits for R92C_RQPN. */
479 #define R92C_RQPN_HPQ_M 0x000000ff
480 #define R92C_RQPN_HPQ_S 0
481 #define R92C_RQPN_LPQ_M 0x0000ff00
482 #define R92C_RQPN_LPQ_S 8
483 #define R92C_RQPN_PUBQ_M 0x00ff0000
484 #define R92C_RQPN_PUBQ_S 16
485 #define R92C_RQPN_LD 0x80000000
487 /* Bits for R92C_TDECTRL. */
488 #define R92C_TDECTRL_BLK_DESC_NUM_M 0x000000f0
489 #define R92C_TDECTRL_BLK_DESC_NUM_S 4
490 #define R92C_TDECTRL_BCN_VALID 0x00010000
492 /* Bits for R92C_TXDMA_OFFSET_CHK. */
493 #define R92C_TXDMA_OFFSET_DROP_DATA_EN 0x00000200
495 /* Bits for R92C_AUTO_LLT. */
496 #define R92C_AUTO_LLT_INIT 0x00010000
498 /* Bits for R92C_FWHW_TXQ_CTRL. */
499 #define R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW 0x80
500 #define R92C_FWHW_TXQ_CTRL_REAL_BEACON 0x400000
502 /* Bits for R92C_SPEC_SIFS. */
503 #define R92C_SPEC_SIFS_CCK_M 0x00ff
504 #define R92C_SPEC_SIFS_CCK_S 0
505 #define R92C_SPEC_SIFS_OFDM_M 0xff00
506 #define R92C_SPEC_SIFS_OFDM_S 8
508 /* Bits for R92C_RL. */
509 #define R92C_RL_LRL_M 0x003f
510 #define R92C_RL_LRL_S 0
511 #define R92C_RL_SRL_M 0x3f00
512 #define R92C_RL_SRL_S 8
514 /* Size of R92C_DARFRC. */
515 #define R92C_DARFRC_SIZE 8
517 /* Bits for R92C_RRSR. */
518 #define R92C_RRSR_RATE_BITMAP_M 0x000fffff
519 #define R92C_RRSR_RATE_BITMAP_S 0
520 #define R92C_RRSR_RATE_CCK_ONLY_1M 0xffff1
521 #define R92C_RRSR_RATE_ALL 0xfffff
522 #define R92C_RRSR_RSC_LOWSUBCHNL 0x00200000
523 #define R92C_RRSR_RSC_UPSUBCHNL 0x00400000
524 #define R92C_RRSR_SHORT 0x00800000
526 /* Bits for R92C_EDCA_XX_PARAM. */
527 #define R92C_EDCA_PARAM_AIFS_M 0x000000ff
528 #define R92C_EDCA_PARAM_AIFS_S 0
529 #define R92C_EDCA_PARAM_ECWMIN_M 0x00000f00
530 #define R92C_EDCA_PARAM_ECWMIN_S 8
531 #define R92C_EDCA_PARAM_ECWMAX_M 0x0000f000
532 #define R92C_EDCA_PARAM_ECWMAX_S 12
533 #define R92C_EDCA_PARAM_TXOP_M 0xffff0000
534 #define R92C_EDCA_PARAM_TXOP_S 16
536 /* Bits for R92C_HWSEQ_CTRL / R92C_TXPAUSE. */
537 #define R92C_TX_QUEUE_VO 0x01
538 #define R92C_TX_QUEUE_VI 0x02
539 #define R92C_TX_QUEUE_BE 0x04
540 #define R92C_TX_QUEUE_BK 0x08
541 #define R92C_TX_QUEUE_MGT 0x10
542 #define R92C_TX_QUEUE_HIGH 0x20
543 #define R92C_TX_QUEUE_BCN 0x40
546 #define R92C_TX_QUEUE_AC \
547 (R92C_TX_QUEUE_VO | R92C_TX_QUEUE_VI | \
548 R92C_TX_QUEUE_BE | R92C_TX_QUEUE_BK)
550 #define R92C_TX_QUEUE_ALL \
551 (R92C_TX_QUEUE_AC | R92C_TX_QUEUE_MGT | \
552 R92C_TX_QUEUE_HIGH | R92C_TX_QUEUE_BCN | 0x80) /* XXX */
554 /* Bits for R92C_BCN_CTRL. */
555 #define R92C_BCN_CTRL_EN_MBSSID 0x02
556 #define R92C_BCN_CTRL_TXBCN_RPT 0x04
557 #define R92C_BCN_CTRL_EN_BCN 0x08
558 #define R92C_BCN_CTRL_DIS_TSF_UDT0 0x10
560 /* Bits for R92C_DUAL_TSF_RST. */
561 #define R92C_DUAL_TSF_RESET(id) (0x01 << (id))
562 #define R92C_DUAL_TSF_RST_TXOK 0x20
564 /* Bits for R92C_ACMHWCTRL. */
565 #define R92C_ACMHWCTRL_EN 0x01
566 #define R92C_ACMHWCTRL_BE 0x02
567 #define R92C_ACMHWCTRL_VI 0x04
568 #define R92C_ACMHWCTRL_VO 0x08
569 #define R92C_ACMHWCTRL_ACM_MASK 0x0f
571 /* Bits for R92C_APSD_CTRL. */
572 #define R92C_APSD_CTRL_OFF 0x40
573 #define R92C_APSD_CTRL_OFF_STATUS 0x80
575 /* Bits for R92C_BWOPMODE. */
576 #define R92C_BWOPMODE_11J 0x01
577 #define R92C_BWOPMODE_5G 0x02
578 #define R92C_BWOPMODE_20MHZ 0x04
580 /* Bits for R92C_TCR. */
581 #define R92C_TCR_TSFRST 0x00000001
582 #define R92C_TCR_DIS_GCLK 0x00000002
583 #define R92C_TCR_PAD_SEL 0x00000004
584 #define R92C_TCR_PWR_ST 0x00000040
585 #define R92C_TCR_PWRBIT_OW_EN 0x00000080
586 #define R92C_TCR_ACRC 0x00000100
587 #define R92C_TCR_CFENDFORM 0x00000200
588 #define R92C_TCR_ICV 0x00000400
590 /* Bits for R92C_RCR. */
591 #define R92C_RCR_AAP 0x00000001
592 #define R92C_RCR_APM 0x00000002
593 #define R92C_RCR_AM 0x00000004
594 #define R92C_RCR_AB 0x00000008
595 #define R92C_RCR_ADD3 0x00000010
596 #define R92C_RCR_APWRMGT 0x00000020
597 #define R92C_RCR_CBSSID_DATA 0x00000040
598 #define R92C_RCR_CBSSID_BCN 0x00000080
599 #define R92C_RCR_ACRC32 0x00000100
600 #define R92C_RCR_AICV 0x00000200
601 #define R92C_RCR_ADF 0x00000800
602 #define R92C_RCR_ACF 0x00001000
603 #define R92C_RCR_AMF 0x00002000
604 #define R92C_RCR_HTC_LOC_CTRL 0x00004000
605 #define R92C_RCR_MFBEN 0x00400000
606 #define R92C_RCR_LSIGEN 0x00800000
607 #define R92C_RCR_ENMBID 0x01000000
608 #define R92C_RCR_APP_BA_SSN 0x08000000
609 #define R92C_RCR_APP_PHYSTS 0x10000000
610 #define R92C_RCR_APP_ICV 0x20000000
611 #define R92C_RCR_APP_MIC 0x40000000
612 #define R92C_RCR_APPFCS 0x80000000
614 /* Bits for R92C_RX_DRVINFO_SZ. */
615 /* XXX other values will not work */
616 #define R92C_RX_DRVINFO_SZ_DEF ((RTWN_PHY_STATUS_SIZE) / 8)
618 /* Bits for R92C_WMAC_TRXPTCL_CTL. */
619 #define R92C_WMAC_TRXPTCL_SHPRE 0x00020000
621 /* Bits for R92C_CAMCMD. */
622 #define R92C_CAMCMD_ADDR_M 0x0000ffff
623 #define R92C_CAMCMD_ADDR_S 0
624 #define R92C_CAMCMD_WRITE 0x00010000
625 #define R92C_CAMCMD_CLR 0x40000000
626 #define R92C_CAMCMD_POLLING 0x80000000
632 #define R92C_CAM_CTL0(entry) ((entry) * 8 + 0)
633 #define R92C_CAM_CTL1(entry) ((entry) * 8 + 1)
634 #define R92C_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i))
635 #define R92C_CAM_CTL6(entry) ((entry) * 8 + 6)
636 #define R92C_CAM_CTL7(entry) ((entry) * 8 + 7)
638 /* Bits for R92C_CAM_CTL0(i). */
639 #define R92C_CAM_KEYID_M 0x00000003
640 #define R92C_CAM_KEYID_S 0
641 #define R92C_CAM_ALGO_M 0x0000001c
642 #define R92C_CAM_ALGO_S 2
643 #define R92C_CAM_ALGO_NONE 0
644 #define R92C_CAM_ALGO_WEP40 1
645 #define R92C_CAM_ALGO_TKIP 2
646 #define R92C_CAM_ALGO_AES 4
647 #define R92C_CAM_ALGO_WEP104 5
648 #define R92C_CAM_VALID 0x00008000
649 #define R92C_CAM_MACLO_M 0xffff0000
650 #define R92C_CAM_MACLO_S 16
652 /* Bits for R92C_SECCFG. */
653 #define R92C_SECCFG_TXUCKEY_DEF 0x0001
654 #define R92C_SECCFG_RXUCKEY_DEF 0x0002
655 #define R92C_SECCFG_TXENC_ENA 0x0004
656 #define R92C_SECCFG_RXDEC_ENA 0x0008
657 #define R92C_SECCFG_CMP_A2 0x0010
658 #define R92C_SECCFG_MC_SRCH_DIS 0x0020
659 #define R92C_SECCFG_TXBCKEY_DEF 0x0040
660 #define R92C_SECCFG_RXBCKEY_DEF 0x0080
662 /* Bits for R92C_RXFLTMAP*. */
663 #define R92C_RXFLTMAP_SUBTYPE(subtype) \
664 (1 << ((subtype) >> IEEE80211_FC0_SUBTYPE_SHIFT))
668 * Baseband registers.
670 #define R92C_FPGA0_RFMOD 0x800
671 #define R92C_FPGA0_TXINFO 0x804
672 #define R92C_HSSI_PARAM1(chain) (0x820 + (chain) * 8)
673 #define R92C_HSSI_PARAM2(chain) (0x824 + (chain) * 8)
674 #define R92C_TXAGC_RATE18_06(i) (((i) == 0) ? 0xe00 : 0x830)
675 #define R92C_TXAGC_RATE54_24(i) (((i) == 0) ? 0xe04 : 0x834)
676 #define R92C_TXAGC_A_CCK1_MCS32 0xe08
677 #define R92C_TXAGC_B_CCK1_55_MCS32 0x838
678 #define R92C_TXAGC_B_CCK11_A_CCK2_11 0x86c
679 #define R92C_TXAGC_MCS03_MCS00(i) (((i) == 0) ? 0xe10 : 0x83c)
680 #define R92C_TXAGC_MCS07_MCS04(i) (((i) == 0) ? 0xe14 : 0x848)
681 #define R92C_TXAGC_MCS11_MCS08(i) (((i) == 0) ? 0xe18 : 0x84c)
682 #define R92C_TXAGC_MCS15_MCS12(i) (((i) == 0) ? 0xe1c : 0x868)
683 #define R92C_LSSI_PARAM(chain) (0x840 + (chain) * 4)
684 #define R92C_FPGA0_RFIFACEOE(chain) (0x860 + (chain) * 4)
685 #define R92C_FPGA0_RFIFACESW(idx) (0x870 + (idx) * 4)
686 #define R92C_FPGA0_RFPARAM(idx) (0x878 + (idx) * 4)
687 #define R92C_FPGA0_ANAPARAM2 0x884
688 #define R92C_LSSI_READBACK(chain) (0x8a0 + (chain) * 4)
689 #define R92C_HSPI_READBACK(chain) (0x8b8 + (chain) * 4)
690 #define R92C_FPGA1_RFMOD 0x900
691 #define R92C_FPGA1_TXINFO 0x90c
692 #define R92C_CCK0_SYSTEM 0xa00
693 #define R92C_CCK0_AFESETTING 0xa04
694 #define R92C_OFDM0_TRXPATHENA 0xc04
695 #define R92C_OFDM0_TRMUXPAR 0xc08
696 #define R92C_OFDM0_RXIQIMBALANCE(chain) (0xc14 + (chain) * 8)
697 #define R92C_OFDM0_ECCATHRESHOLD 0xc4c
698 #define R92C_OFDM0_AGCCORE1(chain) (0xc50 + (chain) * 8)
699 #define R92C_OFDM0_AGCPARAM1 0xc70
700 #define R92C_OFDM0_AGCRSSITABLE 0xc78
701 #define R92C_OFDM0_TXIQIMBALANCE(chain) (0xc80 + (chain) * 8)
702 #define R92C_OFDM0_TXAFE(chain) (0xc94 + (chain) * 8)
703 #define R92C_OFDM0_RXIQEXTANTA 0xca0
704 #define R92C_OFDM0_TXPSEUDONOISEWGT 0xce4
705 #define R92C_OFDM1_LSTF 0xd00
707 /* Bits for R92C_FPGA[01]_RFMOD. */
708 #define R92C_RFMOD_40MHZ 0x00000001
709 #define R92C_RFMOD_JAPAN 0x00000002
710 #define R92C_RFMOD_CCK_TXSC 0x00000030
711 #define R92C_RFMOD_CCK_EN 0x01000000
712 #define R92C_RFMOD_OFDM_EN 0x02000000
714 /* Bits for R92C_HSSI_PARAM1(i). */
715 #define R92C_HSSI_PARAM1_PI 0x00000100
717 /* Bits for R92C_HSSI_PARAM2(i). */
718 #define R92C_HSSI_PARAM2_CCK_HIPWR 0x00000200
719 #define R92C_HSSI_PARAM2_ADDR_LENGTH 0x00000400
720 #define R92C_HSSI_PARAM2_DATA_LENGTH 0x00000800
721 #define R92C_HSSI_PARAM2_READ_ADDR_M 0x7f800000
722 #define R92C_HSSI_PARAM2_READ_ADDR_S 23
723 #define R92C_HSSI_PARAM2_READ_EDGE 0x80000000
725 /* Bits for R92C_TXAGC_A_CCK1_MCS32. */
726 #define R92C_TXAGC_A_CCK1_M 0x0000ff00
727 #define R92C_TXAGC_A_CCK1_S 8
729 /* Bits for R92C_TXAGC_B_CCK11_A_CCK2_11. */
730 #define R92C_TXAGC_B_CCK11_M 0x000000ff
731 #define R92C_TXAGC_B_CCK11_S 0
732 #define R92C_TXAGC_A_CCK2_M 0x0000ff00
733 #define R92C_TXAGC_A_CCK2_S 8
734 #define R92C_TXAGC_A_CCK55_M 0x00ff0000
735 #define R92C_TXAGC_A_CCK55_S 16
736 #define R92C_TXAGC_A_CCK11_M 0xff000000
737 #define R92C_TXAGC_A_CCK11_S 24
739 /* Bits for R92C_TXAGC_B_CCK1_55_MCS32. */
740 #define R92C_TXAGC_B_CCK1_M 0x0000ff00
741 #define R92C_TXAGC_B_CCK1_S 8
742 #define R92C_TXAGC_B_CCK2_M 0x00ff0000
743 #define R92C_TXAGC_B_CCK2_S 16
744 #define R92C_TXAGC_B_CCK55_M 0xff000000
745 #define R92C_TXAGC_B_CCK55_S 24
747 /* Bits for R92C_TXAGC_RATE18_06(x). */
748 #define R92C_TXAGC_RATE06_M 0x000000ff
749 #define R92C_TXAGC_RATE06_S 0
750 #define R92C_TXAGC_RATE09_M 0x0000ff00
751 #define R92C_TXAGC_RATE09_S 8
752 #define R92C_TXAGC_RATE12_M 0x00ff0000
753 #define R92C_TXAGC_RATE12_S 16
754 #define R92C_TXAGC_RATE18_M 0xff000000
755 #define R92C_TXAGC_RATE18_S 24
757 /* Bits for R92C_TXAGC_RATE54_24(x). */
758 #define R92C_TXAGC_RATE24_M 0x000000ff
759 #define R92C_TXAGC_RATE24_S 0
760 #define R92C_TXAGC_RATE36_M 0x0000ff00
761 #define R92C_TXAGC_RATE36_S 8
762 #define R92C_TXAGC_RATE48_M 0x00ff0000
763 #define R92C_TXAGC_RATE48_S 16
764 #define R92C_TXAGC_RATE54_M 0xff000000
765 #define R92C_TXAGC_RATE54_S 24
767 /* Bits for R92C_TXAGC_MCS03_MCS00(x). */
768 #define R92C_TXAGC_MCS00_M 0x000000ff
769 #define R92C_TXAGC_MCS00_S 0
770 #define R92C_TXAGC_MCS01_M 0x0000ff00
771 #define R92C_TXAGC_MCS01_S 8
772 #define R92C_TXAGC_MCS02_M 0x00ff0000
773 #define R92C_TXAGC_MCS02_S 16
774 #define R92C_TXAGC_MCS03_M 0xff000000
775 #define R92C_TXAGC_MCS03_S 24
777 /* Bits for R92C_TXAGC_MCS07_MCS04(x). */
778 #define R92C_TXAGC_MCS04_M 0x000000ff
779 #define R92C_TXAGC_MCS04_S 0
780 #define R92C_TXAGC_MCS05_M 0x0000ff00
781 #define R92C_TXAGC_MCS05_S 8
782 #define R92C_TXAGC_MCS06_M 0x00ff0000
783 #define R92C_TXAGC_MCS06_S 16
784 #define R92C_TXAGC_MCS07_M 0xff000000
785 #define R92C_TXAGC_MCS07_S 24
787 /* Bits for R92C_TXAGC_MCS11_MCS08(x). */
788 #define R92C_TXAGC_MCS08_M 0x000000ff
789 #define R92C_TXAGC_MCS08_S 0
790 #define R92C_TXAGC_MCS09_M 0x0000ff00
791 #define R92C_TXAGC_MCS09_S 8
792 #define R92C_TXAGC_MCS10_M 0x00ff0000
793 #define R92C_TXAGC_MCS10_S 16
794 #define R92C_TXAGC_MCS11_M 0xff000000
795 #define R92C_TXAGC_MCS11_S 24
797 /* Bits for R92C_TXAGC_MCS15_MCS12(x). */
798 #define R92C_TXAGC_MCS12_M 0x000000ff
799 #define R92C_TXAGC_MCS12_S 0
800 #define R92C_TXAGC_MCS13_M 0x0000ff00
801 #define R92C_TXAGC_MCS13_S 8
802 #define R92C_TXAGC_MCS14_M 0x00ff0000
803 #define R92C_TXAGC_MCS14_S 16
804 #define R92C_TXAGC_MCS15_M 0xff000000
805 #define R92C_TXAGC_MCS15_S 24
807 /* Bits for R92C_LSSI_PARAM(i). */
808 #define R92C_LSSI_PARAM_DATA_M 0x000fffff
809 #define R92C_LSSI_PARAM_DATA_S 0
810 #define R92C_LSSI_PARAM_ADDR_M 0x03f00000
811 #define R92C_LSSI_PARAM_ADDR_S 20
813 /* Bits for R92C_FPGA0_RFIFACEOE(0). */
814 #define R92C_FPGA0_RFIFACEOE0_ANT_M 0x00000300
815 #define R92C_FPGA0_RFIFACEOE0_ANT_S 8
817 /* Bits for R92C_FPGA0_ANAPARAM2. */
818 #define R92C_FPGA0_ANAPARAM2_CBW20 0x00000400
820 /* Bits for R92C_LSSI_READBACK(i). */
821 #define R92C_LSSI_READBACK_DATA_M 0x000fffff
822 #define R92C_LSSI_READBACK_DATA_S 0
824 /* Bits for R92C_CCK0_SYSTEM. */
825 #define R92C_CCK0_SYSTEM_CCK_SIDEBAND 0x00000010
827 /* Bits for R92C_OFDM0_AGCCORE1(i). */
828 #define R92C_OFDM0_AGCCORE1_GAIN_M 0x0000007f
829 #define R92C_OFDM0_AGCCORE1_GAIN_S 0
833 * RF (6052) registers.
835 #define R92C_RF_AC 0x00
836 #define R92C_RF_IQADJ_G(i) (0x01 + (i))
837 #define R92C_RF_POW_TRSW 0x05
838 #define R92C_RF_GAIN_RX 0x06
839 #define R92C_RF_GAIN_TX 0x07
840 #define R92C_RF_TXM_IDAC 0x08
841 #define R92C_RF_BS_IQGEN 0x0f
842 #define R92C_RF_MODE1 0x10
843 #define R92C_RF_MODE2 0x11
844 #define R92C_RF_RX_AGC_HP 0x12
845 #define R92C_RF_TX_AGC 0x13
846 #define R92C_RF_BIAS 0x14
847 #define R92C_RF_IPA 0x15
848 #define R92C_RF_POW_ABILITY 0x17
849 #define R92C_RF_CHNLBW 0x18
850 #define R92C_RF_RX_G1 0x1a
851 #define R92C_RF_RX_G2 0x1b
852 #define R92C_RF_RX_BB2 0x1c
853 #define R92C_RF_RX_BB1 0x1d
854 #define R92C_RF_RCK1 0x1e
855 #define R92C_RF_RCK2 0x1f
856 #define R92C_RF_TX_G(i) (0x20 + (i))
857 #define R92C_RF_TX_BB1 0x23
858 #define R92C_RF_T_METER 0x24
859 #define R92C_RF_SYN_G(i) (0x25 + (i))
860 #define R92C_RF_RCK_OS 0x30
861 #define R92C_RF_TXPA_G(i) (0x31 + (i))
863 /* Bits for R92C_RF_AC. */
864 #define R92C_RF_AC_MODE_M 0x70000
865 #define R92C_RF_AC_MODE_S 16
866 #define R92C_RF_AC_MODE_STANDBY 1
868 /* Bits for R92C_RF_CHNLBW. */
869 #define R92C_RF_CHNLBW_CHNL_M 0x003ff
870 #define R92C_RF_CHNLBW_CHNL_S 0
871 #define R92C_RF_CHNLBW_BW20 0x00400
872 #define R92C_RF_CHNLBW_LCSTART 0x08000
874 /* Bits for R92C_RF_T_METER. */
875 #define R92C_RF_T_METER_START 0x60
876 #define R92C_RF_T_METER_VAL_M 0x1f
877 #define R92C_RF_T_METER_VAL_S 0
879 #endif /* R92C_REG_H */
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