2 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
3 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org>
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $OpenBSD: if_urtwnreg.h,v 1.3 2010/11/16 18:02:59 damien Exp $
21 #ifndef R92C_TX_DESC_H
22 #define R92C_TX_DESC_H
24 /* Tx MAC descriptor (common part). */
29 #define R92C_FLAGS0_BMCAST 0x01
30 #define R92C_FLAGS0_LSG 0x04
31 #define R92C_FLAGS0_FSG 0x08
32 #define R92C_FLAGS0_OWN 0x80
35 #define R92C_TXDW1_MACID_M 0x0000001f
36 #define R92C_TXDW1_MACID_S 0
37 #define R92C_TXDW1_AGGEN 0x00000020
38 #define R92C_TXDW1_AGGBK 0x00000040
40 #define R92C_TXDW1_QSEL_M 0x00001f00
41 #define R92C_TXDW1_QSEL_S 8
43 #define R92C_TXDW1_QSEL_BE 0x00 /* or 0x03 */
44 #define R92C_TXDW1_QSEL_BK 0x01 /* or 0x02 */
45 #define R92C_TXDW1_QSEL_VI 0x04 /* or 0x05 */
46 #define R92C_TXDW1_QSEL_VO 0x06 /* or 0x07 */
47 #define RTWN_MAX_TID 8
49 #define R92C_TXDW1_QSEL_BEACON 0x10
50 #define R92C_TXDW1_QSEL_MGNT 0x12
52 #define R92C_TXDW1_RAID_M 0x000f0000
53 #define R92C_TXDW1_RAID_S 16
54 #define R92C_TXDW1_CIPHER_M 0x00c00000
55 #define R92C_TXDW1_CIPHER_S 22
56 #define R92C_TXDW1_CIPHER_NONE 0
57 #define R92C_TXDW1_CIPHER_RC4 1
58 #define R92C_TXDW1_CIPHER_AES 3
59 #define R92C_TXDW1_PKTOFF_M 0x7c000000
60 #define R92C_TXDW1_PKTOFF_S 26
63 #define R92C_TXDW2_CCX_RPT 0x00080000
64 #define R92C_TXDW2_AMPDU_DEN_M 0x00700000
65 #define R92C_TXDW2_AMPDU_DEN_S 20
71 #define R92C_TXDW4_RTSRATE_M 0x0000001f
72 #define R92C_TXDW4_RTSRATE_S 0
73 #define R92C_TXDW4_SEQ_SEL_M 0x00000040
74 #define R92C_TXDW4_SEQ_SEL_S 6
75 #define R92C_TXDW4_HWSEQ_EN 0x00000080
76 #define R92C_TXDW4_DRVRATE 0x00000100
77 #define R92C_TXDW4_CTS2SELF 0x00000800
78 #define R92C_TXDW4_RTSEN 0x00001000
79 #define R92C_TXDW4_HWRTSEN 0x00002000
80 #define R92C_TXDW4_PORT_ID_M 0x00004000
81 #define R92C_TXDW4_PORT_ID_S 14
82 #define R92C_TXDW4_DATA_SCO_M 0x00300000
83 #define R92C_TXDW4_DATA_SCO_S 20
84 #define R92C_TXDW4_SCO_SCA 1
85 #define R92C_TXDW4_SCO_SCB 2
86 #define R92C_TXDW4_DATA_SHPRE 0x01000000
87 #define R92C_TXDW4_DATA_BW40 0x02000000
88 #define R92C_TXDW4_RTS_SHORT 0x04000000
89 #define R92C_TXDW4_RTS_BW40 0x08000000
90 #define R92C_TXDW4_RTS_SCO_M 0x30000000
91 #define R92C_TXDW4_RTS_SCO_S 28
94 #define R92C_TXDW5_DATARATE_M 0x0000003f
95 #define R92C_TXDW5_DATARATE_S 0
96 #define R92C_TXDW5_SGI 0x00000040
97 #define R92C_TXDW5_DATARATE_FB_LMT_M 0x00001f00
98 #define R92C_TXDW5_DATARATE_FB_LMT_S 8
99 #define R92C_TXDW5_RTSRATE_FB_LMT_M 0x0001e000
100 #define R92C_TXDW5_RTSRATE_FB_LMT_S 13
101 #define R92C_TXDW5_RTY_LMT_ENA 0x00020000
102 #define R92C_TXDW5_RTY_LMT_M 0x00fc0000
103 #define R92C_TXDW5_RTY_LMT_S 18
104 #define R92C_TXDW5_AGGNUM_M 0xff000000
105 #define R92C_TXDW5_AGGNUM_S 24
108 #define R92C_TXDW6_MAX_AGG_M 0x0000f800
109 #define R92C_TXDW6_MAX_AGG_S 11
110 } __packed __attribute__((aligned(4)));
113 /* Rate adaptation modes. */
114 #define R92C_RAID_11BGN 0
115 #define R92C_RAID_11GN 1
116 #define R92C_RAID_11BN 2
117 #define R92C_RAID_11N 3
118 #define R92C_RAID_11BG 4
119 #define R92C_RAID_11G 5 /* "pure" 11g */
120 #define R92C_RAID_11B 6
122 #endif /* R92C_TX_DESC_H */