sys/dev/rtwn/rtl8192c/usb/r92cu_init.c

   1 /*      $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $   */
   2
   3 /*-
   4  * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
   5  * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org>
   6  * Copyright (c) 2015-2016 Andriy Voskoboinyk <avos@FreeBSD.org>
   7  *
   8  * Permission to use, copy, modify, and distribute this software for any
   9  * purpose with or without fee is hereby granted, provided that the above
  10  * copyright notice and this permission notice appear in all copies.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  13  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  14  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  15  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  16  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  17  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  18  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  19  */
  20
  21 #include <sys/cdefs.h>
  22 __FBSDID("$FreeBSD$");
  23
  24 #include "opt_wlan.h"
  25
  26 #include <sys/param.h>
  27 #include <sys/lock.h>
  28 #include <sys/mutex.h>
  29 #include <sys/mbuf.h>
  30 #include <sys/kernel.h>
  31 #include <sys/socket.h>
  32 #include <sys/systm.h>
  33 #include <sys/malloc.h>
  34 #include <sys/queue.h>
  35 #include <sys/taskqueue.h>
  36 #include <sys/bus.h>
  37 #include <sys/endian.h>
  38 #include <sys/linker.h>
  39
  40 #include <net/if.h>
  41 #include <net/ethernet.h>
  42 #include <net/if_media.h>
  43
  44 #include <net80211/ieee80211_var.h>
  45 #include <net80211/ieee80211_radiotap.h>
  46
  47 #include <dev/rtwn/if_rtwnreg.h>
  48 #include <dev/rtwn/if_rtwnvar.h>
  49 #include <dev/rtwn/if_rtwn_debug.h>
  50
  51 #include <dev/rtwn/usb/rtwn_usb_var.h>
  52
  53 #include <dev/rtwn/rtl8192c/r92c_var.h>
  54
  55 #include <dev/rtwn/rtl8192c/usb/r92cu.h>
  56 #include <dev/rtwn/rtl8192c/usb/r92cu_reg.h>
  57
  58
  59 void
  60 r92cu_init_bb(struct rtwn_softc *sc)
  61 {
  62
  63         /* Enable BB and RF. */
  64         rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
  65             R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
  66             R92C_SYS_FUNC_EN_DIO_RF);
  67
  68         rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83);
  69
  70         rtwn_write_1(sc, R92C_RF_CTRL,
  71             R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
  72         rtwn_write_1(sc, R92C_SYS_FUNC_EN,
  73             R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD |
  74             R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB);
  75
  76         rtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f);
  77         rtwn_write_1(sc, 0x15, 0xe9);
  78         rtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80);
  79
  80         r92c_init_bb_common(sc);
  81 }
  82
  83 int
  84 r92cu_power_on(struct rtwn_softc *sc)
  85 {
  86 #define RTWN_CHK(res) do {      \
  87         if (res != 0)           \
  88                 return (EIO);   \
  89 } while(0)
  90         uint32_t reg;
  91         int ntries;
  92
  93         /* Wait for autoload done bit. */
  94         for (ntries = 0; ntries < 5000; ntries++) {
  95                 if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN)
  96                         break;
  97                 rtwn_delay(sc, 10);
  98         }
  99         if (ntries == 5000) {
 100                 device_printf(sc->sc_dev,
 101                     "timeout waiting for chip autoload\n");
 102                 return (ETIMEDOUT);
 103         }
 104
 105         /* Unlock ISO/CLK/Power control register. */
 106         RTWN_CHK(rtwn_write_1(sc, R92C_RSV_CTRL, 0));
 107
 108         /* Move SPS into PWM mode. */
 109         RTWN_CHK(rtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b));
 110
 111         /* just in case if power_off() was not properly executed. */
 112         rtwn_delay(sc, 100);
 113
 114         reg = rtwn_read_1(sc, R92C_LDOV12D_CTRL);
 115         if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) {
 116                 RTWN_CHK(rtwn_write_1(sc, R92C_LDOV12D_CTRL,
 117                     reg | R92C_LDOV12D_CTRL_LDV12_EN));
 118
 119                 rtwn_delay(sc, 100);
 120
 121                 RTWN_CHK(rtwn_setbits_1(sc, R92C_SYS_ISO_CTRL,
 122                     R92C_SYS_ISO_CTRL_MD2PP, 0));
 123         }
 124
 125         /* Auto enable WLAN. */
 126         RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
 127             R92C_APS_FSMCO_APFM_ONMAC, 1));
 128
 129         for (ntries = 0; ntries < 5000; ntries++) {
 130                 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
 131                     R92C_APS_FSMCO_APFM_ONMAC))
 132                         break;
 133                 rtwn_delay(sc, 10);
 134         }
 135         if (ntries == 5000) {
 136                 device_printf(sc->sc_dev,
 137                     "timeout waiting for MAC auto ON\n");
 138                 return (ETIMEDOUT);
 139         }
 140
 141         /* Enable radio, GPIO and LED functions. */
 142         RTWN_CHK(rtwn_write_2(sc, R92C_APS_FSMCO,
 143             R92C_APS_FSMCO_AFSM_HSUS |
 144             R92C_APS_FSMCO_PDN_EN |
 145             R92C_APS_FSMCO_PFM_ALDN));
 146
 147         /* Release RF digital isolation. */
 148         RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_SYS_ISO_CTRL,
 149             R92C_SYS_ISO_CTRL_DIOR, 0, 1));
 150
 151         /* Initialize MAC. */
 152         RTWN_CHK(rtwn_setbits_1(sc, R92C_APSD_CTRL,
 153             R92C_APSD_CTRL_OFF, 0));
 154         for (ntries = 0; ntries < 1000; ntries++) {
 155                 if (!(rtwn_read_1(sc, R92C_APSD_CTRL) &
 156                     R92C_APSD_CTRL_OFF_STATUS))
 157                         break;
 158                 rtwn_delay(sc, 50);
 159         }
 160         if (ntries == 1000) {
 161                 device_printf(sc->sc_dev,
 162                     "timeout waiting for MAC initialization\n");
 163                 return (ETIMEDOUT);
 164         }
 165
 166         /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
 167         RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
 168             R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN |
 169             R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN |
 170             R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN |
 171             ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
 172             R92C_CR_CALTMR_EN));
 173
 174         RTWN_CHK(rtwn_write_1(sc, 0xfe10, 0x19));
 175
 176         return (0);
 177 #undef RTWN_CHK
 178 }
 179
 180 void
 181 r92cu_power_off(struct rtwn_softc *sc)
 182 {
 183 #ifndef RTWN_WITHOUT_UCODE
 184         struct r92c_softc *rs = sc->sc_priv;
 185 #endif
 186         uint32_t reg;
 187         int error;
 188
 189         /* Deinit C2H event handler. */
 190 #ifndef RTWN_WITHOUT_UCODE
 191         callout_stop(&rs->rs_c2h_report);
 192         rs->rs_c2h_paused = 0;
 193         rs->rs_c2h_pending = 0;
 194         rs->rs_c2h_timeout = hz;
 195 #endif
 196
 197         /* Block all Tx queues. */
 198         error = rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
 199         if (error == ENXIO)     /* hardware gone */
 200                 return;
 201
 202         /* Disable RF */
 203         rtwn_rf_write(sc, 0, 0, 0);
 204
 205         rtwn_write_1(sc, R92C_APSD_CTRL, R92C_APSD_CTRL_OFF);
 206
 207         /* Reset BB state machine */
 208         rtwn_write_1(sc, R92C_SYS_FUNC_EN,
 209             R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA |
 210             R92C_SYS_FUNC_EN_BB_GLB_RST);
 211         rtwn_write_1(sc, R92C_SYS_FUNC_EN,
 212             R92C_SYS_FUNC_EN_USBD | R92C_SYS_FUNC_EN_USBA);
 213
 214         /*
 215          * Reset digital sequence
 216          */
 217 #ifndef RTWN_WITHOUT_UCODE
 218         if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY) {
 219                 /* Reset MCU ready status */
 220                 rtwn_write_1(sc, R92C_MCUFWDL, 0);
 221
 222                 /* If firmware in ram code, do reset */
 223                 r92c_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN);
 224         }
 225 #endif
 226
 227         /* Reset MAC and Enable 8051 */
 228         rtwn_write_1(sc, R92C_SYS_FUNC_EN + 1,
 229             (R92C_SYS_FUNC_EN_CPUEN |
 230              R92C_SYS_FUNC_EN_ELDR |
 231              R92C_SYS_FUNC_EN_HWPDN) >> 8);
 232
 233         /* Reset MCU ready status */
 234         rtwn_write_1(sc, R92C_MCUFWDL, 0);
 235
 236         /* Disable MAC clock */
 237         rtwn_write_2(sc, R92C_SYS_CLKR,
 238             R92C_SYS_CLKR_ANAD16V_EN |
 239             R92C_SYS_CLKR_ANA8M |
 240             R92C_SYS_CLKR_LOADER_EN |
 241             R92C_SYS_CLKR_80M_SSC_DIS |
 242             R92C_SYS_CLKR_SYS_EN |
 243             R92C_SYS_CLKR_RING_EN |
 244             0x4000);
 245
 246         /* Disable AFE PLL */
 247         rtwn_write_1(sc, R92C_AFE_PLL_CTRL, 0x80);
 248
 249         /* Gated AFE DIG_CLOCK */
 250         rtwn_write_2(sc, R92C_AFE_XTAL_CTRL, 0x880F);
 251
 252         /* Isolated digital to PON */
 253         rtwn_write_1(sc, R92C_SYS_ISO_CTRL,
 254             R92C_SYS_ISO_CTRL_MD2PP |
 255             R92C_SYS_ISO_CTRL_PA2PCIE |
 256             R92C_SYS_ISO_CTRL_PD2CORE |
 257             R92C_SYS_ISO_CTRL_IP2MAC |
 258             R92C_SYS_ISO_CTRL_DIOP |
 259             R92C_SYS_ISO_CTRL_DIOE);
 260
 261         /*
 262          * Pull GPIO PIN to balance level and LED control
 263          */
 264         /* 1. Disable GPIO[7:0] */
 265         rtwn_write_2(sc, R92C_GPIO_IOSEL, 0x0000);
 266
 267         reg = rtwn_read_4(sc, R92C_GPIO_PIN_CTRL) & ~0x0000ff00;
 268         reg |= ((reg << 8) & 0x0000ff00) | 0x00ff0000;
 269         rtwn_write_4(sc, R92C_GPIO_PIN_CTRL, reg);
 270
 271         /* Disable GPIO[10:8] */
 272         rtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 0x00);
 273
 274         reg = rtwn_read_2(sc, R92C_GPIO_IO_SEL) & ~0x00f0;
 275         reg |= (((reg & 0x000f) << 4) | 0x0780);
 276         rtwn_write_2(sc, R92C_GPIO_IO_SEL, reg);
 277
 278         /* Disable LED0 & 1 */
 279         rtwn_write_2(sc, R92C_LEDCFG0, 0x8080);
 280
 281         /*
 282          * Reset digital sequence
 283          */
 284         /* Disable ELDR clock */
 285         rtwn_write_2(sc, R92C_SYS_CLKR,
 286             R92C_SYS_CLKR_ANAD16V_EN |
 287             R92C_SYS_CLKR_ANA8M |
 288             R92C_SYS_CLKR_LOADER_EN |
 289             R92C_SYS_CLKR_80M_SSC_DIS |
 290             R92C_SYS_CLKR_SYS_EN |
 291             R92C_SYS_CLKR_RING_EN |
 292             0x4000);
 293
 294         /* Isolated ELDR to PON */
 295         rtwn_write_1(sc, R92C_SYS_ISO_CTRL + 1,
 296             (R92C_SYS_ISO_CTRL_DIOR |
 297              R92C_SYS_ISO_CTRL_PWC_EV12V) >> 8);
 298
 299         /*
 300          * Disable analog sequence
 301          */
 302         /* Disable A15 power */
 303         rtwn_write_1(sc, R92C_LDOA15_CTRL, R92C_LDOA15_CTRL_OBUF);
 304         /* Disable digital core power */
 305         rtwn_setbits_1(sc, R92C_LDOV12D_CTRL,
 306             R92C_LDOV12D_CTRL_LDV12_EN, 0);
 307
 308         /* Enter PFM mode */
 309         rtwn_write_1(sc, R92C_SPS0_CTRL, 0x23);
 310
 311         /* Set USB suspend */
 312         rtwn_write_2(sc, R92C_APS_FSMCO,
 313             R92C_APS_FSMCO_APDM_HOST |
 314             R92C_APS_FSMCO_AFSM_HSUS |
 315             R92C_APS_FSMCO_PFM_ALDN);
 316
 317         /* Lock ISO/CLK/Power control register. */
 318         rtwn_write_1(sc, R92C_RSV_CTRL, 0x0E);
 319 }
 320
 321 void
 322 r92cu_init_intr(struct rtwn_softc *sc)
 323 {
 324         rtwn_write_4(sc, R92C_HISR, 0xffffffff);
 325         rtwn_write_4(sc, R92C_HIMR, 0xffffffff);
 326 }
 327
 328 void
 329 r92cu_init_tx_agg(struct rtwn_softc *sc)
 330 {
 331         struct rtwn_usb_softc *uc = RTWN_USB_SOFTC(sc);
 332         uint32_t reg;
 333
 334         reg = rtwn_read_4(sc, R92C_TDECTRL);
 335         reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, uc->tx_agg_desc_num);
 336         rtwn_write_4(sc, R92C_TDECTRL, reg);
 337 }
 338
 339 void
 340 r92cu_init_rx_agg(struct rtwn_softc *sc)
 341 {
 342
 343         /* Rx aggregation (DMA & USB). */
 344         rtwn_setbits_1(sc, R92C_TRXDMA_CTRL, 0,
 345             R92C_TRXDMA_CTRL_RXDMA_AGG_EN);
 346         rtwn_setbits_1(sc, R92C_USB_SPECIAL_OPTION, 0,
 347             R92C_USB_SPECIAL_OPTION_AGG_EN);
 348
 349         /* XXX dehardcode */
 350         rtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48);
 351         rtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4);
 352         rtwn_write_1(sc, R92C_USB_AGG_TH, 8);
 353         rtwn_write_1(sc, R92C_USB_AGG_TO, 6);
 354 }
 355
 356 void
 357 r92cu_post_init(struct rtwn_softc *sc)
 358 {
 359
 360         /* Perform LO and IQ calibrations. */
 361         r92c_iq_calib(sc);
 362         /* Perform LC calibration. */
 363         r92c_lc_calib(sc);
 364
 365         /* Fix USB interference issue. */
 366         rtwn_write_1(sc, 0xfe40, 0xe0);
 367         rtwn_write_1(sc, 0xfe41, 0x8d);
 368         rtwn_write_1(sc, 0xfe42, 0x80);
 369
 370         r92c_pa_bias_init(sc);
 371
 372         /* Fix for lower temperature. */
 373         rtwn_write_1(sc, 0x15, 0xe9);
 374
 375 #ifndef RTWN_WITHOUT_UCODE
 376         if (sc->sc_flags & RTWN_FW_LOADED) {
 377                 struct r92c_softc *rs = sc->sc_priv;
 378
 379                 if (sc->sc_ratectl_sysctl == RTWN_RATECTL_FW) {
 380                         /* XXX firmware RA does not work yet */
 381                         sc->sc_ratectl = RTWN_RATECTL_NET80211;
 382                 } else
 383                         sc->sc_ratectl = sc->sc_ratectl_sysctl;
 384
 385                 /* Start C2H event handling. */
 386                 callout_reset(&rs->rs_c2h_report, rs->rs_c2h_timeout,
 387                     r92c_handle_c2h_report, sc);
 388         } else
 389 #endif
 390                 sc->sc_ratectl = RTWN_RATECTL_NONE;
 391 }