sys/dev/rtwn/rtl8192e/r92e_init.c

   1 /*-
   2  * Copyright (c) 2017 Kevin Lo <kevlo@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include "opt_wlan.h"
  31
  32 #include <sys/param.h>
  33 #include <sys/lock.h>
  34 #include <sys/mutex.h>
  35 #include <sys/mbuf.h>
  36 #include <sys/kernel.h>
  37 #include <sys/socket.h>
  38 #include <sys/systm.h>
  39 #include <sys/malloc.h>
  40 #include <sys/queue.h>
  41 #include <sys/taskqueue.h>
  42 #include <sys/bus.h>
  43 #include <sys/endian.h>
  44 #include <sys/linker.h>
  45
  46 #include <net/if.h>
  47 #include <net/ethernet.h>
  48 #include <net/if_media.h>
  49
  50 #include <net80211/ieee80211_var.h>
  51 #include <net80211/ieee80211_radiotap.h>
  52
  53 #include <dev/rtwn/if_rtwnreg.h>
  54 #include <dev/rtwn/if_rtwnvar.h>
  55
  56 #include <dev/rtwn/if_rtwn_debug.h>
  57
  58 #include <dev/rtwn/rtl8192c/r92c.h>
  59
  60 #include <dev/rtwn/rtl8192e/r92e.h>
  61 #include <dev/rtwn/rtl8192e/r92e_reg.h>
  62 #include <dev/rtwn/rtl8192e/r92e_priv.h>
  63 #include <dev/rtwn/rtl8192e/r92e_var.h>
  64
  65 int
  66 r92e_llt_init(struct rtwn_softc *sc)
  67 {
  68         int ntries, error;
  69
  70         error = rtwn_setbits_4(sc, R92C_AUTO_LLT, 0, R92C_AUTO_LLT_INIT);
  71         if (error != 0)
  72                 return (error);
  73         for (ntries = 0; ntries < 1000; ntries++) {
  74                 if (!(rtwn_read_4(sc, R92C_AUTO_LLT) & R92C_AUTO_LLT_INIT))
  75                         return (0);
  76                 rtwn_delay(sc, 1);
  77         }
  78         return (ETIMEDOUT);
  79 }
  80
  81 static void
  82 r92e_crystalcap_write(struct rtwn_softc *sc)
  83 {
  84         struct r92e_softc *rs = sc->sc_priv;
  85         uint32_t reg;
  86         uint8_t val;
  87
  88         val = rs->crystalcap & 0x3f;
  89         reg = rtwn_bb_read(sc, R92E_AFE_XTAL_CTRL);
  90         rtwn_bb_write(sc, R92E_AFE_XTAL_CTRL,
  91             RW(reg, R92E_AFE_XTAL_CTRL_ADDR, val | val << 6));
  92         rtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 0x000f81fb);
  93 }
  94
  95 void
  96 r92e_init_bb(struct rtwn_softc *sc)
  97 {
  98         int i, j;
  99
 100         rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
 101             R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD);
 102
 103         /* Enable BB and RF. */
 104         rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
 105             R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
 106             R92C_SYS_FUNC_EN_DIO_RF);
 107
 108         /* PathA RF Power On. */
 109         rtwn_write_1(sc, R92C_RF_CTRL,
 110             R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
 111
 112         /* Write BB initialization values. */
 113         for (i = 0; i < sc->bb_size; i++) {
 114                 const struct rtwn_bb_prog *bb_prog = &sc->bb_prog[i];
 115
 116                 while (!rtwn_check_condition(sc, bb_prog->cond)) {
 117                         KASSERT(bb_prog->next != NULL,
 118                             ("%s: wrong condition value (i %d)\n",
 119                             __func__, i));
 120                         bb_prog = bb_prog->next;
 121                 }
 122
 123                 for (j = 0; j < bb_prog->count; j++) {
 124                         RTWN_DPRINTF(sc, RTWN_DEBUG_RESET,
 125                             "BB: reg 0x%03x, val 0x%08x\n",
 126                             bb_prog->reg[j], bb_prog->val[j]);
 127
 128                         rtwn_bb_write(sc, bb_prog->reg[j], bb_prog->val[j]);
 129                         rtwn_delay(sc, 1);
 130                 }
 131         }
 132
 133         /* Write AGC values. */
 134         for (i = 0; i < sc->agc_size; i++) {
 135                 const struct rtwn_agc_prog *agc_prog = &sc->agc_prog[i];
 136
 137                 while (!rtwn_check_condition(sc, agc_prog->cond)) {
 138                         KASSERT(agc_prog->next != NULL,
 139                             ("%s: wrong condition value (2) (i %d)\n",
 140                             __func__, i));
 141                         agc_prog = agc_prog->next;
 142                 }
 143
 144                 for (j = 0; j < agc_prog->count; j++) {
 145                         RTWN_DPRINTF(sc, RTWN_DEBUG_RESET,
 146                             "AGC: val 0x%08x\n", agc_prog->val[j]);
 147
 148                         rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE,
 149                             agc_prog->val[j]);
 150                         rtwn_delay(sc, 1);
 151                 }
 152         }
 153
 154         if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & R92C_HSSI_PARAM2_CCK_HIPWR)
 155                 sc->sc_flags |= RTWN_FLAG_CCK_HIPWR;
 156
 157         rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040022);
 158         rtwn_delay(sc, 1);
 159         rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x00040020);
 160         rtwn_delay(sc, 1);
 161
 162         r92e_crystalcap_write(sc);
 163 }
 164
 165 void
 166 r92e_init_rf(struct rtwn_softc *sc)
 167 {
 168         struct r92e_softc *rs = sc->sc_priv;
 169         uint32_t reg, type;
 170         int i, chain, idx, off;
 171
 172         for (chain = 0, i = 0; chain < sc->nrxchains; chain++, i++) {
 173                 /* Save RF_ENV control type. */
 174                 idx = chain / 2;
 175                 off = (chain % 2) * 16;
 176                 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
 177                 type = (reg >> off) & 0x10;
 178
 179                 /* Set RF_ENV enable. */
 180                 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(chain),
 181                     0, 0x100000);
 182                 rtwn_delay(sc, 1);
 183                 /* Set RF_ENV output high. */
 184                 rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(chain),
 185                     0, 0x10);
 186                 rtwn_delay(sc, 1);
 187                 /* Set address and data lengths of RF registers. */
 188                 rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(chain),
 189                     R92C_HSSI_PARAM2_ADDR_LENGTH, 0);
 190                 rtwn_delay(sc, 1);
 191                 rtwn_bb_setbits(sc, R92C_HSSI_PARAM2(chain),
 192                     R92C_HSSI_PARAM2_DATA_LENGTH, 0);
 193                 rtwn_delay(sc, 1);
 194
 195                 /* Write RF initialization values for this chain. */
 196                 i += r92c_init_rf_chain(sc, &sc->rf_prog[i], chain);
 197
 198                 /* Cache RF register CHNLBW. */
 199                 rs->rf_chnlbw[chain] = rtwn_rf_read(sc, chain, R92C_RF_CHNLBW);
 200         }
 201
 202         /* Turn CCK and OFDM blocks on. */
 203         rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_CCK_EN);
 204         rtwn_bb_setbits(sc, R92C_FPGA0_RFMOD, 0, R92C_RFMOD_OFDM_EN);
 205 }
 206
 207 static void
 208 r92e_adj_crystal(struct rtwn_softc *sc)
 209 {
 210
 211         rtwn_setbits_1(sc, R92C_AFE_PLL_CTRL, R92C_AFE_PLL_CTRL_FREF_SEL, 0);
 212         rtwn_setbits_4(sc, R92E_APE_PLL_CTRL_EXT, 0x00000380, 0);
 213         rtwn_setbits_1(sc, R92C_AFE_PLL_CTRL, 0x40, 0);
 214         rtwn_setbits_4(sc, R92E_APE_PLL_CTRL_EXT, 0x00200000, 0);
 215 }
 216
 217 int
 218 r92e_power_on(struct rtwn_softc *sc)
 219 {
 220 #define RTWN_CHK(res) do {      \
 221         if (res != 0)           \
 222                 return (EIO);   \
 223 } while(0)
 224         int ntries;
 225
 226         if (rtwn_read_4(sc, R92C_SYS_CFG) & R92C_SYS_CFG_TRP_BT_EN)
 227                 RTWN_CHK(rtwn_write_1(sc, R92C_LDO_SWR_CTRL, 0xc3));
 228         else {
 229                 RTWN_CHK(rtwn_setbits_4(sc, R92E_LDOV12_CTRL, 0x00100000,
 230                     0x00500000));
 231                 RTWN_CHK(rtwn_write_1(sc, R92C_LDO_SWR_CTRL, 0x83));
 232         }
 233
 234         r92e_adj_crystal(sc);
 235
 236         /* Enable WL suspend. */
 237         RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
 238             R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE, 0, 1));
 239
 240         /* Disable HWPDN, SW LPS and WL suspend. */
 241         RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
 242             R92C_APS_FSMCO_APFM_RSM | R92C_APS_FSMCO_AFSM_HSUS |
 243             R92C_APS_FSMCO_AFSM_PCIE | R92C_APS_FSMCO_APDM_HPDN, 0, 1));
 244
 245         /* Wait for power ready bit. */
 246         for (ntries = 0; ntries < 5000; ntries++) {
 247                 if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
 248                         break;
 249                 rtwn_delay(sc, 10);
 250         }
 251         if (ntries == 5000) {
 252                 device_printf(sc->sc_dev,
 253                     "timeout waiting for chip power up\n");
 254                 return (ETIMEDOUT);
 255         }
 256
 257         /* Release WLON reset. */
 258         RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
 259             R92C_APS_FSMCO_RDY_MACON, 2));
 260
 261         RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
 262             R92C_APS_FSMCO_APFM_ONMAC, 1));
 263         for (ntries = 0; ntries < 5000; ntries++) {
 264                 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
 265                     R92C_APS_FSMCO_APFM_ONMAC))
 266                         break;
 267                 rtwn_delay(sc, 10);
 268         }
 269         if (ntries == 5000)
 270                 return (ETIMEDOUT);
 271
 272         /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
 273         RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0));
 274         RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
 275             R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN |
 276             R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN |
 277             R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN |
 278             ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
 279             R92C_CR_CALTMR_EN));
 280
 281         return (0);
 282 }
 283
 284 void
 285 r92e_power_off(struct rtwn_softc *sc)
 286 {
 287         int error, ntries;
 288
 289         /* Stop Rx. */
 290         error = rtwn_write_1(sc, R92C_CR, 0);
 291         if (error == ENXIO)     /* hardware gone */
 292                 return;
 293
 294         /* Move card to Low Power state. */
 295         /* Block all Tx queues. */
 296         rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
 297
 298         for (ntries = 0; ntries < 5000; ntries++) {
 299                 /* Should be zero if no packet is transmitting. */
 300                 if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
 301                         break;
 302
 303                 rtwn_delay(sc, 10);
 304         }
 305         if (ntries == 5000) {
 306                 device_printf(sc->sc_dev, "%s: failed to block Tx queues\n",
 307                     __func__);
 308                 return;
 309         }
 310
 311         /* CCK and OFDM are disabled, and clock are gated. */
 312         rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0);
 313
 314         rtwn_delay(sc, 1);
 315
 316         /* Reset whole BB. */
 317         rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
 318
 319         /* Reset MAC TRX. */
 320         rtwn_write_1(sc, R92C_CR,
 321             R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN);
 322
 323         /* Check if removed later. */
 324         rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
 325
 326         /* Respond TxOK to scheduler */
 327         rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, R92C_DUAL_TSF_RST_TXOK);
 328
 329         /* Reset MCU. */
 330         rtwn_write_1(sc, R92C_MCUFWDL, 0);
 331
 332 #ifndef RTWN_WITHOUT_UCODE
 333         /* Reset MCU IO wrapper. */
 334         rtwn_setbits_1(sc, R92C_RSV_CTRL + 1, 0x01, 0);
 335
 336         rtwn_setbits_1_shift(sc, R92C_SYS_FUNC_EN,
 337             R92C_SYS_FUNC_EN_CPUEN, 0, 1);
 338
 339         /* Enable MCU IO wrapper. */
 340         rtwn_setbits_1(sc, R92C_RSV_CTRL + 1, 0, 0x01);
 341 #endif
 342
 343         /* Move card to Disabled state. */
 344         /* Turn off RF. */
 345         rtwn_write_1(sc, R92C_RF_CTRL, 0);
 346
 347         /* Switch DPDT_SEL_P output. */
 348         rtwn_setbits_1(sc, R92C_LEDCFG2, 0x80, 0);
 349
 350         /* Turn off MAC by HW state machine */
 351         rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_OFF,
 352             1);
 353
 354         for (ntries = 0; ntries < 5000; ntries++) {
 355                 /* Wait until it will be disabled. */
 356                 if ((rtwn_read_2(sc, R92C_APS_FSMCO) &
 357                     R92C_APS_FSMCO_APFM_OFF) == 0)
 358                         break;
 359
 360                 rtwn_delay(sc, 10);
 361         }
 362         if (ntries == 5000) {
 363                 device_printf(sc->sc_dev, "%s: could not turn off MAC\n",
 364                     __func__);
 365                 return;
 366         }
 367
 368         /* SOP option to disable BG/MB. */
 369         rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff,
 370            R92C_APS_FSMCO_SOP_RCK, 3);
 371
 372         /* Unlock small LDO Register. */
 373         rtwn_setbits_1(sc, 0xcc, 0, 0x4);
 374
 375         /* Disable small LDO. */
 376         rtwn_setbits_1(sc, R92C_SPS0_CTRL, 0x1, 0);
 377
 378         /* Enable WL suspend. */
 379         rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_AFSM_PCIE,
 380             R92C_APS_FSMCO_AFSM_HSUS, 1);
 381
 382         /* Enable SW LPS. */
 383         rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
 384             R92C_APS_FSMCO_APFM_RSM, 1);
 385 }