sys/dev/rtwn/rtl8812a/r12a_chan.c

   1 /*-
   2  * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 #include <sys/cdefs.h>
  28 __FBSDID("$FreeBSD$");
  29
  30 #include "opt_wlan.h"
  31
  32 #include <sys/param.h>
  33 #include <sys/lock.h>
  34 #include <sys/mutex.h>
  35 #include <sys/mbuf.h>
  36 #include <sys/kernel.h>
  37 #include <sys/socket.h>
  38 #include <sys/systm.h>
  39 #include <sys/malloc.h>
  40 #include <sys/queue.h>
  41 #include <sys/taskqueue.h>
  42 #include <sys/bus.h>
  43 #include <sys/endian.h>
  44 #include <sys/linker.h>
  45
  46 #include <net/if.h>
  47 #include <net/ethernet.h>
  48 #include <net/if_media.h>
  49
  50 #include <net80211/ieee80211_var.h>
  51 #include <net80211/ieee80211_radiotap.h>
  52
  53 #include <dev/rtwn/if_rtwnreg.h>
  54 #include <dev/rtwn/if_rtwnvar.h>
  55
  56 #include <dev/rtwn/if_rtwn_debug.h>
  57 #include <dev/rtwn/if_rtwn_ridx.h>
  58 #include <dev/rtwn/if_rtwn_rx.h>
  59
  60 #include <dev/rtwn/rtl8812a/r12a.h>
  61 #include <dev/rtwn/rtl8812a/r12a_reg.h>
  62 #include <dev/rtwn/rtl8812a/r12a_var.h>
  63
  64 static void
  65 r12a_write_txpower(struct rtwn_softc *sc, int chain,
  66     struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT])
  67 {
  68
  69         if (IEEE80211_IS_CHAN_2GHZ(c)) {
  70                 /* Write per-CCK rate Tx power. */
  71                 rtwn_bb_write(sc, R12A_TXAGC_CCK11_1(chain),
  72                     SM(R12A_TXAGC_CCK1,  power[RTWN_RIDX_CCK1]) |
  73                     SM(R12A_TXAGC_CCK2,  power[RTWN_RIDX_CCK2]) |
  74                     SM(R12A_TXAGC_CCK55, power[RTWN_RIDX_CCK55]) |
  75                     SM(R12A_TXAGC_CCK11, power[RTWN_RIDX_CCK11]));
  76         }
  77
  78         /* Write per-OFDM rate Tx power. */
  79         rtwn_bb_write(sc, R12A_TXAGC_OFDM18_6(chain),
  80             SM(R12A_TXAGC_OFDM06, power[RTWN_RIDX_OFDM6]) |
  81             SM(R12A_TXAGC_OFDM09, power[RTWN_RIDX_OFDM9]) |
  82             SM(R12A_TXAGC_OFDM12, power[RTWN_RIDX_OFDM12]) |
  83             SM(R12A_TXAGC_OFDM18, power[RTWN_RIDX_OFDM18]));
  84         rtwn_bb_write(sc, R12A_TXAGC_OFDM54_24(chain),
  85             SM(R12A_TXAGC_OFDM24, power[RTWN_RIDX_OFDM24]) |
  86             SM(R12A_TXAGC_OFDM36, power[RTWN_RIDX_OFDM36]) |
  87             SM(R12A_TXAGC_OFDM48, power[RTWN_RIDX_OFDM48]) |
  88             SM(R12A_TXAGC_OFDM54, power[RTWN_RIDX_OFDM54]));
  89         /* Write per-MCS Tx power. */
  90         rtwn_bb_write(sc, R12A_TXAGC_MCS3_0(chain),
  91             SM(R12A_TXAGC_MCS0, power[RTWN_RIDX_HT_MCS(0)]) |
  92             SM(R12A_TXAGC_MCS1, power[RTWN_RIDX_HT_MCS(1)]) |
  93             SM(R12A_TXAGC_MCS2, power[RTWN_RIDX_HT_MCS(2)]) |
  94             SM(R12A_TXAGC_MCS3, power[RTWN_RIDX_HT_MCS(3)]));
  95         rtwn_bb_write(sc, R12A_TXAGC_MCS7_4(chain),
  96             SM(R12A_TXAGC_MCS4, power[RTWN_RIDX_HT_MCS(4)]) |
  97             SM(R12A_TXAGC_MCS5, power[RTWN_RIDX_HT_MCS(5)]) |
  98             SM(R12A_TXAGC_MCS6, power[RTWN_RIDX_HT_MCS(6)]) |
  99             SM(R12A_TXAGC_MCS7, power[RTWN_RIDX_HT_MCS(7)]));
 100         if (sc->ntxchains >= 2) {
 101                 rtwn_bb_write(sc, R12A_TXAGC_MCS11_8(chain),
 102                     SM(R12A_TXAGC_MCS8,  power[RTWN_RIDX_HT_MCS(8)]) |
 103                     SM(R12A_TXAGC_MCS9,  power[RTWN_RIDX_HT_MCS(9)]) |
 104                     SM(R12A_TXAGC_MCS10, power[RTWN_RIDX_HT_MCS(10)]) |
 105                     SM(R12A_TXAGC_MCS11, power[RTWN_RIDX_HT_MCS(11)]));
 106                 rtwn_bb_write(sc, R12A_TXAGC_MCS15_12(chain),
 107                     SM(R12A_TXAGC_MCS12, power[RTWN_RIDX_HT_MCS(12)]) |
 108                     SM(R12A_TXAGC_MCS13, power[RTWN_RIDX_HT_MCS(13)]) |
 109                     SM(R12A_TXAGC_MCS14, power[RTWN_RIDX_HT_MCS(14)]) |
 110                     SM(R12A_TXAGC_MCS15, power[RTWN_RIDX_HT_MCS(15)]));
 111         }
 112
 113         /* TODO: VHT rates */
 114 }
 115
 116 static int
 117 r12a_get_power_group(struct rtwn_softc *sc, struct ieee80211_channel *c)
 118 {
 119         uint8_t chan;
 120         int group;
 121
 122         chan = rtwn_chan2centieee(c);
 123         if (IEEE80211_IS_CHAN_2GHZ(c)) {
 124                 if (chan <= 2)                  group = 0;
 125                 else if (chan <= 5)             group = 1;
 126                 else if (chan <= 8)             group = 2;
 127                 else if (chan <= 11)            group = 3;
 128                 else if (chan <= 14)            group = 4;
 129                 else {
 130                         KASSERT(0, ("wrong 2GHz channel %d!\n", chan));
 131                         return (-1);
 132                 }
 133         } else if (IEEE80211_IS_CHAN_5GHZ(c)) {
 134                 if (chan < 36)
 135                         return (-1);
 136
 137                 if (chan <= 42)                 group = 0;
 138                 else if (chan <= 48)            group = 1;
 139                 else if (chan <= 58)            group = 2;
 140                 else if (chan <= 64)            group = 3;
 141                 else if (chan <= 106)           group = 4;
 142                 else if (chan <= 114)           group = 5;
 143                 else if (chan <= 122)           group = 6;
 144                 else if (chan <= 130)           group = 7;
 145                 else if (chan <= 138)           group = 8;
 146                 else if (chan <= 144)           group = 9;
 147                 else if (chan <= 155)           group = 10;
 148                 else if (chan <= 161)           group = 11;
 149                 else if (chan <= 171)           group = 12;
 150                 else if (chan <= 177)           group = 13;
 151                 else {
 152                         KASSERT(0, ("wrong 5GHz channel %d!\n", chan));
 153                         return (-1);
 154                 }
 155         } else {
 156                 KASSERT(0, ("wrong channel band (flags %08X)\n", c->ic_flags));
 157                 return (-1);
 158         }
 159
 160         return (group);
 161 }
 162
 163 static void
 164 r12a_get_txpower(struct rtwn_softc *sc, int chain,
 165     struct ieee80211_channel *c, uint8_t power[RTWN_RIDX_COUNT])
 166 {
 167         struct r12a_softc *rs = sc->sc_priv;
 168         int i, ridx, group, max_mcs;
 169
 170         /* Determine channel group. */
 171         group = r12a_get_power_group(sc, c);
 172         if (group == -1) {      /* shouldn't happen */
 173                 device_printf(sc->sc_dev, "%s: incorrect channel\n", __func__);
 174                 return;
 175         }
 176
 177         /* TODO: VHT rates. */
 178         max_mcs = RTWN_RIDX_HT_MCS(sc->ntxchains * 8 - 1);
 179
 180         /* XXX regulatory */
 181         /* XXX net80211 regulatory */
 182
 183         if (IEEE80211_IS_CHAN_2GHZ(c)) {
 184                 for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++)
 185                         power[ridx] = rs->cck_tx_pwr[chain][group];
 186                 for (ridx = RTWN_RIDX_OFDM6; ridx <= max_mcs; ridx++)
 187                         power[ridx] = rs->ht40_tx_pwr_2g[chain][group];
 188
 189                 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++)
 190                         power[ridx] += rs->ofdm_tx_pwr_diff_2g[chain][0];
 191
 192                 for (i = 0; i < sc->ntxchains; i++) {
 193                         uint8_t min_mcs;
 194                         uint8_t pwr_diff;
 195
 196 #ifdef notyet
 197                         if (IEEE80211_IS_CHAN_HT80(c)) {
 198                                 /* Vendor driver uses HT40 values here. */
 199                                 pwr_diff = rs->bw40_tx_pwr_diff_2g[chain][i];
 200                         } else
 201 #endif
 202                         if (IEEE80211_IS_CHAN_HT40(c))
 203                                 pwr_diff = rs->bw40_tx_pwr_diff_2g[chain][i];
 204                         else
 205                                 pwr_diff = rs->bw20_tx_pwr_diff_2g[chain][i];
 206
 207                         min_mcs = RTWN_RIDX_HT_MCS(i * 8);
 208                         for (ridx = min_mcs; ridx <= max_mcs; ridx++)
 209                                 power[ridx] += pwr_diff;
 210                 }
 211         } else {        /* 5GHz */
 212                 for (ridx = RTWN_RIDX_OFDM6; ridx <= max_mcs; ridx++)
 213                         power[ridx] = rs->ht40_tx_pwr_5g[chain][group];
 214
 215                 for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++)
 216                         power[ridx] += rs->ofdm_tx_pwr_diff_5g[chain][0];
 217
 218                 for (i = 0; i < sc->ntxchains; i++) {
 219                         uint8_t min_mcs;
 220                         uint8_t pwr_diff;
 221
 222 #ifdef notyet
 223                         if (IEEE80211_IS_CHAN_HT80(c)) {
 224                                 /* TODO: calculate base value. */
 225                                 pwr_diff = rs->bw80_tx_pwr_diff_5g[chain][i];
 226                         } else
 227 #endif
 228                         if (IEEE80211_IS_CHAN_HT40(c))
 229                                 pwr_diff = rs->bw40_tx_pwr_diff_5g[chain][i];
 230                         else
 231                                 pwr_diff = rs->bw20_tx_pwr_diff_5g[chain][i];
 232
 233                         min_mcs = RTWN_RIDX_HT_MCS(i * 8);
 234                         for (ridx = min_mcs; ridx <= max_mcs; ridx++)
 235                                 power[ridx] += pwr_diff;
 236                 }
 237         }
 238
 239         /* Apply max limit. */
 240         for (ridx = RTWN_RIDX_CCK1; ridx <= max_mcs; ridx++) {
 241                 if (power[ridx] > R92C_MAX_TX_PWR)
 242                         power[ridx] = R92C_MAX_TX_PWR;
 243         }
 244
 245 #ifdef RTWN_DEBUG
 246         if (sc->sc_debug & RTWN_DEBUG_TXPWR) {
 247                 /* Dump per-rate Tx power values. */
 248                 printf("Tx power for chain %d:\n", chain);
 249                 for (ridx = RTWN_RIDX_CCK1; ridx <= max_mcs; ridx++)
 250                         printf("Rate %d = %u\n", ridx, power[ridx]);
 251         }
 252 #endif
 253 }
 254
 255 static void
 256 r12a_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c)
 257 {
 258         uint8_t power[RTWN_RIDX_COUNT];
 259         int i;
 260
 261         for (i = 0; i < sc->ntxchains; i++) {
 262                 memset(power, 0, sizeof(power));
 263                 /* Compute per-rate Tx power values. */
 264                 r12a_get_txpower(sc, i, c, power);
 265                 /* Write per-rate Tx power values to hardware. */
 266                 r12a_write_txpower(sc, i, c, power);
 267         }
 268 }
 269
 270 void
 271 r12a_fix_spur(struct rtwn_softc *sc, struct ieee80211_channel *c)
 272 {
 273         struct r12a_softc *rs = sc->sc_priv;
 274         uint16_t chan = rtwn_chan2centieee(c);
 275
 276         if (rs->chip & R12A_CHIP_C_CUT) {
 277                 if (IEEE80211_IS_CHAN_HT40(c) && chan == 11) {
 278                         rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0xc00);
 279                         rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0, 0x40000000);
 280                 } else {
 281                         rtwn_bb_setbits(sc, R12A_RFMOD, 0x400, 0x800);
 282
 283                         if (!IEEE80211_IS_CHAN_HT40(c) &&       /* 20 MHz */
 284                             (chan == 13 || chan == 14)) {
 285                                 rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0x300);
 286                                 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK,
 287                                     0, 0x40000000);
 288                         } else {        /* !80 Mhz */
 289                                 rtwn_bb_setbits(sc, R12A_RFMOD, 0x100, 0x200);
 290                                 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK,
 291                                     0x40000000, 0);
 292                         }
 293                 }
 294         } else {
 295                 /* Set ADC clock to 160M to resolve 2480 MHz spur. */
 296                 if (!IEEE80211_IS_CHAN_HT40(c) &&       /* 20 MHz */
 297                     (chan == 13 || chan == 14))
 298                         rtwn_bb_setbits(sc, R12A_RFMOD, 0, 0x300);
 299                 else if (IEEE80211_IS_CHAN_2GHZ(c))
 300                         rtwn_bb_setbits(sc, R12A_RFMOD, 0x100, 0x200);
 301         }
 302 }
 303
 304 static void
 305 r12a_set_band(struct rtwn_softc *sc, struct ieee80211_channel *c)
 306 {
 307         struct ieee80211com *ic = &sc->sc_ic;
 308         struct r12a_softc *rs = sc->sc_priv;
 309         uint32_t basicrates;
 310         uint8_t swing;
 311         int i;
 312
 313         /* Check if band was changed. */
 314         if ((sc->sc_flags & (RTWN_STARTED | RTWN_RUNNING)) !=
 315             RTWN_STARTED && IEEE80211_IS_CHAN_5GHZ(c) ^
 316             !(rtwn_read_1(sc, R12A_CCK_CHECK) & R12A_CCK_CHECK_5GHZ))
 317                 return;
 318
 319         rtwn_get_rates(sc, ieee80211_get_suprates(ic, c), NULL, &basicrates,
 320             NULL, 1);
 321         if (IEEE80211_IS_CHAN_2GHZ(c)) {
 322                 rtwn_r12a_set_band_2ghz(sc, basicrates);
 323                 swing = rs->tx_bbswing_2g;
 324         } else if (IEEE80211_IS_CHAN_5GHZ(c)) {
 325                 rtwn_r12a_set_band_5ghz(sc, basicrates);
 326                 swing = rs->tx_bbswing_5g;
 327         } else {
 328                 KASSERT(0, ("wrong channel flags %08X\n", c->ic_flags));
 329                 return;
 330         }
 331
 332         /* XXX PATH_B is set by vendor driver. */
 333         for (i = 0; i < 2; i++) {
 334                 uint16_t val = 0;
 335
 336                 switch ((swing >> i * 2) & 0x3) {
 337                 case 0:
 338                         val = 0x200;    /* 0 dB */
 339                         break;
 340                 case 1:
 341                         val = 0x16a;    /* -3 dB */
 342                         break;
 343                 case 2:
 344                         val = 0x101;    /* -6 dB */
 345                         break;
 346                 case 3:
 347                         val = 0xb6;     /* -9 dB */
 348                         break;
 349                 }
 350
 351                 rtwn_bb_setbits(sc, R12A_TX_SCALE(i), R12A_TX_SCALE_SWING_M,
 352                     val << R12A_TX_SCALE_SWING_S);
 353         }
 354 }
 355
 356 void
 357 r12a_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c)
 358 {
 359         uint32_t val;
 360         uint16_t chan;
 361         int i;
 362
 363         r12a_set_band(sc, c);
 364
 365         chan = rtwn_chan2centieee(c);
 366         if (36 <= chan && chan <= 48)
 367                 val = 0x09280000;
 368         else if (50 <= chan && chan <= 64)
 369                 val = 0x08a60000;
 370         else if (100 <= chan && chan <= 116)
 371                 val = 0x08a40000;
 372         else if (118 <= chan)
 373                 val = 0x08240000;
 374         else
 375                 val = 0x12d40000;
 376
 377         rtwn_bb_setbits(sc, R12A_FC_AREA, 0x1ffe0000, val);
 378
 379         for (i = 0; i < sc->nrxchains; i++) {
 380                 if (36 <= chan && chan <= 64)
 381                         val = 0x10100;
 382                 else if (100 <= chan && chan <= 140)
 383                         val = 0x30100;
 384                 else if (140 < chan)
 385                         val = 0x50100;
 386                 else
 387                         val = 0x00000;
 388
 389                 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0x70300, val);
 390
 391                 /* RTL8812AU-specific */
 392                 rtwn_r12a_fix_spur(sc, c);
 393
 394                 KASSERT(chan <= 0xff, ("%s: chan %d\n", __func__, chan));
 395                 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0xff, chan);
 396         }
 397
 398 #ifdef notyet
 399         if (IEEE80211_IS_CHAN_HT80(c)) {        /* 80 MHz */
 400                 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x80, 0x100);
 401
 402                 /* TODO */
 403
 404                 val = 0x0;
 405         } else
 406 #endif
 407         if (IEEE80211_IS_CHAN_HT40(c)) {        /* 40 MHz */
 408                 uint8_t ext_chan;
 409
 410                 if (IEEE80211_IS_CHAN_HT40U(c))
 411                         ext_chan = R12A_DATA_SEC_PRIM_DOWN_20;
 412                 else
 413                         ext_chan = R12A_DATA_SEC_PRIM_UP_20;
 414
 415                 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x100, 0x80);
 416                 rtwn_write_1(sc, R12A_DATA_SEC, ext_chan);
 417
 418                 rtwn_bb_setbits(sc, R12A_RFMOD, 0x003003c3, 0x00300201);
 419                 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0x40000000, 0);
 420
 421                 /* discard high 4 bits */
 422                 val = rtwn_bb_read(sc, R12A_RFMOD);
 423                 val = RW(val, R12A_RFMOD_EXT_CHAN, ext_chan);
 424                 rtwn_bb_write(sc, R12A_RFMOD, val);
 425
 426                 val = rtwn_bb_read(sc, R12A_CCA_ON_SEC);
 427                 val = RW(val, R12A_CCA_ON_SEC_EXT_CHAN, ext_chan);
 428                 rtwn_bb_write(sc, R12A_CCA_ON_SEC, val);
 429
 430                 if (rtwn_read_1(sc, 0x837) & 0x04)
 431                         val = 0x01800000;
 432                 else if (sc->nrxchains == 2 && sc->ntxchains == 2)
 433                         val = 0x01c00000;
 434                 else
 435                         val = 0x02000000;
 436
 437                 rtwn_bb_setbits(sc, R12A_L1_PEAK_TH, 0x03c00000, val);
 438
 439                 if (IEEE80211_IS_CHAN_HT40U(c))
 440                         rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 0x10, 0);
 441                 else
 442                         rtwn_bb_setbits(sc, R92C_CCK0_SYSTEM, 0, 0x10);
 443
 444                 val = 0x400;
 445         } else {        /* 20 MHz */
 446                 rtwn_setbits_2(sc, R92C_WMAC_TRXPTCL_CTL, 0x180, 0);
 447                 rtwn_write_1(sc, R12A_DATA_SEC, R12A_DATA_SEC_NO_EXT);
 448
 449                 rtwn_bb_setbits(sc, R12A_RFMOD, 0x003003c3, 0x00300200);
 450                 rtwn_bb_setbits(sc, R12A_ADC_BUF_CLK, 0x40000000, 0);
 451
 452                 if (sc->nrxchains == 2 && sc->ntxchains == 2)
 453                         val = 0x01c00000;
 454                 else
 455                         val = 0x02000000;
 456
 457                 rtwn_bb_setbits(sc, R12A_L1_PEAK_TH, 0x03c00000, val);
 458
 459                 val = 0xc00;
 460         }
 461
 462         /* RTL8812AU-specific */
 463         rtwn_r12a_fix_spur(sc, c);
 464
 465         for (i = 0; i < sc->nrxchains; i++)
 466                 rtwn_rf_setbits(sc, i, R92C_RF_CHNLBW, 0xc00, val);
 467
 468         /* Set Tx power for this new channel. */
 469         r12a_set_txpower(sc, c);
 470 }
 471
 472 void
 473 r12a_set_band_2ghz(struct rtwn_softc *sc, uint32_t basicrates)
 474 {
 475         struct r12a_softc *rs = sc->sc_priv;
 476
 477         /* Enable CCK / OFDM. */
 478         rtwn_bb_setbits(sc, R12A_OFDMCCK_EN,
 479             0, R12A_OFDMCCK_EN_CCK | R12A_OFDMCCK_EN_OFDM);
 480
 481         rtwn_bb_setbits(sc, R12A_BW_INDICATION, 0x02, 0x01);
 482         rtwn_bb_setbits(sc, R12A_PWED_TH, 0x3e000, 0x2e000);
 483
 484         /* Select AGC table. */
 485         rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x03, 0);
 486
 487         switch (rs->rfe_type) {
 488         case 0:
 489         case 1:
 490         case 2:
 491                 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77777777);
 492                 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777);
 493                 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0);
 494                 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0);
 495                 break;
 496         case 3:
 497                 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x54337770);
 498                 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x54337770);
 499                 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000);
 500                 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);
 501                 rtwn_bb_setbits(sc, R12A_ANTSEL_SW, 0x0303, 0x01);
 502                 break;
 503         case 4:
 504                 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77777777);
 505                 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777);
 506                 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x00100000);
 507                 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x00100000);
 508                 break;
 509         case 5:
 510                 rtwn_write_1(sc, R12A_RFE_PINMUX(0) + 2, 0x77);
 511                 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77777777);
 512                 rtwn_setbits_1(sc, R12A_RFE_INV(0) + 3, 0x01, 0);
 513                 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0);
 514                 break;
 515         default:
 516                 break;
 517         }
 518
 519         rtwn_bb_setbits(sc, R12A_TX_PATH, 0xf0, 0x10);
 520         rtwn_bb_setbits(sc, R12A_CCK_RX_PATH, 0x0f000000, 0x01000000);
 521
 522         /* Write basic rates. */
 523         rtwn_set_basicrates(sc, basicrates);
 524
 525         rtwn_write_1(sc, R12A_CCK_CHECK, 0);
 526 }
 527
 528 void
 529 r12a_set_band_5ghz(struct rtwn_softc *sc, uint32_t basicrates)
 530 {
 531         struct r12a_softc *rs = sc->sc_priv;
 532         int ntries;
 533
 534         rtwn_write_1(sc, R12A_CCK_CHECK, R12A_CCK_CHECK_5GHZ);
 535
 536         for (ntries = 0; ntries < 100; ntries++) {
 537                 if ((rtwn_read_2(sc, R12A_TXPKT_EMPTY) & 0x30) == 0x30)
 538                         break;
 539
 540                 rtwn_delay(sc, 25);
 541         }
 542         if (ntries == 100) {
 543                 device_printf(sc->sc_dev,
 544                     "%s: TXPKT_EMPTY check failed (%04X)\n",
 545                     __func__, rtwn_read_2(sc, R12A_TXPKT_EMPTY));
 546         }
 547
 548         /* Enable OFDM. */
 549         rtwn_bb_setbits(sc, R12A_OFDMCCK_EN, R12A_OFDMCCK_EN_CCK,
 550             R12A_OFDMCCK_EN_OFDM);
 551
 552         rtwn_bb_setbits(sc, R12A_BW_INDICATION, 0x01, 0x02);
 553         rtwn_bb_setbits(sc, R12A_PWED_TH, 0x3e000, 0x2a000);
 554
 555         /* Select AGC table. */
 556         rtwn_bb_setbits(sc, R12A_TXAGC_TABLE_SELECT, 0x03, 0x01);
 557
 558         switch (rs->rfe_type) {
 559         case 0:
 560                 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337717);
 561                 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337717);
 562                 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000);
 563                 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);
 564                 break;
 565         case 1:
 566                 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337717);
 567                 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337717);
 568                 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0);
 569                 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0);
 570                 break;
 571         case 2:
 572         case 4:
 573                 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x77337777);
 574                 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337777);
 575                 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000);
 576                 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);
 577                 break;
 578         case 3:
 579                 rtwn_bb_write(sc, R12A_RFE_PINMUX(0), 0x54337717);
 580                 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x54337717);
 581                 rtwn_bb_setbits(sc, R12A_RFE_INV(0), 0x3ff00000, 0x01000000);
 582                 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);
 583                 rtwn_bb_setbits(sc, R12A_ANTSEL_SW, 0x0303, 0x01);
 584                 break;
 585         case 5:
 586                 rtwn_write_1(sc, R12A_RFE_PINMUX(0) + 2, 0x33);
 587                 rtwn_bb_write(sc, R12A_RFE_PINMUX(1), 0x77337777);
 588                 rtwn_setbits_1(sc, R12A_RFE_INV(0) + 3, 0, 0x01);
 589                 rtwn_bb_setbits(sc, R12A_RFE_INV(1), 0x3ff00000, 0x01000000);
 590                 break;
 591         default:
 592                 break;
 593         }
 594
 595         rtwn_bb_setbits(sc, R12A_TX_PATH, 0xf0, 0);
 596         rtwn_bb_setbits(sc, R12A_CCK_RX_PATH, 0, 0x0f000000);
 597
 598         /* Write basic rates. */
 599         rtwn_set_basicrates(sc, basicrates);
 600 }