2 * Copyright (c) 2016 Andriy Voskoboinyk <avos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <dev/rtwn/rtl8188e/r88e_reg.h>
37 /* System Configuration. */
38 #define R12A_SDIO_CTRL 0x070
39 #define R12A_RF_B_CTRL 0x076
40 /* Rx DMA Configuration. */
41 #define R12A_RXDMA_PRO 0x290
42 #define R12A_EARLY_MODE_CONTROL 0x2bc
43 /* Protocol Configuration. */
44 #define R12A_TXPKT_EMPTY 0x41a
45 #define R12A_ARFR_5G(i) (0x444 + (i) * 8)
46 #define R12A_CCK_CHECK 0x454
47 #define R12A_AMPDU_MAX_TIME 0x456
48 #define R12A_AMPDU_MAX_LENGTH R92C_AGGLEN_LMT
49 #define R12A_DATA_SEC 0x483
50 #define R12A_ARFR_2G(i) (0x48c + (i) * 8)
51 #define R12A_HT_SINGLE_AMPDU 0x4c7
54 /* Bits for R92C_MAC_PHY_CTRL. */
55 #define R12A_MAC_PHY_CRYSTALCAP_M 0x7ff80000
56 #define R12A_MAC_PHY_CRYSTALCAP_S 19
58 /* Bits for R92C_LEDCFG2. */
59 #define R12A_LEDCFG2_ENA 0x20
61 /* Bits for R12A_RXDMA_PRO. */
62 #define R12A_DMA_MODE 0x02
63 #define R12A_BURST_CNT_M 0x0c
64 #define R12A_BURST_CNT_S 2
65 #define R12A_BURST_SZ_M 0x30
66 #define R12A_BURST_SZ_S 4
67 #define R12A_BURST_SZ_USB3 0
68 #define R12A_BURST_SZ_USB2 1
69 #define R12A_BURST_SZ_USB1 2
71 /* Bits for R12A_CCK_CHECK. */
72 #define R12A_CCK_CHECK_BCN1 0x20
73 #define R12A_CCK_CHECK_5GHZ 0x80
75 /* Bits for R12A_DATA_SEC. */
76 #define R12A_DATA_SEC_NO_EXT 0x00
77 #define R12A_DATA_SEC_PRIM_UP_20 0x01
78 #define R12A_DATA_SEC_PRIM_DOWN_20 0x02
79 #define R12A_DATA_SEC_PRIM_UPPER_20 0x03
80 #define R12A_DATA_SEC_PRIM_LOWER_20 0x04
81 #define R12A_DATA_SEC_PRIM_UP_40 0x90
82 #define R12A_DATA_SEC_PRIM_DOWN_40 0xa0
84 /* Bits for R12A_HT_SINGLE_AMPDU. */
85 #define R12A_HT_SINGLE_AMPDU_PKT_ENA 0x80
87 /* Bits for R92C_RCR. */
88 #define R12A_RCR_DIS_CHK_14 0x00200000
89 #define R12A_RCR_TCP_OFFLD_EN 0x02000000
90 #define R12A_RCR_VHT_ACK 0x04000000
96 #define R12A_CCK_RPT_FORMAT 0x804
97 #define R12A_OFDMCCK_EN 0x808
98 #define R12A_RX_PATH R12A_OFDMCCK_EN
99 #define R12A_TX_PATH 0x80c
100 #define R12A_TXAGC_TABLE_SELECT 0x82c
101 #define R12A_PWED_TH 0x830
102 #define R12A_BW_INDICATION 0x834
103 #define R12A_CCA_ON_SEC 0x838
104 #define R12A_L1_PEAK_TH 0x848
105 #define R12A_FC_AREA 0x860
106 #define R12A_RFMOD 0x8ac
107 #define R12A_HSSI_PARAM2 0x8b0
108 #define R12A_ADC_BUF_CLK 0x8c4
109 #define R12A_ANTSEL_SW 0x900
110 #define R12A_SINGLETONE_CONT_TX 0x914
111 #define R12A_CCK_RX_PATH 0xa04
112 #define R12A_HSSI_PARAM1(chain) (0xc00 + (chain) * 0x200)
113 #define R12A_TX_SCALE(chain) (0xc1c + (chain) * 0x200)
114 #define R12A_TXAGC_CCK11_1(chain) (0xc20 + (chain) * 0x200)
115 #define R12A_TXAGC_OFDM18_6(chain) (0xc24 + (chain) * 0x200)
116 #define R12A_TXAGC_OFDM54_24(chain) (0xc28 + (chain) * 0x200)
117 #define R12A_TXAGC_MCS3_0(chain) (0xc2c + (chain) * 0x200)
118 #define R12A_TXAGC_MCS7_4(chain) (0xc30 + (chain) * 0x200)
119 #define R12A_TXAGC_MCS11_8(chain) (0xc34 + (chain) * 0x200)
120 #define R12A_TXAGC_MCS15_12(chain) (0xc38 + (chain) * 0x200)
121 #define R12A_TXAGC_NSS1IX3_1IX0(chain) (0xc3c + (chain) * 0x200)
122 #define R12A_TXAGC_NSS1IX7_1IX4(chain) (0xc40 + (chain) * 0x200)
123 #define R12A_TXAGC_NSS2IX1_1IX8(chain) (0xc44 + (chain) * 0x200)
124 #define R12A_TXAGC_NSS2IX5_2IX2(chain) (0xc48 + (chain) * 0x200)
125 #define R12A_TXAGC_NSS2IX9_2IX6(chain) (0xc4c + (chain) * 0x200)
126 #define R12A_INITIAL_GAIN(chain) (0xc50 + (chain) * 0x200)
127 #define R12A_AFE_POWER_1(chain) (0xc60 + (chain) * 0x200)
128 #define R12A_AFE_POWER_2(chain) (0xc64 + (chain) * 0x200)
129 #define R12A_SLEEP_NAV(chain) (0xc80 + (chain) * 0x200)
130 #define R12A_PMPD(chain) (0xc84 + (chain) * 0x200)
131 #define R12A_LSSI_PARAM(chain) (0xc90 + (chain) * 0x200)
132 #define R12A_RFE_PINMUX(chain) (0xcb0 + (chain) * 0x200)
133 #define R12A_RFE_INV(chain) (0xcb4 + (chain) * 0x200)
134 #define R12A_RFE(chain) (0xcb8 + (chain) * 0x200)
135 #define R12A_HSPI_READBACK(chain) (0xd04 + (chain) * 0x40)
136 #define R12A_LSSI_READBACK(chain) (0xd08 + (chain) * 0x40)
138 /* Bits for R12A_CCK_RPT_FORMAT. */
139 #define R12A_CCK_RPT_FORMAT_HIPWR 0x00010000
141 /* Bits for R12A_OFDMCCK_EN. */
142 #define R12A_OFDMCCK_EN_CCK 0x10000000
143 #define R12A_OFDMCCK_EN_OFDM 0x20000000
145 /* Bits for R12A_CCA_ON_SEC. */
146 #define R12A_CCA_ON_SEC_EXT_CHAN_M 0xf0000000
147 #define R12A_CCA_ON_SEC_EXT_CHAN_S 28
149 /* Bits for R12A_RFE_PINMUX(i). */
150 #define R12A_RFE_PINMUX_PA_A_MASK 0x000000f0
151 #define R12A_RFE_PINMUX_LNA_MASK 0x0000f000
153 /* Bits for R12A_RFMOD. */
154 #define R12A_RFMOD_EXT_CHAN_M 0x3C
155 #define R12A_RFMOD_EXT_CHAN_S 2
157 /* Bits for R12A_HSSI_PARAM2. */
158 #define R12A_HSSI_PARAM2_READ_ADDR_MASK 0xff
160 /* Bits for R12A_HSSI_PARAM1(i). */
161 #define R12A_HSSI_PARAM1_PI 0x00000004
163 /* Bits for R12A_TX_SCALE(i). */
164 #define R12A_TX_SCALE_SWING_M 0xffe00000
165 #define R12A_TX_SCALE_SWING_S 21
167 /* Bits for R12A_TXAGC_CCK11_1(i). */
168 #define R12A_TXAGC_CCK1_M 0x000000ff
169 #define R12A_TXAGC_CCK1_S 0
170 #define R12A_TXAGC_CCK2_M 0x0000ff00
171 #define R12A_TXAGC_CCK2_S 8
172 #define R12A_TXAGC_CCK55_M 0x00ff0000
173 #define R12A_TXAGC_CCK55_S 16
174 #define R12A_TXAGC_CCK11_M 0xff000000
175 #define R12A_TXAGC_CCK11_S 24
177 /* Bits for R12A_TXAGC_OFDM18_6(i). */
178 #define R12A_TXAGC_OFDM06_M 0x000000ff
179 #define R12A_TXAGC_OFDM06_S 0
180 #define R12A_TXAGC_OFDM09_M 0x0000ff00
181 #define R12A_TXAGC_OFDM09_S 8
182 #define R12A_TXAGC_OFDM12_M 0x00ff0000
183 #define R12A_TXAGC_OFDM12_S 16
184 #define R12A_TXAGC_OFDM18_M 0xff000000
185 #define R12A_TXAGC_OFDM18_S 24
187 /* Bits for R12A_TXAGC_OFDM54_24(i). */
188 #define R12A_TXAGC_OFDM24_M 0x000000ff
189 #define R12A_TXAGC_OFDM24_S 0
190 #define R12A_TXAGC_OFDM36_M 0x0000ff00
191 #define R12A_TXAGC_OFDM36_S 8
192 #define R12A_TXAGC_OFDM48_M 0x00ff0000
193 #define R12A_TXAGC_OFDM48_S 16
194 #define R12A_TXAGC_OFDM54_M 0xff000000
195 #define R12A_TXAGC_OFDM54_S 24
197 /* Bits for R12A_TXAGC_MCS3_0(i). */
198 #define R12A_TXAGC_MCS0_M 0x000000ff
199 #define R12A_TXAGC_MCS0_S 0
200 #define R12A_TXAGC_MCS1_M 0x0000ff00
201 #define R12A_TXAGC_MCS1_S 8
202 #define R12A_TXAGC_MCS2_M 0x00ff0000
203 #define R12A_TXAGC_MCS2_S 16
204 #define R12A_TXAGC_MCS3_M 0xff000000
205 #define R12A_TXAGC_MCS3_S 24
207 /* Bits for R12A_TXAGC_MCS7_4(i). */
208 #define R12A_TXAGC_MCS4_M 0x000000ff
209 #define R12A_TXAGC_MCS4_S 0
210 #define R12A_TXAGC_MCS5_M 0x0000ff00
211 #define R12A_TXAGC_MCS5_S 8
212 #define R12A_TXAGC_MCS6_M 0x00ff0000
213 #define R12A_TXAGC_MCS6_S 16
214 #define R12A_TXAGC_MCS7_M 0xff000000
215 #define R12A_TXAGC_MCS7_S 24
217 /* Bits for R12A_TXAGC_MCS11_8(i). */
218 #define R12A_TXAGC_MCS8_M 0x000000ff
219 #define R12A_TXAGC_MCS8_S 0
220 #define R12A_TXAGC_MCS9_M 0x0000ff00
221 #define R12A_TXAGC_MCS9_S 8
222 #define R12A_TXAGC_MCS10_M 0x00ff0000
223 #define R12A_TXAGC_MCS10_S 16
224 #define R12A_TXAGC_MCS11_M 0xff000000
225 #define R12A_TXAGC_MCS11_S 24
227 /* Bits for R12A_TXAGC_MCS15_12(i). */
228 #define R12A_TXAGC_MCS12_M 0x000000ff
229 #define R12A_TXAGC_MCS12_S 0
230 #define R12A_TXAGC_MCS13_M 0x0000ff00
231 #define R12A_TXAGC_MCS13_S 8
232 #define R12A_TXAGC_MCS14_M 0x00ff0000
233 #define R12A_TXAGC_MCS14_S 16
234 #define R12A_TXAGC_MCS15_M 0xff000000
235 #define R12A_TXAGC_MCS15_S 24
239 * RF (6052) registers.
241 #define R12A_RF_LCK 0xb4
243 /* Bits for R12A_RF_LCK. */
244 #define R12A_RF_LCK_MODE 0x4000
246 #endif /* R12A_REG_H */