2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2003 Sam Leffler, Errno Consulting
5 * Copyright (c) 2003 Global Technology Associates, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * SafeNet SafeXcel-1141 hardware crypto accelerator
38 #include <sys/param.h>
39 #include <sys/systm.h>
41 #include <sys/errno.h>
42 #include <sys/malloc.h>
43 #include <sys/kernel.h>
45 #include <sys/module.h>
47 #include <sys/mutex.h>
48 #include <sys/sysctl.h>
49 #include <sys/endian.h>
54 #include <machine/bus.h>
55 #include <machine/resource.h>
59 #include <crypto/sha1.h>
60 #include <opencrypto/cryptodev.h>
61 #include <opencrypto/cryptosoft.h>
63 #include <sys/random.h>
66 #include "cryptodev_if.h"
68 #include <dev/pci/pcivar.h>
69 #include <dev/pci/pcireg.h>
72 #include <dev/rndtest/rndtest.h>
74 #include <dev/safe/safereg.h>
75 #include <dev/safe/safevar.h>
82 * Prototypes and count for the pci_device structure
84 static int safe_probe(device_t);
85 static int safe_attach(device_t);
86 static int safe_detach(device_t);
87 static int safe_suspend(device_t);
88 static int safe_resume(device_t);
89 static int safe_shutdown(device_t);
91 static int safe_newsession(device_t, crypto_session_t, struct cryptoini *);
92 static int safe_process(device_t, struct cryptop *, int);
94 static device_method_t safe_methods[] = {
95 /* Device interface */
96 DEVMETHOD(device_probe, safe_probe),
97 DEVMETHOD(device_attach, safe_attach),
98 DEVMETHOD(device_detach, safe_detach),
99 DEVMETHOD(device_suspend, safe_suspend),
100 DEVMETHOD(device_resume, safe_resume),
101 DEVMETHOD(device_shutdown, safe_shutdown),
103 /* crypto device methods */
104 DEVMETHOD(cryptodev_newsession, safe_newsession),
105 DEVMETHOD(cryptodev_process, safe_process),
109 static driver_t safe_driver = {
112 sizeof (struct safe_softc)
114 static devclass_t safe_devclass;
116 DRIVER_MODULE(safe, pci, safe_driver, safe_devclass, 0, 0);
117 MODULE_DEPEND(safe, crypto, 1, 1, 1);
119 MODULE_DEPEND(safe, rndtest, 1, 1, 1);
122 static void safe_intr(void *);
123 static void safe_callback(struct safe_softc *, struct safe_ringentry *);
124 static void safe_feed(struct safe_softc *, struct safe_ringentry *);
125 static void safe_mcopy(struct mbuf *, struct mbuf *, u_int);
127 static void safe_rng_init(struct safe_softc *);
128 static void safe_rng(void *);
129 #endif /* SAFE_NO_RNG */
130 static int safe_dma_malloc(struct safe_softc *, bus_size_t,
131 struct safe_dma_alloc *, int);
132 #define safe_dma_sync(_dma, _flags) \
133 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags))
134 static void safe_dma_free(struct safe_softc *, struct safe_dma_alloc *);
135 static int safe_dmamap_aligned(const struct safe_operand *);
136 static int safe_dmamap_uniform(const struct safe_operand *);
138 static void safe_reset_board(struct safe_softc *);
139 static void safe_init_board(struct safe_softc *);
140 static void safe_init_pciregs(device_t dev);
141 static void safe_cleanchip(struct safe_softc *);
142 static void safe_totalreset(struct safe_softc *);
144 static int safe_free_entry(struct safe_softc *, struct safe_ringentry *);
146 static SYSCTL_NODE(_hw, OID_AUTO, safe, CTLFLAG_RD, 0,
147 "SafeNet driver parameters");
150 static void safe_dump_dmastatus(struct safe_softc *, const char *);
151 static void safe_dump_ringstate(struct safe_softc *, const char *);
152 static void safe_dump_intrstate(struct safe_softc *, const char *);
153 static void safe_dump_request(struct safe_softc *, const char *,
154 struct safe_ringentry *);
156 static struct safe_softc *safec; /* for use by hw.safe.dump */
158 static int safe_debug = 0;
159 SYSCTL_INT(_hw_safe, OID_AUTO, debug, CTLFLAG_RW, &safe_debug,
160 0, "control debugging msgs");
161 #define DPRINTF(_x) if (safe_debug) printf _x
166 #define READ_REG(sc,r) \
167 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r))
169 #define WRITE_REG(sc,reg,val) \
170 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val)
172 struct safe_stats safestats;
173 SYSCTL_STRUCT(_hw_safe, OID_AUTO, stats, CTLFLAG_RD, &safestats,
174 safe_stats, "driver statistics");
176 static int safe_rnginterval = 1; /* poll once a second */
177 SYSCTL_INT(_hw_safe, OID_AUTO, rnginterval, CTLFLAG_RW, &safe_rnginterval,
178 0, "RNG polling interval (secs)");
179 static int safe_rngbufsize = 16; /* 64 bytes each poll */
180 SYSCTL_INT(_hw_safe, OID_AUTO, rngbufsize, CTLFLAG_RW, &safe_rngbufsize,
181 0, "RNG polling buffer size (32-bit words)");
182 static int safe_rngmaxalarm = 8; /* max alarms before reset */
183 SYSCTL_INT(_hw_safe, OID_AUTO, rngmaxalarm, CTLFLAG_RW, &safe_rngmaxalarm,
184 0, "RNG max alarms before reset");
185 #endif /* SAFE_NO_RNG */
188 safe_probe(device_t dev)
190 if (pci_get_vendor(dev) == PCI_VENDOR_SAFENET &&
191 pci_get_device(dev) == PCI_PRODUCT_SAFEXCEL)
192 return (BUS_PROBE_DEFAULT);
197 safe_partname(struct safe_softc *sc)
199 /* XXX sprintf numbers when not decoded */
200 switch (pci_get_vendor(sc->sc_dev)) {
201 case PCI_VENDOR_SAFENET:
202 switch (pci_get_device(sc->sc_dev)) {
203 case PCI_PRODUCT_SAFEXCEL: return "SafeNet SafeXcel-1141";
205 return "SafeNet unknown-part";
207 return "Unknown-vendor unknown-part";
212 default_harvest(struct rndtest_state *rsp, void *buf, u_int count)
214 /* MarkM: FIX!! Check that this does not swamp the harvester! */
215 random_harvest_queue(buf, count, RANDOM_PURE_SAFE);
217 #endif /* SAFE_NO_RNG */
220 safe_attach(device_t dev)
222 struct safe_softc *sc = device_get_softc(dev);
224 u_int32_t i, devinfo;
227 bzero(sc, sizeof (*sc));
230 /* XXX handle power management */
232 pci_enable_busmaster(dev);
235 * Setup memory-mapping of PCI registers.
238 sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
240 if (sc->sc_sr == NULL) {
241 device_printf(dev, "cannot map register space\n");
244 sc->sc_st = rman_get_bustag(sc->sc_sr);
245 sc->sc_sh = rman_get_bushandle(sc->sc_sr);
248 * Arrange interrupt line.
251 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
252 RF_SHAREABLE|RF_ACTIVE);
253 if (sc->sc_irq == NULL) {
254 device_printf(dev, "could not map interrupt\n");
258 * NB: Network code assumes we are blocked with splimp()
259 * so make sure the IRQ is mapped appropriately.
261 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE,
262 NULL, safe_intr, sc, &sc->sc_ih)) {
263 device_printf(dev, "could not establish interrupt\n");
267 sc->sc_cid = crypto_get_driverid(dev, sizeof(struct safe_session),
268 CRYPTOCAP_F_HARDWARE);
269 if (sc->sc_cid < 0) {
270 device_printf(dev, "could not get crypto driver id\n");
274 sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) &
275 (SAFE_DEVINFO_REV_MAJ | SAFE_DEVINFO_REV_MIN);
278 * Setup DMA descriptor area.
280 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
282 SAFE_DMA_BOUNDARY, /* boundary */
283 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
284 BUS_SPACE_MAXADDR, /* highaddr */
285 NULL, NULL, /* filter, filterarg */
286 SAFE_MAX_DMA, /* maxsize */
287 SAFE_MAX_PART, /* nsegments */
288 SAFE_MAX_SSIZE, /* maxsegsize */
289 BUS_DMA_ALLOCNOW, /* flags */
290 NULL, NULL, /* locking */
292 device_printf(dev, "cannot allocate DMA tag\n");
295 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
297 SAFE_MAX_DSIZE, /* boundary */
298 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
299 BUS_SPACE_MAXADDR, /* highaddr */
300 NULL, NULL, /* filter, filterarg */
301 SAFE_MAX_DMA, /* maxsize */
302 SAFE_MAX_PART, /* nsegments */
303 SAFE_MAX_DSIZE, /* maxsegsize */
304 BUS_DMA_ALLOCNOW, /* flags */
305 NULL, NULL, /* locking */
307 device_printf(dev, "cannot allocate DMA tag\n");
312 * Allocate packet engine descriptors.
314 if (safe_dma_malloc(sc,
315 SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry),
316 &sc->sc_ringalloc, 0)) {
317 device_printf(dev, "cannot allocate PE descriptor ring\n");
318 bus_dma_tag_destroy(sc->sc_srcdmat);
322 * Hookup the static portion of all our data structures.
324 sc->sc_ring = (struct safe_ringentry *) sc->sc_ringalloc.dma_vaddr;
325 sc->sc_ringtop = sc->sc_ring + SAFE_MAX_NQUEUE;
326 sc->sc_front = sc->sc_ring;
327 sc->sc_back = sc->sc_ring;
328 raddr = sc->sc_ringalloc.dma_paddr;
329 bzero(sc->sc_ring, SAFE_MAX_NQUEUE * sizeof(struct safe_ringentry));
330 for (i = 0; i < SAFE_MAX_NQUEUE; i++) {
331 struct safe_ringentry *re = &sc->sc_ring[i];
333 re->re_desc.d_sa = raddr +
334 offsetof(struct safe_ringentry, re_sa);
335 re->re_sa.sa_staterec = raddr +
336 offsetof(struct safe_ringentry, re_sastate);
338 raddr += sizeof (struct safe_ringentry);
340 mtx_init(&sc->sc_ringmtx, device_get_nameunit(dev),
341 "packet engine ring", MTX_DEF);
344 * Allocate scatter and gather particle descriptors.
346 if (safe_dma_malloc(sc, SAFE_TOTAL_SPART * sizeof (struct safe_pdesc),
347 &sc->sc_spalloc, 0)) {
348 device_printf(dev, "cannot allocate source particle "
349 "descriptor ring\n");
350 mtx_destroy(&sc->sc_ringmtx);
351 safe_dma_free(sc, &sc->sc_ringalloc);
352 bus_dma_tag_destroy(sc->sc_srcdmat);
355 sc->sc_spring = (struct safe_pdesc *) sc->sc_spalloc.dma_vaddr;
356 sc->sc_springtop = sc->sc_spring + SAFE_TOTAL_SPART;
357 sc->sc_spfree = sc->sc_spring;
358 bzero(sc->sc_spring, SAFE_TOTAL_SPART * sizeof(struct safe_pdesc));
360 if (safe_dma_malloc(sc, SAFE_TOTAL_DPART * sizeof (struct safe_pdesc),
361 &sc->sc_dpalloc, 0)) {
362 device_printf(dev, "cannot allocate destination particle "
363 "descriptor ring\n");
364 mtx_destroy(&sc->sc_ringmtx);
365 safe_dma_free(sc, &sc->sc_spalloc);
366 safe_dma_free(sc, &sc->sc_ringalloc);
367 bus_dma_tag_destroy(sc->sc_dstdmat);
370 sc->sc_dpring = (struct safe_pdesc *) sc->sc_dpalloc.dma_vaddr;
371 sc->sc_dpringtop = sc->sc_dpring + SAFE_TOTAL_DPART;
372 sc->sc_dpfree = sc->sc_dpring;
373 bzero(sc->sc_dpring, SAFE_TOTAL_DPART * sizeof(struct safe_pdesc));
375 device_printf(sc->sc_dev, "%s", safe_partname(sc));
377 devinfo = READ_REG(sc, SAFE_DEVINFO);
378 if (devinfo & SAFE_DEVINFO_RNG) {
379 sc->sc_flags |= SAFE_FLAGS_RNG;
382 if (devinfo & SAFE_DEVINFO_PKEY) {
385 sc->sc_flags |= SAFE_FLAGS_KEY;
386 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0);
387 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0);
390 if (devinfo & SAFE_DEVINFO_DES) {
392 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0);
393 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0);
395 if (devinfo & SAFE_DEVINFO_AES) {
397 crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0);
399 if (devinfo & SAFE_DEVINFO_MD5) {
401 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0);
403 if (devinfo & SAFE_DEVINFO_SHA1) {
405 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0);
408 crypto_register(sc->sc_cid, CRYPTO_NULL_CBC, 0, 0);
409 crypto_register(sc->sc_cid, CRYPTO_NULL_HMAC, 0, 0);
410 /* XXX other supported algorithms */
413 safe_reset_board(sc); /* reset h/w */
414 safe_init_pciregs(dev); /* init pci settings */
415 safe_init_board(sc); /* init h/w */
418 if (sc->sc_flags & SAFE_FLAGS_RNG) {
420 sc->sc_rndtest = rndtest_attach(dev);
422 sc->sc_harvest = rndtest_harvest;
424 sc->sc_harvest = default_harvest;
426 sc->sc_harvest = default_harvest;
430 callout_init(&sc->sc_rngto, 1);
431 callout_reset(&sc->sc_rngto, hz*safe_rnginterval, safe_rng, sc);
433 #endif /* SAFE_NO_RNG */
435 safec = sc; /* for use by hw.safe.dump */
439 crypto_unregister_all(sc->sc_cid);
441 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
443 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
445 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
451 * Detach a device that successfully probed.
454 safe_detach(device_t dev)
456 struct safe_softc *sc = device_get_softc(dev);
458 /* XXX wait/abort active ops */
460 WRITE_REG(sc, SAFE_HI_MASK, 0); /* disable interrupts */
462 callout_stop(&sc->sc_rngto);
464 crypto_unregister_all(sc->sc_cid);
468 rndtest_detach(sc->sc_rndtest);
472 safe_dma_free(sc, &sc->sc_dpalloc);
473 safe_dma_free(sc, &sc->sc_spalloc);
474 mtx_destroy(&sc->sc_ringmtx);
475 safe_dma_free(sc, &sc->sc_ringalloc);
477 bus_generic_detach(dev);
478 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
479 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
481 bus_dma_tag_destroy(sc->sc_srcdmat);
482 bus_dma_tag_destroy(sc->sc_dstdmat);
483 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
489 * Stop all chip i/o so that the kernel's probe routines don't
490 * get confused by errant DMAs when rebooting.
493 safe_shutdown(device_t dev)
496 safe_stop(device_get_softc(dev));
502 * Device suspend routine.
505 safe_suspend(device_t dev)
507 struct safe_softc *sc = device_get_softc(dev);
510 /* XXX stop the device and save PCI settings */
512 sc->sc_suspended = 1;
518 safe_resume(device_t dev)
520 struct safe_softc *sc = device_get_softc(dev);
523 /* XXX retore PCI settings and start the device */
525 sc->sc_suspended = 0;
530 * SafeXcel Interrupt routine
535 struct safe_softc *sc = arg;
536 volatile u_int32_t stat;
538 stat = READ_REG(sc, SAFE_HM_STAT);
539 if (stat == 0) /* shared irq, not for us */
542 WRITE_REG(sc, SAFE_HI_CLR, stat); /* IACK */
544 if ((stat & SAFE_INT_PE_DDONE)) {
546 * Descriptor(s) done; scan the ring and
547 * process completed operations.
549 mtx_lock(&sc->sc_ringmtx);
550 while (sc->sc_back != sc->sc_front) {
551 struct safe_ringentry *re = sc->sc_back;
554 safe_dump_ringstate(sc, __func__);
555 safe_dump_request(sc, __func__, re);
559 * safe_process marks ring entries that were allocated
560 * but not used with a csr of zero. This insures the
561 * ring front pointer never needs to be set backwards
562 * in the event that an entry is allocated but not used
563 * because of a setup error.
565 if (re->re_desc.d_csr != 0) {
566 if (!SAFE_PE_CSR_IS_DONE(re->re_desc.d_csr))
568 if (!SAFE_PE_LEN_IS_DONE(re->re_desc.d_len))
571 safe_callback(sc, re);
573 if (++(sc->sc_back) == sc->sc_ringtop)
574 sc->sc_back = sc->sc_ring;
576 mtx_unlock(&sc->sc_ringmtx);
580 * Check to see if we got any DMA Error
582 if (stat & SAFE_INT_PE_ERROR) {
583 DPRINTF(("dmaerr dmastat %08x\n",
584 READ_REG(sc, SAFE_PE_DMASTAT)));
585 safestats.st_dmaerr++;
592 if (sc->sc_needwakeup) { /* XXX check high watermark */
593 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ);
594 DPRINTF(("%s: wakeup crypto %x\n", __func__,
596 sc->sc_needwakeup &= ~wakeup;
597 crypto_unblock(sc->sc_cid, wakeup);
602 * safe_feed() - post a request to chip
605 safe_feed(struct safe_softc *sc, struct safe_ringentry *re)
607 bus_dmamap_sync(sc->sc_srcdmat, re->re_src_map, BUS_DMASYNC_PREWRITE);
608 if (re->re_dst_map != NULL)
609 bus_dmamap_sync(sc->sc_dstdmat, re->re_dst_map,
610 BUS_DMASYNC_PREREAD);
611 /* XXX have no smaller granularity */
612 safe_dma_sync(&sc->sc_ringalloc,
613 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
614 safe_dma_sync(&sc->sc_spalloc, BUS_DMASYNC_PREWRITE);
615 safe_dma_sync(&sc->sc_dpalloc, BUS_DMASYNC_PREWRITE);
619 safe_dump_ringstate(sc, __func__);
620 safe_dump_request(sc, __func__, re);
624 if (sc->sc_nqchip > safestats.st_maxqchip)
625 safestats.st_maxqchip = sc->sc_nqchip;
626 /* poke h/w to check descriptor ring, any value can be written */
627 WRITE_REG(sc, SAFE_HI_RD_DESCR, 0);
630 #define N(a) (sizeof(a) / sizeof (a[0]))
632 safe_setup_enckey(struct safe_session *ses, caddr_t key)
636 bcopy(key, ses->ses_key, ses->ses_klen / 8);
638 /* PE is little-endian, insure proper byte order */
639 for (i = 0; i < N(ses->ses_key); i++)
640 ses->ses_key[i] = htole32(ses->ses_key[i]);
644 safe_setup_mackey(struct safe_session *ses, int algo, caddr_t key, int klen)
651 for (i = 0; i < klen; i++)
652 key[i] ^= HMAC_IPAD_VAL;
654 if (algo == CRYPTO_MD5_HMAC) {
656 MD5Update(&md5ctx, key, klen);
657 MD5Update(&md5ctx, hmac_ipad_buffer, MD5_BLOCK_LEN - klen);
658 bcopy(md5ctx.state, ses->ses_hminner, sizeof(md5ctx.state));
661 SHA1Update(&sha1ctx, key, klen);
662 SHA1Update(&sha1ctx, hmac_ipad_buffer,
663 SHA1_BLOCK_LEN - klen);
664 bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32));
667 for (i = 0; i < klen; i++)
668 key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL);
670 if (algo == CRYPTO_MD5_HMAC) {
672 MD5Update(&md5ctx, key, klen);
673 MD5Update(&md5ctx, hmac_opad_buffer, MD5_BLOCK_LEN - klen);
674 bcopy(md5ctx.state, ses->ses_hmouter, sizeof(md5ctx.state));
677 SHA1Update(&sha1ctx, key, klen);
678 SHA1Update(&sha1ctx, hmac_opad_buffer,
679 SHA1_BLOCK_LEN - klen);
680 bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32));
683 for (i = 0; i < klen; i++)
684 key[i] ^= HMAC_OPAD_VAL;
686 /* PE is little-endian, insure proper byte order */
687 for (i = 0; i < N(ses->ses_hminner); i++) {
688 ses->ses_hminner[i] = htole32(ses->ses_hminner[i]);
689 ses->ses_hmouter[i] = htole32(ses->ses_hmouter[i]);
695 * Allocate a new 'session' and return an encoded session id. 'sidp'
696 * contains our registration id, and should contain an encoded session
697 * id on successful allocation.
700 safe_newsession(device_t dev, crypto_session_t cses, struct cryptoini *cri)
702 struct safe_softc *sc = device_get_softc(dev);
703 struct cryptoini *c, *encini = NULL, *macini = NULL;
704 struct safe_session *ses = NULL;
706 if (cri == NULL || sc == NULL)
709 for (c = cri; c != NULL; c = c->cri_next) {
710 if (c->cri_alg == CRYPTO_MD5_HMAC ||
711 c->cri_alg == CRYPTO_SHA1_HMAC ||
712 c->cri_alg == CRYPTO_NULL_HMAC) {
716 } else if (c->cri_alg == CRYPTO_DES_CBC ||
717 c->cri_alg == CRYPTO_3DES_CBC ||
718 c->cri_alg == CRYPTO_AES_CBC ||
719 c->cri_alg == CRYPTO_NULL_CBC) {
726 if (encini == NULL && macini == NULL)
728 if (encini) { /* validate key length */
729 switch (encini->cri_alg) {
731 if (encini->cri_klen != 64)
734 case CRYPTO_3DES_CBC:
735 if (encini->cri_klen != 192)
739 if (encini->cri_klen != 128 &&
740 encini->cri_klen != 192 &&
741 encini->cri_klen != 256)
747 ses = crypto_get_driver_session(cses);
750 /* XXX may read fewer than requested */
751 read_random(ses->ses_iv, sizeof(ses->ses_iv));
753 ses->ses_klen = encini->cri_klen;
754 if (encini->cri_key != NULL)
755 safe_setup_enckey(ses, encini->cri_key);
759 ses->ses_mlen = macini->cri_mlen;
760 if (ses->ses_mlen == 0) {
761 if (macini->cri_alg == CRYPTO_MD5_HMAC)
762 ses->ses_mlen = MD5_HASH_LEN;
764 ses->ses_mlen = SHA1_HASH_LEN;
767 if (macini->cri_key != NULL) {
768 safe_setup_mackey(ses, macini->cri_alg, macini->cri_key,
769 macini->cri_klen / 8);
777 safe_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error)
779 struct safe_operand *op = arg;
781 DPRINTF(("%s: mapsize %u nsegs %d error %d\n", __func__,
782 (u_int) mapsize, nsegs, error));
785 op->mapsize = mapsize;
787 bcopy(seg, op->segs, nsegs * sizeof (seg[0]));
791 safe_process(device_t dev, struct cryptop *crp, int hint)
793 struct safe_softc *sc = device_get_softc(dev);
794 int err = 0, i, nicealign, uniform;
795 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
796 int bypass, oplen, ivsize;
799 struct safe_session *ses;
800 struct safe_ringentry *re;
801 struct safe_sarec *sa;
802 struct safe_pdesc *pd;
803 u_int32_t cmd0, cmd1, staterec;
805 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) {
806 safestats.st_invalid++;
810 mtx_lock(&sc->sc_ringmtx);
811 if (sc->sc_front == sc->sc_back && sc->sc_nqchip != 0) {
812 safestats.st_ringfull++;
813 sc->sc_needwakeup |= CRYPTO_SYMQ;
814 mtx_unlock(&sc->sc_ringmtx);
819 staterec = re->re_sa.sa_staterec; /* save */
820 /* NB: zero everything but the PE descriptor */
821 bzero(&re->re_sa, sizeof(struct safe_ringentry) - sizeof(re->re_desc));
822 re->re_sa.sa_staterec = staterec; /* restore */
826 if (crp->crp_flags & CRYPTO_F_IMBUF) {
827 re->re_src_m = (struct mbuf *)crp->crp_buf;
828 re->re_dst_m = (struct mbuf *)crp->crp_buf;
829 } else if (crp->crp_flags & CRYPTO_F_IOV) {
830 re->re_src_io = (struct uio *)crp->crp_buf;
831 re->re_dst_io = (struct uio *)crp->crp_buf;
833 safestats.st_badflags++;
835 goto errout; /* XXX we don't handle contiguous blocks! */
839 ses = crypto_get_driver_session(crp->crp_session);
841 crd1 = crp->crp_desc;
843 safestats.st_nodesc++;
847 crd2 = crd1->crd_next;
849 cmd0 = SAFE_SA_CMD0_BASIC; /* basic group operation */
852 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
853 crd1->crd_alg == CRYPTO_SHA1_HMAC ||
854 crd1->crd_alg == CRYPTO_NULL_HMAC) {
857 cmd0 |= SAFE_SA_CMD0_OP_HASH;
858 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
859 crd1->crd_alg == CRYPTO_3DES_CBC ||
860 crd1->crd_alg == CRYPTO_AES_CBC ||
861 crd1->crd_alg == CRYPTO_NULL_CBC) {
864 cmd0 |= SAFE_SA_CMD0_OP_CRYPT;
866 safestats.st_badalg++;
871 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
872 crd1->crd_alg == CRYPTO_SHA1_HMAC ||
873 crd1->crd_alg == CRYPTO_NULL_HMAC) &&
874 (crd2->crd_alg == CRYPTO_DES_CBC ||
875 crd2->crd_alg == CRYPTO_3DES_CBC ||
876 crd2->crd_alg == CRYPTO_AES_CBC ||
877 crd2->crd_alg == CRYPTO_NULL_CBC) &&
878 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
881 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
882 crd1->crd_alg == CRYPTO_3DES_CBC ||
883 crd1->crd_alg == CRYPTO_AES_CBC ||
884 crd1->crd_alg == CRYPTO_NULL_CBC) &&
885 (crd2->crd_alg == CRYPTO_MD5_HMAC ||
886 crd2->crd_alg == CRYPTO_SHA1_HMAC ||
887 crd2->crd_alg == CRYPTO_NULL_HMAC) &&
888 (crd1->crd_flags & CRD_F_ENCRYPT)) {
892 safestats.st_badalg++;
896 cmd0 |= SAFE_SA_CMD0_OP_BOTH;
900 if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT)
901 safe_setup_enckey(ses, enccrd->crd_key);
903 if (enccrd->crd_alg == CRYPTO_DES_CBC) {
904 cmd0 |= SAFE_SA_CMD0_DES;
905 cmd1 |= SAFE_SA_CMD1_CBC;
906 ivsize = 2*sizeof(u_int32_t);
907 } else if (enccrd->crd_alg == CRYPTO_3DES_CBC) {
908 cmd0 |= SAFE_SA_CMD0_3DES;
909 cmd1 |= SAFE_SA_CMD1_CBC;
910 ivsize = 2*sizeof(u_int32_t);
911 } else if (enccrd->crd_alg == CRYPTO_AES_CBC) {
912 cmd0 |= SAFE_SA_CMD0_AES;
913 cmd1 |= SAFE_SA_CMD1_CBC;
914 if (ses->ses_klen == 128)
915 cmd1 |= SAFE_SA_CMD1_AES128;
916 else if (ses->ses_klen == 192)
917 cmd1 |= SAFE_SA_CMD1_AES192;
919 cmd1 |= SAFE_SA_CMD1_AES256;
920 ivsize = 4*sizeof(u_int32_t);
922 cmd0 |= SAFE_SA_CMD0_CRYPT_NULL;
927 * Setup encrypt/decrypt state. When using basic ops
928 * we can't use an inline IV because hash/crypt offset
929 * must be from the end of the IV to the start of the
930 * crypt data and this leaves out the preceding header
931 * from the hash calculation. Instead we place the IV
932 * in the state record and set the hash/crypt offset to
933 * copy both the header+IV.
935 if (enccrd->crd_flags & CRD_F_ENCRYPT) {
936 cmd0 |= SAFE_SA_CMD0_OUTBOUND;
938 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
941 iv = (caddr_t) ses->ses_iv;
942 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) {
943 crypto_copyback(crp->crp_flags, crp->crp_buf,
944 enccrd->crd_inject, ivsize, iv);
946 bcopy(iv, re->re_sastate.sa_saved_iv, ivsize);
947 cmd0 |= SAFE_SA_CMD0_IVLD_STATE | SAFE_SA_CMD0_SAVEIV;
948 re->re_flags |= SAFE_QFLAGS_COPYOUTIV;
950 cmd0 |= SAFE_SA_CMD0_INBOUND;
952 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) {
953 bcopy(enccrd->crd_iv,
954 re->re_sastate.sa_saved_iv, ivsize);
956 crypto_copydata(crp->crp_flags, crp->crp_buf,
957 enccrd->crd_inject, ivsize,
958 (caddr_t)re->re_sastate.sa_saved_iv);
960 cmd0 |= SAFE_SA_CMD0_IVLD_STATE;
963 * For basic encryption use the zero pad algorithm.
964 * This pads results to an 8-byte boundary and
965 * suppresses padding verification for inbound (i.e.
966 * decrypt) operations.
968 * NB: Not sure if the 8-byte pad boundary is a problem.
970 cmd0 |= SAFE_SA_CMD0_PAD_ZERO;
972 /* XXX assert key bufs have the same size */
973 bcopy(ses->ses_key, sa->sa_key, sizeof(sa->sa_key));
977 if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
978 safe_setup_mackey(ses, maccrd->crd_alg,
979 maccrd->crd_key, maccrd->crd_klen / 8);
982 if (maccrd->crd_alg == CRYPTO_MD5_HMAC) {
983 cmd0 |= SAFE_SA_CMD0_MD5;
984 cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */
985 } else if (maccrd->crd_alg == CRYPTO_SHA1_HMAC) {
986 cmd0 |= SAFE_SA_CMD0_SHA1;
987 cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */
989 cmd0 |= SAFE_SA_CMD0_HASH_NULL;
992 * Digest data is loaded from the SA and the hash
993 * result is saved to the state block where we
994 * retrieve it for return to the caller.
996 /* XXX assert digest bufs have the same size */
997 bcopy(ses->ses_hminner, sa->sa_indigest,
998 sizeof(sa->sa_indigest));
999 bcopy(ses->ses_hmouter, sa->sa_outdigest,
1000 sizeof(sa->sa_outdigest));
1002 cmd0 |= SAFE_SA_CMD0_HSLD_SA | SAFE_SA_CMD0_SAVEHASH;
1003 re->re_flags |= SAFE_QFLAGS_COPYOUTICV;
1006 if (enccrd && maccrd) {
1008 * The offset from hash data to the start of
1009 * crypt data is the difference in the skips.
1011 bypass = maccrd->crd_skip;
1012 coffset = enccrd->crd_skip - maccrd->crd_skip;
1014 DPRINTF(("%s: hash does not precede crypt; "
1015 "mac skip %u enc skip %u\n",
1016 __func__, maccrd->crd_skip, enccrd->crd_skip));
1017 safestats.st_skipmismatch++;
1021 oplen = enccrd->crd_skip + enccrd->crd_len;
1022 if (maccrd->crd_skip + maccrd->crd_len != oplen) {
1023 DPRINTF(("%s: hash amount %u != crypt amount %u\n",
1024 __func__, maccrd->crd_skip + maccrd->crd_len,
1026 safestats.st_lenmismatch++;
1032 printf("mac: skip %d, len %d, inject %d\n",
1033 maccrd->crd_skip, maccrd->crd_len,
1034 maccrd->crd_inject);
1035 printf("enc: skip %d, len %d, inject %d\n",
1036 enccrd->crd_skip, enccrd->crd_len,
1037 enccrd->crd_inject);
1038 printf("bypass %d coffset %d oplen %d\n",
1039 bypass, coffset, oplen);
1042 if (coffset & 3) { /* offset must be 32-bit aligned */
1043 DPRINTF(("%s: coffset %u misaligned\n",
1044 __func__, coffset));
1045 safestats.st_coffmisaligned++;
1050 if (coffset > 255) { /* offset must be <256 dwords */
1051 DPRINTF(("%s: coffset %u too big\n",
1052 __func__, coffset));
1053 safestats.st_cofftoobig++;
1058 * Tell the hardware to copy the header to the output.
1059 * The header is defined as the data from the end of
1060 * the bypass to the start of data to be encrypted.
1061 * Typically this is the inline IV. Note that you need
1062 * to do this even if src+dst are the same; it appears
1063 * that w/o this bit the crypted data is written
1064 * immediately after the bypass data.
1066 cmd1 |= SAFE_SA_CMD1_HDRCOPY;
1068 * Disable IP header mutable bit handling. This is
1069 * needed to get correct HMAC calculations.
1071 cmd1 |= SAFE_SA_CMD1_MUTABLE;
1074 bypass = enccrd->crd_skip;
1075 oplen = bypass + enccrd->crd_len;
1077 bypass = maccrd->crd_skip;
1078 oplen = bypass + maccrd->crd_len;
1082 /* XXX verify multiple of 4 when using s/g */
1083 if (bypass > 96) { /* bypass offset must be <= 96 bytes */
1084 DPRINTF(("%s: bypass %u too big\n", __func__, bypass));
1085 safestats.st_bypasstoobig++;
1090 if (bus_dmamap_create(sc->sc_srcdmat, BUS_DMA_NOWAIT, &re->re_src_map)) {
1091 safestats.st_nomap++;
1095 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1096 if (bus_dmamap_load_mbuf(sc->sc_srcdmat, re->re_src_map,
1097 re->re_src_m, safe_op_cb,
1098 &re->re_src, BUS_DMA_NOWAIT) != 0) {
1099 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map);
1100 re->re_src_map = NULL;
1101 safestats.st_noload++;
1105 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1106 if (bus_dmamap_load_uio(sc->sc_srcdmat, re->re_src_map,
1107 re->re_src_io, safe_op_cb,
1108 &re->re_src, BUS_DMA_NOWAIT) != 0) {
1109 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map);
1110 re->re_src_map = NULL;
1111 safestats.st_noload++;
1116 nicealign = safe_dmamap_aligned(&re->re_src);
1117 uniform = safe_dmamap_uniform(&re->re_src);
1119 DPRINTF(("src nicealign %u uniform %u nsegs %u\n",
1120 nicealign, uniform, re->re_src.nsegs));
1121 if (re->re_src.nsegs > 1) {
1122 re->re_desc.d_src = sc->sc_spalloc.dma_paddr +
1123 ((caddr_t) sc->sc_spfree - (caddr_t) sc->sc_spring);
1124 for (i = 0; i < re->re_src_nsegs; i++) {
1125 /* NB: no need to check if there's space */
1127 if (++(sc->sc_spfree) == sc->sc_springtop)
1128 sc->sc_spfree = sc->sc_spring;
1130 KASSERT((pd->pd_flags&3) == 0 ||
1131 (pd->pd_flags&3) == SAFE_PD_DONE,
1132 ("bogus source particle descriptor; flags %x",
1134 pd->pd_addr = re->re_src_segs[i].ds_addr;
1135 pd->pd_size = re->re_src_segs[i].ds_len;
1136 pd->pd_flags = SAFE_PD_READY;
1138 cmd0 |= SAFE_SA_CMD0_IGATHER;
1141 * No need for gather, reference the operand directly.
1143 re->re_desc.d_src = re->re_src_segs[0].ds_addr;
1146 if (enccrd == NULL && maccrd != NULL) {
1148 * Hash op; no destination needed.
1151 if (crp->crp_flags & CRYPTO_F_IOV) {
1153 safestats.st_iovmisaligned++;
1159 * Source is not suitable for direct use as
1160 * the destination. Create a new scatter/gather
1161 * list based on the destination requirements
1162 * and check if that's ok.
1164 if (bus_dmamap_create(sc->sc_dstdmat,
1165 BUS_DMA_NOWAIT, &re->re_dst_map)) {
1166 safestats.st_nomap++;
1170 if (bus_dmamap_load_uio(sc->sc_dstdmat,
1171 re->re_dst_map, re->re_dst_io,
1172 safe_op_cb, &re->re_dst,
1173 BUS_DMA_NOWAIT) != 0) {
1174 bus_dmamap_destroy(sc->sc_dstdmat,
1176 re->re_dst_map = NULL;
1177 safestats.st_noload++;
1181 uniform = safe_dmamap_uniform(&re->re_dst);
1184 * There's no way to handle the DMA
1185 * requirements with this uio. We
1186 * could create a separate DMA area for
1187 * the result and then copy it back,
1188 * but for now we just bail and return
1189 * an error. Note that uio requests
1190 * > SAFE_MAX_DSIZE are handled because
1191 * the DMA map and segment list for the
1192 * destination wil result in a
1193 * destination particle list that does
1194 * the necessary scatter DMA.
1196 safestats.st_iovnotuniform++;
1201 re->re_dst = re->re_src;
1202 } else if (crp->crp_flags & CRYPTO_F_IMBUF) {
1203 if (nicealign && uniform == 1) {
1205 * Source layout is suitable for direct
1206 * sharing of the DMA map and segment list.
1208 re->re_dst = re->re_src;
1209 } else if (nicealign && uniform == 2) {
1211 * The source is properly aligned but requires a
1212 * different particle list to handle DMA of the
1213 * result. Create a new map and do the load to
1214 * create the segment list. The particle
1215 * descriptor setup code below will handle the
1218 if (bus_dmamap_create(sc->sc_dstdmat,
1219 BUS_DMA_NOWAIT, &re->re_dst_map)) {
1220 safestats.st_nomap++;
1224 if (bus_dmamap_load_mbuf(sc->sc_dstdmat,
1225 re->re_dst_map, re->re_dst_m,
1226 safe_op_cb, &re->re_dst,
1227 BUS_DMA_NOWAIT) != 0) {
1228 bus_dmamap_destroy(sc->sc_dstdmat,
1230 re->re_dst_map = NULL;
1231 safestats.st_noload++;
1235 } else { /* !(aligned and/or uniform) */
1237 struct mbuf *m, *top, **mp;
1240 * DMA constraints require that we allocate a
1241 * new mbuf chain for the destination. We
1242 * allocate an entire new set of mbufs of
1243 * optimal/required size and then tell the
1244 * hardware to copy any bits that are not
1245 * created as a byproduct of the operation.
1248 safestats.st_unaligned++;
1250 safestats.st_notuniform++;
1251 totlen = re->re_src_mapsize;
1252 if (re->re_src_m->m_flags & M_PKTHDR) {
1254 MGETHDR(m, M_NOWAIT, MT_DATA);
1255 if (m && !m_dup_pkthdr(m, re->re_src_m,
1262 MGET(m, M_NOWAIT, MT_DATA);
1265 safestats.st_nombuf++;
1266 err = sc->sc_nqchip ? ERESTART : ENOMEM;
1269 if (totlen >= MINCLSIZE) {
1270 if (!(MCLGET(m, M_NOWAIT))) {
1272 safestats.st_nomcl++;
1273 err = sc->sc_nqchip ?
1283 while (totlen > 0) {
1285 MGET(m, M_NOWAIT, MT_DATA);
1288 safestats.st_nombuf++;
1289 err = sc->sc_nqchip ?
1295 if (top && totlen >= MINCLSIZE) {
1296 if (!(MCLGET(m, M_NOWAIT))) {
1299 safestats.st_nomcl++;
1300 err = sc->sc_nqchip ?
1306 m->m_len = len = min(totlen, len);
1312 if (bus_dmamap_create(sc->sc_dstdmat,
1313 BUS_DMA_NOWAIT, &re->re_dst_map) != 0) {
1314 safestats.st_nomap++;
1318 if (bus_dmamap_load_mbuf(sc->sc_dstdmat,
1319 re->re_dst_map, re->re_dst_m,
1320 safe_op_cb, &re->re_dst,
1321 BUS_DMA_NOWAIT) != 0) {
1322 bus_dmamap_destroy(sc->sc_dstdmat,
1324 re->re_dst_map = NULL;
1325 safestats.st_noload++;
1329 if (re->re_src.mapsize > oplen) {
1331 * There's data following what the
1332 * hardware will copy for us. If this
1333 * isn't just the ICV (that's going to
1334 * be written on completion), copy it
1338 (re->re_src.mapsize-oplen) == 12 &&
1339 maccrd->crd_inject == oplen))
1340 safe_mcopy(re->re_src_m,
1344 safestats.st_noicvcopy++;
1348 safestats.st_badflags++;
1353 if (re->re_dst.nsegs > 1) {
1354 re->re_desc.d_dst = sc->sc_dpalloc.dma_paddr +
1355 ((caddr_t) sc->sc_dpfree - (caddr_t) sc->sc_dpring);
1356 for (i = 0; i < re->re_dst_nsegs; i++) {
1358 KASSERT((pd->pd_flags&3) == 0 ||
1359 (pd->pd_flags&3) == SAFE_PD_DONE,
1360 ("bogus dest particle descriptor; flags %x",
1362 if (++(sc->sc_dpfree) == sc->sc_dpringtop)
1363 sc->sc_dpfree = sc->sc_dpring;
1364 pd->pd_addr = re->re_dst_segs[i].ds_addr;
1365 pd->pd_flags = SAFE_PD_READY;
1367 cmd0 |= SAFE_SA_CMD0_OSCATTER;
1370 * No need for scatter, reference the operand directly.
1372 re->re_desc.d_dst = re->re_dst_segs[0].ds_addr;
1377 * All done with setup; fillin the SA command words
1378 * and the packet engine descriptor. The operation
1379 * is now ready for submission to the hardware.
1381 sa->sa_cmd0 = cmd0 | SAFE_SA_CMD0_IPCI | SAFE_SA_CMD0_OPCI;
1383 | (coffset << SAFE_SA_CMD1_OFFSET_S)
1384 | SAFE_SA_CMD1_SAREV1 /* Rev 1 SA data structure */
1385 | SAFE_SA_CMD1_SRPCI
1388 * NB: the order of writes is important here. In case the
1389 * chip is scanning the ring because of an outstanding request
1390 * it might nab this one too. In that case we need to make
1391 * sure the setup is complete before we write the length
1392 * field of the descriptor as it signals the descriptor is
1393 * ready for processing.
1395 re->re_desc.d_csr = SAFE_PE_CSR_READY | SAFE_PE_CSR_SAPCI;
1397 re->re_desc.d_csr |= SAFE_PE_CSR_LOADSA | SAFE_PE_CSR_HASHFINAL;
1398 re->re_desc.d_len = oplen
1400 | (bypass << SAFE_PE_LEN_BYPASS_S)
1403 safestats.st_ipackets++;
1404 safestats.st_ibytes += oplen;
1406 if (++(sc->sc_front) == sc->sc_ringtop)
1407 sc->sc_front = sc->sc_ring;
1409 /* XXX honor batching */
1411 mtx_unlock(&sc->sc_ringmtx);
1415 if ((re->re_dst_m != NULL) && (re->re_src_m != re->re_dst_m))
1416 m_freem(re->re_dst_m);
1418 if (re->re_dst_map != NULL && re->re_dst_map != re->re_src_map) {
1419 bus_dmamap_unload(sc->sc_dstdmat, re->re_dst_map);
1420 bus_dmamap_destroy(sc->sc_dstdmat, re->re_dst_map);
1422 if (re->re_src_map != NULL) {
1423 bus_dmamap_unload(sc->sc_srcdmat, re->re_src_map);
1424 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map);
1426 mtx_unlock(&sc->sc_ringmtx);
1427 if (err != ERESTART) {
1428 crp->crp_etype = err;
1431 sc->sc_needwakeup |= CRYPTO_SYMQ;
1437 safe_callback(struct safe_softc *sc, struct safe_ringentry *re)
1439 struct cryptop *crp = (struct cryptop *)re->re_crp;
1440 struct safe_session *ses;
1441 struct cryptodesc *crd;
1443 ses = crypto_get_driver_session(crp->crp_session);
1445 safestats.st_opackets++;
1446 safestats.st_obytes += re->re_dst.mapsize;
1448 safe_dma_sync(&sc->sc_ringalloc,
1449 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1450 if (re->re_desc.d_csr & SAFE_PE_CSR_STATUS) {
1451 device_printf(sc->sc_dev, "csr 0x%x cmd0 0x%x cmd1 0x%x\n",
1453 re->re_sa.sa_cmd0, re->re_sa.sa_cmd1);
1454 safestats.st_peoperr++;
1455 crp->crp_etype = EIO; /* something more meaningful? */
1457 if (re->re_dst_map != NULL && re->re_dst_map != re->re_src_map) {
1458 bus_dmamap_sync(sc->sc_dstdmat, re->re_dst_map,
1459 BUS_DMASYNC_POSTREAD);
1460 bus_dmamap_unload(sc->sc_dstdmat, re->re_dst_map);
1461 bus_dmamap_destroy(sc->sc_dstdmat, re->re_dst_map);
1463 bus_dmamap_sync(sc->sc_srcdmat, re->re_src_map, BUS_DMASYNC_POSTWRITE);
1464 bus_dmamap_unload(sc->sc_srcdmat, re->re_src_map);
1465 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map);
1468 * If result was written to a differet mbuf chain, swap
1469 * it in as the return value and reclaim the original.
1471 if ((crp->crp_flags & CRYPTO_F_IMBUF) && re->re_src_m != re->re_dst_m) {
1472 m_freem(re->re_src_m);
1473 crp->crp_buf = (caddr_t)re->re_dst_m;
1476 if (re->re_flags & SAFE_QFLAGS_COPYOUTIV) {
1477 /* copy out IV for future use */
1478 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1481 if (crd->crd_alg == CRYPTO_DES_CBC ||
1482 crd->crd_alg == CRYPTO_3DES_CBC) {
1483 ivsize = 2*sizeof(u_int32_t);
1484 } else if (crd->crd_alg == CRYPTO_AES_CBC) {
1485 ivsize = 4*sizeof(u_int32_t);
1488 crypto_copydata(crp->crp_flags, crp->crp_buf,
1489 crd->crd_skip + crd->crd_len - ivsize, ivsize,
1490 (caddr_t)ses->ses_iv);
1495 if (re->re_flags & SAFE_QFLAGS_COPYOUTICV) {
1496 /* copy out ICV result */
1497 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1498 if (!(crd->crd_alg == CRYPTO_MD5_HMAC ||
1499 crd->crd_alg == CRYPTO_SHA1_HMAC ||
1500 crd->crd_alg == CRYPTO_NULL_HMAC))
1502 if (crd->crd_alg == CRYPTO_SHA1_HMAC) {
1504 * SHA-1 ICV's are byte-swapped; fix 'em up
1505 * before copy them to their destination.
1507 re->re_sastate.sa_saved_indigest[0] =
1508 bswap32(re->re_sastate.sa_saved_indigest[0]);
1509 re->re_sastate.sa_saved_indigest[1] =
1510 bswap32(re->re_sastate.sa_saved_indigest[1]);
1511 re->re_sastate.sa_saved_indigest[2] =
1512 bswap32(re->re_sastate.sa_saved_indigest[2]);
1514 crypto_copyback(crp->crp_flags, crp->crp_buf,
1515 crd->crd_inject, ses->ses_mlen,
1516 (caddr_t)re->re_sastate.sa_saved_indigest);
1524 * Copy all data past offset from srcm to dstm.
1527 safe_mcopy(struct mbuf *srcm, struct mbuf *dstm, u_int offset)
1529 u_int j, dlen, slen;
1533 * Advance src and dst to offset.
1536 while (j >= srcm->m_len) {
1538 srcm = srcm->m_next;
1542 sptr = mtod(srcm, caddr_t) + j;
1543 slen = srcm->m_len - j;
1546 while (j >= dstm->m_len) {
1548 dstm = dstm->m_next;
1552 dptr = mtod(dstm, caddr_t) + j;
1553 dlen = dstm->m_len - j;
1556 * Copy everything that remains.
1559 j = min(slen, dlen);
1560 bcopy(sptr, dptr, j);
1562 srcm = srcm->m_next;
1565 sptr = srcm->m_data;
1568 sptr += j, slen -= j;
1570 dstm = dstm->m_next;
1573 dptr = dstm->m_data;
1576 dptr += j, dlen -= j;
1581 #define SAFE_RNG_MAXWAIT 1000
1584 safe_rng_init(struct safe_softc *sc)
1589 WRITE_REG(sc, SAFE_RNG_CTRL, 0);
1590 /* use default value according to the manual */
1591 WRITE_REG(sc, SAFE_RNG_CNFG, 0x834); /* magic from SafeNet */
1592 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0);
1595 * There is a bug in rev 1.0 of the 1140 that when the RNG
1596 * is brought out of reset the ready status flag does not
1597 * work until the RNG has finished its internal initialization.
1599 * So in order to determine the device is through its
1600 * initialization we must read the data register, using the
1601 * status reg in the read in case it is initialized. Then read
1602 * the data register until it changes from the first read.
1603 * Once it changes read the data register until it changes
1604 * again. At this time the RNG is considered initialized.
1605 * This could take between 750ms - 1000ms in time.
1608 w = READ_REG(sc, SAFE_RNG_OUT);
1610 v = READ_REG(sc, SAFE_RNG_OUT);
1616 } while (++i < SAFE_RNG_MAXWAIT);
1618 /* Wait Until data changes again */
1621 v = READ_REG(sc, SAFE_RNG_OUT);
1625 } while (++i < SAFE_RNG_MAXWAIT);
1628 static __inline void
1629 safe_rng_disable_short_cycle(struct safe_softc *sc)
1631 WRITE_REG(sc, SAFE_RNG_CTRL,
1632 READ_REG(sc, SAFE_RNG_CTRL) &~ SAFE_RNG_CTRL_SHORTEN);
1635 static __inline void
1636 safe_rng_enable_short_cycle(struct safe_softc *sc)
1638 WRITE_REG(sc, SAFE_RNG_CTRL,
1639 READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN);
1642 static __inline u_int32_t
1643 safe_rng_read(struct safe_softc *sc)
1648 while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT)
1650 return READ_REG(sc, SAFE_RNG_OUT);
1656 struct safe_softc *sc = arg;
1657 u_int32_t buf[SAFE_RNG_MAXBUFSIZ]; /* NB: maybe move to softc */
1663 * Fetch the next block of data.
1665 maxwords = safe_rngbufsize;
1666 if (maxwords > SAFE_RNG_MAXBUFSIZ)
1667 maxwords = SAFE_RNG_MAXBUFSIZ;
1669 for (i = 0; i < maxwords; i++)
1670 buf[i] = safe_rng_read(sc);
1672 * Check the comparator alarm count and reset the h/w if
1673 * it exceeds our threshold. This guards against the
1674 * hardware oscillators resonating with external signals.
1676 if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) {
1677 u_int32_t freq_inc, w;
1679 DPRINTF(("%s: alarm count %u exceeds threshold %u\n", __func__,
1680 READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm));
1681 safestats.st_rngalarm++;
1682 safe_rng_enable_short_cycle(sc);
1684 for (i = 0; i < 64; i++) {
1685 w = READ_REG(sc, SAFE_RNG_CNFG);
1686 freq_inc = ((w + freq_inc) & 0x3fL);
1687 w = ((w & ~0x3fL) | freq_inc);
1688 WRITE_REG(sc, SAFE_RNG_CNFG, w);
1690 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0);
1692 (void) safe_rng_read(sc);
1695 if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) {
1696 safe_rng_disable_short_cycle(sc);
1701 safe_rng_disable_short_cycle(sc);
1703 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0);
1705 (*sc->sc_harvest)(sc->sc_rndtest, buf, maxwords*sizeof (u_int32_t));
1706 callout_reset(&sc->sc_rngto,
1707 hz * (safe_rnginterval ? safe_rnginterval : 1), safe_rng, sc);
1709 #endif /* SAFE_NO_RNG */
1712 safe_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1714 bus_addr_t *paddr = (bus_addr_t*) arg;
1715 *paddr = segs->ds_addr;
1720 struct safe_softc *sc,
1722 struct safe_dma_alloc *dma,
1728 r = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
1729 sizeof(u_int32_t), 0, /* alignment, bounds */
1730 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1731 BUS_SPACE_MAXADDR, /* highaddr */
1732 NULL, NULL, /* filter, filterarg */
1735 size, /* maxsegsize */
1736 BUS_DMA_ALLOCNOW, /* flags */
1737 NULL, NULL, /* locking */
1740 device_printf(sc->sc_dev, "safe_dma_malloc: "
1741 "bus_dma_tag_create failed; error %u\n", r);
1745 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr,
1746 BUS_DMA_NOWAIT, &dma->dma_map);
1748 device_printf(sc->sc_dev, "safe_dma_malloc: "
1749 "bus_dmammem_alloc failed; size %ju, error %u\n",
1750 (uintmax_t)size, r);
1754 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,
1758 mapflags | BUS_DMA_NOWAIT);
1760 device_printf(sc->sc_dev, "safe_dma_malloc: "
1761 "bus_dmamap_load failed; error %u\n", r);
1765 dma->dma_size = size;
1768 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1770 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1772 bus_dma_tag_destroy(dma->dma_tag);
1774 dma->dma_tag = NULL;
1779 safe_dma_free(struct safe_softc *sc, struct safe_dma_alloc *dma)
1781 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1782 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1783 bus_dma_tag_destroy(dma->dma_tag);
1787 * Resets the board. Values in the regesters are left as is
1788 * from the reset (i.e. initial values are assigned elsewhere).
1791 safe_reset_board(struct safe_softc *sc)
1795 * Reset the device. The manual says no delay
1796 * is needed between marking and clearing reset.
1798 v = READ_REG(sc, SAFE_PE_DMACFG) &~
1799 (SAFE_PE_DMACFG_PERESET | SAFE_PE_DMACFG_PDRRESET |
1800 SAFE_PE_DMACFG_SGRESET);
1801 WRITE_REG(sc, SAFE_PE_DMACFG, v
1802 | SAFE_PE_DMACFG_PERESET
1803 | SAFE_PE_DMACFG_PDRRESET
1804 | SAFE_PE_DMACFG_SGRESET);
1805 WRITE_REG(sc, SAFE_PE_DMACFG, v);
1809 * Initialize registers we need to touch only once.
1812 safe_init_board(struct safe_softc *sc)
1814 u_int32_t v, dwords;
1816 v = READ_REG(sc, SAFE_PE_DMACFG);
1817 v &=~ SAFE_PE_DMACFG_PEMODE;
1818 v |= SAFE_PE_DMACFG_FSENA /* failsafe enable */
1819 | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */
1820 | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */
1821 | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */
1822 | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */
1823 | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */
1825 WRITE_REG(sc, SAFE_PE_DMACFG, v);
1827 /* XXX select byte swap based on host byte order */
1828 WRITE_REG(sc, SAFE_ENDIAN, 0x1b);
1830 if (sc->sc_chiprev == SAFE_REV(1,0)) {
1832 * Avoid large PCI DMA transfers. Rev 1.0 has a bug where
1833 * "target mode transfers" done while the chip is DMA'ing
1834 * >1020 bytes cause the hardware to lockup. To avoid this
1835 * we reduce the max PCI transfer size and use small source
1836 * particle descriptors (<= 256 bytes).
1838 WRITE_REG(sc, SAFE_DMA_CFG, 256);
1839 device_printf(sc->sc_dev,
1840 "Reduce max DMA size to %u words for rev %u.%u WAR\n",
1841 (READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff,
1842 SAFE_REV_MAJ(sc->sc_chiprev),
1843 SAFE_REV_MIN(sc->sc_chiprev));
1846 /* NB: operands+results are overlaid */
1847 WRITE_REG(sc, SAFE_PE_PDRBASE, sc->sc_ringalloc.dma_paddr);
1848 WRITE_REG(sc, SAFE_PE_RDRBASE, sc->sc_ringalloc.dma_paddr);
1850 * Configure ring entry size and number of items in the ring.
1852 KASSERT((sizeof(struct safe_ringentry) % sizeof(u_int32_t)) == 0,
1853 ("PE ring entry not 32-bit aligned!"));
1854 dwords = sizeof(struct safe_ringentry) / sizeof(u_int32_t);
1855 WRITE_REG(sc, SAFE_PE_RINGCFG,
1856 (dwords << SAFE_PE_RINGCFG_OFFSET_S) | SAFE_MAX_NQUEUE);
1857 WRITE_REG(sc, SAFE_PE_RINGPOLL, 0); /* disable polling */
1859 WRITE_REG(sc, SAFE_PE_GRNGBASE, sc->sc_spalloc.dma_paddr);
1860 WRITE_REG(sc, SAFE_PE_SRNGBASE, sc->sc_dpalloc.dma_paddr);
1861 WRITE_REG(sc, SAFE_PE_PARTSIZE,
1862 (SAFE_TOTAL_DPART<<16) | SAFE_TOTAL_SPART);
1864 * NB: destination particles are fixed size. We use
1865 * an mbuf cluster and require all results go to
1866 * clusters or smaller.
1868 WRITE_REG(sc, SAFE_PE_PARTCFG, SAFE_MAX_DSIZE);
1870 /* it's now safe to enable PE mode, do it */
1871 WRITE_REG(sc, SAFE_PE_DMACFG, v | SAFE_PE_DMACFG_PEMODE);
1874 * Configure hardware to use level-triggered interrupts and
1875 * to interrupt after each descriptor is processed.
1877 WRITE_REG(sc, SAFE_HI_CFG, SAFE_HI_CFG_LEVEL);
1878 WRITE_REG(sc, SAFE_HI_DESC_CNT, 1);
1879 WRITE_REG(sc, SAFE_HI_MASK, SAFE_INT_PE_DDONE | SAFE_INT_PE_ERROR);
1883 * Init PCI registers
1886 safe_init_pciregs(device_t dev)
1891 * Clean up after a chip crash.
1892 * It is assumed that the caller in splimp()
1895 safe_cleanchip(struct safe_softc *sc)
1898 if (sc->sc_nqchip != 0) {
1899 struct safe_ringentry *re = sc->sc_back;
1901 while (re != sc->sc_front) {
1902 if (re->re_desc.d_csr != 0)
1903 safe_free_entry(sc, re);
1904 if (++re == sc->sc_ringtop)
1914 * It is assumed that the caller is within splimp().
1917 safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re)
1919 struct cryptop *crp;
1924 if ((re->re_dst_m != NULL) && (re->re_src_m != re->re_dst_m))
1925 m_freem(re->re_dst_m);
1927 crp = (struct cryptop *)re->re_crp;
1929 re->re_desc.d_csr = 0;
1931 crp->crp_etype = EFAULT;
1937 * Routine to reset the chip and clean up.
1938 * It is assumed that the caller is in splimp()
1941 safe_totalreset(struct safe_softc *sc)
1943 safe_reset_board(sc);
1944 safe_init_board(sc);
1949 * Is the operand suitable aligned for direct DMA. Each
1950 * segment must be aligned on a 32-bit boundary and all
1951 * but the last segment must be a multiple of 4 bytes.
1954 safe_dmamap_aligned(const struct safe_operand *op)
1958 for (i = 0; i < op->nsegs; i++) {
1959 if (op->segs[i].ds_addr & 3)
1961 if (i != (op->nsegs - 1) && (op->segs[i].ds_len & 3))
1968 * Is the operand suitable for direct DMA as the destination
1969 * of an operation. The hardware requires that each ``particle''
1970 * but the last in an operation result have the same size. We
1971 * fix that size at SAFE_MAX_DSIZE bytes. This routine returns
1972 * 0 if some segment is not a multiple of of this size, 1 if all
1973 * segments are exactly this size, or 2 if segments are at worst
1974 * a multple of this size.
1977 safe_dmamap_uniform(const struct safe_operand *op)
1981 if (op->nsegs > 0) {
1984 for (i = 0; i < op->nsegs-1; i++) {
1985 if (op->segs[i].ds_len % SAFE_MAX_DSIZE)
1987 if (op->segs[i].ds_len != SAFE_MAX_DSIZE)
1996 safe_dump_dmastatus(struct safe_softc *sc, const char *tag)
1998 printf("%s: ENDIAN 0x%x SRC 0x%x DST 0x%x STAT 0x%x\n"
2000 , READ_REG(sc, SAFE_DMA_ENDIAN)
2001 , READ_REG(sc, SAFE_DMA_SRCADDR)
2002 , READ_REG(sc, SAFE_DMA_DSTADDR)
2003 , READ_REG(sc, SAFE_DMA_STAT)
2008 safe_dump_intrstate(struct safe_softc *sc, const char *tag)
2010 printf("%s: HI_CFG 0x%x HI_MASK 0x%x HI_DESC_CNT 0x%x HU_STAT 0x%x HM_STAT 0x%x\n"
2012 , READ_REG(sc, SAFE_HI_CFG)
2013 , READ_REG(sc, SAFE_HI_MASK)
2014 , READ_REG(sc, SAFE_HI_DESC_CNT)
2015 , READ_REG(sc, SAFE_HU_STAT)
2016 , READ_REG(sc, SAFE_HM_STAT)
2021 safe_dump_ringstate(struct safe_softc *sc, const char *tag)
2023 u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT);
2025 /* NB: assume caller has lock on ring */
2026 printf("%s: ERNGSTAT %x (next %u) back %lu front %lu\n",
2028 estat, (estat >> SAFE_PE_ERNGSTAT_NEXT_S),
2029 (unsigned long)(sc->sc_back - sc->sc_ring),
2030 (unsigned long)(sc->sc_front - sc->sc_ring));
2034 safe_dump_request(struct safe_softc *sc, const char* tag, struct safe_ringentry *re)
2038 ix = re - sc->sc_ring;
2039 printf("%s: %p (%u): csr %x src %x dst %x sa %x len %x\n"
2048 if (re->re_src.nsegs > 1) {
2049 ix = (re->re_desc.d_src - sc->sc_spalloc.dma_paddr) /
2050 sizeof(struct safe_pdesc);
2051 for (nsegs = re->re_src.nsegs; nsegs; nsegs--) {
2052 printf(" spd[%u] %p: %p size %u flags %x"
2053 , ix, &sc->sc_spring[ix]
2054 , (caddr_t)(uintptr_t) sc->sc_spring[ix].pd_addr
2055 , sc->sc_spring[ix].pd_size
2056 , sc->sc_spring[ix].pd_flags
2058 if (sc->sc_spring[ix].pd_size == 0)
2061 if (++ix == SAFE_TOTAL_SPART)
2065 if (re->re_dst.nsegs > 1) {
2066 ix = (re->re_desc.d_dst - sc->sc_dpalloc.dma_paddr) /
2067 sizeof(struct safe_pdesc);
2068 for (nsegs = re->re_dst.nsegs; nsegs; nsegs--) {
2069 printf(" dpd[%u] %p: %p flags %x\n"
2070 , ix, &sc->sc_dpring[ix]
2071 , (caddr_t)(uintptr_t) sc->sc_dpring[ix].pd_addr
2072 , sc->sc_dpring[ix].pd_flags
2074 if (++ix == SAFE_TOTAL_DPART)
2078 printf("sa: cmd0 %08x cmd1 %08x staterec %x\n",
2079 re->re_sa.sa_cmd0, re->re_sa.sa_cmd1, re->re_sa.sa_staterec);
2080 printf("sa: key %x %x %x %x %x %x %x %x\n"
2081 , re->re_sa.sa_key[0]
2082 , re->re_sa.sa_key[1]
2083 , re->re_sa.sa_key[2]
2084 , re->re_sa.sa_key[3]
2085 , re->re_sa.sa_key[4]
2086 , re->re_sa.sa_key[5]
2087 , re->re_sa.sa_key[6]
2088 , re->re_sa.sa_key[7]
2090 printf("sa: indigest %x %x %x %x %x\n"
2091 , re->re_sa.sa_indigest[0]
2092 , re->re_sa.sa_indigest[1]
2093 , re->re_sa.sa_indigest[2]
2094 , re->re_sa.sa_indigest[3]
2095 , re->re_sa.sa_indigest[4]
2097 printf("sa: outdigest %x %x %x %x %x\n"
2098 , re->re_sa.sa_outdigest[0]
2099 , re->re_sa.sa_outdigest[1]
2100 , re->re_sa.sa_outdigest[2]
2101 , re->re_sa.sa_outdigest[3]
2102 , re->re_sa.sa_outdigest[4]
2104 printf("sr: iv %x %x %x %x\n"
2105 , re->re_sastate.sa_saved_iv[0]
2106 , re->re_sastate.sa_saved_iv[1]
2107 , re->re_sastate.sa_saved_iv[2]
2108 , re->re_sastate.sa_saved_iv[3]
2110 printf("sr: hashbc %u indigest %x %x %x %x %x\n"
2111 , re->re_sastate.sa_saved_hashbc
2112 , re->re_sastate.sa_saved_indigest[0]
2113 , re->re_sastate.sa_saved_indigest[1]
2114 , re->re_sastate.sa_saved_indigest[2]
2115 , re->re_sastate.sa_saved_indigest[3]
2116 , re->re_sastate.sa_saved_indigest[4]
2121 safe_dump_ring(struct safe_softc *sc, const char *tag)
2123 mtx_lock(&sc->sc_ringmtx);
2124 printf("\nSafeNet Ring State:\n");
2125 safe_dump_intrstate(sc, tag);
2126 safe_dump_dmastatus(sc, tag);
2127 safe_dump_ringstate(sc, tag);
2128 if (sc->sc_nqchip) {
2129 struct safe_ringentry *re = sc->sc_back;
2131 safe_dump_request(sc, tag, re);
2132 if (++re == sc->sc_ringtop)
2134 } while (re != sc->sc_front);
2136 mtx_unlock(&sc->sc_ringmtx);
2140 sysctl_hw_safe_dump(SYSCTL_HANDLER_ARGS)
2145 strncpy(dmode, "", sizeof(dmode) - 1);
2146 dmode[sizeof(dmode) - 1] = '\0';
2147 error = sysctl_handle_string(oidp, &dmode[0], sizeof(dmode), req);
2149 if (error == 0 && req->newptr != NULL) {
2150 struct safe_softc *sc = safec;
2154 if (strncmp(dmode, "dma", 3) == 0)
2155 safe_dump_dmastatus(sc, "safe0");
2156 else if (strncmp(dmode, "int", 3) == 0)
2157 safe_dump_intrstate(sc, "safe0");
2158 else if (strncmp(dmode, "ring", 4) == 0)
2159 safe_dump_ring(sc, "safe0");
2165 SYSCTL_PROC(_hw_safe, OID_AUTO, dump, CTLTYPE_STRING | CTLFLAG_RW,
2166 0, 0, sysctl_hw_safe_dump, "A", "Dump driver state");
2167 #endif /* SAFE_DEBUG */