2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2003 Sam Leffler, Errno Consulting
5 * Copyright (c) 2003 Global Technology Associates, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * SafeNet SafeXcel-1141 hardware crypto accelerator
38 #include <sys/param.h>
39 #include <sys/systm.h>
41 #include <sys/errno.h>
42 #include <sys/malloc.h>
43 #include <sys/kernel.h>
45 #include <sys/module.h>
47 #include <sys/mutex.h>
48 #include <sys/sysctl.h>
49 #include <sys/endian.h>
54 #include <machine/bus.h>
55 #include <machine/resource.h>
59 #include <crypto/sha1.h>
60 #include <opencrypto/cryptodev.h>
61 #include <opencrypto/cryptosoft.h>
63 #include <sys/random.h>
66 #include "cryptodev_if.h"
68 #include <dev/pci/pcivar.h>
69 #include <dev/pci/pcireg.h>
72 #include <dev/rndtest/rndtest.h>
74 #include <dev/safe/safereg.h>
75 #include <dev/safe/safevar.h>
82 * Prototypes and count for the pci_device structure
84 static int safe_probe(device_t);
85 static int safe_attach(device_t);
86 static int safe_detach(device_t);
87 static int safe_suspend(device_t);
88 static int safe_resume(device_t);
89 static int safe_shutdown(device_t);
91 static int safe_newsession(device_t, u_int32_t *, struct cryptoini *);
92 static int safe_freesession(device_t, u_int64_t);
93 static int safe_process(device_t, struct cryptop *, int);
95 static device_method_t safe_methods[] = {
96 /* Device interface */
97 DEVMETHOD(device_probe, safe_probe),
98 DEVMETHOD(device_attach, safe_attach),
99 DEVMETHOD(device_detach, safe_detach),
100 DEVMETHOD(device_suspend, safe_suspend),
101 DEVMETHOD(device_resume, safe_resume),
102 DEVMETHOD(device_shutdown, safe_shutdown),
104 /* crypto device methods */
105 DEVMETHOD(cryptodev_newsession, safe_newsession),
106 DEVMETHOD(cryptodev_freesession,safe_freesession),
107 DEVMETHOD(cryptodev_process, safe_process),
111 static driver_t safe_driver = {
114 sizeof (struct safe_softc)
116 static devclass_t safe_devclass;
118 DRIVER_MODULE(safe, pci, safe_driver, safe_devclass, 0, 0);
119 MODULE_DEPEND(safe, crypto, 1, 1, 1);
121 MODULE_DEPEND(safe, rndtest, 1, 1, 1);
124 static void safe_intr(void *);
125 static void safe_callback(struct safe_softc *, struct safe_ringentry *);
126 static void safe_feed(struct safe_softc *, struct safe_ringentry *);
127 static void safe_mcopy(struct mbuf *, struct mbuf *, u_int);
129 static void safe_rng_init(struct safe_softc *);
130 static void safe_rng(void *);
131 #endif /* SAFE_NO_RNG */
132 static int safe_dma_malloc(struct safe_softc *, bus_size_t,
133 struct safe_dma_alloc *, int);
134 #define safe_dma_sync(_dma, _flags) \
135 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags))
136 static void safe_dma_free(struct safe_softc *, struct safe_dma_alloc *);
137 static int safe_dmamap_aligned(const struct safe_operand *);
138 static int safe_dmamap_uniform(const struct safe_operand *);
140 static void safe_reset_board(struct safe_softc *);
141 static void safe_init_board(struct safe_softc *);
142 static void safe_init_pciregs(device_t dev);
143 static void safe_cleanchip(struct safe_softc *);
144 static void safe_totalreset(struct safe_softc *);
146 static int safe_free_entry(struct safe_softc *, struct safe_ringentry *);
148 static SYSCTL_NODE(_hw, OID_AUTO, safe, CTLFLAG_RD, 0,
149 "SafeNet driver parameters");
152 static void safe_dump_dmastatus(struct safe_softc *, const char *);
153 static void safe_dump_ringstate(struct safe_softc *, const char *);
154 static void safe_dump_intrstate(struct safe_softc *, const char *);
155 static void safe_dump_request(struct safe_softc *, const char *,
156 struct safe_ringentry *);
158 static struct safe_softc *safec; /* for use by hw.safe.dump */
160 static int safe_debug = 0;
161 SYSCTL_INT(_hw_safe, OID_AUTO, debug, CTLFLAG_RW, &safe_debug,
162 0, "control debugging msgs");
163 #define DPRINTF(_x) if (safe_debug) printf _x
168 #define READ_REG(sc,r) \
169 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r))
171 #define WRITE_REG(sc,reg,val) \
172 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val)
174 struct safe_stats safestats;
175 SYSCTL_STRUCT(_hw_safe, OID_AUTO, stats, CTLFLAG_RD, &safestats,
176 safe_stats, "driver statistics");
178 static int safe_rnginterval = 1; /* poll once a second */
179 SYSCTL_INT(_hw_safe, OID_AUTO, rnginterval, CTLFLAG_RW, &safe_rnginterval,
180 0, "RNG polling interval (secs)");
181 static int safe_rngbufsize = 16; /* 64 bytes each poll */
182 SYSCTL_INT(_hw_safe, OID_AUTO, rngbufsize, CTLFLAG_RW, &safe_rngbufsize,
183 0, "RNG polling buffer size (32-bit words)");
184 static int safe_rngmaxalarm = 8; /* max alarms before reset */
185 SYSCTL_INT(_hw_safe, OID_AUTO, rngmaxalarm, CTLFLAG_RW, &safe_rngmaxalarm,
186 0, "RNG max alarms before reset");
187 #endif /* SAFE_NO_RNG */
190 safe_probe(device_t dev)
192 if (pci_get_vendor(dev) == PCI_VENDOR_SAFENET &&
193 pci_get_device(dev) == PCI_PRODUCT_SAFEXCEL)
194 return (BUS_PROBE_DEFAULT);
199 safe_partname(struct safe_softc *sc)
201 /* XXX sprintf numbers when not decoded */
202 switch (pci_get_vendor(sc->sc_dev)) {
203 case PCI_VENDOR_SAFENET:
204 switch (pci_get_device(sc->sc_dev)) {
205 case PCI_PRODUCT_SAFEXCEL: return "SafeNet SafeXcel-1141";
207 return "SafeNet unknown-part";
209 return "Unknown-vendor unknown-part";
214 default_harvest(struct rndtest_state *rsp, void *buf, u_int count)
216 /* MarkM: FIX!! Check that this does not swamp the harvester! */
217 random_harvest_queue(buf, count, count*NBBY/2, RANDOM_PURE_SAFE);
219 #endif /* SAFE_NO_RNG */
222 safe_attach(device_t dev)
224 struct safe_softc *sc = device_get_softc(dev);
226 u_int32_t i, devinfo;
229 bzero(sc, sizeof (*sc));
232 /* XXX handle power management */
234 pci_enable_busmaster(dev);
237 * Setup memory-mapping of PCI registers.
240 sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
242 if (sc->sc_sr == NULL) {
243 device_printf(dev, "cannot map register space\n");
246 sc->sc_st = rman_get_bustag(sc->sc_sr);
247 sc->sc_sh = rman_get_bushandle(sc->sc_sr);
250 * Arrange interrupt line.
253 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
254 RF_SHAREABLE|RF_ACTIVE);
255 if (sc->sc_irq == NULL) {
256 device_printf(dev, "could not map interrupt\n");
260 * NB: Network code assumes we are blocked with splimp()
261 * so make sure the IRQ is mapped appropriately.
263 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE,
264 NULL, safe_intr, sc, &sc->sc_ih)) {
265 device_printf(dev, "could not establish interrupt\n");
269 sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE);
270 if (sc->sc_cid < 0) {
271 device_printf(dev, "could not get crypto driver id\n");
275 sc->sc_chiprev = READ_REG(sc, SAFE_DEVINFO) &
276 (SAFE_DEVINFO_REV_MAJ | SAFE_DEVINFO_REV_MIN);
279 * Setup DMA descriptor area.
281 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
283 SAFE_DMA_BOUNDARY, /* boundary */
284 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
285 BUS_SPACE_MAXADDR, /* highaddr */
286 NULL, NULL, /* filter, filterarg */
287 SAFE_MAX_DMA, /* maxsize */
288 SAFE_MAX_PART, /* nsegments */
289 SAFE_MAX_SSIZE, /* maxsegsize */
290 BUS_DMA_ALLOCNOW, /* flags */
291 NULL, NULL, /* locking */
293 device_printf(dev, "cannot allocate DMA tag\n");
296 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
298 SAFE_MAX_DSIZE, /* boundary */
299 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
300 BUS_SPACE_MAXADDR, /* highaddr */
301 NULL, NULL, /* filter, filterarg */
302 SAFE_MAX_DMA, /* maxsize */
303 SAFE_MAX_PART, /* nsegments */
304 SAFE_MAX_DSIZE, /* maxsegsize */
305 BUS_DMA_ALLOCNOW, /* flags */
306 NULL, NULL, /* locking */
308 device_printf(dev, "cannot allocate DMA tag\n");
313 * Allocate packet engine descriptors.
315 if (safe_dma_malloc(sc,
316 SAFE_MAX_NQUEUE * sizeof (struct safe_ringentry),
317 &sc->sc_ringalloc, 0)) {
318 device_printf(dev, "cannot allocate PE descriptor ring\n");
319 bus_dma_tag_destroy(sc->sc_srcdmat);
323 * Hookup the static portion of all our data structures.
325 sc->sc_ring = (struct safe_ringentry *) sc->sc_ringalloc.dma_vaddr;
326 sc->sc_ringtop = sc->sc_ring + SAFE_MAX_NQUEUE;
327 sc->sc_front = sc->sc_ring;
328 sc->sc_back = sc->sc_ring;
329 raddr = sc->sc_ringalloc.dma_paddr;
330 bzero(sc->sc_ring, SAFE_MAX_NQUEUE * sizeof(struct safe_ringentry));
331 for (i = 0; i < SAFE_MAX_NQUEUE; i++) {
332 struct safe_ringentry *re = &sc->sc_ring[i];
334 re->re_desc.d_sa = raddr +
335 offsetof(struct safe_ringentry, re_sa);
336 re->re_sa.sa_staterec = raddr +
337 offsetof(struct safe_ringentry, re_sastate);
339 raddr += sizeof (struct safe_ringentry);
341 mtx_init(&sc->sc_ringmtx, device_get_nameunit(dev),
342 "packet engine ring", MTX_DEF);
345 * Allocate scatter and gather particle descriptors.
347 if (safe_dma_malloc(sc, SAFE_TOTAL_SPART * sizeof (struct safe_pdesc),
348 &sc->sc_spalloc, 0)) {
349 device_printf(dev, "cannot allocate source particle "
350 "descriptor ring\n");
351 mtx_destroy(&sc->sc_ringmtx);
352 safe_dma_free(sc, &sc->sc_ringalloc);
353 bus_dma_tag_destroy(sc->sc_srcdmat);
356 sc->sc_spring = (struct safe_pdesc *) sc->sc_spalloc.dma_vaddr;
357 sc->sc_springtop = sc->sc_spring + SAFE_TOTAL_SPART;
358 sc->sc_spfree = sc->sc_spring;
359 bzero(sc->sc_spring, SAFE_TOTAL_SPART * sizeof(struct safe_pdesc));
361 if (safe_dma_malloc(sc, SAFE_TOTAL_DPART * sizeof (struct safe_pdesc),
362 &sc->sc_dpalloc, 0)) {
363 device_printf(dev, "cannot allocate destination particle "
364 "descriptor ring\n");
365 mtx_destroy(&sc->sc_ringmtx);
366 safe_dma_free(sc, &sc->sc_spalloc);
367 safe_dma_free(sc, &sc->sc_ringalloc);
368 bus_dma_tag_destroy(sc->sc_dstdmat);
371 sc->sc_dpring = (struct safe_pdesc *) sc->sc_dpalloc.dma_vaddr;
372 sc->sc_dpringtop = sc->sc_dpring + SAFE_TOTAL_DPART;
373 sc->sc_dpfree = sc->sc_dpring;
374 bzero(sc->sc_dpring, SAFE_TOTAL_DPART * sizeof(struct safe_pdesc));
376 device_printf(sc->sc_dev, "%s", safe_partname(sc));
378 devinfo = READ_REG(sc, SAFE_DEVINFO);
379 if (devinfo & SAFE_DEVINFO_RNG) {
380 sc->sc_flags |= SAFE_FLAGS_RNG;
383 if (devinfo & SAFE_DEVINFO_PKEY) {
386 sc->sc_flags |= SAFE_FLAGS_KEY;
387 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0);
388 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0);
391 if (devinfo & SAFE_DEVINFO_DES) {
393 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0);
394 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0);
396 if (devinfo & SAFE_DEVINFO_AES) {
398 crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0);
400 if (devinfo & SAFE_DEVINFO_MD5) {
402 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0);
404 if (devinfo & SAFE_DEVINFO_SHA1) {
406 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0);
409 crypto_register(sc->sc_cid, CRYPTO_NULL_CBC, 0, 0);
410 crypto_register(sc->sc_cid, CRYPTO_NULL_HMAC, 0, 0);
411 /* XXX other supported algorithms */
414 safe_reset_board(sc); /* reset h/w */
415 safe_init_pciregs(dev); /* init pci settings */
416 safe_init_board(sc); /* init h/w */
419 if (sc->sc_flags & SAFE_FLAGS_RNG) {
421 sc->sc_rndtest = rndtest_attach(dev);
423 sc->sc_harvest = rndtest_harvest;
425 sc->sc_harvest = default_harvest;
427 sc->sc_harvest = default_harvest;
431 callout_init(&sc->sc_rngto, 1);
432 callout_reset(&sc->sc_rngto, hz*safe_rnginterval, safe_rng, sc);
434 #endif /* SAFE_NO_RNG */
436 safec = sc; /* for use by hw.safe.dump */
440 crypto_unregister_all(sc->sc_cid);
442 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
444 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
446 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
452 * Detach a device that successfully probed.
455 safe_detach(device_t dev)
457 struct safe_softc *sc = device_get_softc(dev);
459 /* XXX wait/abort active ops */
461 WRITE_REG(sc, SAFE_HI_MASK, 0); /* disable interrupts */
463 callout_stop(&sc->sc_rngto);
465 crypto_unregister_all(sc->sc_cid);
469 rndtest_detach(sc->sc_rndtest);
473 safe_dma_free(sc, &sc->sc_dpalloc);
474 safe_dma_free(sc, &sc->sc_spalloc);
475 mtx_destroy(&sc->sc_ringmtx);
476 safe_dma_free(sc, &sc->sc_ringalloc);
478 bus_generic_detach(dev);
479 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
480 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
482 bus_dma_tag_destroy(sc->sc_srcdmat);
483 bus_dma_tag_destroy(sc->sc_dstdmat);
484 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
490 * Stop all chip i/o so that the kernel's probe routines don't
491 * get confused by errant DMAs when rebooting.
494 safe_shutdown(device_t dev)
497 safe_stop(device_get_softc(dev));
503 * Device suspend routine.
506 safe_suspend(device_t dev)
508 struct safe_softc *sc = device_get_softc(dev);
511 /* XXX stop the device and save PCI settings */
513 sc->sc_suspended = 1;
519 safe_resume(device_t dev)
521 struct safe_softc *sc = device_get_softc(dev);
524 /* XXX retore PCI settings and start the device */
526 sc->sc_suspended = 0;
531 * SafeXcel Interrupt routine
536 struct safe_softc *sc = arg;
537 volatile u_int32_t stat;
539 stat = READ_REG(sc, SAFE_HM_STAT);
540 if (stat == 0) /* shared irq, not for us */
543 WRITE_REG(sc, SAFE_HI_CLR, stat); /* IACK */
545 if ((stat & SAFE_INT_PE_DDONE)) {
547 * Descriptor(s) done; scan the ring and
548 * process completed operations.
550 mtx_lock(&sc->sc_ringmtx);
551 while (sc->sc_back != sc->sc_front) {
552 struct safe_ringentry *re = sc->sc_back;
555 safe_dump_ringstate(sc, __func__);
556 safe_dump_request(sc, __func__, re);
560 * safe_process marks ring entries that were allocated
561 * but not used with a csr of zero. This insures the
562 * ring front pointer never needs to be set backwards
563 * in the event that an entry is allocated but not used
564 * because of a setup error.
566 if (re->re_desc.d_csr != 0) {
567 if (!SAFE_PE_CSR_IS_DONE(re->re_desc.d_csr))
569 if (!SAFE_PE_LEN_IS_DONE(re->re_desc.d_len))
572 safe_callback(sc, re);
574 if (++(sc->sc_back) == sc->sc_ringtop)
575 sc->sc_back = sc->sc_ring;
577 mtx_unlock(&sc->sc_ringmtx);
581 * Check to see if we got any DMA Error
583 if (stat & SAFE_INT_PE_ERROR) {
584 DPRINTF(("dmaerr dmastat %08x\n",
585 READ_REG(sc, SAFE_PE_DMASTAT)));
586 safestats.st_dmaerr++;
593 if (sc->sc_needwakeup) { /* XXX check high watermark */
594 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ);
595 DPRINTF(("%s: wakeup crypto %x\n", __func__,
597 sc->sc_needwakeup &= ~wakeup;
598 crypto_unblock(sc->sc_cid, wakeup);
603 * safe_feed() - post a request to chip
606 safe_feed(struct safe_softc *sc, struct safe_ringentry *re)
608 bus_dmamap_sync(sc->sc_srcdmat, re->re_src_map, BUS_DMASYNC_PREWRITE);
609 if (re->re_dst_map != NULL)
610 bus_dmamap_sync(sc->sc_dstdmat, re->re_dst_map,
611 BUS_DMASYNC_PREREAD);
612 /* XXX have no smaller granularity */
613 safe_dma_sync(&sc->sc_ringalloc,
614 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
615 safe_dma_sync(&sc->sc_spalloc, BUS_DMASYNC_PREWRITE);
616 safe_dma_sync(&sc->sc_dpalloc, BUS_DMASYNC_PREWRITE);
620 safe_dump_ringstate(sc, __func__);
621 safe_dump_request(sc, __func__, re);
625 if (sc->sc_nqchip > safestats.st_maxqchip)
626 safestats.st_maxqchip = sc->sc_nqchip;
627 /* poke h/w to check descriptor ring, any value can be written */
628 WRITE_REG(sc, SAFE_HI_RD_DESCR, 0);
631 #define N(a) (sizeof(a) / sizeof (a[0]))
633 safe_setup_enckey(struct safe_session *ses, caddr_t key)
637 bcopy(key, ses->ses_key, ses->ses_klen / 8);
639 /* PE is little-endian, insure proper byte order */
640 for (i = 0; i < N(ses->ses_key); i++)
641 ses->ses_key[i] = htole32(ses->ses_key[i]);
645 safe_setup_mackey(struct safe_session *ses, int algo, caddr_t key, int klen)
652 for (i = 0; i < klen; i++)
653 key[i] ^= HMAC_IPAD_VAL;
655 if (algo == CRYPTO_MD5_HMAC) {
657 MD5Update(&md5ctx, key, klen);
658 MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen);
659 bcopy(md5ctx.state, ses->ses_hminner, sizeof(md5ctx.state));
662 SHA1Update(&sha1ctx, key, klen);
663 SHA1Update(&sha1ctx, hmac_ipad_buffer,
664 SHA1_HMAC_BLOCK_LEN - klen);
665 bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32));
668 for (i = 0; i < klen; i++)
669 key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL);
671 if (algo == CRYPTO_MD5_HMAC) {
673 MD5Update(&md5ctx, key, klen);
674 MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen);
675 bcopy(md5ctx.state, ses->ses_hmouter, sizeof(md5ctx.state));
678 SHA1Update(&sha1ctx, key, klen);
679 SHA1Update(&sha1ctx, hmac_opad_buffer,
680 SHA1_HMAC_BLOCK_LEN - klen);
681 bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32));
684 for (i = 0; i < klen; i++)
685 key[i] ^= HMAC_OPAD_VAL;
687 /* PE is little-endian, insure proper byte order */
688 for (i = 0; i < N(ses->ses_hminner); i++) {
689 ses->ses_hminner[i] = htole32(ses->ses_hminner[i]);
690 ses->ses_hmouter[i] = htole32(ses->ses_hmouter[i]);
696 * Allocate a new 'session' and return an encoded session id. 'sidp'
697 * contains our registration id, and should contain an encoded session
698 * id on successful allocation.
701 safe_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri)
703 struct safe_softc *sc = device_get_softc(dev);
704 struct cryptoini *c, *encini = NULL, *macini = NULL;
705 struct safe_session *ses = NULL;
708 if (sidp == NULL || cri == NULL || sc == NULL)
711 for (c = cri; c != NULL; c = c->cri_next) {
712 if (c->cri_alg == CRYPTO_MD5_HMAC ||
713 c->cri_alg == CRYPTO_SHA1_HMAC ||
714 c->cri_alg == CRYPTO_NULL_HMAC) {
718 } else if (c->cri_alg == CRYPTO_DES_CBC ||
719 c->cri_alg == CRYPTO_3DES_CBC ||
720 c->cri_alg == CRYPTO_AES_CBC ||
721 c->cri_alg == CRYPTO_NULL_CBC) {
728 if (encini == NULL && macini == NULL)
730 if (encini) { /* validate key length */
731 switch (encini->cri_alg) {
733 if (encini->cri_klen != 64)
736 case CRYPTO_3DES_CBC:
737 if (encini->cri_klen != 192)
741 if (encini->cri_klen != 128 &&
742 encini->cri_klen != 192 &&
743 encini->cri_klen != 256)
749 if (sc->sc_sessions == NULL) {
750 ses = sc->sc_sessions = (struct safe_session *)malloc(
751 sizeof(struct safe_session), M_DEVBUF, M_NOWAIT);
755 sc->sc_nsessions = 1;
757 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
758 if (sc->sc_sessions[sesn].ses_used == 0) {
759 ses = &sc->sc_sessions[sesn];
765 sesn = sc->sc_nsessions;
766 ses = (struct safe_session *)malloc((sesn + 1) *
767 sizeof(struct safe_session), M_DEVBUF, M_NOWAIT);
770 bcopy(sc->sc_sessions, ses, sesn *
771 sizeof(struct safe_session));
772 bzero(sc->sc_sessions, sesn *
773 sizeof(struct safe_session));
774 free(sc->sc_sessions, M_DEVBUF);
775 sc->sc_sessions = ses;
776 ses = &sc->sc_sessions[sesn];
781 bzero(ses, sizeof(struct safe_session));
786 /* XXX may read fewer than requested */
787 read_random(ses->ses_iv, sizeof(ses->ses_iv));
789 ses->ses_klen = encini->cri_klen;
790 if (encini->cri_key != NULL)
791 safe_setup_enckey(ses, encini->cri_key);
795 ses->ses_mlen = macini->cri_mlen;
796 if (ses->ses_mlen == 0) {
797 if (macini->cri_alg == CRYPTO_MD5_HMAC)
798 ses->ses_mlen = MD5_HASH_LEN;
800 ses->ses_mlen = SHA1_HASH_LEN;
803 if (macini->cri_key != NULL) {
804 safe_setup_mackey(ses, macini->cri_alg, macini->cri_key,
805 macini->cri_klen / 8);
809 *sidp = SAFE_SID(device_get_unit(sc->sc_dev), sesn);
814 * Deallocate a session.
817 safe_freesession(device_t dev, u_int64_t tid)
819 struct safe_softc *sc = device_get_softc(dev);
821 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff;
826 session = SAFE_SESSION(sid);
827 if (session < sc->sc_nsessions) {
828 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session]));
836 safe_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error)
838 struct safe_operand *op = arg;
840 DPRINTF(("%s: mapsize %u nsegs %d error %d\n", __func__,
841 (u_int) mapsize, nsegs, error));
844 op->mapsize = mapsize;
846 bcopy(seg, op->segs, nsegs * sizeof (seg[0]));
850 safe_process(device_t dev, struct cryptop *crp, int hint)
852 struct safe_softc *sc = device_get_softc(dev);
853 int err = 0, i, nicealign, uniform;
854 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
855 int bypass, oplen, ivsize;
858 struct safe_session *ses;
859 struct safe_ringentry *re;
860 struct safe_sarec *sa;
861 struct safe_pdesc *pd;
862 u_int32_t cmd0, cmd1, staterec;
864 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) {
865 safestats.st_invalid++;
868 if (SAFE_SESSION(crp->crp_sid) >= sc->sc_nsessions) {
869 safestats.st_badsession++;
873 mtx_lock(&sc->sc_ringmtx);
874 if (sc->sc_front == sc->sc_back && sc->sc_nqchip != 0) {
875 safestats.st_ringfull++;
876 sc->sc_needwakeup |= CRYPTO_SYMQ;
877 mtx_unlock(&sc->sc_ringmtx);
882 staterec = re->re_sa.sa_staterec; /* save */
883 /* NB: zero everything but the PE descriptor */
884 bzero(&re->re_sa, sizeof(struct safe_ringentry) - sizeof(re->re_desc));
885 re->re_sa.sa_staterec = staterec; /* restore */
888 re->re_sesn = SAFE_SESSION(crp->crp_sid);
890 if (crp->crp_flags & CRYPTO_F_IMBUF) {
891 re->re_src_m = (struct mbuf *)crp->crp_buf;
892 re->re_dst_m = (struct mbuf *)crp->crp_buf;
893 } else if (crp->crp_flags & CRYPTO_F_IOV) {
894 re->re_src_io = (struct uio *)crp->crp_buf;
895 re->re_dst_io = (struct uio *)crp->crp_buf;
897 safestats.st_badflags++;
899 goto errout; /* XXX we don't handle contiguous blocks! */
903 ses = &sc->sc_sessions[re->re_sesn];
905 crd1 = crp->crp_desc;
907 safestats.st_nodesc++;
911 crd2 = crd1->crd_next;
913 cmd0 = SAFE_SA_CMD0_BASIC; /* basic group operation */
916 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
917 crd1->crd_alg == CRYPTO_SHA1_HMAC ||
918 crd1->crd_alg == CRYPTO_NULL_HMAC) {
921 cmd0 |= SAFE_SA_CMD0_OP_HASH;
922 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
923 crd1->crd_alg == CRYPTO_3DES_CBC ||
924 crd1->crd_alg == CRYPTO_AES_CBC ||
925 crd1->crd_alg == CRYPTO_NULL_CBC) {
928 cmd0 |= SAFE_SA_CMD0_OP_CRYPT;
930 safestats.st_badalg++;
935 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
936 crd1->crd_alg == CRYPTO_SHA1_HMAC ||
937 crd1->crd_alg == CRYPTO_NULL_HMAC) &&
938 (crd2->crd_alg == CRYPTO_DES_CBC ||
939 crd2->crd_alg == CRYPTO_3DES_CBC ||
940 crd2->crd_alg == CRYPTO_AES_CBC ||
941 crd2->crd_alg == CRYPTO_NULL_CBC) &&
942 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
945 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
946 crd1->crd_alg == CRYPTO_3DES_CBC ||
947 crd1->crd_alg == CRYPTO_AES_CBC ||
948 crd1->crd_alg == CRYPTO_NULL_CBC) &&
949 (crd2->crd_alg == CRYPTO_MD5_HMAC ||
950 crd2->crd_alg == CRYPTO_SHA1_HMAC ||
951 crd2->crd_alg == CRYPTO_NULL_HMAC) &&
952 (crd1->crd_flags & CRD_F_ENCRYPT)) {
956 safestats.st_badalg++;
960 cmd0 |= SAFE_SA_CMD0_OP_BOTH;
964 if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT)
965 safe_setup_enckey(ses, enccrd->crd_key);
967 if (enccrd->crd_alg == CRYPTO_DES_CBC) {
968 cmd0 |= SAFE_SA_CMD0_DES;
969 cmd1 |= SAFE_SA_CMD1_CBC;
970 ivsize = 2*sizeof(u_int32_t);
971 } else if (enccrd->crd_alg == CRYPTO_3DES_CBC) {
972 cmd0 |= SAFE_SA_CMD0_3DES;
973 cmd1 |= SAFE_SA_CMD1_CBC;
974 ivsize = 2*sizeof(u_int32_t);
975 } else if (enccrd->crd_alg == CRYPTO_AES_CBC) {
976 cmd0 |= SAFE_SA_CMD0_AES;
977 cmd1 |= SAFE_SA_CMD1_CBC;
978 if (ses->ses_klen == 128)
979 cmd1 |= SAFE_SA_CMD1_AES128;
980 else if (ses->ses_klen == 192)
981 cmd1 |= SAFE_SA_CMD1_AES192;
983 cmd1 |= SAFE_SA_CMD1_AES256;
984 ivsize = 4*sizeof(u_int32_t);
986 cmd0 |= SAFE_SA_CMD0_CRYPT_NULL;
991 * Setup encrypt/decrypt state. When using basic ops
992 * we can't use an inline IV because hash/crypt offset
993 * must be from the end of the IV to the start of the
994 * crypt data and this leaves out the preceding header
995 * from the hash calculation. Instead we place the IV
996 * in the state record and set the hash/crypt offset to
997 * copy both the header+IV.
999 if (enccrd->crd_flags & CRD_F_ENCRYPT) {
1000 cmd0 |= SAFE_SA_CMD0_OUTBOUND;
1002 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1003 iv = enccrd->crd_iv;
1005 iv = (caddr_t) ses->ses_iv;
1006 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) {
1007 crypto_copyback(crp->crp_flags, crp->crp_buf,
1008 enccrd->crd_inject, ivsize, iv);
1010 bcopy(iv, re->re_sastate.sa_saved_iv, ivsize);
1011 cmd0 |= SAFE_SA_CMD0_IVLD_STATE | SAFE_SA_CMD0_SAVEIV;
1012 re->re_flags |= SAFE_QFLAGS_COPYOUTIV;
1014 cmd0 |= SAFE_SA_CMD0_INBOUND;
1016 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) {
1017 bcopy(enccrd->crd_iv,
1018 re->re_sastate.sa_saved_iv, ivsize);
1020 crypto_copydata(crp->crp_flags, crp->crp_buf,
1021 enccrd->crd_inject, ivsize,
1022 (caddr_t)re->re_sastate.sa_saved_iv);
1024 cmd0 |= SAFE_SA_CMD0_IVLD_STATE;
1027 * For basic encryption use the zero pad algorithm.
1028 * This pads results to an 8-byte boundary and
1029 * suppresses padding verification for inbound (i.e.
1030 * decrypt) operations.
1032 * NB: Not sure if the 8-byte pad boundary is a problem.
1034 cmd0 |= SAFE_SA_CMD0_PAD_ZERO;
1036 /* XXX assert key bufs have the same size */
1037 bcopy(ses->ses_key, sa->sa_key, sizeof(sa->sa_key));
1041 if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) {
1042 safe_setup_mackey(ses, maccrd->crd_alg,
1043 maccrd->crd_key, maccrd->crd_klen / 8);
1046 if (maccrd->crd_alg == CRYPTO_MD5_HMAC) {
1047 cmd0 |= SAFE_SA_CMD0_MD5;
1048 cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */
1049 } else if (maccrd->crd_alg == CRYPTO_SHA1_HMAC) {
1050 cmd0 |= SAFE_SA_CMD0_SHA1;
1051 cmd1 |= SAFE_SA_CMD1_HMAC; /* NB: enable HMAC */
1053 cmd0 |= SAFE_SA_CMD0_HASH_NULL;
1056 * Digest data is loaded from the SA and the hash
1057 * result is saved to the state block where we
1058 * retrieve it for return to the caller.
1060 /* XXX assert digest bufs have the same size */
1061 bcopy(ses->ses_hminner, sa->sa_indigest,
1062 sizeof(sa->sa_indigest));
1063 bcopy(ses->ses_hmouter, sa->sa_outdigest,
1064 sizeof(sa->sa_outdigest));
1066 cmd0 |= SAFE_SA_CMD0_HSLD_SA | SAFE_SA_CMD0_SAVEHASH;
1067 re->re_flags |= SAFE_QFLAGS_COPYOUTICV;
1070 if (enccrd && maccrd) {
1072 * The offset from hash data to the start of
1073 * crypt data is the difference in the skips.
1075 bypass = maccrd->crd_skip;
1076 coffset = enccrd->crd_skip - maccrd->crd_skip;
1078 DPRINTF(("%s: hash does not precede crypt; "
1079 "mac skip %u enc skip %u\n",
1080 __func__, maccrd->crd_skip, enccrd->crd_skip));
1081 safestats.st_skipmismatch++;
1085 oplen = enccrd->crd_skip + enccrd->crd_len;
1086 if (maccrd->crd_skip + maccrd->crd_len != oplen) {
1087 DPRINTF(("%s: hash amount %u != crypt amount %u\n",
1088 __func__, maccrd->crd_skip + maccrd->crd_len,
1090 safestats.st_lenmismatch++;
1096 printf("mac: skip %d, len %d, inject %d\n",
1097 maccrd->crd_skip, maccrd->crd_len,
1098 maccrd->crd_inject);
1099 printf("enc: skip %d, len %d, inject %d\n",
1100 enccrd->crd_skip, enccrd->crd_len,
1101 enccrd->crd_inject);
1102 printf("bypass %d coffset %d oplen %d\n",
1103 bypass, coffset, oplen);
1106 if (coffset & 3) { /* offset must be 32-bit aligned */
1107 DPRINTF(("%s: coffset %u misaligned\n",
1108 __func__, coffset));
1109 safestats.st_coffmisaligned++;
1114 if (coffset > 255) { /* offset must be <256 dwords */
1115 DPRINTF(("%s: coffset %u too big\n",
1116 __func__, coffset));
1117 safestats.st_cofftoobig++;
1122 * Tell the hardware to copy the header to the output.
1123 * The header is defined as the data from the end of
1124 * the bypass to the start of data to be encrypted.
1125 * Typically this is the inline IV. Note that you need
1126 * to do this even if src+dst are the same; it appears
1127 * that w/o this bit the crypted data is written
1128 * immediately after the bypass data.
1130 cmd1 |= SAFE_SA_CMD1_HDRCOPY;
1132 * Disable IP header mutable bit handling. This is
1133 * needed to get correct HMAC calculations.
1135 cmd1 |= SAFE_SA_CMD1_MUTABLE;
1138 bypass = enccrd->crd_skip;
1139 oplen = bypass + enccrd->crd_len;
1141 bypass = maccrd->crd_skip;
1142 oplen = bypass + maccrd->crd_len;
1146 /* XXX verify multiple of 4 when using s/g */
1147 if (bypass > 96) { /* bypass offset must be <= 96 bytes */
1148 DPRINTF(("%s: bypass %u too big\n", __func__, bypass));
1149 safestats.st_bypasstoobig++;
1154 if (bus_dmamap_create(sc->sc_srcdmat, BUS_DMA_NOWAIT, &re->re_src_map)) {
1155 safestats.st_nomap++;
1159 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1160 if (bus_dmamap_load_mbuf(sc->sc_srcdmat, re->re_src_map,
1161 re->re_src_m, safe_op_cb,
1162 &re->re_src, BUS_DMA_NOWAIT) != 0) {
1163 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map);
1164 re->re_src_map = NULL;
1165 safestats.st_noload++;
1169 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1170 if (bus_dmamap_load_uio(sc->sc_srcdmat, re->re_src_map,
1171 re->re_src_io, safe_op_cb,
1172 &re->re_src, BUS_DMA_NOWAIT) != 0) {
1173 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map);
1174 re->re_src_map = NULL;
1175 safestats.st_noload++;
1180 nicealign = safe_dmamap_aligned(&re->re_src);
1181 uniform = safe_dmamap_uniform(&re->re_src);
1183 DPRINTF(("src nicealign %u uniform %u nsegs %u\n",
1184 nicealign, uniform, re->re_src.nsegs));
1185 if (re->re_src.nsegs > 1) {
1186 re->re_desc.d_src = sc->sc_spalloc.dma_paddr +
1187 ((caddr_t) sc->sc_spfree - (caddr_t) sc->sc_spring);
1188 for (i = 0; i < re->re_src_nsegs; i++) {
1189 /* NB: no need to check if there's space */
1191 if (++(sc->sc_spfree) == sc->sc_springtop)
1192 sc->sc_spfree = sc->sc_spring;
1194 KASSERT((pd->pd_flags&3) == 0 ||
1195 (pd->pd_flags&3) == SAFE_PD_DONE,
1196 ("bogus source particle descriptor; flags %x",
1198 pd->pd_addr = re->re_src_segs[i].ds_addr;
1199 pd->pd_size = re->re_src_segs[i].ds_len;
1200 pd->pd_flags = SAFE_PD_READY;
1202 cmd0 |= SAFE_SA_CMD0_IGATHER;
1205 * No need for gather, reference the operand directly.
1207 re->re_desc.d_src = re->re_src_segs[0].ds_addr;
1210 if (enccrd == NULL && maccrd != NULL) {
1212 * Hash op; no destination needed.
1215 if (crp->crp_flags & CRYPTO_F_IOV) {
1217 safestats.st_iovmisaligned++;
1223 * Source is not suitable for direct use as
1224 * the destination. Create a new scatter/gather
1225 * list based on the destination requirements
1226 * and check if that's ok.
1228 if (bus_dmamap_create(sc->sc_dstdmat,
1229 BUS_DMA_NOWAIT, &re->re_dst_map)) {
1230 safestats.st_nomap++;
1234 if (bus_dmamap_load_uio(sc->sc_dstdmat,
1235 re->re_dst_map, re->re_dst_io,
1236 safe_op_cb, &re->re_dst,
1237 BUS_DMA_NOWAIT) != 0) {
1238 bus_dmamap_destroy(sc->sc_dstdmat,
1240 re->re_dst_map = NULL;
1241 safestats.st_noload++;
1245 uniform = safe_dmamap_uniform(&re->re_dst);
1248 * There's no way to handle the DMA
1249 * requirements with this uio. We
1250 * could create a separate DMA area for
1251 * the result and then copy it back,
1252 * but for now we just bail and return
1253 * an error. Note that uio requests
1254 * > SAFE_MAX_DSIZE are handled because
1255 * the DMA map and segment list for the
1256 * destination wil result in a
1257 * destination particle list that does
1258 * the necessary scatter DMA.
1260 safestats.st_iovnotuniform++;
1265 re->re_dst = re->re_src;
1266 } else if (crp->crp_flags & CRYPTO_F_IMBUF) {
1267 if (nicealign && uniform == 1) {
1269 * Source layout is suitable for direct
1270 * sharing of the DMA map and segment list.
1272 re->re_dst = re->re_src;
1273 } else if (nicealign && uniform == 2) {
1275 * The source is properly aligned but requires a
1276 * different particle list to handle DMA of the
1277 * result. Create a new map and do the load to
1278 * create the segment list. The particle
1279 * descriptor setup code below will handle the
1282 if (bus_dmamap_create(sc->sc_dstdmat,
1283 BUS_DMA_NOWAIT, &re->re_dst_map)) {
1284 safestats.st_nomap++;
1288 if (bus_dmamap_load_mbuf(sc->sc_dstdmat,
1289 re->re_dst_map, re->re_dst_m,
1290 safe_op_cb, &re->re_dst,
1291 BUS_DMA_NOWAIT) != 0) {
1292 bus_dmamap_destroy(sc->sc_dstdmat,
1294 re->re_dst_map = NULL;
1295 safestats.st_noload++;
1299 } else { /* !(aligned and/or uniform) */
1301 struct mbuf *m, *top, **mp;
1304 * DMA constraints require that we allocate a
1305 * new mbuf chain for the destination. We
1306 * allocate an entire new set of mbufs of
1307 * optimal/required size and then tell the
1308 * hardware to copy any bits that are not
1309 * created as a byproduct of the operation.
1312 safestats.st_unaligned++;
1314 safestats.st_notuniform++;
1315 totlen = re->re_src_mapsize;
1316 if (re->re_src_m->m_flags & M_PKTHDR) {
1318 MGETHDR(m, M_NOWAIT, MT_DATA);
1319 if (m && !m_dup_pkthdr(m, re->re_src_m,
1326 MGET(m, M_NOWAIT, MT_DATA);
1329 safestats.st_nombuf++;
1330 err = sc->sc_nqchip ? ERESTART : ENOMEM;
1333 if (totlen >= MINCLSIZE) {
1334 if (!(MCLGET(m, M_NOWAIT))) {
1336 safestats.st_nomcl++;
1337 err = sc->sc_nqchip ?
1347 while (totlen > 0) {
1349 MGET(m, M_NOWAIT, MT_DATA);
1352 safestats.st_nombuf++;
1353 err = sc->sc_nqchip ?
1359 if (top && totlen >= MINCLSIZE) {
1360 if (!(MCLGET(m, M_NOWAIT))) {
1363 safestats.st_nomcl++;
1364 err = sc->sc_nqchip ?
1370 m->m_len = len = min(totlen, len);
1376 if (bus_dmamap_create(sc->sc_dstdmat,
1377 BUS_DMA_NOWAIT, &re->re_dst_map) != 0) {
1378 safestats.st_nomap++;
1382 if (bus_dmamap_load_mbuf(sc->sc_dstdmat,
1383 re->re_dst_map, re->re_dst_m,
1384 safe_op_cb, &re->re_dst,
1385 BUS_DMA_NOWAIT) != 0) {
1386 bus_dmamap_destroy(sc->sc_dstdmat,
1388 re->re_dst_map = NULL;
1389 safestats.st_noload++;
1393 if (re->re_src.mapsize > oplen) {
1395 * There's data following what the
1396 * hardware will copy for us. If this
1397 * isn't just the ICV (that's going to
1398 * be written on completion), copy it
1402 (re->re_src.mapsize-oplen) == 12 &&
1403 maccrd->crd_inject == oplen))
1404 safe_mcopy(re->re_src_m,
1408 safestats.st_noicvcopy++;
1412 safestats.st_badflags++;
1417 if (re->re_dst.nsegs > 1) {
1418 re->re_desc.d_dst = sc->sc_dpalloc.dma_paddr +
1419 ((caddr_t) sc->sc_dpfree - (caddr_t) sc->sc_dpring);
1420 for (i = 0; i < re->re_dst_nsegs; i++) {
1422 KASSERT((pd->pd_flags&3) == 0 ||
1423 (pd->pd_flags&3) == SAFE_PD_DONE,
1424 ("bogus dest particle descriptor; flags %x",
1426 if (++(sc->sc_dpfree) == sc->sc_dpringtop)
1427 sc->sc_dpfree = sc->sc_dpring;
1428 pd->pd_addr = re->re_dst_segs[i].ds_addr;
1429 pd->pd_flags = SAFE_PD_READY;
1431 cmd0 |= SAFE_SA_CMD0_OSCATTER;
1434 * No need for scatter, reference the operand directly.
1436 re->re_desc.d_dst = re->re_dst_segs[0].ds_addr;
1441 * All done with setup; fillin the SA command words
1442 * and the packet engine descriptor. The operation
1443 * is now ready for submission to the hardware.
1445 sa->sa_cmd0 = cmd0 | SAFE_SA_CMD0_IPCI | SAFE_SA_CMD0_OPCI;
1447 | (coffset << SAFE_SA_CMD1_OFFSET_S)
1448 | SAFE_SA_CMD1_SAREV1 /* Rev 1 SA data structure */
1449 | SAFE_SA_CMD1_SRPCI
1452 * NB: the order of writes is important here. In case the
1453 * chip is scanning the ring because of an outstanding request
1454 * it might nab this one too. In that case we need to make
1455 * sure the setup is complete before we write the length
1456 * field of the descriptor as it signals the descriptor is
1457 * ready for processing.
1459 re->re_desc.d_csr = SAFE_PE_CSR_READY | SAFE_PE_CSR_SAPCI;
1461 re->re_desc.d_csr |= SAFE_PE_CSR_LOADSA | SAFE_PE_CSR_HASHFINAL;
1462 re->re_desc.d_len = oplen
1464 | (bypass << SAFE_PE_LEN_BYPASS_S)
1467 safestats.st_ipackets++;
1468 safestats.st_ibytes += oplen;
1470 if (++(sc->sc_front) == sc->sc_ringtop)
1471 sc->sc_front = sc->sc_ring;
1473 /* XXX honor batching */
1475 mtx_unlock(&sc->sc_ringmtx);
1479 if ((re->re_dst_m != NULL) && (re->re_src_m != re->re_dst_m))
1480 m_freem(re->re_dst_m);
1482 if (re->re_dst_map != NULL && re->re_dst_map != re->re_src_map) {
1483 bus_dmamap_unload(sc->sc_dstdmat, re->re_dst_map);
1484 bus_dmamap_destroy(sc->sc_dstdmat, re->re_dst_map);
1486 if (re->re_src_map != NULL) {
1487 bus_dmamap_unload(sc->sc_srcdmat, re->re_src_map);
1488 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map);
1490 mtx_unlock(&sc->sc_ringmtx);
1491 if (err != ERESTART) {
1492 crp->crp_etype = err;
1495 sc->sc_needwakeup |= CRYPTO_SYMQ;
1501 safe_callback(struct safe_softc *sc, struct safe_ringentry *re)
1503 struct cryptop *crp = (struct cryptop *)re->re_crp;
1504 struct cryptodesc *crd;
1506 safestats.st_opackets++;
1507 safestats.st_obytes += re->re_dst.mapsize;
1509 safe_dma_sync(&sc->sc_ringalloc,
1510 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1511 if (re->re_desc.d_csr & SAFE_PE_CSR_STATUS) {
1512 device_printf(sc->sc_dev, "csr 0x%x cmd0 0x%x cmd1 0x%x\n",
1514 re->re_sa.sa_cmd0, re->re_sa.sa_cmd1);
1515 safestats.st_peoperr++;
1516 crp->crp_etype = EIO; /* something more meaningful? */
1518 if (re->re_dst_map != NULL && re->re_dst_map != re->re_src_map) {
1519 bus_dmamap_sync(sc->sc_dstdmat, re->re_dst_map,
1520 BUS_DMASYNC_POSTREAD);
1521 bus_dmamap_unload(sc->sc_dstdmat, re->re_dst_map);
1522 bus_dmamap_destroy(sc->sc_dstdmat, re->re_dst_map);
1524 bus_dmamap_sync(sc->sc_srcdmat, re->re_src_map, BUS_DMASYNC_POSTWRITE);
1525 bus_dmamap_unload(sc->sc_srcdmat, re->re_src_map);
1526 bus_dmamap_destroy(sc->sc_srcdmat, re->re_src_map);
1529 * If result was written to a differet mbuf chain, swap
1530 * it in as the return value and reclaim the original.
1532 if ((crp->crp_flags & CRYPTO_F_IMBUF) && re->re_src_m != re->re_dst_m) {
1533 m_freem(re->re_src_m);
1534 crp->crp_buf = (caddr_t)re->re_dst_m;
1537 if (re->re_flags & SAFE_QFLAGS_COPYOUTIV) {
1538 /* copy out IV for future use */
1539 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1542 if (crd->crd_alg == CRYPTO_DES_CBC ||
1543 crd->crd_alg == CRYPTO_3DES_CBC) {
1544 ivsize = 2*sizeof(u_int32_t);
1545 } else if (crd->crd_alg == CRYPTO_AES_CBC) {
1546 ivsize = 4*sizeof(u_int32_t);
1549 crypto_copydata(crp->crp_flags, crp->crp_buf,
1550 crd->crd_skip + crd->crd_len - ivsize, ivsize,
1551 (caddr_t)sc->sc_sessions[re->re_sesn].ses_iv);
1556 if (re->re_flags & SAFE_QFLAGS_COPYOUTICV) {
1557 /* copy out ICV result */
1558 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1559 if (!(crd->crd_alg == CRYPTO_MD5_HMAC ||
1560 crd->crd_alg == CRYPTO_SHA1_HMAC ||
1561 crd->crd_alg == CRYPTO_NULL_HMAC))
1563 if (crd->crd_alg == CRYPTO_SHA1_HMAC) {
1565 * SHA-1 ICV's are byte-swapped; fix 'em up
1566 * before copy them to their destination.
1568 re->re_sastate.sa_saved_indigest[0] =
1569 bswap32(re->re_sastate.sa_saved_indigest[0]);
1570 re->re_sastate.sa_saved_indigest[1] =
1571 bswap32(re->re_sastate.sa_saved_indigest[1]);
1572 re->re_sastate.sa_saved_indigest[2] =
1573 bswap32(re->re_sastate.sa_saved_indigest[2]);
1575 crypto_copyback(crp->crp_flags, crp->crp_buf,
1577 sc->sc_sessions[re->re_sesn].ses_mlen,
1578 (caddr_t)re->re_sastate.sa_saved_indigest);
1586 * Copy all data past offset from srcm to dstm.
1589 safe_mcopy(struct mbuf *srcm, struct mbuf *dstm, u_int offset)
1591 u_int j, dlen, slen;
1595 * Advance src and dst to offset.
1598 while (j >= srcm->m_len) {
1600 srcm = srcm->m_next;
1604 sptr = mtod(srcm, caddr_t) + j;
1605 slen = srcm->m_len - j;
1608 while (j >= dstm->m_len) {
1610 dstm = dstm->m_next;
1614 dptr = mtod(dstm, caddr_t) + j;
1615 dlen = dstm->m_len - j;
1618 * Copy everything that remains.
1621 j = min(slen, dlen);
1622 bcopy(sptr, dptr, j);
1624 srcm = srcm->m_next;
1627 sptr = srcm->m_data;
1630 sptr += j, slen -= j;
1632 dstm = dstm->m_next;
1635 dptr = dstm->m_data;
1638 dptr += j, dlen -= j;
1643 #define SAFE_RNG_MAXWAIT 1000
1646 safe_rng_init(struct safe_softc *sc)
1651 WRITE_REG(sc, SAFE_RNG_CTRL, 0);
1652 /* use default value according to the manual */
1653 WRITE_REG(sc, SAFE_RNG_CNFG, 0x834); /* magic from SafeNet */
1654 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0);
1657 * There is a bug in rev 1.0 of the 1140 that when the RNG
1658 * is brought out of reset the ready status flag does not
1659 * work until the RNG has finished its internal initialization.
1661 * So in order to determine the device is through its
1662 * initialization we must read the data register, using the
1663 * status reg in the read in case it is initialized. Then read
1664 * the data register until it changes from the first read.
1665 * Once it changes read the data register until it changes
1666 * again. At this time the RNG is considered initialized.
1667 * This could take between 750ms - 1000ms in time.
1670 w = READ_REG(sc, SAFE_RNG_OUT);
1672 v = READ_REG(sc, SAFE_RNG_OUT);
1678 } while (++i < SAFE_RNG_MAXWAIT);
1680 /* Wait Until data changes again */
1683 v = READ_REG(sc, SAFE_RNG_OUT);
1687 } while (++i < SAFE_RNG_MAXWAIT);
1690 static __inline void
1691 safe_rng_disable_short_cycle(struct safe_softc *sc)
1693 WRITE_REG(sc, SAFE_RNG_CTRL,
1694 READ_REG(sc, SAFE_RNG_CTRL) &~ SAFE_RNG_CTRL_SHORTEN);
1697 static __inline void
1698 safe_rng_enable_short_cycle(struct safe_softc *sc)
1700 WRITE_REG(sc, SAFE_RNG_CTRL,
1701 READ_REG(sc, SAFE_RNG_CTRL) | SAFE_RNG_CTRL_SHORTEN);
1704 static __inline u_int32_t
1705 safe_rng_read(struct safe_softc *sc)
1710 while (READ_REG(sc, SAFE_RNG_STAT) != 0 && ++i < SAFE_RNG_MAXWAIT)
1712 return READ_REG(sc, SAFE_RNG_OUT);
1718 struct safe_softc *sc = arg;
1719 u_int32_t buf[SAFE_RNG_MAXBUFSIZ]; /* NB: maybe move to softc */
1725 * Fetch the next block of data.
1727 maxwords = safe_rngbufsize;
1728 if (maxwords > SAFE_RNG_MAXBUFSIZ)
1729 maxwords = SAFE_RNG_MAXBUFSIZ;
1731 for (i = 0; i < maxwords; i++)
1732 buf[i] = safe_rng_read(sc);
1734 * Check the comparator alarm count and reset the h/w if
1735 * it exceeds our threshold. This guards against the
1736 * hardware oscillators resonating with external signals.
1738 if (READ_REG(sc, SAFE_RNG_ALM_CNT) > safe_rngmaxalarm) {
1739 u_int32_t freq_inc, w;
1741 DPRINTF(("%s: alarm count %u exceeds threshold %u\n", __func__,
1742 READ_REG(sc, SAFE_RNG_ALM_CNT), safe_rngmaxalarm));
1743 safestats.st_rngalarm++;
1744 safe_rng_enable_short_cycle(sc);
1746 for (i = 0; i < 64; i++) {
1747 w = READ_REG(sc, SAFE_RNG_CNFG);
1748 freq_inc = ((w + freq_inc) & 0x3fL);
1749 w = ((w & ~0x3fL) | freq_inc);
1750 WRITE_REG(sc, SAFE_RNG_CNFG, w);
1752 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0);
1754 (void) safe_rng_read(sc);
1757 if (READ_REG(sc, SAFE_RNG_ALM_CNT) == 0) {
1758 safe_rng_disable_short_cycle(sc);
1763 safe_rng_disable_short_cycle(sc);
1765 WRITE_REG(sc, SAFE_RNG_ALM_CNT, 0);
1767 (*sc->sc_harvest)(sc->sc_rndtest, buf, maxwords*sizeof (u_int32_t));
1768 callout_reset(&sc->sc_rngto,
1769 hz * (safe_rnginterval ? safe_rnginterval : 1), safe_rng, sc);
1771 #endif /* SAFE_NO_RNG */
1774 safe_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1776 bus_addr_t *paddr = (bus_addr_t*) arg;
1777 *paddr = segs->ds_addr;
1782 struct safe_softc *sc,
1784 struct safe_dma_alloc *dma,
1790 r = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
1791 sizeof(u_int32_t), 0, /* alignment, bounds */
1792 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1793 BUS_SPACE_MAXADDR, /* highaddr */
1794 NULL, NULL, /* filter, filterarg */
1797 size, /* maxsegsize */
1798 BUS_DMA_ALLOCNOW, /* flags */
1799 NULL, NULL, /* locking */
1802 device_printf(sc->sc_dev, "safe_dma_malloc: "
1803 "bus_dma_tag_create failed; error %u\n", r);
1807 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr,
1808 BUS_DMA_NOWAIT, &dma->dma_map);
1810 device_printf(sc->sc_dev, "safe_dma_malloc: "
1811 "bus_dmammem_alloc failed; size %ju, error %u\n",
1812 (uintmax_t)size, r);
1816 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,
1820 mapflags | BUS_DMA_NOWAIT);
1822 device_printf(sc->sc_dev, "safe_dma_malloc: "
1823 "bus_dmamap_load failed; error %u\n", r);
1827 dma->dma_size = size;
1830 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1832 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1834 bus_dma_tag_destroy(dma->dma_tag);
1836 dma->dma_tag = NULL;
1841 safe_dma_free(struct safe_softc *sc, struct safe_dma_alloc *dma)
1843 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1844 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1845 bus_dma_tag_destroy(dma->dma_tag);
1849 * Resets the board. Values in the regesters are left as is
1850 * from the reset (i.e. initial values are assigned elsewhere).
1853 safe_reset_board(struct safe_softc *sc)
1857 * Reset the device. The manual says no delay
1858 * is needed between marking and clearing reset.
1860 v = READ_REG(sc, SAFE_PE_DMACFG) &~
1861 (SAFE_PE_DMACFG_PERESET | SAFE_PE_DMACFG_PDRRESET |
1862 SAFE_PE_DMACFG_SGRESET);
1863 WRITE_REG(sc, SAFE_PE_DMACFG, v
1864 | SAFE_PE_DMACFG_PERESET
1865 | SAFE_PE_DMACFG_PDRRESET
1866 | SAFE_PE_DMACFG_SGRESET);
1867 WRITE_REG(sc, SAFE_PE_DMACFG, v);
1871 * Initialize registers we need to touch only once.
1874 safe_init_board(struct safe_softc *sc)
1876 u_int32_t v, dwords;
1878 v = READ_REG(sc, SAFE_PE_DMACFG);
1879 v &=~ SAFE_PE_DMACFG_PEMODE;
1880 v |= SAFE_PE_DMACFG_FSENA /* failsafe enable */
1881 | SAFE_PE_DMACFG_GPRPCI /* gather ring on PCI */
1882 | SAFE_PE_DMACFG_SPRPCI /* scatter ring on PCI */
1883 | SAFE_PE_DMACFG_ESDESC /* endian-swap descriptors */
1884 | SAFE_PE_DMACFG_ESSA /* endian-swap SA's */
1885 | SAFE_PE_DMACFG_ESPDESC /* endian-swap part. desc's */
1887 WRITE_REG(sc, SAFE_PE_DMACFG, v);
1889 /* XXX select byte swap based on host byte order */
1890 WRITE_REG(sc, SAFE_ENDIAN, 0x1b);
1892 if (sc->sc_chiprev == SAFE_REV(1,0)) {
1894 * Avoid large PCI DMA transfers. Rev 1.0 has a bug where
1895 * "target mode transfers" done while the chip is DMA'ing
1896 * >1020 bytes cause the hardware to lockup. To avoid this
1897 * we reduce the max PCI transfer size and use small source
1898 * particle descriptors (<= 256 bytes).
1900 WRITE_REG(sc, SAFE_DMA_CFG, 256);
1901 device_printf(sc->sc_dev,
1902 "Reduce max DMA size to %u words for rev %u.%u WAR\n",
1903 (READ_REG(sc, SAFE_DMA_CFG)>>2) & 0xff,
1904 SAFE_REV_MAJ(sc->sc_chiprev),
1905 SAFE_REV_MIN(sc->sc_chiprev));
1908 /* NB: operands+results are overlaid */
1909 WRITE_REG(sc, SAFE_PE_PDRBASE, sc->sc_ringalloc.dma_paddr);
1910 WRITE_REG(sc, SAFE_PE_RDRBASE, sc->sc_ringalloc.dma_paddr);
1912 * Configure ring entry size and number of items in the ring.
1914 KASSERT((sizeof(struct safe_ringentry) % sizeof(u_int32_t)) == 0,
1915 ("PE ring entry not 32-bit aligned!"));
1916 dwords = sizeof(struct safe_ringentry) / sizeof(u_int32_t);
1917 WRITE_REG(sc, SAFE_PE_RINGCFG,
1918 (dwords << SAFE_PE_RINGCFG_OFFSET_S) | SAFE_MAX_NQUEUE);
1919 WRITE_REG(sc, SAFE_PE_RINGPOLL, 0); /* disable polling */
1921 WRITE_REG(sc, SAFE_PE_GRNGBASE, sc->sc_spalloc.dma_paddr);
1922 WRITE_REG(sc, SAFE_PE_SRNGBASE, sc->sc_dpalloc.dma_paddr);
1923 WRITE_REG(sc, SAFE_PE_PARTSIZE,
1924 (SAFE_TOTAL_DPART<<16) | SAFE_TOTAL_SPART);
1926 * NB: destination particles are fixed size. We use
1927 * an mbuf cluster and require all results go to
1928 * clusters or smaller.
1930 WRITE_REG(sc, SAFE_PE_PARTCFG, SAFE_MAX_DSIZE);
1932 /* it's now safe to enable PE mode, do it */
1933 WRITE_REG(sc, SAFE_PE_DMACFG, v | SAFE_PE_DMACFG_PEMODE);
1936 * Configure hardware to use level-triggered interrupts and
1937 * to interrupt after each descriptor is processed.
1939 WRITE_REG(sc, SAFE_HI_CFG, SAFE_HI_CFG_LEVEL);
1940 WRITE_REG(sc, SAFE_HI_DESC_CNT, 1);
1941 WRITE_REG(sc, SAFE_HI_MASK, SAFE_INT_PE_DDONE | SAFE_INT_PE_ERROR);
1945 * Init PCI registers
1948 safe_init_pciregs(device_t dev)
1953 * Clean up after a chip crash.
1954 * It is assumed that the caller in splimp()
1957 safe_cleanchip(struct safe_softc *sc)
1960 if (sc->sc_nqchip != 0) {
1961 struct safe_ringentry *re = sc->sc_back;
1963 while (re != sc->sc_front) {
1964 if (re->re_desc.d_csr != 0)
1965 safe_free_entry(sc, re);
1966 if (++re == sc->sc_ringtop)
1976 * It is assumed that the caller is within splimp().
1979 safe_free_entry(struct safe_softc *sc, struct safe_ringentry *re)
1981 struct cryptop *crp;
1986 if ((re->re_dst_m != NULL) && (re->re_src_m != re->re_dst_m))
1987 m_freem(re->re_dst_m);
1989 crp = (struct cryptop *)re->re_crp;
1991 re->re_desc.d_csr = 0;
1993 crp->crp_etype = EFAULT;
1999 * Routine to reset the chip and clean up.
2000 * It is assumed that the caller is in splimp()
2003 safe_totalreset(struct safe_softc *sc)
2005 safe_reset_board(sc);
2006 safe_init_board(sc);
2011 * Is the operand suitable aligned for direct DMA. Each
2012 * segment must be aligned on a 32-bit boundary and all
2013 * but the last segment must be a multiple of 4 bytes.
2016 safe_dmamap_aligned(const struct safe_operand *op)
2020 for (i = 0; i < op->nsegs; i++) {
2021 if (op->segs[i].ds_addr & 3)
2023 if (i != (op->nsegs - 1) && (op->segs[i].ds_len & 3))
2030 * Is the operand suitable for direct DMA as the destination
2031 * of an operation. The hardware requires that each ``particle''
2032 * but the last in an operation result have the same size. We
2033 * fix that size at SAFE_MAX_DSIZE bytes. This routine returns
2034 * 0 if some segment is not a multiple of of this size, 1 if all
2035 * segments are exactly this size, or 2 if segments are at worst
2036 * a multple of this size.
2039 safe_dmamap_uniform(const struct safe_operand *op)
2043 if (op->nsegs > 0) {
2046 for (i = 0; i < op->nsegs-1; i++) {
2047 if (op->segs[i].ds_len % SAFE_MAX_DSIZE)
2049 if (op->segs[i].ds_len != SAFE_MAX_DSIZE)
2058 safe_dump_dmastatus(struct safe_softc *sc, const char *tag)
2060 printf("%s: ENDIAN 0x%x SRC 0x%x DST 0x%x STAT 0x%x\n"
2062 , READ_REG(sc, SAFE_DMA_ENDIAN)
2063 , READ_REG(sc, SAFE_DMA_SRCADDR)
2064 , READ_REG(sc, SAFE_DMA_DSTADDR)
2065 , READ_REG(sc, SAFE_DMA_STAT)
2070 safe_dump_intrstate(struct safe_softc *sc, const char *tag)
2072 printf("%s: HI_CFG 0x%x HI_MASK 0x%x HI_DESC_CNT 0x%x HU_STAT 0x%x HM_STAT 0x%x\n"
2074 , READ_REG(sc, SAFE_HI_CFG)
2075 , READ_REG(sc, SAFE_HI_MASK)
2076 , READ_REG(sc, SAFE_HI_DESC_CNT)
2077 , READ_REG(sc, SAFE_HU_STAT)
2078 , READ_REG(sc, SAFE_HM_STAT)
2083 safe_dump_ringstate(struct safe_softc *sc, const char *tag)
2085 u_int32_t estat = READ_REG(sc, SAFE_PE_ERNGSTAT);
2087 /* NB: assume caller has lock on ring */
2088 printf("%s: ERNGSTAT %x (next %u) back %lu front %lu\n",
2090 estat, (estat >> SAFE_PE_ERNGSTAT_NEXT_S),
2091 (unsigned long)(sc->sc_back - sc->sc_ring),
2092 (unsigned long)(sc->sc_front - sc->sc_ring));
2096 safe_dump_request(struct safe_softc *sc, const char* tag, struct safe_ringentry *re)
2100 ix = re - sc->sc_ring;
2101 printf("%s: %p (%u): csr %x src %x dst %x sa %x len %x\n"
2110 if (re->re_src.nsegs > 1) {
2111 ix = (re->re_desc.d_src - sc->sc_spalloc.dma_paddr) /
2112 sizeof(struct safe_pdesc);
2113 for (nsegs = re->re_src.nsegs; nsegs; nsegs--) {
2114 printf(" spd[%u] %p: %p size %u flags %x"
2115 , ix, &sc->sc_spring[ix]
2116 , (caddr_t)(uintptr_t) sc->sc_spring[ix].pd_addr
2117 , sc->sc_spring[ix].pd_size
2118 , sc->sc_spring[ix].pd_flags
2120 if (sc->sc_spring[ix].pd_size == 0)
2123 if (++ix == SAFE_TOTAL_SPART)
2127 if (re->re_dst.nsegs > 1) {
2128 ix = (re->re_desc.d_dst - sc->sc_dpalloc.dma_paddr) /
2129 sizeof(struct safe_pdesc);
2130 for (nsegs = re->re_dst.nsegs; nsegs; nsegs--) {
2131 printf(" dpd[%u] %p: %p flags %x\n"
2132 , ix, &sc->sc_dpring[ix]
2133 , (caddr_t)(uintptr_t) sc->sc_dpring[ix].pd_addr
2134 , sc->sc_dpring[ix].pd_flags
2136 if (++ix == SAFE_TOTAL_DPART)
2140 printf("sa: cmd0 %08x cmd1 %08x staterec %x\n",
2141 re->re_sa.sa_cmd0, re->re_sa.sa_cmd1, re->re_sa.sa_staterec);
2142 printf("sa: key %x %x %x %x %x %x %x %x\n"
2143 , re->re_sa.sa_key[0]
2144 , re->re_sa.sa_key[1]
2145 , re->re_sa.sa_key[2]
2146 , re->re_sa.sa_key[3]
2147 , re->re_sa.sa_key[4]
2148 , re->re_sa.sa_key[5]
2149 , re->re_sa.sa_key[6]
2150 , re->re_sa.sa_key[7]
2152 printf("sa: indigest %x %x %x %x %x\n"
2153 , re->re_sa.sa_indigest[0]
2154 , re->re_sa.sa_indigest[1]
2155 , re->re_sa.sa_indigest[2]
2156 , re->re_sa.sa_indigest[3]
2157 , re->re_sa.sa_indigest[4]
2159 printf("sa: outdigest %x %x %x %x %x\n"
2160 , re->re_sa.sa_outdigest[0]
2161 , re->re_sa.sa_outdigest[1]
2162 , re->re_sa.sa_outdigest[2]
2163 , re->re_sa.sa_outdigest[3]
2164 , re->re_sa.sa_outdigest[4]
2166 printf("sr: iv %x %x %x %x\n"
2167 , re->re_sastate.sa_saved_iv[0]
2168 , re->re_sastate.sa_saved_iv[1]
2169 , re->re_sastate.sa_saved_iv[2]
2170 , re->re_sastate.sa_saved_iv[3]
2172 printf("sr: hashbc %u indigest %x %x %x %x %x\n"
2173 , re->re_sastate.sa_saved_hashbc
2174 , re->re_sastate.sa_saved_indigest[0]
2175 , re->re_sastate.sa_saved_indigest[1]
2176 , re->re_sastate.sa_saved_indigest[2]
2177 , re->re_sastate.sa_saved_indigest[3]
2178 , re->re_sastate.sa_saved_indigest[4]
2183 safe_dump_ring(struct safe_softc *sc, const char *tag)
2185 mtx_lock(&sc->sc_ringmtx);
2186 printf("\nSafeNet Ring State:\n");
2187 safe_dump_intrstate(sc, tag);
2188 safe_dump_dmastatus(sc, tag);
2189 safe_dump_ringstate(sc, tag);
2190 if (sc->sc_nqchip) {
2191 struct safe_ringentry *re = sc->sc_back;
2193 safe_dump_request(sc, tag, re);
2194 if (++re == sc->sc_ringtop)
2196 } while (re != sc->sc_front);
2198 mtx_unlock(&sc->sc_ringmtx);
2202 sysctl_hw_safe_dump(SYSCTL_HANDLER_ARGS)
2207 strncpy(dmode, "", sizeof(dmode) - 1);
2208 dmode[sizeof(dmode) - 1] = '\0';
2209 error = sysctl_handle_string(oidp, &dmode[0], sizeof(dmode), req);
2211 if (error == 0 && req->newptr != NULL) {
2212 struct safe_softc *sc = safec;
2216 if (strncmp(dmode, "dma", 3) == 0)
2217 safe_dump_dmastatus(sc, "safe0");
2218 else if (strncmp(dmode, "int", 3) == 0)
2219 safe_dump_intrstate(sc, "safe0");
2220 else if (strncmp(dmode, "ring", 4) == 0)
2221 safe_dump_ring(sc, "safe0");
2227 SYSCTL_PROC(_hw_safe, OID_AUTO, dump, CTLTYPE_STRING | CTLFLAG_RW,
2228 0, 0, sysctl_hw_safe_dump, "A", "Dump driver state");
2229 #endif /* SAFE_DEBUG */