2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2003 Sam Leffler, Errno Consulting
5 * Copyright (c) 2003 Global Technology Associates, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #ifndef _SAFE_SAFEVAR_H_
32 #define _SAFE_SAFEVAR_H_
34 /* Maximum queue length */
35 #ifndef SAFE_MAX_NQUEUE
36 #define SAFE_MAX_NQUEUE 60
39 #define SAFE_MAX_PART 64 /* Maximum scatter/gather depth */
40 #define SAFE_DMA_BOUNDARY 0 /* No boundary for source DMA ops */
41 #define SAFE_MAX_DSIZE MCLBYTES /* Fixed scatter particle size */
42 #define SAFE_MAX_SSIZE 0x0ffff /* Maximum gather particle size */
43 #define SAFE_MAX_DMA 0xfffff /* Maximum PE operand size (20 bits) */
44 /* total src+dst particle descriptors */
45 #define SAFE_TOTAL_DPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART)
46 #define SAFE_TOTAL_SPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART)
48 #define SAFE_RNG_MAXBUFSIZ 128 /* 32-bit words */
50 #define SAFE_DEF_RTY 0xff /* PCI Retry Timeout */
51 #define SAFE_DEF_TOUT 0xff /* PCI TRDY Timeout */
52 #define SAFE_DEF_CACHELINE 0x01 /* Cache Line setting */
56 * State associated with the allocation of each chunk
57 * of memory setup for DMA.
59 struct safe_dma_alloc {
60 u_int32_t dma_paddr; /* physical address */
61 caddr_t dma_vaddr; /* virtual address */
62 bus_dma_tag_t dma_tag; /* bus dma tag used */
63 bus_dmamap_t dma_map; /* associated map */
64 bus_dma_segment_t dma_seg;
65 bus_size_t dma_size; /* mapped memory size (bytes) */
66 int dma_nseg; /* number of segments */
70 * Cryptographic operand state. One of these exists for each
71 * source and destination operand passed in from the crypto
72 * subsystem. When possible source and destination operands
73 * refer to the same memory. More often they are distinct.
74 * We track the virtual address of each operand as well as
75 * where each is mapped for DMA.
85 bus_dma_segment_t segs[SAFE_MAX_PART];
89 * Packet engine ring entry and cryptographic operation state.
90 * The packet engine requires a ring of descriptors that contain
91 * pointers to various cryptographic state. However the ring
92 * configuration register allows you to specify an arbitrary size
93 * for ring entries. We use this feature to collect most of the
94 * state for each cryptographic request into one spot. Other than
95 * ring entries only the ``particle descriptors'' (scatter/gather
96 * lists) and the actual operand data are kept separate. The
97 * particle descriptors must also be organized in rings. The
98 * operand data can be located aribtrarily (modulo alignment constraints).
100 * Note that the descriptor ring is mapped onto the PCI bus so
101 * the hardware can DMA data. This means the entire ring must be
104 struct safe_ringentry {
105 struct safe_desc re_desc; /* command descriptor */
106 struct safe_sarec re_sa; /* SA record */
107 struct safe_sastate re_sastate; /* SA state record */
108 struct cryptop *re_crp; /* crypto operation */
110 struct safe_operand re_src; /* source operand */
111 struct safe_operand re_dst; /* destination operand */
115 #define SAFE_QFLAGS_COPYOUTIV 0x1 /* copy back on completion */
116 #define SAFE_QFLAGS_COPYOUTICV 0x2 /* copy back on completion */
119 #define re_src_m re_src.u.m
120 #define re_src_io re_src.u.io
121 #define re_src_map re_src.map
122 #define re_src_nsegs re_src.nsegs
123 #define re_src_segs re_src.segs
124 #define re_src_mapsize re_src.mapsize
126 #define re_dst_m re_dst.u.m
127 #define re_dst_io re_dst.u.io
128 #define re_dst_map re_dst.map
129 #define re_dst_nsegs re_dst.nsegs
130 #define re_dst_segs re_dst.segs
131 #define re_dst_mapsize re_dst.mapsize
133 struct rndstate_test;
135 struct safe_session {
136 u_int32_t ses_klen; /* key length in bits */
137 u_int32_t ses_key[8]; /* DES/3DES/AES key */
138 u_int32_t ses_mlen; /* hmac length in bytes */
139 u_int32_t ses_hminner[5]; /* hmac inner state */
140 u_int32_t ses_hmouter[5]; /* hmac outer state */
141 u_int32_t ses_iv[4]; /* DES/3DES/AES iv */
145 device_t sc_dev; /* device backpointer */
146 struct resource *sc_irq;
147 void *sc_ih; /* interrupt handler cookie */
148 bus_space_handle_t sc_sh; /* memory handle */
149 bus_space_tag_t sc_st; /* memory tag */
150 struct resource *sc_sr; /* memory resource */
151 bus_dma_tag_t sc_srcdmat; /* source dma tag */
152 bus_dma_tag_t sc_dstdmat; /* destination dma tag */
153 u_int sc_chiprev; /* major/minor chip revision */
154 int sc_flags; /* device specific flags */
155 #define SAFE_FLAGS_KEY 0x01 /* has key accelerator */
156 #define SAFE_FLAGS_RNG 0x02 /* hardware rng */
158 int sc_needwakeup; /* notify crypto layer */
159 int32_t sc_cid; /* crypto tag */
160 struct safe_dma_alloc sc_ringalloc; /* PE ring allocation state */
161 struct safe_ringentry *sc_ring; /* PE ring */
162 struct safe_ringentry *sc_ringtop; /* PE ring top */
163 struct safe_ringentry *sc_front; /* next free entry */
164 struct safe_ringentry *sc_back; /* next pending entry */
165 int sc_nqchip; /* # passed to chip */
166 struct mtx sc_ringmtx; /* PE ring lock */
167 struct safe_pdesc *sc_spring; /* src particle ring */
168 struct safe_pdesc *sc_springtop; /* src particle ring top */
169 struct safe_pdesc *sc_spfree; /* next free src particle */
170 struct safe_dma_alloc sc_spalloc; /* src particle ring state */
171 struct safe_pdesc *sc_dpring; /* dest particle ring */
172 struct safe_pdesc *sc_dpringtop; /* dest particle ring top */
173 struct safe_pdesc *sc_dpfree; /* next free dest particle */
174 struct safe_dma_alloc sc_dpalloc; /* dst particle ring state */
176 struct callout sc_rngto; /* rng timeout */
177 struct rndtest_state *sc_rndtest; /* RNG test state */
178 void (*sc_harvest)(struct rndtest_state *,
186 u_int32_t st_ipackets;
187 u_int32_t st_opackets;
188 u_int32_t st_invalid; /* invalid argument */
189 u_int32_t st_badsession; /* invalid session id */
190 u_int32_t st_badflags; /* flags indicate !(mbuf | uio) */
191 u_int32_t st_nodesc; /* op submitted w/o descriptors */
192 u_int32_t st_badalg; /* unsupported algorithm */
193 u_int32_t st_ringfull; /* PE descriptor ring full */
194 u_int32_t st_peoperr; /* PE marked error */
195 u_int32_t st_dmaerr; /* PE DMA error */
196 u_int32_t st_bypasstoobig; /* bypass > 96 bytes */
197 u_int32_t st_skipmismatch; /* enc part begins before auth part */
198 u_int32_t st_lenmismatch; /* enc length different auth length */
199 u_int32_t st_coffmisaligned; /* crypto offset not 32-bit aligned */
200 u_int32_t st_cofftoobig; /* crypto offset > 255 words */
201 u_int32_t st_iovmisaligned; /* iov op not aligned */
202 u_int32_t st_iovnotuniform; /* iov op not suitable */
203 u_int32_t st_unaligned; /* unaligned src caused copy */
204 u_int32_t st_notuniform; /* non-uniform src caused copy */
205 u_int32_t st_nomap; /* bus_dmamap_create failed */
206 u_int32_t st_noload; /* bus_dmamap_load_* failed */
207 u_int32_t st_nombuf; /* MGET* failed */
208 u_int32_t st_nomcl; /* MCLGET* failed */
209 u_int32_t st_maxqchip; /* max mcr1 ops out for processing */
210 u_int32_t st_rng; /* RNG requests */
211 u_int32_t st_rngalarm; /* RNG alarm requests */
212 u_int32_t st_noicvcopy; /* ICV data copies suppressed */
214 #endif /* _SAFE_SAFEVAR_H_ */