2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 * SDHCI driver glue for Freescale i.MX SoC and QorIQ families.
33 * This supports both eSDHC (earlier SoCs) and uSDHC (more recent SoCs).
36 #include "opt_mmccam.h"
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/types.h>
42 #include <sys/callout.h>
43 #include <sys/kernel.h>
44 #include <sys/libkern.h>
46 #include <sys/malloc.h>
47 #include <sys/module.h>
48 #include <sys/mutex.h>
49 #include <sys/resource.h>
51 #include <sys/sysctl.h>
52 #include <sys/taskqueue.h>
55 #include <machine/bus.h>
56 #include <machine/resource.h>
58 #include <machine/intr.h>
60 #include <arm/freescale/imx/imx_ccmvar.h>
64 #include <powerpc/mpc85xx/mpc85xx.h>
67 #include <dev/gpio/gpiobusvar.h>
69 #include <dev/ofw/ofw_bus.h>
70 #include <dev/ofw/ofw_bus_subr.h>
72 #include <dev/mmc/bridge.h>
74 #include <dev/sdhci/sdhci.h>
75 #include <dev/sdhci/sdhci_fdt_gpio.h>
80 struct fsl_sdhci_softc {
82 struct resource * mem_res;
83 struct resource * irq_res;
85 struct sdhci_slot slot;
86 struct callout r1bfix_callout;
87 sbintime_t r1bfix_timeout_at;
88 struct sdhci_fdt_gpio * gpio;
90 uint32_t cmd_and_mode;
91 uint32_t r1bfix_intmask;
92 uint16_t sdclockreg_freq_bits;
97 #define R1BFIX_NONE 0 /* No fix needed at next interrupt. */
98 #define R1BFIX_NODATA 1 /* Synthesize DATA_END for R1B w/o data. */
99 #define R1BFIX_AC12 2 /* Wait for busy after auto command 12. */
101 #define HWTYPE_NONE 0 /* Hardware not recognized/supported. */
102 #define HWTYPE_ESDHC 1 /* fsl5x and earlier. */
103 #define HWTYPE_USDHC 2 /* fsl6. */
106 * Freescale-specific registers, or in some cases the layout of bits within the
107 * sdhci-defined register is different on Freescale. These names all begin with
108 * SDHC_ (not SDHCI_).
111 #define SDHC_WTMK_LVL 0x44 /* Watermark Level register. */
112 #define USDHC_MIX_CONTROL 0x48 /* Mix(ed) Control register. */
113 #define SDHC_VEND_SPEC 0xC0 /* Vendor-specific register. */
114 #define SDHC_VEND_FRC_SDCLK_ON (1 << 8)
115 #define SDHC_VEND_IPGEN (1 << 11)
116 #define SDHC_VEND_HCKEN (1 << 12)
117 #define SDHC_VEND_PEREN (1 << 13)
119 #define SDHC_PRES_STATE 0x24
120 #define SDHC_PRES_CIHB (1 << 0)
121 #define SDHC_PRES_CDIHB (1 << 1)
122 #define SDHC_PRES_DLA (1 << 2)
123 #define SDHC_PRES_SDSTB (1 << 3)
124 #define SDHC_PRES_IPGOFF (1 << 4)
125 #define SDHC_PRES_HCKOFF (1 << 5)
126 #define SDHC_PRES_PEROFF (1 << 6)
127 #define SDHC_PRES_SDOFF (1 << 7)
128 #define SDHC_PRES_WTA (1 << 8)
129 #define SDHC_PRES_RTA (1 << 9)
130 #define SDHC_PRES_BWEN (1 << 10)
131 #define SDHC_PRES_BREN (1 << 11)
132 #define SDHC_PRES_RTR (1 << 12)
133 #define SDHC_PRES_CINST (1 << 16)
134 #define SDHC_PRES_CDPL (1 << 18)
135 #define SDHC_PRES_WPSPL (1 << 19)
136 #define SDHC_PRES_CLSL (1 << 23)
137 #define SDHC_PRES_DLSL_SHIFT 24
138 #define SDHC_PRES_DLSL_MASK (0xffU << SDHC_PRES_DLSL_SHIFT)
140 #define SDHC_PROT_CTRL 0x28
141 #define SDHC_PROT_LED (1 << 0)
142 #define SDHC_PROT_WIDTH_1BIT (0 << 1)
143 #define SDHC_PROT_WIDTH_4BIT (1 << 1)
144 #define SDHC_PROT_WIDTH_8BIT (2 << 1)
145 #define SDHC_PROT_WIDTH_MASK (3 << 1)
146 #define SDHC_PROT_D3CD (1 << 3)
147 #define SDHC_PROT_EMODE_BIG (0 << 4)
148 #define SDHC_PROT_EMODE_HALF (1 << 4)
149 #define SDHC_PROT_EMODE_LITTLE (2 << 4)
150 #define SDHC_PROT_EMODE_MASK (3 << 4)
151 #define SDHC_PROT_SDMA (0 << 8)
152 #define SDHC_PROT_ADMA1 (1 << 8)
153 #define SDHC_PROT_ADMA2 (2 << 8)
154 #define SDHC_PROT_ADMA264 (3 << 8)
155 #define SDHC_PROT_DMA_MASK (3 << 8)
156 #define SDHC_PROT_CDTL (1 << 6)
157 #define SDHC_PROT_CDSS (1 << 7)
159 #define SDHC_SYS_CTRL 0x2c
162 * The clock enable bits exist in different registers for ESDHC vs USDHC, but
163 * they are the same bits in both cases. The divisor values go into the
164 * standard sdhci clock register, but in different bit positions and meanings
165 than the sdhci spec values.
167 #define SDHC_CLK_IPGEN (1 << 0)
168 #define SDHC_CLK_HCKEN (1 << 1)
169 #define SDHC_CLK_PEREN (1 << 2)
170 #define SDHC_CLK_SDCLKEN (1 << 3)
171 #define SDHC_CLK_ENABLE_MASK 0x0000000f
172 #define SDHC_CLK_DIVISOR_MASK 0x000000f0
173 #define SDHC_CLK_DIVISOR_SHIFT 4
174 #define SDHC_CLK_PRESCALE_MASK 0x0000ff00
175 #define SDHC_CLK_PRESCALE_SHIFT 8
177 static struct ofw_compat_data compat_data[] = {
178 {"fsl,imx6q-usdhc", HWTYPE_USDHC},
179 {"fsl,imx6sl-usdhc", HWTYPE_USDHC},
180 {"fsl,imx53-esdhc", HWTYPE_ESDHC},
181 {"fsl,imx51-esdhc", HWTYPE_ESDHC},
182 {"fsl,esdhc", HWTYPE_ESDHC},
186 static uint16_t fsl_sdhc_get_clock(struct fsl_sdhci_softc *sc);
187 static void fsl_sdhc_set_clock(struct fsl_sdhci_softc *sc, uint16_t val);
188 static void fsl_sdhci_r1bfix_func(void *arg);
190 static inline uint32_t
191 RD4(struct fsl_sdhci_softc *sc, bus_size_t off)
194 return (bus_read_4(sc->mem_res, off));
198 WR4(struct fsl_sdhci_softc *sc, bus_size_t off, uint32_t val)
201 bus_write_4(sc->mem_res, off, val);
205 fsl_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
207 struct fsl_sdhci_softc *sc = device_get_softc(dev);
208 uint32_t val32, wrk32;
211 * Most of the things in the standard host control register are in the
212 * hardware's wider protocol control register, but some of the bits are
215 if (off == SDHCI_HOST_CONTROL) {
216 wrk32 = RD4(sc, SDHC_PROT_CTRL);
217 val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET |
218 SDHCI_CTRL_FORCE_CARD);
219 switch (wrk32 & SDHC_PROT_WIDTH_MASK) {
220 case SDHC_PROT_WIDTH_1BIT:
221 /* Value is already 0. */
223 case SDHC_PROT_WIDTH_4BIT:
224 val32 |= SDHCI_CTRL_4BITBUS;
226 case SDHC_PROT_WIDTH_8BIT:
227 val32 |= SDHCI_CTRL_8BITBUS;
230 switch (wrk32 & SDHC_PROT_DMA_MASK) {
232 /* Value is already 0. */
234 case SDHC_PROT_ADMA1:
235 /* This value is deprecated, should never appear. */
237 case SDHC_PROT_ADMA2:
238 val32 |= SDHCI_CTRL_ADMA2;
240 case SDHC_PROT_ADMA264:
241 val32 |= SDHCI_CTRL_ADMA264;
248 * XXX can't find the bus power on/off knob. For now we have to say the
249 * power is always on and always set to the same voltage.
251 if (off == SDHCI_POWER_CONTROL) {
252 return (SDHCI_POWER_ON | SDHCI_POWER_300);
256 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff);
260 fsl_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
262 struct fsl_sdhci_softc *sc = device_get_softc(dev);
265 if (sc->hwtype == HWTYPE_USDHC) {
267 * The USDHC hardware has nothing in the version register, but
268 * it's v3 compatible with all our translation code.
270 if (off == SDHCI_HOST_VERSION) {
271 return (SDHCI_SPEC_300 << SDHCI_SPEC_VER_SHIFT);
274 * The USDHC hardware moved the transfer mode bits to the mixed
275 * control register, fetch them from there.
277 if (off == SDHCI_TRANSFER_MODE)
278 return (RD4(sc, USDHC_MIX_CONTROL) & 0x37);
280 } else if (sc->hwtype == HWTYPE_ESDHC) {
283 * The ESDHC hardware has the typical 32-bit combined "command
284 * and mode" register that we have to cache so that command
285 * isn't written until after mode. On a read, just retrieve the
286 * cached values last written.
288 if (off == SDHCI_TRANSFER_MODE) {
289 return (sc->cmd_and_mode & 0x0000ffff);
290 } else if (off == SDHCI_COMMAND_FLAGS) {
291 return (sc->cmd_and_mode >> 16);
296 * This hardware only manages one slot. Synthesize a slot interrupt
297 * status register... if there are any enabled interrupts active they
298 * must be coming from our one and only slot.
300 if (off == SDHCI_SLOT_INT_STATUS) {
301 val32 = RD4(sc, SDHCI_INT_STATUS);
302 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE);
303 return (val32 ? 1 : 0);
307 * Clock bits are scattered into various registers which differ by
308 * hardware type, complex enough to have their own function.
310 if (off == SDHCI_CLOCK_CONTROL) {
311 return (fsl_sdhc_get_clock(sc));
314 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff);
318 fsl_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
320 struct fsl_sdhci_softc *sc = device_get_softc(dev);
321 uint32_t val32, wrk32;
323 val32 = RD4(sc, off);
326 * The hardware leaves the base clock frequency out of the capabilities
327 * register, but we filled it in by setting slot->max_clk at attach time
328 * rather than here, because we can't represent frequencies above 63MHz
329 * in an sdhci 2.0 capabliities register. The timeout clock is the same
330 * as the active output sdclock; we indicate that with a quirk setting
331 * so don't populate the timeout frequency bits.
333 * XXX Turn off (for now) features the hardware can do but this driver
334 * doesn't yet handle (1.8v, suspend/resume, etc).
336 if (off == SDHCI_CAPABILITIES) {
337 val32 &= ~SDHCI_CAN_VDD_180;
338 val32 &= ~SDHCI_CAN_DO_SUSPEND;
339 val32 |= SDHCI_CAN_DO_8BITBUS;
344 * The hardware moves bits around in the present state register to make
345 * room for all 8 data line state bits. To translate, mask out all the
346 * bits which are not in the same position in both registers (this also
347 * masks out some Freescale-specific bits in locations defined as
348 * reserved by sdhci), then shift the data line and retune request bits
349 * down to their standard locations.
351 if (off == SDHCI_PRESENT_STATE) {
354 val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK;
355 val32 |= (wrk32 >> 9) & SDHCI_RETUNE_REQUEST;
360 * fsl_sdhci_intr() can synthesize a DATA_END interrupt following a
361 * command with an R1B response, mix it into the hardware status.
363 if (off == SDHCI_INT_STATUS) {
364 return (val32 | sc->r1bfix_intmask);
371 fsl_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
372 uint32_t *data, bus_size_t count)
374 struct fsl_sdhci_softc *sc = device_get_softc(dev);
376 bus_read_multi_4(sc->mem_res, off, data, count);
380 fsl_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
382 struct fsl_sdhci_softc *sc = device_get_softc(dev);
386 * Most of the things in the standard host control register are in the
387 * hardware's wider protocol control register, but some of the bits are
390 if (off == SDHCI_HOST_CONTROL) {
391 val32 = RD4(sc, SDHC_PROT_CTRL);
392 val32 &= ~(SDHC_PROT_LED | SDHC_PROT_DMA_MASK |
393 SDHC_PROT_WIDTH_MASK | SDHC_PROT_CDTL | SDHC_PROT_CDSS);
394 val32 |= (val & SDHCI_CTRL_LED);
395 if (val & SDHCI_CTRL_8BITBUS)
396 val32 |= SDHC_PROT_WIDTH_8BIT;
398 val32 |= (val & SDHCI_CTRL_4BITBUS);
399 val32 |= (val & (SDHCI_CTRL_SDMA | SDHCI_CTRL_ADMA2)) << 4;
400 val32 |= (val & (SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD));
401 WR4(sc, SDHC_PROT_CTRL, val32);
405 /* XXX I can't find the bus power on/off knob; do nothing. */
406 if (off == SDHCI_POWER_CONTROL) {
410 /* XXX Reset doesn't seem to work as expected. Do nothing for now. */
411 if (off == SDHCI_SOFTWARE_RESET)
415 val32 = RD4(sc, off & ~3);
416 val32 &= ~(0xff << (off & 3) * 8);
417 val32 |= (val << (off & 3) * 8);
419 WR4(sc, off & ~3, val32);
423 fsl_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
425 struct fsl_sdhci_softc *sc = device_get_softc(dev);
429 * The clock control stuff is complex enough to have its own function
430 * that can handle the ESDHC versus USDHC differences.
432 if (off == SDHCI_CLOCK_CONTROL) {
433 fsl_sdhc_set_clock(sc, val);
438 * Figure out whether we need to check the DAT0 line for busy status at
439 * interrupt time. The controller should be doing this, but for some
440 * reason it doesn't. There are two cases:
441 * - R1B response with no data transfer should generate a DATA_END (aka
442 * TRANSFER_COMPLETE) interrupt after waiting for busy, but if
443 * there's no data transfer there's no DATA_END interrupt. This is
444 * documented; they seem to think it's a feature.
445 * - R1B response after Auto-CMD12 appears to not work, even though
446 * there's a control bit for it (bit 3) in the vendor register.
447 * When we're starting a command that needs a manual DAT0 line check at
448 * interrupt time, we leave ourselves a note in r1bfix_type so that we
449 * can do the extra work in fsl_sdhci_intr().
451 if (off == SDHCI_COMMAND_FLAGS) {
452 if (val & SDHCI_CMD_DATA) {
453 const uint32_t MBAUTOCMD = SDHCI_TRNS_ACMD12 | SDHCI_TRNS_MULTI;
454 val32 = RD4(sc, USDHC_MIX_CONTROL);
455 if ((val32 & MBAUTOCMD) == MBAUTOCMD)
456 sc->r1bfix_type = R1BFIX_AC12;
458 if ((val & SDHCI_CMD_RESP_MASK) == SDHCI_CMD_RESP_SHORT_BUSY) {
459 WR4(sc, SDHCI_INT_ENABLE, slot->intmask | SDHCI_INT_RESPONSE);
460 WR4(sc, SDHCI_SIGNAL_ENABLE, slot->intmask | SDHCI_INT_RESPONSE);
461 sc->r1bfix_type = R1BFIX_NODATA;
467 * The USDHC hardware moved the transfer mode bits to mixed control; we
468 * just write them there and we're done. The ESDHC hardware has the
469 * typical combined cmd-and-mode register that allows only 32-bit
470 * access, so when writing the mode bits just save them, then later when
471 * writing the command bits, add in the saved mode bits.
473 if (sc->hwtype == HWTYPE_USDHC) {
474 if (off == SDHCI_TRANSFER_MODE) {
475 val32 = RD4(sc, USDHC_MIX_CONTROL);
478 // XXX acmd23 not supported here (or by sdhci driver)
479 WR4(sc, USDHC_MIX_CONTROL, val32);
482 } else if (sc->hwtype == HWTYPE_ESDHC) {
483 if (off == SDHCI_TRANSFER_MODE) {
485 (sc->cmd_and_mode & 0xffff0000) | val;
487 } else if (off == SDHCI_COMMAND_FLAGS) {
489 (sc->cmd_and_mode & 0xffff) | (val << 16);
490 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode);
495 val32 = RD4(sc, off & ~3);
496 val32 &= ~(0xffff << (off & 3) * 8);
497 val32 |= ((val & 0xffff) << (off & 3) * 8);
498 WR4(sc, off & ~3, val32);
502 fsl_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
504 struct fsl_sdhci_softc *sc = device_get_softc(dev);
506 /* Clear synthesized interrupts, then pass the value to the hardware. */
507 if (off == SDHCI_INT_STATUS) {
508 sc->r1bfix_intmask &= ~val;
515 fsl_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
516 uint32_t *data, bus_size_t count)
518 struct fsl_sdhci_softc *sc = device_get_softc(dev);
520 bus_write_multi_4(sc->mem_res, off, data, count);
524 fsl_sdhc_get_clock(struct fsl_sdhci_softc *sc)
529 * Whenever the sdhci driver writes the clock register we save a
530 * snapshot of just the frequency bits, so that we can play them back
531 * here on a register read without recalculating the frequency from the
532 * prescalar and divisor bits in the real register. We'll start with
533 * those bits, and mix in the clock status and enable bits that come
534 * from different places depending on which hardware we've got.
536 val = sc->sdclockreg_freq_bits;
539 * The internal clock is always enabled (actually, the hardware manages
540 * it). Whether the internal clock is stable yet after a frequency
541 * change comes from the present-state register on both hardware types.
543 val |= SDHCI_CLOCK_INT_EN;
544 if (RD4(sc, SDHC_PRES_STATE) & SDHC_PRES_SDSTB)
545 val |= SDHCI_CLOCK_INT_STABLE;
548 * On i.MX ESDHC hardware the card bus clock enable is in the usual
549 * sdhci register but it's a different bit, so transcribe it (note the
550 * difference between standard SDHCI_ and Freescale SDHC_ prefixes
551 * here). On USDHC and QorIQ ESDHC hardware there is a force-on bit, but
552 * no force-off for the card bus clock (the hardware runs the clock when
553 * transfers are active no matter what), so we always say the clock is
555 * XXX Maybe we should say it's in whatever state the sdhci driver last
558 if (sc->hwtype == HWTYPE_ESDHC) {
560 if (RD4(sc, SDHC_SYS_CTRL) & SDHC_CLK_SDCLKEN)
562 val |= SDHCI_CLOCK_CARD_EN;
564 val |= SDHCI_CLOCK_CARD_EN;
571 fsl_sdhc_set_clock(struct fsl_sdhci_softc *sc, uint16_t val)
573 uint32_t divisor, freq, prescale, val32;
575 val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
578 * Save the frequency-setting bits in SDHCI format so that we can play
579 * them back in get_clock without complex decoding of hardware regs,
580 * then deal with the freqency part of the value based on hardware type.
582 sc->sdclockreg_freq_bits = val & SDHCI_DIVIDERS_MASK;
583 if (sc->hwtype == HWTYPE_ESDHC) {
585 * The i.MX5 ESDHC hardware requires the driver to manually
586 * start and stop the sd bus clock. If the enable bit is not
587 * set, turn off the clock in hardware and we're done, otherwise
588 * decode the requested frequency. ESDHC hardware is sdhci 2.0;
589 * the sdhci driver will use the original 8-bit divisor field
590 * and the "base / 2^N" divisor scheme.
592 if ((val & SDHCI_CLOCK_CARD_EN) == 0) {
594 /* On QorIQ, this is a reserved bit. */
595 WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHC_CLK_SDCLKEN);
600 divisor = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK;
601 freq = sc->baseclk_hz >> ffs(divisor);
604 * The USDHC hardware provides only "force always on" control
605 * over the sd bus clock, but no way to turn it off. (If a cmd
606 * or data transfer is in progress the clock is on, otherwise it
607 * is off.) If the clock is being disabled, we can just return
608 * now, otherwise we decode the requested frequency. USDHC
609 * hardware is sdhci 3.0; the sdhci driver will use a 10-bit
610 * divisor using the "base / 2*N" divisor scheme.
612 if ((val & SDHCI_CLOCK_CARD_EN) == 0)
614 divisor = ((val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK) |
615 ((val >> SDHCI_DIVIDER_HI_SHIFT) & SDHCI_DIVIDER_HI_MASK) <<
616 SDHCI_DIVIDER_MASK_LEN;
618 freq = sc->baseclk_hz;
620 freq = sc->baseclk_hz / (2 * divisor);
624 * Get a prescaler and final divisor to achieve the desired frequency.
626 for (prescale = 2; freq < sc->baseclk_hz / (prescale * 16);)
629 for (divisor = 1; freq < sc->baseclk_hz / (prescale * divisor);)
633 device_printf(sc->dev,
634 "desired SD freq: %d, actual: %d; base %d prescale %d divisor %d\n",
635 freq, sc->baseclk_hz / (prescale * divisor), sc->baseclk_hz,
640 * Adjust to zero-based values, and store them to the hardware.
645 val32 &= ~(SDHC_CLK_DIVISOR_MASK | SDHC_CLK_PRESCALE_MASK);
646 val32 |= divisor << SDHC_CLK_DIVISOR_SHIFT;
647 val32 |= prescale << SDHC_CLK_PRESCALE_SHIFT;
648 val32 |= SDHC_CLK_IPGEN;
649 WR4(sc, SDHCI_CLOCK_CONTROL, val32);
653 fsl_sdhci_r1bfix_is_wait_done(struct fsl_sdhci_softc *sc)
657 mtx_assert(&sc->slot.mtx, MA_OWNED);
660 * Check the DAT0 line status using both the DLA (data line active) and
661 * CDIHB (data inhibit) bits in the present state register. In theory
662 * just DLA should do the trick, but in practice it takes both. If the
663 * DAT0 line is still being held and we're not yet beyond the timeout
664 * point, just schedule another callout to check again later.
666 inhibit = RD4(sc, SDHC_PRES_STATE) & (SDHC_PRES_DLA | SDHC_PRES_CDIHB);
668 if (inhibit && getsbinuptime() < sc->r1bfix_timeout_at) {
669 callout_reset_sbt(&sc->r1bfix_callout, SBT_1MS, 0,
670 fsl_sdhci_r1bfix_func, sc, 0);
675 * If we reach this point with the inhibit bits still set, we've got a
676 * timeout, synthesize a DATA_TIMEOUT interrupt. Otherwise the DAT0
677 * line has been released, and we synthesize a DATA_END, and if the type
678 * of fix needed was on a command-without-data we also now add in the
679 * original INT_RESPONSE that we suppressed earlier.
682 sc->r1bfix_intmask |= SDHCI_INT_DATA_TIMEOUT;
684 sc->r1bfix_intmask |= SDHCI_INT_DATA_END;
685 if (sc->r1bfix_type == R1BFIX_NODATA)
686 sc->r1bfix_intmask |= SDHCI_INT_RESPONSE;
689 sc->r1bfix_type = R1BFIX_NONE;
694 fsl_sdhci_r1bfix_func(void * arg)
696 struct fsl_sdhci_softc *sc = arg;
697 boolean_t r1bwait_done;
699 mtx_lock(&sc->slot.mtx);
700 r1bwait_done = fsl_sdhci_r1bfix_is_wait_done(sc);
701 mtx_unlock(&sc->slot.mtx);
703 sdhci_generic_intr(&sc->slot);
707 fsl_sdhci_intr(void *arg)
709 struct fsl_sdhci_softc *sc = arg;
712 mtx_lock(&sc->slot.mtx);
715 * Manually check the DAT0 line for R1B response types that the
716 * controller fails to handle properly. The controller asserts the done
717 * interrupt while the card is still asserting busy with the DAT0 line.
719 * We check DAT0 immediately because most of the time, especially on a
720 * read, the card will actually be done by time we get here. If it's
721 * not, then the wait_done routine will schedule a callout to re-check
722 * periodically until it is done. In that case we clear the interrupt
723 * out of the hardware now so that we can present it later when the DAT0
726 * If we need to wait for the DAT0 line to be released, we set up a
727 * timeout point 250ms in the future. This number comes from the SD
728 * spec, which allows a command to take that long. In the real world,
729 * cards tend to take 10-20ms for a long-running command such as a write
730 * or erase that spans two pages.
732 switch (sc->r1bfix_type) {
734 intmask = RD4(sc, SDHCI_INT_STATUS) & SDHCI_INT_RESPONSE;
737 intmask = RD4(sc, SDHCI_INT_STATUS) & SDHCI_INT_DATA_END;
744 sc->r1bfix_timeout_at = getsbinuptime() + 250 * SBT_1MS;
745 if (!fsl_sdhci_r1bfix_is_wait_done(sc)) {
746 WR4(sc, SDHCI_INT_STATUS, intmask);
747 bus_barrier(sc->mem_res, SDHCI_INT_STATUS, 4,
748 BUS_SPACE_BARRIER_WRITE);
752 mtx_unlock(&sc->slot.mtx);
753 sdhci_generic_intr(&sc->slot);
757 fsl_sdhci_get_ro(device_t bus, device_t child)
759 struct fsl_sdhci_softc *sc = device_get_softc(bus);
761 return (sdhci_fdt_gpio_get_readonly(sc->gpio));
765 fsl_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot)
767 struct fsl_sdhci_softc *sc = device_get_softc(dev);
769 return (sdhci_fdt_gpio_get_present(sc->gpio));
774 fsl_sdhci_get_platform_clock(device_t dev)
779 node = ofw_bus_get_node(dev);
781 /* Get sdhci node properties */
782 if((OF_getprop(node, "clock-frequency", (void *)&clock,
783 sizeof(clock)) <= 0) || (clock == 0)) {
785 clock = mpc85xx_get_system_clock();
788 device_printf(dev,"Cannot acquire correct sdhci "
789 "frequency from DTS.\n");
796 device_printf(dev, "Acquired clock: %d from DTS\n", clock);
804 fsl_sdhci_detach(device_t dev)
806 struct fsl_sdhci_softc *sc = device_get_softc(dev);
808 if (sc->gpio != NULL)
809 sdhci_fdt_gpio_teardown(sc->gpio);
811 callout_drain(&sc->r1bfix_callout);
813 if (sc->intr_cookie != NULL)
814 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
815 if (sc->irq_res != NULL)
816 bus_release_resource(dev, SYS_RES_IRQ,
817 rman_get_rid(sc->irq_res), sc->irq_res);
819 if (sc->mem_res != NULL) {
820 sdhci_cleanup_slot(&sc->slot);
821 bus_release_resource(dev, SYS_RES_MEMORY,
822 rman_get_rid(sc->mem_res), sc->mem_res);
829 fsl_sdhci_attach(device_t dev)
831 struct fsl_sdhci_softc *sc = device_get_softc(dev);
840 sc->hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
841 if (sc->hwtype == HWTYPE_NONE)
842 panic("Impossible: not compatible in fsl_sdhci_attach()");
845 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
848 device_printf(dev, "cannot allocate memory window\n");
854 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
857 device_printf(dev, "cannot allocate interrupt\n");
862 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
863 NULL, fsl_sdhci_intr, sc, &sc->intr_cookie)) {
864 device_printf(dev, "cannot setup interrupt handler\n");
869 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
872 * DMA is not really broken, I just haven't implemented it yet.
874 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA;
877 * Set the buffer watermark level to 128 words (512 bytes) for both read
878 * and write. The hardware has a restriction that when the read or
879 * write ready status is asserted, that means you can read exactly the
880 * number of words set in the watermark register before you have to
881 * re-check the status and potentially wait for more data. The main
882 * sdhci driver provides no hook for doing status checking on less than
883 * a full block boundary, so we set the watermark level to be a full
884 * block. Reads and writes where the block size is less than the
885 * watermark size will work correctly too, no need to change the
886 * watermark for different size blocks. However, 128 is the maximum
887 * allowed for the watermark, so PIO is limitted to 512 byte blocks
888 * (which works fine for SD cards, may be a problem for SDIO some day).
890 * XXX need named constants for this stuff.
892 /* P1022 has the '*_BRST_LEN' fields as reserved, always reading 0x10 */
893 if (ofw_bus_is_compatible(dev, "fsl,p1022-esdhc"))
894 WR4(sc, SDHC_WTMK_LVL, 0x10801080);
896 WR4(sc, SDHC_WTMK_LVL, 0x08800880);
899 * We read in native byte order in the main driver, but the register
900 * defaults to little endian.
903 sc->baseclk_hz = fsl_sdhci_get_platform_clock(dev);
905 sc->baseclk_hz = imx_ccm_sdhci_hz();
907 sc->slot.max_clk = sc->baseclk_hz;
910 * Set up any gpio pin handling described in the FDT data. This cannot
911 * fail; see comments in sdhci_fdt_gpio.h for details.
913 sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot);
916 node = ofw_bus_get_node(dev);
917 /* Default to big-endian on powerpc */
918 protctl = RD4(sc, SDHC_PROT_CTRL);
919 protctl &= ~SDHC_PROT_EMODE_MASK;
920 if (OF_hasprop(node, "little-endian"))
921 protctl |= SDHC_PROT_EMODE_LITTLE;
923 protctl |= SDHC_PROT_EMODE_BIG;
924 WR4(sc, SDHC_PROT_CTRL, protctl);
927 callout_init(&sc->r1bfix_callout, 1);
928 sdhci_init_slot(dev, &sc->slot, 0);
930 bus_generic_probe(dev);
931 bus_generic_attach(dev);
933 sdhci_start_slot(&sc->slot);
938 fsl_sdhci_detach(dev);
943 fsl_sdhci_probe(device_t dev)
946 if (!ofw_bus_status_okay(dev))
949 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) {
951 device_set_desc(dev, "Freescale eSDHC controller");
952 return (BUS_PROBE_DEFAULT);
954 device_set_desc(dev, "Freescale uSDHC controller");
955 return (BUS_PROBE_DEFAULT);
962 static device_method_t fsl_sdhci_methods[] = {
963 /* Device interface */
964 DEVMETHOD(device_probe, fsl_sdhci_probe),
965 DEVMETHOD(device_attach, fsl_sdhci_attach),
966 DEVMETHOD(device_detach, fsl_sdhci_detach),
969 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
970 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
972 /* MMC bridge interface */
973 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
974 DEVMETHOD(mmcbr_request, sdhci_generic_request),
975 DEVMETHOD(mmcbr_get_ro, fsl_sdhci_get_ro),
976 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
977 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
979 /* SDHCI accessors */
980 DEVMETHOD(sdhci_read_1, fsl_sdhci_read_1),
981 DEVMETHOD(sdhci_read_2, fsl_sdhci_read_2),
982 DEVMETHOD(sdhci_read_4, fsl_sdhci_read_4),
983 DEVMETHOD(sdhci_read_multi_4, fsl_sdhci_read_multi_4),
984 DEVMETHOD(sdhci_write_1, fsl_sdhci_write_1),
985 DEVMETHOD(sdhci_write_2, fsl_sdhci_write_2),
986 DEVMETHOD(sdhci_write_4, fsl_sdhci_write_4),
987 DEVMETHOD(sdhci_write_multi_4, fsl_sdhci_write_multi_4),
988 DEVMETHOD(sdhci_get_card_present,fsl_sdhci_get_card_present),
993 static devclass_t fsl_sdhci_devclass;
995 static driver_t fsl_sdhci_driver = {
998 sizeof(struct fsl_sdhci_softc),
1001 DRIVER_MODULE(sdhci_fsl, simplebus, fsl_sdhci_driver, fsl_sdhci_devclass,
1003 MODULE_DEPEND(sdhci_fsl, sdhci, 1, 1, 1);
1006 MMC_DECLARE_BRIDGE(sdhci_fsl);