2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
29 #include <sys/param.h>
30 #include <sys/systm.h>
32 #include <sys/callout.h>
34 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
38 #include <sys/resource.h>
40 #include <sys/sysctl.h>
41 #include <sys/taskqueue.h>
43 #include <machine/bus.h>
44 #include <machine/resource.h>
45 #include <machine/stdarg.h>
47 #include <dev/mmc/bridge.h>
48 #include <dev/mmc/mmcreg.h>
49 #include <dev/mmc/mmcbrvar.h>
55 SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver");
57 static int sdhci_debug;
58 TUNABLE_INT("hw.sdhci.debug", &sdhci_debug);
59 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0, "Debug level");
61 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
62 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
63 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
64 #define RD_MULTI_4(slot, off, ptr, count) \
65 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
67 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
68 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
69 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
70 #define WR_MULTI_4(slot, off, ptr, count) \
71 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
73 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
74 static void sdhci_start(struct sdhci_slot *slot);
75 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data);
77 static void sdhci_card_task(void *, int);
80 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx)
81 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx)
82 #define SDHCI_LOCK_INIT(_slot) \
83 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
84 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx);
85 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED);
86 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED);
88 #define SDHCI_DEFAULT_MAX_FREQ 50
90 #define SDHCI_200_MAX_DIVIDER 256
91 #define SDHCI_300_MAX_DIVIDER 2046
94 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
97 printf("getaddr: error %d\n", error);
100 *(bus_addr_t *)arg = segs[0].ds_addr;
104 slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
109 retval = printf("%s-slot%d: ",
110 device_get_nameunit(slot->bus), slot->num);
113 retval += vprintf(fmt, ap);
119 sdhci_dumpregs(struct sdhci_slot *slot)
122 "============== REGISTER DUMP ==============\n");
124 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n",
125 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
126 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
127 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT));
128 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n",
129 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
130 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n",
131 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
132 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n",
133 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));
134 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n",
135 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
136 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n",
137 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
138 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n",
139 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
140 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n",
141 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS));
142 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n",
143 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT));
146 "===========================================\n");
150 sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
155 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
156 if (!(RD4(slot, SDHCI_PRESENT_STATE) &
161 /* Some controllers need this kick or reset won't work. */
162 if ((mask & SDHCI_RESET_ALL) == 0 &&
163 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
166 /* This is to force an update */
169 sdhci_set_clock(slot, clock);
172 WR1(slot, SDHCI_SOFTWARE_RESET, mask);
174 if (mask & SDHCI_RESET_ALL) {
179 /* Wait max 100 ms */
181 /* Controller clears the bits when it's done */
182 while ((res = RD1(slot, SDHCI_SOFTWARE_RESET)) & mask) {
185 "Reset 0x%x never completed - 0x%x.\n",
186 (int)mask, (int)res);
187 sdhci_dumpregs(slot);
196 sdhci_init(struct sdhci_slot *slot)
199 sdhci_reset(slot, SDHCI_RESET_ALL);
201 /* Enable interrupts. */
202 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
203 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
204 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
205 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
206 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
207 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
209 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
210 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
214 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
221 if (clock == slot->clock)
225 /* Turn off the clock. */
226 clk = RD2(slot, SDHCI_CLOCK_CONTROL);
227 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN);
228 /* If no clock requested - left it so. */
232 /* Recalculate timeout clock frequency based on the new sd clock. */
233 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
234 slot->timeout_clk = slot->clock / 1000;
236 if (slot->version < SDHCI_SPEC_300) {
237 /* Looking for highest freq <= clock. */
239 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) {
244 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
248 /* Version 3.0 divisors are multiples of two up to 1023*2 */
249 if (clock >= slot->max_clk)
252 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) {
253 if ((slot->max_clk / div) <= clock)
260 if (bootverbose || sdhci_debug)
261 slot_printf(slot, "Divider %d for freq %d (max %d)\n",
262 div, clock, slot->max_clk);
264 /* Now we have got divider, set it. */
265 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
266 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK)
267 << SDHCI_DIVIDER_HI_SHIFT;
269 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
271 clk |= SDHCI_CLOCK_INT_EN;
272 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
273 /* Wait up to 10 ms until it stabilize. */
275 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
276 & SDHCI_CLOCK_INT_STABLE)) {
279 "Internal clock never stabilised.\n");
280 sdhci_dumpregs(slot);
286 /* Pass clock signal to the bus. */
287 clk |= SDHCI_CLOCK_CARD_EN;
288 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
292 sdhci_set_power(struct sdhci_slot *slot, u_char power)
296 if (slot->power == power)
301 /* Turn off the power. */
303 WR1(slot, SDHCI_POWER_CONTROL, pwr);
304 /* If power down requested - left it so. */
308 switch (1 << power) {
309 case MMC_OCR_LOW_VOLTAGE:
310 pwr |= SDHCI_POWER_180;
312 case MMC_OCR_290_300:
313 case MMC_OCR_300_310:
314 pwr |= SDHCI_POWER_300;
316 case MMC_OCR_320_330:
317 case MMC_OCR_330_340:
318 pwr |= SDHCI_POWER_330;
321 WR1(slot, SDHCI_POWER_CONTROL, pwr);
322 /* Turn on the power. */
323 pwr |= SDHCI_POWER_ON;
324 WR1(slot, SDHCI_POWER_CONTROL, pwr);
328 sdhci_read_block_pio(struct sdhci_slot *slot)
334 buffer = slot->curcmd->data->data;
335 buffer += slot->offset;
336 /* Transfer one block at a time. */
337 left = min(512, slot->curcmd->data->len - slot->offset);
338 slot->offset += left;
340 /* If we are too fast, broken controllers return zeroes. */
341 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
343 /* Handle unaligned and aligned buffer cases. */
344 if ((intptr_t)buffer & 3) {
346 data = RD4(slot, SDHCI_BUFFER);
348 buffer[1] = (data >> 8);
349 buffer[2] = (data >> 16);
350 buffer[3] = (data >> 24);
355 RD_MULTI_4(slot, SDHCI_BUFFER,
356 (uint32_t *)buffer, left >> 2);
359 /* Handle uneven size case. */
361 data = RD4(slot, SDHCI_BUFFER);
371 sdhci_write_block_pio(struct sdhci_slot *slot)
377 buffer = slot->curcmd->data->data;
378 buffer += slot->offset;
379 /* Transfer one block at a time. */
380 left = min(512, slot->curcmd->data->len - slot->offset);
381 slot->offset += left;
383 /* Handle unaligned and aligned buffer cases. */
384 if ((intptr_t)buffer & 3) {
392 WR4(slot, SDHCI_BUFFER, data);
395 WR_MULTI_4(slot, SDHCI_BUFFER,
396 (uint32_t *)buffer, left >> 2);
399 /* Handle uneven size case. */
406 WR4(slot, SDHCI_BUFFER, data);
411 sdhci_transfer_pio(struct sdhci_slot *slot)
414 /* Read as many blocks as possible. */
415 if (slot->curcmd->data->flags & MMC_DATA_READ) {
416 while (RD4(slot, SDHCI_PRESENT_STATE) &
417 SDHCI_DATA_AVAILABLE) {
418 sdhci_read_block_pio(slot);
419 if (slot->offset >= slot->curcmd->data->len)
423 while (RD4(slot, SDHCI_PRESENT_STATE) &
424 SDHCI_SPACE_AVAILABLE) {
425 sdhci_write_block_pio(slot);
426 if (slot->offset >= slot->curcmd->data->len)
433 sdhci_card_delay(void *arg)
435 struct sdhci_slot *slot = arg;
437 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task);
441 sdhci_card_task(void *arg, int pending)
443 struct sdhci_slot *slot = arg;
446 if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) {
447 if (slot->dev == NULL) {
448 /* If card is present - attach mmc bus. */
449 slot->dev = device_add_child(slot->bus, "mmc", -1);
450 device_set_ivars(slot->dev, slot);
452 device_probe_and_attach(slot->dev);
456 if (slot->dev != NULL) {
457 /* If no card present - detach mmc bus. */
458 device_t d = slot->dev;
461 device_delete_child(slot->bus, d);
468 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
473 SDHCI_LOCK_INIT(slot);
477 /* Allocate DMA tag. */
478 err = bus_dma_tag_create(bus_get_dma_tag(dev),
479 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
480 BUS_SPACE_MAXADDR, NULL, NULL,
481 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE,
482 BUS_DMA_ALLOCNOW, NULL, NULL,
485 device_printf(dev, "Can't create DMA tag\n");
486 SDHCI_LOCK_DESTROY(slot);
489 /* Allocate DMA memory. */
490 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
491 BUS_DMA_NOWAIT, &slot->dmamap);
493 device_printf(dev, "Can't alloc DMA memory\n");
494 SDHCI_LOCK_DESTROY(slot);
497 /* Map the memory. */
498 err = bus_dmamap_load(slot->dmatag, slot->dmamap,
499 (void *)slot->dmamem, DMA_BLOCK_SIZE,
500 sdhci_getaddr, &slot->paddr, 0);
501 if (err != 0 || slot->paddr == 0) {
502 device_printf(dev, "Can't load DMA memory\n");
503 SDHCI_LOCK_DESTROY(slot);
510 /* Initialize slot. */
512 slot->version = (RD2(slot, SDHCI_HOST_VERSION)
513 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK;
514 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS)
517 caps = RD4(slot, SDHCI_CAPABILITIES);
518 /* Calculate base clock frequency. */
519 if (slot->version >= SDHCI_SPEC_300)
520 freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
521 SDHCI_CLOCK_BASE_SHIFT;
523 freq = (caps & SDHCI_CLOCK_BASE_MASK) >>
524 SDHCI_CLOCK_BASE_SHIFT;
526 slot->max_clk = freq * 1000000;
528 * If the frequency wasn't in the capabilities and the hardware driver
529 * hasn't already set max_clk we're probably not going to work right
530 * with an assumption, so complain about it.
532 if (slot->max_clk == 0) {
533 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000;
534 device_printf(dev, "Hardware doesn't specify base clock "
535 "frequency, using %dMHz as default.\n", SDHCI_DEFAULT_MAX_FREQ);
537 /* Calculate timeout clock frequency. */
538 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
539 slot->timeout_clk = slot->max_clk / 1000;
542 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
543 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
544 slot->timeout_clk *= 1000;
547 * If the frequency wasn't in the capabilities and the hardware driver
548 * hasn't already set timeout_clk we'll probably work okay using the
549 * max timeout, but still mention it.
551 if (slot->timeout_clk == 0) {
552 device_printf(dev, "Hardware doesn't specify timeout clock "
553 "frequency, setting BROKEN_TIMEOUT quirk.\n");
554 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
557 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot);
558 slot->host.f_max = slot->max_clk;
559 slot->host.host_ocr = 0;
560 if (caps & SDHCI_CAN_VDD_330)
561 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
562 if (caps & SDHCI_CAN_VDD_300)
563 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
564 if (caps & SDHCI_CAN_VDD_180)
565 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
566 if (slot->host.host_ocr == 0) {
567 device_printf(dev, "Hardware doesn't report any "
568 "support voltages.\n");
570 slot->host.caps = MMC_CAP_4_BIT_DATA;
571 if (caps & SDHCI_CAN_DO_HISPD)
572 slot->host.caps |= MMC_CAP_HSPEED;
573 /* Decide if we have usable DMA. */
574 if (caps & SDHCI_CAN_DO_DMA)
575 slot->opt |= SDHCI_HAVE_DMA;
577 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA)
578 slot->opt &= ~SDHCI_HAVE_DMA;
579 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA)
580 slot->opt |= SDHCI_HAVE_DMA;
583 * Use platform-provided transfer backend
584 * with PIO as a fallback mechanism
586 if (slot->opt & SDHCI_PLATFORM_TRANSFER)
587 slot->opt &= ~SDHCI_HAVE_DMA;
589 if (bootverbose || sdhci_debug) {
590 slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n",
591 slot->max_clk / 1000000,
592 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
593 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
594 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
595 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "",
596 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO");
597 sdhci_dumpregs(slot);
600 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
601 callout_init(&slot->card_callout, 1);
602 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0);
607 sdhci_start_slot(struct sdhci_slot *slot)
609 sdhci_card_task(slot, 0);
613 sdhci_cleanup_slot(struct sdhci_slot *slot)
617 callout_drain(&slot->timeout_callout);
618 callout_drain(&slot->card_callout);
619 taskqueue_drain(taskqueue_swi_giant, &slot->card_task);
626 device_delete_child(slot->bus, d);
629 sdhci_reset(slot, SDHCI_RESET_ALL);
631 bus_dmamap_unload(slot->dmatag, slot->dmamap);
632 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
633 bus_dma_tag_destroy(slot->dmatag);
635 SDHCI_LOCK_DESTROY(slot);
641 sdhci_generic_suspend(struct sdhci_slot *slot)
643 sdhci_reset(slot, SDHCI_RESET_ALL);
649 sdhci_generic_resume(struct sdhci_slot *slot)
657 sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot)
659 if (slot->version >= SDHCI_SPEC_300)
660 return (slot->max_clk / SDHCI_300_MAX_DIVIDER);
662 return (slot->max_clk / SDHCI_200_MAX_DIVIDER);
666 sdhci_generic_update_ios(device_t brdev, device_t reqdev)
668 struct sdhci_slot *slot = device_get_ivars(reqdev);
669 struct mmc_ios *ios = &slot->host.ios;
672 /* Do full reset on bus power down to clear from any state. */
673 if (ios->power_mode == power_off) {
674 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
677 /* Configure the bus. */
678 sdhci_set_clock(slot, ios->clock);
679 sdhci_set_power(slot, (ios->power_mode == power_off)?0:ios->vdd);
680 if (ios->bus_width == bus_width_4)
681 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
683 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
684 if (ios->timing == bus_timing_hs)
685 slot->hostctrl |= SDHCI_CTRL_HISPD;
687 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
688 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
689 /* Some controllers like reset after bus changes. */
690 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
691 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
698 sdhci_req_done(struct sdhci_slot *slot)
700 struct mmc_request *req;
702 if (slot->req != NULL && slot->curcmd != NULL) {
703 callout_stop(&slot->timeout_callout);
712 sdhci_timeout(void *arg)
714 struct sdhci_slot *slot = arg;
716 if (slot->curcmd != NULL) {
717 sdhci_reset(slot, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
718 slot->curcmd->error = MMC_ERR_TIMEOUT;
719 sdhci_req_done(slot);
724 sdhci_set_transfer_mode(struct sdhci_slot *slot,
725 struct mmc_data *data)
732 mode = SDHCI_TRNS_BLK_CNT_EN;
734 mode |= SDHCI_TRNS_MULTI;
735 if (data->flags & MMC_DATA_READ)
736 mode |= SDHCI_TRNS_READ;
738 mode |= SDHCI_TRNS_ACMD12;
739 if (slot->flags & SDHCI_USE_DMA)
740 mode |= SDHCI_TRNS_DMA;
742 WR2(slot, SDHCI_TRANSFER_MODE, mode);
746 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
749 uint32_t mask, state;
754 cmd->error = MMC_ERR_NONE;
756 /* This flags combination is not supported by controller. */
757 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
758 slot_printf(slot, "Unsupported response type!\n");
759 cmd->error = MMC_ERR_FAILED;
760 sdhci_req_done(slot);
764 /* Read controller present state. */
765 state = RD4(slot, SDHCI_PRESENT_STATE);
766 /* Do not issue command if there is no card, clock or power.
767 * Controller will not detect timeout without clock active. */
768 if ((state & SDHCI_CARD_PRESENT) == 0 ||
771 cmd->error = MMC_ERR_FAILED;
772 sdhci_req_done(slot);
775 /* Always wait for free CMD bus. */
776 mask = SDHCI_CMD_INHIBIT;
777 /* Wait for free DAT if we have data or busy signal. */
778 if (cmd->data || (cmd->flags & MMC_RSP_BUSY))
779 mask |= SDHCI_DAT_INHIBIT;
780 /* We shouldn't wait for DAT for stop commands. */
781 if (cmd == slot->req->stop)
782 mask &= ~SDHCI_DAT_INHIBIT;
784 * Wait for bus no more then 250 ms. Typically there will be no wait
785 * here at all, but when writing a crash dump we may be bypassing the
786 * host platform's interrupt handler, and in some cases that handler
787 * may be working around hardware quirks such as not respecting r1b
788 * busy indications. In those cases, this wait-loop serves the purpose
789 * of waiting for the prior command and data transfers to be done, and
790 * SD cards are allowed to take up to 250ms for write and erase ops.
791 * (It's usually more like 20-30ms in the real world.)
794 while (state & mask) {
796 slot_printf(slot, "Controller never released "
797 "inhibit bit(s).\n");
798 sdhci_dumpregs(slot);
799 cmd->error = MMC_ERR_FAILED;
800 sdhci_req_done(slot);
805 state = RD4(slot, SDHCI_PRESENT_STATE);
808 /* Prepare command flags. */
809 if (!(cmd->flags & MMC_RSP_PRESENT))
810 flags = SDHCI_CMD_RESP_NONE;
811 else if (cmd->flags & MMC_RSP_136)
812 flags = SDHCI_CMD_RESP_LONG;
813 else if (cmd->flags & MMC_RSP_BUSY)
814 flags = SDHCI_CMD_RESP_SHORT_BUSY;
816 flags = SDHCI_CMD_RESP_SHORT;
817 if (cmd->flags & MMC_RSP_CRC)
818 flags |= SDHCI_CMD_CRC;
819 if (cmd->flags & MMC_RSP_OPCODE)
820 flags |= SDHCI_CMD_INDEX;
822 flags |= SDHCI_CMD_DATA;
823 if (cmd->opcode == MMC_STOP_TRANSMISSION)
824 flags |= SDHCI_CMD_TYPE_ABORT;
826 sdhci_start_data(slot, cmd->data);
828 * Interrupt aggregation: To reduce total number of interrupts
829 * group response interrupt with data interrupt when possible.
830 * If there going to be data interrupt, mask response one.
832 if (slot->data_done == 0) {
833 WR4(slot, SDHCI_SIGNAL_ENABLE,
834 slot->intmask &= ~SDHCI_INT_RESPONSE);
836 /* Set command argument. */
837 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
838 /* Set data transfer mode. */
839 sdhci_set_transfer_mode(slot, cmd->data);
841 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
842 /* Start timeout callout. */
843 callout_reset(&slot->timeout_callout, 2*hz, sdhci_timeout, slot);
847 sdhci_finish_command(struct sdhci_slot *slot)
852 /* Interrupt aggregation: Restore command interrupt.
853 * Main restore point for the case when command interrupt
855 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE);
856 /* In case of error - reset host and return. */
857 if (slot->curcmd->error) {
858 sdhci_reset(slot, SDHCI_RESET_CMD);
859 sdhci_reset(slot, SDHCI_RESET_DATA);
863 /* If command has response - fetch it. */
864 if (slot->curcmd->flags & MMC_RSP_PRESENT) {
865 if (slot->curcmd->flags & MMC_RSP_136) {
866 /* CRC is stripped so we need one byte shift. */
868 for (i = 0; i < 4; i++) {
869 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4);
870 if (slot->quirks & SDHCI_QUIRK_DONT_SHIFT_RESPONSE)
871 slot->curcmd->resp[3 - i] = val;
873 slot->curcmd->resp[3 - i] =
879 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
881 /* If data ready - finish. */
887 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data)
889 uint32_t target_timeout, current_timeout;
892 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
899 /* Calculate and set data timeout.*/
900 /* XXX: We should have this from mmc layer, now assume 1 sec. */
901 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) {
904 target_timeout = 1000000;
906 current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
907 while (current_timeout < target_timeout && div < 0xE) {
909 current_timeout <<= 1;
911 /* Compensate for an off-by-one error in the CaFe chip.*/
913 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) {
917 WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
922 /* Use DMA if possible. */
923 if ((slot->opt & SDHCI_HAVE_DMA))
924 slot->flags |= SDHCI_USE_DMA;
925 /* If data is small, broken DMA may return zeroes instead of data, */
926 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
928 slot->flags &= ~SDHCI_USE_DMA;
929 /* Some controllers require even block sizes. */
930 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
932 slot->flags &= ~SDHCI_USE_DMA;
933 /* Load DMA buffer. */
934 if (slot->flags & SDHCI_USE_DMA) {
935 if (data->flags & MMC_DATA_READ)
936 bus_dmamap_sync(slot->dmatag, slot->dmamap,
937 BUS_DMASYNC_PREREAD);
939 memcpy(slot->dmamem, data->data,
940 (data->len < DMA_BLOCK_SIZE) ?
941 data->len : DMA_BLOCK_SIZE);
942 bus_dmamap_sync(slot->dmatag, slot->dmamap,
943 BUS_DMASYNC_PREWRITE);
945 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
946 /* Interrupt aggregation: Mask border interrupt
947 * for the last page and unmask else. */
948 if (data->len == DMA_BLOCK_SIZE)
949 slot->intmask &= ~SDHCI_INT_DMA_END;
951 slot->intmask |= SDHCI_INT_DMA_END;
952 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
954 /* Current data offset for both PIO and DMA. */
956 /* Set block size and request IRQ on 4K border. */
957 WR2(slot, SDHCI_BLOCK_SIZE,
958 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512));
959 /* Set block count. */
960 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512);
964 sdhci_finish_data(struct sdhci_slot *slot)
966 struct mmc_data *data = slot->curcmd->data;
969 /* Interrupt aggregation: Restore command interrupt.
970 * Auxiliary restore point for the case when data interrupt
972 if (!slot->cmd_done) {
973 WR4(slot, SDHCI_SIGNAL_ENABLE,
974 slot->intmask |= SDHCI_INT_RESPONSE);
976 /* Unload rest of data from DMA buffer. */
977 if (slot->flags & SDHCI_USE_DMA) {
978 if (data->flags & MMC_DATA_READ) {
979 size_t left = data->len - slot->offset;
980 bus_dmamap_sync(slot->dmatag, slot->dmamap,
981 BUS_DMASYNC_POSTREAD);
982 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
983 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
985 bus_dmamap_sync(slot->dmatag, slot->dmamap,
986 BUS_DMASYNC_POSTWRITE);
988 /* If there was error - reset the host. */
989 if (slot->curcmd->error) {
990 sdhci_reset(slot, SDHCI_RESET_CMD);
991 sdhci_reset(slot, SDHCI_RESET_DATA);
995 /* If we already have command response - finish. */
1001 sdhci_start(struct sdhci_slot *slot)
1003 struct mmc_request *req;
1009 if (!(slot->flags & CMD_STARTED)) {
1010 slot->flags |= CMD_STARTED;
1011 sdhci_start_command(slot, req->cmd);
1014 /* We don't need this until using Auto-CMD12 feature
1015 if (!(slot->flags & STOP_STARTED) && req->stop) {
1016 slot->flags |= STOP_STARTED;
1017 sdhci_start_command(slot, req->stop);
1021 if (sdhci_debug > 1)
1022 slot_printf(slot, "result: %d\n", req->cmd->error);
1023 if (!req->cmd->error &&
1024 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
1025 sdhci_reset(slot, SDHCI_RESET_CMD);
1026 sdhci_reset(slot, SDHCI_RESET_DATA);
1029 sdhci_req_done(slot);
1033 sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req)
1035 struct sdhci_slot *slot = device_get_ivars(reqdev);
1038 if (slot->req != NULL) {
1042 if (sdhci_debug > 1) {
1043 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
1044 req->cmd->opcode, req->cmd->arg, req->cmd->flags,
1045 (req->cmd->data)?(u_int)req->cmd->data->len:0,
1046 (req->cmd->data)?req->cmd->data->flags:0);
1053 while (slot->req != NULL) {
1054 sdhci_generic_intr(slot);
1062 sdhci_generic_get_ro(device_t brdev, device_t reqdev)
1064 struct sdhci_slot *slot = device_get_ivars(reqdev);
1068 val = RD4(slot, SDHCI_PRESENT_STATE);
1070 return (!(val & SDHCI_WRITE_PROTECT));
1074 sdhci_generic_acquire_host(device_t brdev, device_t reqdev)
1076 struct sdhci_slot *slot = device_get_ivars(reqdev);
1080 while (slot->bus_busy)
1081 msleep(slot, &slot->mtx, 0, "sdhciah", 0);
1084 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
1090 sdhci_generic_release_host(device_t brdev, device_t reqdev)
1092 struct sdhci_slot *slot = device_get_ivars(reqdev);
1095 /* Deactivate led. */
1096 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
1104 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask)
1107 if (!slot->curcmd) {
1108 slot_printf(slot, "Got command interrupt 0x%08x, but "
1109 "there is no active command.\n", intmask);
1110 sdhci_dumpregs(slot);
1113 if (intmask & SDHCI_INT_TIMEOUT)
1114 slot->curcmd->error = MMC_ERR_TIMEOUT;
1115 else if (intmask & SDHCI_INT_CRC)
1116 slot->curcmd->error = MMC_ERR_BADCRC;
1117 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
1118 slot->curcmd->error = MMC_ERR_FIFO;
1120 sdhci_finish_command(slot);
1124 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask)
1127 if (!slot->curcmd) {
1128 slot_printf(slot, "Got data interrupt 0x%08x, but "
1129 "there is no active command.\n", intmask);
1130 sdhci_dumpregs(slot);
1133 if (slot->curcmd->data == NULL &&
1134 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1135 slot_printf(slot, "Got data interrupt 0x%08x, but "
1136 "there is no active data operation.\n",
1138 sdhci_dumpregs(slot);
1141 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1142 slot->curcmd->error = MMC_ERR_TIMEOUT;
1143 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1144 slot->curcmd->error = MMC_ERR_BADCRC;
1145 if (slot->curcmd->data == NULL &&
1146 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
1147 SDHCI_INT_DMA_END))) {
1148 slot_printf(slot, "Got data interrupt 0x%08x, but "
1149 "there is busy-only command.\n", intmask);
1150 sdhci_dumpregs(slot);
1151 slot->curcmd->error = MMC_ERR_INVALID;
1153 if (slot->curcmd->error) {
1154 /* No need to continue after any error. */
1155 if (slot->flags & PLATFORM_DATA_STARTED) {
1156 slot->flags &= ~PLATFORM_DATA_STARTED;
1157 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
1159 sdhci_finish_data(slot);
1163 /* Handle PIO interrupt. */
1164 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
1165 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) &&
1166 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) {
1167 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, &intmask);
1168 slot->flags |= PLATFORM_DATA_STARTED;
1170 sdhci_transfer_pio(slot);
1172 /* Handle DMA border. */
1173 if (intmask & SDHCI_INT_DMA_END) {
1174 struct mmc_data *data = slot->curcmd->data;
1177 /* Unload DMA buffer... */
1178 left = data->len - slot->offset;
1179 if (data->flags & MMC_DATA_READ) {
1180 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1181 BUS_DMASYNC_POSTREAD);
1182 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1183 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1185 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1186 BUS_DMASYNC_POSTWRITE);
1188 /* ... and reload it again. */
1189 slot->offset += DMA_BLOCK_SIZE;
1190 left = data->len - slot->offset;
1191 if (data->flags & MMC_DATA_READ) {
1192 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1193 BUS_DMASYNC_PREREAD);
1195 memcpy(slot->dmamem, (u_char*)data->data + slot->offset,
1196 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1197 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1198 BUS_DMASYNC_PREWRITE);
1200 /* Interrupt aggregation: Mask border interrupt
1201 * for the last page. */
1202 if (left == DMA_BLOCK_SIZE) {
1203 slot->intmask &= ~SDHCI_INT_DMA_END;
1204 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1207 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1209 /* We have got all data. */
1210 if (intmask & SDHCI_INT_DATA_END) {
1211 if (slot->flags & PLATFORM_DATA_STARTED) {
1212 slot->flags &= ~PLATFORM_DATA_STARTED;
1213 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
1215 sdhci_finish_data(slot);
1220 sdhci_acmd_irq(struct sdhci_slot *slot)
1224 err = RD4(slot, SDHCI_ACMD12_ERR);
1225 if (!slot->curcmd) {
1226 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
1227 "there is no active command.\n", err);
1228 sdhci_dumpregs(slot);
1231 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err);
1232 sdhci_reset(slot, SDHCI_RESET_CMD);
1236 sdhci_generic_intr(struct sdhci_slot *slot)
1241 /* Read slot interrupt status. */
1242 intmask = RD4(slot, SDHCI_INT_STATUS);
1243 if (intmask == 0 || intmask == 0xffffffff) {
1247 if (sdhci_debug > 2)
1248 slot_printf(slot, "Interrupt %#x\n", intmask);
1250 /* Handle card presence interrupts. */
1251 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1252 WR4(slot, SDHCI_INT_STATUS, intmask &
1253 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
1255 if (intmask & SDHCI_INT_CARD_REMOVE) {
1256 if (bootverbose || sdhci_debug)
1257 slot_printf(slot, "Card removed\n");
1258 callout_stop(&slot->card_callout);
1259 taskqueue_enqueue(taskqueue_swi_giant,
1262 if (intmask & SDHCI_INT_CARD_INSERT) {
1263 if (bootverbose || sdhci_debug)
1264 slot_printf(slot, "Card inserted\n");
1265 callout_reset(&slot->card_callout, hz / 2,
1266 sdhci_card_delay, slot);
1268 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1270 /* Handle command interrupts. */
1271 if (intmask & SDHCI_INT_CMD_MASK) {
1272 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
1273 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
1275 /* Handle data interrupts. */
1276 if (intmask & SDHCI_INT_DATA_MASK) {
1277 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
1278 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
1280 /* Handle AutoCMD12 error interrupt. */
1281 if (intmask & SDHCI_INT_ACMD12ERR) {
1282 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
1283 sdhci_acmd_irq(slot);
1285 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1286 intmask &= ~SDHCI_INT_ACMD12ERR;
1287 intmask &= ~SDHCI_INT_ERROR;
1288 /* Handle bus power interrupt. */
1289 if (intmask & SDHCI_INT_BUS_POWER) {
1290 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
1292 "Card is consuming too much power!\n");
1293 intmask &= ~SDHCI_INT_BUS_POWER;
1295 /* The rest is unknown. */
1297 WR4(slot, SDHCI_INT_STATUS, intmask);
1298 slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
1300 sdhci_dumpregs(slot);
1307 sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
1309 struct sdhci_slot *slot = device_get_ivars(child);
1314 case MMCBR_IVAR_BUS_MODE:
1315 *result = slot->host.ios.bus_mode;
1317 case MMCBR_IVAR_BUS_WIDTH:
1318 *result = slot->host.ios.bus_width;
1320 case MMCBR_IVAR_CHIP_SELECT:
1321 *result = slot->host.ios.chip_select;
1323 case MMCBR_IVAR_CLOCK:
1324 *result = slot->host.ios.clock;
1326 case MMCBR_IVAR_F_MIN:
1327 *result = slot->host.f_min;
1329 case MMCBR_IVAR_F_MAX:
1330 *result = slot->host.f_max;
1332 case MMCBR_IVAR_HOST_OCR:
1333 *result = slot->host.host_ocr;
1335 case MMCBR_IVAR_MODE:
1336 *result = slot->host.mode;
1338 case MMCBR_IVAR_OCR:
1339 *result = slot->host.ocr;
1341 case MMCBR_IVAR_POWER_MODE:
1342 *result = slot->host.ios.power_mode;
1344 case MMCBR_IVAR_VDD:
1345 *result = slot->host.ios.vdd;
1347 case MMCBR_IVAR_CAPS:
1348 *result = slot->host.caps;
1350 case MMCBR_IVAR_TIMING:
1351 *result = slot->host.ios.timing;
1353 case MMCBR_IVAR_MAX_DATA:
1361 sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
1363 struct sdhci_slot *slot = device_get_ivars(child);
1368 case MMCBR_IVAR_BUS_MODE:
1369 slot->host.ios.bus_mode = value;
1371 case MMCBR_IVAR_BUS_WIDTH:
1372 slot->host.ios.bus_width = value;
1374 case MMCBR_IVAR_CHIP_SELECT:
1375 slot->host.ios.chip_select = value;
1377 case MMCBR_IVAR_CLOCK:
1383 max_clock = slot->max_clk;
1386 if (slot->version < SDHCI_SPEC_300) {
1387 for (i = 0; i < SDHCI_200_MAX_DIVIDER;
1395 for (i = 0; i < SDHCI_300_MAX_DIVIDER;
1399 clock = max_clock / (i + 2);
1403 slot->host.ios.clock = clock;
1405 slot->host.ios.clock = 0;
1407 case MMCBR_IVAR_MODE:
1408 slot->host.mode = value;
1410 case MMCBR_IVAR_OCR:
1411 slot->host.ocr = value;
1413 case MMCBR_IVAR_POWER_MODE:
1414 slot->host.ios.power_mode = value;
1416 case MMCBR_IVAR_VDD:
1417 slot->host.ios.vdd = value;
1419 case MMCBR_IVAR_TIMING:
1420 slot->host.ios.timing = value;
1422 case MMCBR_IVAR_CAPS:
1423 case MMCBR_IVAR_HOST_OCR:
1424 case MMCBR_IVAR_F_MIN:
1425 case MMCBR_IVAR_F_MAX:
1426 case MMCBR_IVAR_MAX_DATA:
1432 MODULE_VERSION(sdhci, 1);