2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
29 #include <sys/param.h>
30 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/mutex.h>
37 #include <sys/resource.h>
39 #include <sys/sysctl.h>
40 #include <sys/taskqueue.h>
42 #include <machine/bus.h>
43 #include <machine/resource.h>
44 #include <machine/stdarg.h>
46 #include <dev/mmc/bridge.h>
47 #include <dev/mmc/mmcreg.h>
48 #include <dev/mmc/mmcbrvar.h>
57 device_t dev; /* Controller device */
58 struct resource *irq_res; /* IRQ resource */
60 void *intrhand; /* Interrupt handle */
62 int num_slots; /* Number of slots on this controller */
63 struct sdhci_slot slots[6];
66 static SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver");
69 TUNABLE_INT("hw.sdhci.debug", &sdhci_debug);
70 SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RW, &sdhci_debug, 0, "Debug level");
72 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
73 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
74 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
75 #define RD_MULTI_4(slot, off, ptr, count) \
76 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
78 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
79 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
80 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
81 #define WR_MULTI_4(slot, off, ptr, count) \
82 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
84 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
85 static void sdhci_start(struct sdhci_slot *slot);
86 static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data);
88 static void sdhci_card_task(void *, int);
91 #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx)
92 #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx)
93 #define SDHCI_LOCK_INIT(_slot) \
94 mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF)
95 #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx);
96 #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED);
97 #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED);
99 #define SDHCI_DEFAULT_MAX_FREQ 50
101 #define SDHCI_200_MAX_DIVIDER 256
102 #define SDHCI_300_MAX_DIVIDER 2046
105 sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
108 printf("getaddr: error %d\n", error);
111 *(bus_addr_t *)arg = segs[0].ds_addr;
115 slot_printf(struct sdhci_slot *slot, const char * fmt, ...)
120 retval = printf("%s-slot%d: ",
121 device_get_nameunit(slot->bus), slot->num);
124 retval += vprintf(fmt, ap);
130 sdhci_dumpregs(struct sdhci_slot *slot)
133 "============== REGISTER DUMP ==============\n");
135 slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n",
136 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));
137 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
138 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT));
139 slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n",
140 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));
141 slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n",
142 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));
143 slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n",
144 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL));
145 slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n",
146 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL));
147 slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n",
148 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
149 slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n",
150 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));
151 slot_printf(slot, "AC12 err: 0x%08x | Slot int: 0x%08x\n",
152 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_SLOT_INT_STATUS));
153 slot_printf(slot, "Caps: 0x%08x | Max curr: 0x%08x\n",
154 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT));
157 "===========================================\n");
161 sdhci_reset(struct sdhci_slot *slot, uint8_t mask)
166 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
167 if (!(RD4(slot, SDHCI_PRESENT_STATE) &
172 /* Some controllers need this kick or reset won't work. */
173 if ((mask & SDHCI_RESET_ALL) == 0 &&
174 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
177 /* This is to force an update */
180 sdhci_set_clock(slot, clock);
183 WR1(slot, SDHCI_SOFTWARE_RESET, mask);
185 if (mask & SDHCI_RESET_ALL) {
190 /* Wait max 100 ms */
192 /* Controller clears the bits when it's done */
193 while ((res = RD1(slot, SDHCI_SOFTWARE_RESET)) & mask) {
196 "Reset 0x%x never completed - 0x%x.\n",
197 (int)mask, (int)res);
198 sdhci_dumpregs(slot);
207 sdhci_init(struct sdhci_slot *slot)
210 sdhci_reset(slot, SDHCI_RESET_ALL);
212 /* Enable interrupts. */
213 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
214 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
215 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
216 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
217 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
218 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
220 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
221 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
225 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)
232 if (clock == slot->clock)
236 /* Turn off the clock. */
237 WR2(slot, SDHCI_CLOCK_CONTROL, 0);
238 /* If no clock requested - left it so. */
241 if (slot->version < SDHCI_SPEC_300) {
242 /* Looking for highest freq <= clock. */
244 for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) {
249 /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */
253 /* Version 3.0 divisors are multiples of two up to 1023*2 */
254 if (clock >= slot->max_clk)
257 for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) {
258 if ((slot->max_clk / div) <= clock)
265 if (bootverbose || sdhci_debug)
266 slot_printf(slot, "Divider %d for freq %d (max %d)\n",
267 div, clock, slot->max_clk);
269 /* Now we have got divider, set it. */
270 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT;
271 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK)
272 << SDHCI_DIVIDER_HI_SHIFT;
274 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
276 clk |= SDHCI_CLOCK_INT_EN;
277 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
278 /* Wait up to 10 ms until it stabilize. */
280 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL))
281 & SDHCI_CLOCK_INT_STABLE)) {
284 "Internal clock never stabilised.\n");
285 sdhci_dumpregs(slot);
291 /* Pass clock signal to the bus. */
292 clk |= SDHCI_CLOCK_CARD_EN;
293 WR2(slot, SDHCI_CLOCK_CONTROL, clk);
297 sdhci_set_power(struct sdhci_slot *slot, u_char power)
301 if (slot->power == power)
306 /* Turn off the power. */
308 WR1(slot, SDHCI_POWER_CONTROL, pwr);
309 /* If power down requested - left it so. */
313 switch (1 << power) {
314 case MMC_OCR_LOW_VOLTAGE:
315 pwr |= SDHCI_POWER_180;
317 case MMC_OCR_290_300:
318 case MMC_OCR_300_310:
319 pwr |= SDHCI_POWER_300;
321 case MMC_OCR_320_330:
322 case MMC_OCR_330_340:
323 pwr |= SDHCI_POWER_330;
326 WR1(slot, SDHCI_POWER_CONTROL, pwr);
327 /* Turn on the power. */
328 pwr |= SDHCI_POWER_ON;
329 WR1(slot, SDHCI_POWER_CONTROL, pwr);
333 sdhci_read_block_pio(struct sdhci_slot *slot)
339 buffer = slot->curcmd->data->data;
340 buffer += slot->offset;
341 /* Transfer one block at a time. */
342 left = min(512, slot->curcmd->data->len - slot->offset);
343 slot->offset += left;
345 /* If we are too fast, broken controllers return zeroes. */
346 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS)
348 /* Handle unalligned and alligned buffer cases. */
349 if ((intptr_t)buffer & 3) {
351 data = RD4(slot, SDHCI_BUFFER);
353 buffer[1] = (data >> 8);
354 buffer[2] = (data >> 16);
355 buffer[3] = (data >> 24);
360 RD_MULTI_4(slot, SDHCI_BUFFER,
361 (uint32_t *)buffer, left >> 2);
364 /* Handle uneven size case. */
366 data = RD4(slot, SDHCI_BUFFER);
376 sdhci_write_block_pio(struct sdhci_slot *slot)
382 buffer = slot->curcmd->data->data;
383 buffer += slot->offset;
384 /* Transfer one block at a time. */
385 left = min(512, slot->curcmd->data->len - slot->offset);
386 slot->offset += left;
388 /* Handle unalligned and alligned buffer cases. */
389 if ((intptr_t)buffer & 3) {
397 WR4(slot, SDHCI_BUFFER, data);
400 WR_MULTI_4(slot, SDHCI_BUFFER,
401 (uint32_t *)buffer, left >> 2);
404 /* Handle uneven size case. */
411 WR4(slot, SDHCI_BUFFER, data);
416 sdhci_transfer_pio(struct sdhci_slot *slot)
419 /* Read as many blocks as possible. */
420 if (slot->curcmd->data->flags & MMC_DATA_READ) {
421 while (RD4(slot, SDHCI_PRESENT_STATE) &
422 SDHCI_DATA_AVAILABLE) {
423 sdhci_read_block_pio(slot);
424 if (slot->offset >= slot->curcmd->data->len)
428 while (RD4(slot, SDHCI_PRESENT_STATE) &
429 SDHCI_SPACE_AVAILABLE) {
430 sdhci_write_block_pio(slot);
431 if (slot->offset >= slot->curcmd->data->len)
438 sdhci_card_delay(void *arg)
440 struct sdhci_slot *slot = arg;
442 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task);
446 sdhci_card_task(void *arg, int pending)
448 struct sdhci_slot *slot = arg;
451 if (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) {
452 if (slot->dev == NULL) {
453 /* If card is present - attach mmc bus. */
454 slot->dev = device_add_child(slot->bus, "mmc", -1);
455 device_set_ivars(slot->dev, slot);
457 device_probe_and_attach(slot->dev);
461 if (slot->dev != NULL) {
462 /* If no card present - detach mmc bus. */
463 device_t d = slot->dev;
466 device_delete_child(slot->bus, d);
473 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num)
478 SDHCI_LOCK_INIT(slot);
482 /* Allocate DMA tag. */
483 err = bus_dma_tag_create(bus_get_dma_tag(dev),
484 DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT,
485 BUS_SPACE_MAXADDR, NULL, NULL,
486 DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE,
487 BUS_DMA_ALLOCNOW, NULL, NULL,
490 device_printf(dev, "Can't create DMA tag\n");
491 SDHCI_LOCK_DESTROY(slot);
494 /* Allocate DMA memory. */
495 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
496 BUS_DMA_NOWAIT, &slot->dmamap);
498 device_printf(dev, "Can't alloc DMA memory\n");
499 SDHCI_LOCK_DESTROY(slot);
502 /* Map the memory. */
503 err = bus_dmamap_load(slot->dmatag, slot->dmamap,
504 (void *)slot->dmamem, DMA_BLOCK_SIZE,
505 sdhci_getaddr, &slot->paddr, 0);
506 if (err != 0 || slot->paddr == 0) {
507 device_printf(dev, "Can't load DMA memory\n");
508 SDHCI_LOCK_DESTROY(slot);
515 /* Initialize slot. */
517 slot->version = (RD2(slot, SDHCI_HOST_VERSION)
518 >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK;
519 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS)
522 caps = RD4(slot, SDHCI_CAPABILITIES);
523 /* Calculate base clock frequency. */
524 if (slot->version >= SDHCI_SPEC_300)
525 slot->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK)
526 >> SDHCI_CLOCK_BASE_SHIFT;
528 slot->max_clk = (caps & SDHCI_CLOCK_BASE_MASK)
529 >> SDHCI_CLOCK_BASE_SHIFT;
530 if (slot->max_clk == 0) {
531 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ;
532 device_printf(dev, "Hardware doesn't specify base clock "
533 "frequency, using %dMHz as default.\n", SDHCI_DEFAULT_MAX_FREQ);
535 slot->max_clk *= 1000000;
536 /* Calculate timeout clock frequency. */
537 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
538 slot->timeout_clk = slot->max_clk / 1000;
541 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
542 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
543 slot->timeout_clk *= 1000;
546 if (slot->timeout_clk == 0) {
547 device_printf(dev, "Hardware doesn't specify timeout clock "
551 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot);
552 slot->host.f_max = slot->max_clk;
553 slot->host.host_ocr = 0;
554 if (caps & SDHCI_CAN_VDD_330)
555 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
556 if (caps & SDHCI_CAN_VDD_300)
557 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
558 if (caps & SDHCI_CAN_VDD_180)
559 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
560 if (slot->host.host_ocr == 0) {
561 device_printf(dev, "Hardware doesn't report any "
562 "support voltages.\n");
564 slot->host.caps = MMC_CAP_4_BIT_DATA;
565 if (caps & SDHCI_CAN_DO_HISPD)
566 slot->host.caps |= MMC_CAP_HSPEED;
567 /* Decide if we have usable DMA. */
568 if (caps & SDHCI_CAN_DO_DMA)
569 slot->opt |= SDHCI_HAVE_DMA;
571 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA)
572 slot->opt &= ~SDHCI_HAVE_DMA;
573 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA)
574 slot->opt |= SDHCI_HAVE_DMA;
577 * Use platform-provided transfer backend
578 * with PIO as a fallback mechanism
580 if (slot->opt & SDHCI_PLATFORM_TRANSFER)
581 slot->opt &= ~SDHCI_HAVE_DMA;
583 if (bootverbose || sdhci_debug) {
584 slot_printf(slot, "%uMHz%s 4bits%s%s%s %s\n",
585 slot->max_clk / 1000000,
586 (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "",
587 (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "",
588 (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "",
589 (caps & SDHCI_CAN_VDD_180) ? " 1.8V" : "",
590 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO");
591 sdhci_dumpregs(slot);
594 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
595 callout_init(&slot->card_callout, 1);
600 sdhci_start_slot(struct sdhci_slot *slot)
602 sdhci_card_task(slot, 0);
606 sdhci_cleanup_slot(struct sdhci_slot *slot)
610 callout_drain(&slot->card_callout);
611 taskqueue_drain(taskqueue_swi_giant, &slot->card_task);
618 device_delete_child(slot->bus, d);
621 sdhci_reset(slot, SDHCI_RESET_ALL);
623 bus_dmamap_unload(slot->dmatag, slot->dmamap);
624 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
625 bus_dma_tag_destroy(slot->dmatag);
627 SDHCI_LOCK_DESTROY(slot);
633 sdhci_generic_suspend(struct sdhci_slot *slot)
635 sdhci_reset(slot, SDHCI_RESET_ALL);
641 sdhci_generic_resume(struct sdhci_slot *slot)
649 sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot)
651 if (slot->version >= SDHCI_SPEC_300)
652 return (slot->max_clk / SDHCI_300_MAX_DIVIDER);
654 return (slot->max_clk / SDHCI_200_MAX_DIVIDER);
658 sdhci_generic_update_ios(device_t brdev, device_t reqdev)
660 struct sdhci_slot *slot = device_get_ivars(reqdev);
661 struct mmc_ios *ios = &slot->host.ios;
664 /* Do full reset on bus power down to clear from any state. */
665 if (ios->power_mode == power_off) {
666 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
669 /* Configure the bus. */
670 sdhci_set_clock(slot, ios->clock);
671 sdhci_set_power(slot, (ios->power_mode == power_off)?0:ios->vdd);
672 if (ios->bus_width == bus_width_4)
673 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
675 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
676 if (ios->timing == bus_timing_hs)
677 slot->hostctrl |= SDHCI_CTRL_HISPD;
679 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
680 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
681 /* Some controllers like reset after bus changes. */
682 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
683 sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
690 sdhci_set_transfer_mode(struct sdhci_slot *slot,
691 struct mmc_data *data)
698 mode = SDHCI_TRNS_BLK_CNT_EN;
700 mode |= SDHCI_TRNS_MULTI;
701 if (data->flags & MMC_DATA_READ)
702 mode |= SDHCI_TRNS_READ;
704 mode |= SDHCI_TRNS_ACMD12;
705 if (slot->flags & SDHCI_USE_DMA)
706 mode |= SDHCI_TRNS_DMA;
708 WR2(slot, SDHCI_TRANSFER_MODE, mode);
712 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd)
714 struct mmc_request *req = slot->req;
716 uint32_t mask, state;
721 cmd->error = MMC_ERR_NONE;
723 /* This flags combination is not supported by controller. */
724 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
725 slot_printf(slot, "Unsupported response type!\n");
726 cmd->error = MMC_ERR_FAILED;
733 /* Read controller present state. */
734 state = RD4(slot, SDHCI_PRESENT_STATE);
735 /* Do not issue command if there is no card, clock or power.
736 * Controller will not detect timeout without clock active. */
737 if ((state & SDHCI_CARD_PRESENT) == 0 ||
740 cmd->error = MMC_ERR_FAILED;
746 /* Always wait for free CMD bus. */
747 mask = SDHCI_CMD_INHIBIT;
748 /* Wait for free DAT if we have data or busy signal. */
749 if (cmd->data || (cmd->flags & MMC_RSP_BUSY))
750 mask |= SDHCI_DAT_INHIBIT;
751 /* We shouldn't wait for DAT for stop commands. */
752 if (cmd == slot->req->stop)
753 mask &= ~SDHCI_DAT_INHIBIT;
754 /* Wait for bus no more then 10 ms. */
756 while (state & mask) {
758 slot_printf(slot, "Controller never released "
759 "inhibit bit(s).\n");
760 sdhci_dumpregs(slot);
761 cmd->error = MMC_ERR_FAILED;
769 state = RD4(slot, SDHCI_PRESENT_STATE);
772 /* Prepare command flags. */
773 if (!(cmd->flags & MMC_RSP_PRESENT))
774 flags = SDHCI_CMD_RESP_NONE;
775 else if (cmd->flags & MMC_RSP_136)
776 flags = SDHCI_CMD_RESP_LONG;
777 else if (cmd->flags & MMC_RSP_BUSY)
778 flags = SDHCI_CMD_RESP_SHORT_BUSY;
780 flags = SDHCI_CMD_RESP_SHORT;
781 if (cmd->flags & MMC_RSP_CRC)
782 flags |= SDHCI_CMD_CRC;
783 if (cmd->flags & MMC_RSP_OPCODE)
784 flags |= SDHCI_CMD_INDEX;
786 flags |= SDHCI_CMD_DATA;
787 if (cmd->opcode == MMC_STOP_TRANSMISSION)
788 flags |= SDHCI_CMD_TYPE_ABORT;
790 sdhci_start_data(slot, cmd->data);
792 * Interrupt aggregation: To reduce total number of interrupts
793 * group response interrupt with data interrupt when possible.
794 * If there going to be data interrupt, mask response one.
796 if (slot->data_done == 0) {
797 WR4(slot, SDHCI_SIGNAL_ENABLE,
798 slot->intmask &= ~SDHCI_INT_RESPONSE);
800 /* Set command argument. */
801 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
802 /* Set data transfer mode. */
803 sdhci_set_transfer_mode(slot, cmd->data);
805 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
809 sdhci_finish_command(struct sdhci_slot *slot)
814 /* Interrupt aggregation: Restore command interrupt.
815 * Main restore point for the case when command interrupt
817 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE);
818 /* In case of error - reset host and return. */
819 if (slot->curcmd->error) {
820 sdhci_reset(slot, SDHCI_RESET_CMD);
821 sdhci_reset(slot, SDHCI_RESET_DATA);
825 /* If command has response - fetch it. */
826 if (slot->curcmd->flags & MMC_RSP_PRESENT) {
827 if (slot->curcmd->flags & MMC_RSP_136) {
828 /* CRC is stripped so we need one byte shift. */
830 for (i = 0; i < 4; i++) {
831 uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4);
832 slot->curcmd->resp[3 - i] = (val << 8) + extra;
836 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
838 /* If data ready - finish. */
844 sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data)
846 uint32_t target_timeout, current_timeout;
849 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
856 /* Calculate and set data timeout.*/
857 /* XXX: We should have this from mmc layer, now assume 1 sec. */
858 target_timeout = 1000000;
860 current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
861 while (current_timeout < target_timeout) {
863 current_timeout <<= 1;
867 /* Compensate for an off-by-one error in the CaFe chip.*/
868 if (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)
871 slot_printf(slot, "Timeout too large!\n");
874 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
876 WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
881 /* Use DMA if possible. */
882 if ((slot->opt & SDHCI_HAVE_DMA))
883 slot->flags |= SDHCI_USE_DMA;
884 /* If data is small, broken DMA may return zeroes instead of data, */
885 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
887 slot->flags &= ~SDHCI_USE_DMA;
888 /* Some controllers require even block sizes. */
889 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
891 slot->flags &= ~SDHCI_USE_DMA;
892 /* Load DMA buffer. */
893 if (slot->flags & SDHCI_USE_DMA) {
894 if (data->flags & MMC_DATA_READ)
895 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREREAD);
897 memcpy(slot->dmamem, data->data,
898 (data->len < DMA_BLOCK_SIZE)?data->len:DMA_BLOCK_SIZE);
899 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREWRITE);
901 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
902 /* Interrupt aggregation: Mask border interrupt
903 * for the last page and unmask else. */
904 if (data->len == DMA_BLOCK_SIZE)
905 slot->intmask &= ~SDHCI_INT_DMA_END;
907 slot->intmask |= SDHCI_INT_DMA_END;
908 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
910 /* Current data offset for both PIO and DMA. */
912 /* Set block size and request IRQ on 4K border. */
913 WR2(slot, SDHCI_BLOCK_SIZE,
914 SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512)?data->len:512));
915 /* Set block count. */
916 WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512);
920 sdhci_finish_data(struct sdhci_slot *slot)
922 struct mmc_data *data = slot->curcmd->data;
925 /* Interrupt aggregation: Restore command interrupt.
926 * Auxillary restore point for the case when data interrupt
928 if (!slot->cmd_done) {
929 WR4(slot, SDHCI_SIGNAL_ENABLE,
930 slot->intmask |= SDHCI_INT_RESPONSE);
932 /* Unload rest of data from DMA buffer. */
933 if (slot->flags & SDHCI_USE_DMA) {
934 if (data->flags & MMC_DATA_READ) {
935 size_t left = data->len - slot->offset;
936 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTREAD);
937 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
938 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
940 bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTWRITE);
942 /* If there was error - reset the host. */
943 if (slot->curcmd->error) {
944 sdhci_reset(slot, SDHCI_RESET_CMD);
945 sdhci_reset(slot, SDHCI_RESET_DATA);
949 /* If we already have command response - finish. */
955 sdhci_start(struct sdhci_slot *slot)
957 struct mmc_request *req;
963 if (!(slot->flags & CMD_STARTED)) {
964 slot->flags |= CMD_STARTED;
965 sdhci_start_command(slot, req->cmd);
968 /* We don't need this until using Auto-CMD12 feature
969 if (!(slot->flags & STOP_STARTED) && req->stop) {
970 slot->flags |= STOP_STARTED;
971 sdhci_start_command(slot, req->stop);
976 slot_printf(slot, "result: %d\n", req->cmd->error);
977 if (!req->cmd->error &&
978 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
979 sdhci_reset(slot, SDHCI_RESET_CMD);
980 sdhci_reset(slot, SDHCI_RESET_DATA);
983 /* We must be done -- bad idea to do this while locked? */
990 sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req)
992 struct sdhci_slot *slot = device_get_ivars(reqdev);
995 if (slot->req != NULL) {
999 if (sdhci_debug > 1) {
1000 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n",
1001 req->cmd->opcode, req->cmd->arg, req->cmd->flags,
1002 (req->cmd->data)?(u_int)req->cmd->data->len:0,
1003 (req->cmd->data)?req->cmd->data->flags:0);
1010 while (slot->req != NULL) {
1011 sdhci_generic_intr(slot);
1019 sdhci_generic_get_ro(device_t brdev, device_t reqdev)
1021 struct sdhci_slot *slot = device_get_ivars(reqdev);
1025 val = RD4(slot, SDHCI_PRESENT_STATE);
1027 return (!(val & SDHCI_WRITE_PROTECT));
1031 sdhci_generic_acquire_host(device_t brdev, device_t reqdev)
1033 struct sdhci_slot *slot = device_get_ivars(reqdev);
1037 while (slot->bus_busy)
1038 msleep(slot, &slot->mtx, 0, "sdhciah", 0);
1041 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
1047 sdhci_generic_release_host(device_t brdev, device_t reqdev)
1049 struct sdhci_slot *slot = device_get_ivars(reqdev);
1052 /* Deactivate led. */
1053 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
1061 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask)
1064 if (!slot->curcmd) {
1065 slot_printf(slot, "Got command interrupt 0x%08x, but "
1066 "there is no active command.\n", intmask);
1067 sdhci_dumpregs(slot);
1070 if (intmask & SDHCI_INT_TIMEOUT)
1071 slot->curcmd->error = MMC_ERR_TIMEOUT;
1072 else if (intmask & SDHCI_INT_CRC)
1073 slot->curcmd->error = MMC_ERR_BADCRC;
1074 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
1075 slot->curcmd->error = MMC_ERR_FIFO;
1077 sdhci_finish_command(slot);
1081 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask)
1084 if (!slot->curcmd) {
1085 slot_printf(slot, "Got data interrupt 0x%08x, but "
1086 "there is no active command.\n", intmask);
1087 sdhci_dumpregs(slot);
1090 if (slot->curcmd->data == NULL &&
1091 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1092 slot_printf(slot, "Got data interrupt 0x%08x, but "
1093 "there is no active data operation.\n",
1095 sdhci_dumpregs(slot);
1098 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1099 slot->curcmd->error = MMC_ERR_TIMEOUT;
1100 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1101 slot->curcmd->error = MMC_ERR_BADCRC;
1102 if (slot->curcmd->data == NULL &&
1103 (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
1104 SDHCI_INT_DMA_END))) {
1105 slot_printf(slot, "Got data interrupt 0x%08x, but "
1106 "there is busy-only command.\n", intmask);
1107 sdhci_dumpregs(slot);
1108 slot->curcmd->error = MMC_ERR_INVALID;
1110 if (slot->curcmd->error) {
1111 /* No need to continue after any error. */
1112 if (slot->flags & PLATFORM_DATA_STARTED) {
1113 slot->flags &= ~PLATFORM_DATA_STARTED;
1114 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
1116 sdhci_finish_data(slot);
1120 /* Handle PIO interrupt. */
1121 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
1122 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) &&
1123 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) {
1124 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, &intmask);
1125 slot->flags |= PLATFORM_DATA_STARTED;
1127 sdhci_transfer_pio(slot);
1129 /* Handle DMA border. */
1130 if (intmask & SDHCI_INT_DMA_END) {
1131 struct mmc_data *data = slot->curcmd->data;
1134 /* Unload DMA buffer... */
1135 left = data->len - slot->offset;
1136 if (data->flags & MMC_DATA_READ) {
1137 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1138 BUS_DMASYNC_POSTREAD);
1139 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
1140 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1142 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1143 BUS_DMASYNC_POSTWRITE);
1145 /* ... and reload it again. */
1146 slot->offset += DMA_BLOCK_SIZE;
1147 left = data->len - slot->offset;
1148 if (data->flags & MMC_DATA_READ) {
1149 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1150 BUS_DMASYNC_PREREAD);
1152 memcpy(slot->dmamem, (u_char*)data->data + slot->offset,
1153 (left < DMA_BLOCK_SIZE)?left:DMA_BLOCK_SIZE);
1154 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1155 BUS_DMASYNC_PREWRITE);
1157 /* Interrupt aggregation: Mask border interrupt
1158 * for the last page. */
1159 if (left == DMA_BLOCK_SIZE) {
1160 slot->intmask &= ~SDHCI_INT_DMA_END;
1161 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1164 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1166 /* We have got all data. */
1167 if (intmask & SDHCI_INT_DATA_END) {
1168 if (slot->flags & PLATFORM_DATA_STARTED) {
1169 slot->flags &= ~PLATFORM_DATA_STARTED;
1170 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
1172 sdhci_finish_data(slot);
1177 sdhci_acmd_irq(struct sdhci_slot *slot)
1181 err = RD4(slot, SDHCI_ACMD12_ERR);
1182 if (!slot->curcmd) {
1183 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
1184 "there is no active command.\n", err);
1185 sdhci_dumpregs(slot);
1188 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err);
1189 sdhci_reset(slot, SDHCI_RESET_CMD);
1193 sdhci_generic_intr(struct sdhci_slot *slot)
1198 /* Read slot interrupt status. */
1199 intmask = RD4(slot, SDHCI_INT_STATUS);
1200 if (intmask == 0 || intmask == 0xffffffff) {
1204 if (sdhci_debug > 2)
1205 slot_printf(slot, "Interrupt %#x\n", intmask);
1207 /* Handle card presence interrupts. */
1208 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1209 WR4(slot, SDHCI_INT_STATUS, intmask &
1210 (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE));
1212 if (intmask & SDHCI_INT_CARD_REMOVE) {
1213 if (bootverbose || sdhci_debug)
1214 slot_printf(slot, "Card removed\n");
1215 callout_stop(&slot->card_callout);
1216 taskqueue_enqueue(taskqueue_swi_giant,
1219 if (intmask & SDHCI_INT_CARD_INSERT) {
1220 if (bootverbose || sdhci_debug)
1221 slot_printf(slot, "Card inserted\n");
1222 callout_reset(&slot->card_callout, hz / 2,
1223 sdhci_card_delay, slot);
1225 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1227 /* Handle command interrupts. */
1228 if (intmask & SDHCI_INT_CMD_MASK) {
1229 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
1230 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
1232 /* Handle data interrupts. */
1233 if (intmask & SDHCI_INT_DATA_MASK) {
1234 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
1235 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
1237 /* Handle AutoCMD12 error interrupt. */
1238 if (intmask & SDHCI_INT_ACMD12ERR) {
1239 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
1240 sdhci_acmd_irq(slot);
1242 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1243 intmask &= ~SDHCI_INT_ACMD12ERR;
1244 intmask &= ~SDHCI_INT_ERROR;
1245 /* Handle bus power interrupt. */
1246 if (intmask & SDHCI_INT_BUS_POWER) {
1247 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
1249 "Card is consuming too much power!\n");
1250 intmask &= ~SDHCI_INT_BUS_POWER;
1252 /* The rest is unknown. */
1254 WR4(slot, SDHCI_INT_STATUS, intmask);
1255 slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
1257 sdhci_dumpregs(slot);
1264 sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result)
1266 struct sdhci_slot *slot = device_get_ivars(child);
1271 case MMCBR_IVAR_BUS_MODE:
1272 *result = slot->host.ios.bus_mode;
1274 case MMCBR_IVAR_BUS_WIDTH:
1275 *result = slot->host.ios.bus_width;
1277 case MMCBR_IVAR_CHIP_SELECT:
1278 *result = slot->host.ios.chip_select;
1280 case MMCBR_IVAR_CLOCK:
1281 *result = slot->host.ios.clock;
1283 case MMCBR_IVAR_F_MIN:
1284 *result = slot->host.f_min;
1286 case MMCBR_IVAR_F_MAX:
1287 *result = slot->host.f_max;
1289 case MMCBR_IVAR_HOST_OCR:
1290 *result = slot->host.host_ocr;
1292 case MMCBR_IVAR_MODE:
1293 *result = slot->host.mode;
1295 case MMCBR_IVAR_OCR:
1296 *result = slot->host.ocr;
1298 case MMCBR_IVAR_POWER_MODE:
1299 *result = slot->host.ios.power_mode;
1301 case MMCBR_IVAR_VDD:
1302 *result = slot->host.ios.vdd;
1304 case MMCBR_IVAR_CAPS:
1305 *result = slot->host.caps;
1307 case MMCBR_IVAR_TIMING:
1308 *result = slot->host.ios.timing;
1310 case MMCBR_IVAR_MAX_DATA:
1318 sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
1320 struct sdhci_slot *slot = device_get_ivars(child);
1325 case MMCBR_IVAR_BUS_MODE:
1326 slot->host.ios.bus_mode = value;
1328 case MMCBR_IVAR_BUS_WIDTH:
1329 slot->host.ios.bus_width = value;
1331 case MMCBR_IVAR_CHIP_SELECT:
1332 slot->host.ios.chip_select = value;
1334 case MMCBR_IVAR_CLOCK:
1340 max_clock = slot->max_clk;
1343 if (slot->version < SDHCI_SPEC_300) {
1344 for (i = 0; i < SDHCI_200_MAX_DIVIDER;
1352 for (i = 0; i < SDHCI_300_MAX_DIVIDER;
1356 clock = max_clock / (i + 2);
1360 slot->host.ios.clock = clock;
1362 slot->host.ios.clock = 0;
1364 case MMCBR_IVAR_MODE:
1365 slot->host.mode = value;
1367 case MMCBR_IVAR_OCR:
1368 slot->host.ocr = value;
1370 case MMCBR_IVAR_POWER_MODE:
1371 slot->host.ios.power_mode = value;
1373 case MMCBR_IVAR_VDD:
1374 slot->host.ios.vdd = value;
1376 case MMCBR_IVAR_TIMING:
1377 slot->host.ios.timing = value;
1379 case MMCBR_IVAR_CAPS:
1380 case MMCBR_IVAR_HOST_OCR:
1381 case MMCBR_IVAR_F_MIN:
1382 case MMCBR_IVAR_F_MAX:
1383 case MMCBR_IVAR_MAX_DATA:
1389 MODULE_VERSION(sdhci, 1);